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add jz4740 touch screen emulation
[qemu/qemu-JZ.git] / hw / mips_jz.c
blob0e853df0287ad482b58b80681797bc0dbe753a69
1 /*
2 * QEMU JZ Soc emulation
3 *
4 * Copyright (c) 2009 yajin (yajin@vm-kernel.org)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25
26 /*
27 * The emulation target is pavo demo board.
28 * http://www.ingenic.cn/eng/productServ/kfyd/Hardware/pffaqQuestionContent.aspx?Category=2&Question=3
29 *
30 */
31
32 #include "hw.h"
33 #include "mips.h"
34 #include "sysemu.h"
35 #include "qemu-timer.h"
36 #include "qemu-char.h"
37 #include "flash.h"
38 #include "soc_dma.h"
39 #include "audio/audio.h"
40 #include "pc.h"
41 #include "osdep.h"
42 #include "mips_jz.h"
43 #include "console.h"
44
45 #define DEBUG /*global debug on/off */
46
47 #define DEBUG_CPM (1<<0x0)
48 #define DEBUG_EMC (1<<0x1)
49 #define DEBUG_GPIO (1<<0x2)
50 #define DEBUG_RTC (1<<0x3)
51 #define DEBUG_TCU (1<<0x4)
52 #define DEBUG_LCDC (1<<0x5)
53 #define DEBUG_DMA (1<<0x6)
54 #define DEBUG_SADC (1<<0x7)
55 #define DEBUG_FLAG DEBUG_SADC //(DEBUG_CPM|DEBUG_EMC|DEBUG_GPIO \
56 // | DEBUG_RTC | DEBUG_TCU | DEBUG_LCDC | DEBUG_DMA)
57 //DEBUG_TCU// (DEBUG_CPM|DEBUG_EMC|DEBUG_GPIO
58 // | DEBUG_RTC | DEBUG_TCU | DEBUG_LCDC | DEBUG_DMA)
59
60
61 #ifdef DEBUG
62 FILE *fp;
63 static void debug_init(void)
64 {
65 fp = fopen("jz4740.txt", "w+");
66 if (fp == NULL)
67 {
68 fprintf(stderr, "can not open jz4740.txt \n");
69 exit(-1);
70 }
71 }
72 static void debug_out(uint32_t flag, const char *format, ...)
73 {
74 va_list ap;
75 if (fp)
76 {
77 if (flag & DEBUG_FLAG)
78 {
79 va_start(ap, format);
80 vfprintf(fp, format, ap);
81 fflush(fp);
82 va_end(ap);
83 }
84 }
85 }
86 #else
87 static void debug_init(void)
88 {
89 }
90 static void debug_out(uint32_t flag, const char *format, ...)
91 {
92 }
93 #endif
94
95 uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr)
96 {
97 uint8_t ret;
98
99 JZ4740_8B_REG(addr);
100 cpu_physical_memory_read(addr, (void *) &ret, 1);
101 return ret;
102 }
103
104 void jz4740_badwidth_write8(void *opaque, target_phys_addr_t addr,
105 uint32_t value)
106 {
107 uint8_t val8 = value;
108
109 JZ4740_8B_REG(addr);
110 cpu_physical_memory_write(addr, (void *) &val8, 1);
111 }
112
113 uint32_t jz4740_badwidth_read16(void *opaque, target_phys_addr_t addr)
114 {
115 uint16_t ret;
116 JZ4740_16B_REG(addr);
117 cpu_physical_memory_read(addr, (void *) &ret, 2);
118 return ret;
119 }
120
121 void jz4740_badwidth_write16(void *opaque, target_phys_addr_t addr,
122 uint32_t value)
123 {
124 uint16_t val16 = value;
125
126 JZ4740_16B_REG(addr);
127 cpu_physical_memory_write(addr, (void *) &val16, 2);
128 }
129
130 uint32_t jz4740_badwidth_read32(void *opaque, target_phys_addr_t addr)
131 {
132 uint32_t ret;
133
134 JZ4740_32B_REG(addr);
135 cpu_physical_memory_read(addr, (void *) &ret, 4);
136 return ret;
137 }
138
139 void jz4740_badwidth_write32(void *opaque, target_phys_addr_t addr,
140 uint32_t value)
141 {
142 JZ4740_32B_REG(addr);
143 cpu_physical_memory_write(addr, (void *) &value, 4);
144 }
145
146
147 /*clock reset and power control*/
148 struct jz4740_cpm_s
149 {
150 target_phys_addr_t base;
151 struct jz_state_s *soc;
152
153 uint32_t cpccr;
154 uint32_t cppcr;
155 uint32_t i2scdr;
156 uint32_t lpcdr;
157 uint32_t msccdr;
158 uint32_t uhccdr;
159 uint32_t uhctst;
160 uint32_t ssicdr;
161
162 uint32_t lcr;
163 uint32_t clkgr;
164 uint32_t scr;
165 };
166
167 static void jz4740_dump_clocks(jz_clk parent)
168 {
169 jz_clk i = parent;
170
171 debug_out(DEBUG_CPM, "clock %s rate %d \n", i->name, i->rate);
172 for (i = i->child1; i; i = i->sibling)
173 jz4740_dump_clocks(i);
174 }
175
176 static inline void jz4740_cpccr_update(struct jz4740_cpm_s *s,
177 uint32_t new_value)
178 {
179 uint32_t ldiv, mdiv, pdiv, hdiv, cdiv, udiv;
180 uint32_t div_table[10] = {
181 1, 2, 3, 4, 6, 8, 12, 16, 24, 32
182 };
183
184 if (unlikely(new_value == s->cpccr))
185 return;
186
187 if (new_value & CPM_CPCCR_PCS)
188 jz_clk_setrate(jz_findclk(s->soc, "pll_divider"), 1, 1);
189 else
190 jz_clk_setrate(jz_findclk(s->soc, "pll_divider"), 2, 1);
191
192
193 ldiv = (new_value & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT;
194 ldiv++;
195
196 mdiv = div_table[(new_value & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT];
197 pdiv = div_table[(new_value & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT];
198 hdiv = div_table[(new_value & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT];
199 cdiv = div_table[(new_value & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT];
200 udiv = div_table[(new_value & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT];
201
202 jz_clk_setrate(jz_findclk(s->soc, "ldclk"), ldiv, 1);
203 jz_clk_setrate(jz_findclk(s->soc, "mclk"), mdiv, 1);
204 jz_clk_setrate(jz_findclk(s->soc, "pclk"), pdiv, 1);
205 jz_clk_setrate(jz_findclk(s->soc, "hclk"), hdiv, 1);
206 jz_clk_setrate(jz_findclk(s->soc, "cclk"), cdiv, 1);
207 jz_clk_setrate(jz_findclk(s->soc, "usbclk"), udiv, 1);
208
209 if (new_value & CPM_CPCCR_UCS)
210 jz_clk_reparent(jz_findclk(s->soc, "usbclk"),
211 jz_findclk(s->soc, "pll_divider"));
212 else
213 jz_clk_reparent(jz_findclk(s->soc, "usbclk"),
214 jz_findclk(s->soc, "osc_extal"));
215
216 if (new_value & CPM_CPCCR_I2CS)
217 jz_clk_reparent(jz_findclk(s->soc, "i2sclk"),
218 jz_findclk(s->soc, "pll_divider"));
219 else
220 jz_clk_reparent(jz_findclk(s->soc, "i2sclk"),
221 jz_findclk(s->soc, "osc_extal"));
222
223 s->cpccr = new_value;
224
225 debug_out(DEBUG_CPM, "write to cpccr 0x%x\n", new_value);
226
227 jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
228
229 }
230
231 static inline void jz4740_cppcr_update(struct jz4740_cpm_s *s,
232 uint32_t new_value)
233 {
234 uint32_t pllm, plln, pllod, pllbp, pllen;
235 uint32_t pll0[4] = {
236 1, 2, 2, 4
237 };
238
239
240 pllen = new_value & CPM_CPPCR_PLLEN;
241 pllbp = new_value & CPM_CPPCR_PLLBP;
242 if ((!pllen) || (pllen && pllbp))
243 {
244 jz_clk_setrate(jz_findclk(s->soc, "pll_output"), 1, 1);
245 debug_out(DEBUG_CPM, "pll is bypassed \n");
246 s->cppcr = new_value | CPM_CPPCR_PLLS;
247 return;
248 }
249
250
251 pllm = (new_value & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT;
252 plln = (new_value & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT;
253 pllod = (new_value & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT;
254 jz_clk_setrate(jz_findclk(s->soc, "pll_output"), (plln + 2) * pll0[pllod],
255 pllm + 2);
256
257 s->cppcr = new_value;
258
259 debug_out(DEBUG_CPM, "write to cppcr 0x%x\n", new_value);
260 jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
261
262 }
263
264 static inline void jz4740_i2scdr_update(struct jz4740_cpm_s *s,
265 uint32_t new_value)
266 {
267 uint32_t i2scdr;
268
269 i2scdr = new_value & CPM_I2SCDR_I2SDIV_MASK;
270 if (unlikely(i2scdr == s->i2scdr))
271 return;
272
273
274 jz_clk_setrate(jz_findclk(s->soc, "i2sclk"), i2scdr + 1, 1);
275
276 s->i2scdr = i2scdr;
277
278 debug_out(DEBUG_CPM, "write to i2scdr 0x%x\n", new_value);
279 jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
280
281 }
282
283 static inline void jz4740_lpcdr_update(struct jz4740_cpm_s *s,
284 uint32_t new_value)
285 {
286 uint32_t ipcdr;
287
288 ipcdr = new_value & CPM_LPCDR_PIXDIV_MASK;
289 /*TODO: */
290 s->lpcdr = ipcdr;
291 }
292
293 static inline void jz4740_msccdr_update(struct jz4740_cpm_s *s,
294 uint32_t new_value)
295 {
296 uint32_t msccdr;
297
298 msccdr = new_value & CPM_MSCCDR_MSCDIV_MASK;
299
300 if (unlikely(msccdr == s->msccdr))
301 return;
302
303
304 jz_clk_setrate(jz_findclk(s->soc, "mscclk"), msccdr + 1, 1);
305
306 s->msccdr = msccdr;
307
308 debug_out(DEBUG_CPM, "write to msccdr 0x%x\n", new_value);
309 jz4740_dump_clocks(jz_findclk(s->soc, "osc_extal"));
310
311 }
312
313 static inline void jz4740_uhccdr_update(struct jz4740_cpm_s *s,
314 uint32_t new_value)
315 {
316 uint32_t uhccdr;
317
318 uhccdr = new_value & 0xf;
319 /*TODO: */
320 s->uhccdr = uhccdr;
321 }
322
323 static void jz4740_cpm_write(void *opaque, target_phys_addr_t addr,
324 uint32_t value)
325 {
326 struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) opaque;
327
328 debug_out(DEBUG_CPM, "write to cpm addr %x value 0x%x\n", addr, value);
329
330 switch (addr)
331 {
332 case 0x0:
333 jz4740_cpccr_update(s, value);
334 break;
335 case 0x4:
336 s->lcr = value & 0xff;
337 break;
338 case 0x20:
339 s->clkgr = value & 0xffff;
340 break;
341 case 0x24:
342 s->scr = value & 0xffff;
343 break;
344 case 0x10:
345 jz4740_cppcr_update(s, value);
346 break;
347 case 0x60:
348 jz4740_i2scdr_update(s, value);
349 break;
350 case 0x64:
351 jz4740_lpcdr_update(s, value);
352 break;
353 case 0x68:
354 jz4740_msccdr_update(s, value);
355 break;
356 case 0x6c:
357 jz4740_uhccdr_update(s, value);
358 break;
359 case 0x70:
360 s->uhctst = value & 0x3f;
361 break;
362 case 0x74:
363 s->ssicdr = value & 0xf;
364 break;
365 default:
366 cpu_abort(s->soc->env,
367 "jz4740_cpm_write undefined addr " JZ_FMT_plx
368 " value %x \n", addr, value);
369 }
370
371 }
372
373
374 static uint32_t jz474_cpm_read(void *opaque, target_phys_addr_t addr)
375 {
376 struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) opaque;
377
378 switch (addr)
379 {
380 case 0x0:
381 return s->cpccr;
382 case 0x4:
383 return s->lcr;
384 case 0x20:
385 return s->clkgr;
386 case 0x24:
387 return s->scr;
388 case 0x10:
389 return s->cppcr;
390 case 0x60:
391 return s->i2scdr;
392 case 0x64:
393 return s->lpcdr;
394 case 0x68:
395 return s->msccdr;
396 case 0x6c:
397 return s->uhccdr;
398 case 0x70:
399 return s->uhctst;
400 case 0x74:
401 return s->ssicdr;
402 default:
403 cpu_abort(s->soc->env,
404 "jz474_cpm_read undefined addr " JZ_FMT_plx " \n", addr);
405 }
406
407 }
408
409
410
411 static CPUReadMemoryFunc *jz4740_cpm_readfn[] = {
412 jz4740_badwidth_read32,
413 jz4740_badwidth_read32,
414 jz474_cpm_read,
415 };
416
417 static CPUWriteMemoryFunc *jz4740_cpm_writefn[] = {
418 jz4740_badwidth_write32,
419 jz4740_badwidth_write32,
420 jz4740_cpm_write,
421 };
422
423 static void jz4740_cpm_reset(struct jz4740_cpm_s *s)
424 {
425 s->cpccr = 0x42040000;
426 s->cppcr = 0x28080011;
427 s->i2scdr = 0x00000004;
428 s->lpcdr = 0x00000004;
429 s->msccdr = 0x00000004;
430 s->uhccdr = 0x00000004;
431 s->uhctst = 0x0;
432 s->ssicdr = 0x00000004;
433
434 s->lcr = 0xf8;
435 s->clkgr = 0x0;
436 s->scr = 0x1500;
437 }
438
439 static struct jz4740_cpm_s *jz4740_cpm_init(struct jz_state_s *soc)
440 {
441 int iomemtype;
442 struct jz4740_cpm_s *s = (struct jz4740_cpm_s *) qemu_mallocz(sizeof(*s));
443 s->base = JZ4740_PHYS_BASE(JZ4740_CPM_BASE);
444 s->soc = soc;
445
446 jz4740_cpm_reset(s);
447
448 iomemtype =
449 cpu_register_io_memory(0, jz4740_cpm_readfn, jz4740_cpm_writefn, s);
450 cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
451 return s;
452 }
453
454
455 /* JZ4740 interrupt controller
456 * It issues INT2 to MIPS
457 */
458 struct jz4740_intc_s
459 {
460 qemu_irq parent_irq;
461
462 target_phys_addr_t base;
463 struct jz_state_s *soc;
464
465 uint32_t icsr;
466 uint32_t icmr;
467 uint32_t icmsr;
468 uint32_t icmcr;
469 uint32_t icpr;
470 };
471
472 static uint32_t jz4740_intc_read(void *opaque, target_phys_addr_t addr)
473 {
474 struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
475
476 switch (addr)
477 {
478 case 0x8:
479 case 0xc:
480 JZ4740_WO_REG(addr);
481 break;
482 case 0x0:
483 return s->icsr;
484 case 0x4:
485 return s->icmr;
486 case 0x10:
487 return s->icpr;
488 default:
489 cpu_abort(s->soc->env,
490 "jz4740_intc_read undefined addr " JZ_FMT_plx " \n", addr);
491
492 }
493 return (0);
494 }
495
496 static void jz4740_intc_write(void *opaque, target_phys_addr_t addr,
497 uint32_t value)
498 {
499 struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
500
501 switch (addr)
502 {
503 case 0x0:
504 JZ4740_RO_REG(addr);
505 break;
506 case 0x4:
507 s->icmr = value;
508 break;
509 case 0x8:
510 s->icmr |= value;
511 break;
512 case 0xc:
513 s->icmr &= ~value;
514 break;
515 case 0x10:
516 s->icpr &= ~value;
517 qemu_set_irq(s->parent_irq, 0);
518 break;
519 default:
520 cpu_abort(s->soc->env,
521 "jz4740_intc_write undefined addr " JZ_FMT_plx
522 " value %x \n", addr, value);
523 }
524 }
525
526
527 static CPUReadMemoryFunc *jz4740_intc_readfn[] = {
528 jz4740_badwidth_read32,
529 jz4740_badwidth_read32,
530 jz4740_intc_read,
531 };
532
533 static CPUWriteMemoryFunc *jz4740_intc_writefn[] = {
534 jz4740_badwidth_write32,
535 jz4740_badwidth_write32,
536 jz4740_intc_write,
537 };
538
539 static void jz4740_intc_reset(struct jz4740_intc_s *s)
540 {
541 s->icsr = 0x0;
542 s->icmr = 0xffffffff;
543 s->icpr = 0x0;
544 }
545
546 static void jz4740_set_irq(void *opaque, int irq, int level)
547 {
548 struct jz4740_intc_s *s = (struct jz4740_intc_s *) opaque;
549 uint32_t irq_mask = 1 << irq;
550
551
552 if (level)
553 {
554 s->icsr |= irq_mask;
555 s->icpr &= ~irq_mask;
556 if (!(s->icmr & irq_mask))
557 {
558 s->icpr |= irq_mask;
559 qemu_set_irq(s->parent_irq, 1);
560 }
561 }
562
563 }
564
565 static qemu_irq *jz4740_intc_init(struct jz_state_s *soc, qemu_irq parent_irq)
566 {
567 int iomemtype;
568 struct jz4740_intc_s *s = (struct jz4740_intc_s *) qemu_mallocz(sizeof(*s));
569 s->base = JZ4740_PHYS_BASE(JZ4740_INTC_BASE);
570 s->parent_irq = parent_irq;
571 s->soc = soc;
572
573 jz4740_intc_reset(s);
574
575 iomemtype =
576 cpu_register_io_memory(0, jz4740_intc_readfn, jz4740_intc_writefn, s);
577 cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
578 return qemu_allocate_irqs(jz4740_set_irq, s, 32);
579 }
580
581 /*external memory controller*/
582 struct jz4740_emc_s
583 {
584 qemu_irq irq;
585 target_phys_addr_t base;
586 struct jz_state_s *soc;
587
588 uint32_t bcr;
589 uint32_t smcr1; /*0x13010014 */
590 uint32_t smcr2; /*0x13010018 */
591 uint32_t smcr3; /*0x1301001c */
592 uint32_t smcr4; /*0x13010020 */
593 uint32_t sacr1; /*0x13010034 */
594 uint32_t sacr2; /*0x13010038 */
595 uint32_t sacr3; /*0x1301003c */
596 uint32_t sacr4; /*0x13010040 */
597
598 uint32_t nfcsr; /*0x13010050 */
599 uint32_t nfeccr; /*0x13010100 */
600 uint32_t nfecc; /*0x13010104 */
601 uint32_t nfpar0; /*0x13010108 */
602 uint32_t nfpar1; /*0x1301010c */
603 uint32_t nfpar2; /*0x13010110 */
604 uint32_t nfints; /*0x13010114 */
605 uint32_t nfinte; /*0x13010118 */
606 uint32_t nferr0; /*0x1301011c */
607 uint32_t nferr1; /*0x13010120 */
608 uint32_t nferr2; /*0x13010124 */
609 uint32_t nferr3; /*0x13010128 */
610
611 uint32_t dmcr; /*0x13010080 */
612 uint32_t rtcsr; /*0x13010084 */
613 uint32_t rtcnt; /*0x13010088 */
614 uint32_t rtcor; /*0x1301008c */
615 uint32_t dmar; /*0x13010090 */
616 uint32_t sdmr; /*0x1301a000 */
617
618 };
619
620
621 static void jz4740_emc_reset(struct jz4740_emc_s *s)
622 {
623 s->smcr1 = 0xfff7700;
624 s->smcr2 = 0xfff7700;
625 s->smcr3 = 0xfff7700;
626 s->smcr4 = 0xfff7700;
627 s->sacr1 = 0x18fc;
628 s->sacr2 = 0x16fe;
629 s->sacr3 = 0x14fe;
630 s->sacr4 = 0xcfc;
631
632 s->nfcsr = 0x0;
633 s->nfeccr = 0x0;
634 s->nfecc = 0x0;
635 s->nfpar0 = 0x0;
636 s->nfpar1 = 0x0;
637 s->nfpar2 = 0x0;
638 s->nfints = 0x0;
639 s->nfinte = 0x0;
640 s->nferr0 = 0x0;
641 s->nferr1 = 0x0;
642 s->nferr2 = 0x0;
643 s->nferr3 = 0x0;
644
645 s->dmcr = 0x0;
646 s->rtcsr = 0x0;
647 s->rtcnt = 0x0;
648 s->rtcor = 0x0;
649 s->dmar = 0x20f8;
650 s->sdmr = 0x0;
651
652 }
653
654 static uint32_t jz4740_emc_read8(void *opaque, target_phys_addr_t addr)
655 {
656 struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
657
658 switch (addr)
659 {
660 case 0x108:
661 case 0x109:
662 case 0x10a:
663 case 0x10b:
664 return (s->nfpar0 >> ((addr - 0x108) * 8)) & 0xff;
665 case 0x10c:
666 case 0x10d:
667 case 0x10e:
668 case 0x10f:
669 return (s->nfpar1 >> ((addr - 0x10c) * 8)) & 0xff;
670 case 0x110:
671 case 0x111:
672 case 0x112:
673 case 0x113:
674 return (s->nfpar2 >> ((addr - 0x110) * 8)) & 0xff;
675 case 0xa000:
676 case 0xa001:
677 case 0xa002:
678 case 0xa003:
679 return (s->sdmr >> ((addr - 0xa000) * 8)) & 0xff;
680 default:
681 cpu_abort(s->soc->env,
682 "jz4740_emc_read8 undefined addr " JZ_FMT_plx " \n", addr);
683
684
685 }
686 return (0);
687 }
688
689 static uint32_t jz4740_emc_read16(void *opaque, target_phys_addr_t addr)
690 {
691 struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
692
693 switch (addr)
694 {
695 case 0x108:
696 case 0x10a:
697 return (s->nfpar0 >> ((addr - 0x108) * 8)) & 0xffff;
698 case 0x10c:
699 case 0x10e:
700 return (s->nfpar1 >> ((addr - 0x10c) * 8)) & 0xffff;
701 case 0x110:
702 case 0x112:
703 return (s->nfpar2 >> ((addr - 0x110) * 8)) & 0xffff;
704 case 0x11c:
705 case 0x11e:
706 return (s->nferr0 >> ((addr - 0x11c) * 8)) & 0xffff;
707 case 0x120:
708 case 0x122:
709 return (s->nferr1 >> ((addr - 0x120) * 8)) & 0xffff;
710 case 0x124:
711 case 0x126:
712 return (s->nferr2 >> ((addr - 0x124) * 8)) & 0xffff;
713 case 0x128:
714 case 0x12a:
715 return (s->nferr3 >> ((addr - 0x128) * 8)) & 0xffff;
716 default:
717 cpu_abort(s->soc->env,
718 "jz4740_emc_read16 undefined addr " JZ_FMT_plx " \n", addr);
719 }
720 return (0);
721 }
722
723 static uint32_t jz4740_emc_read32(void *opaque, target_phys_addr_t addr)
724 {
725 struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
726
727 switch (addr)
728 {
729 case 0x0:
730 return s->bcr;
731 case 0x14:
732 return s->smcr1;
733 case 0x18:
734 return s->smcr2;
735 case 0x1c:
736 return s->smcr3;
737 case 0x20:
738 return s->smcr4;
739 case 0x34:
740 return s->sacr1;
741 case 0x38:
742 return s->sacr2;
743 case 0x3c:
744 return s->sacr3;
745 case 0x40:
746 return s->sacr4;
747 case 0x50:
748 return s->nfcsr;
749 case 0x100:
750 return s->nfeccr;
751 case 0x104:
752 return s->nfecc;
753 case 0x108:
754 return s->nfpar0;
755 case 0x10c:
756 return s->nfpar1;
757 case 0x110:
758 return s->nfpar2;
759 case 0x114:
760 return s->nfints;
761 case 0x118:
762 return s->nfinte;
763 case 0x11c:
764 return s->nferr0;
765 case 0x120:
766 return s->nferr1;
767 case 0x124:
768 return s->nferr2;
769 case 0x128:
770 return s->nferr3;
771 case 0x80:
772 return s->dmcr;
773 case 0x90:
774 return s->dmar;
775 default:
776 cpu_abort(s->soc->env,
777 "jz4740_emc_read32 undefined addr " JZ_FMT_plx " \n", addr);
778 }
779 return (0);
780 }
781
782 static void jz4740_emc_write8(void *opaque, target_phys_addr_t addr,
783 uint32_t value)
784 {
785 struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
786
787 debug_out(DEBUG_EMC, "jz4740_emc_write8 addr %x value %x\n", addr, value);
788
789 switch (addr)
790 {
791 case 0x108:
792 case 0x109:
793 case 0x10a:
794 case 0x10b:
795 s->nfpar0 |= (value & 0xff) << ((addr - 0x108) * 8);
796 break;
797 case 0x10c:
798 case 0x10d:
799 case 0x10e:
800 case 0x10f:
801 s->nfpar1 |= (value & 0xff) << ((addr - 0x10c) * 8);
802 break;
803 case 0x110:
804 case 0x111:
805 case 0x112:
806 case 0x113:
807 s->nfpar2 |= (value & 0xff) << ((addr - 0x110) * 8);
808 break;
809 case 0xa000 ... 0xa3ff:
810 break;
811 default:
812 cpu_abort(s->soc->env,
813 "jz4740_emc_write8 undefined addr " JZ_FMT_plx
814 " value %x \n", addr, value);
815 }
816 }
817 static void jz4740_emc_write16(void *opaque, target_phys_addr_t addr,
818 uint32_t value)
819 {
820 struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
821
822 debug_out(DEBUG_EMC, "jz4740_emc_write16 addr %x value %x\n", addr, value);
823 switch (addr)
824 {
825 case 0x108:
826 case 0x10a:
827 s->nfpar0 |= (value & 0xffff) << ((addr - 0x108) * 8);
828 break;
829 case 0x10c:
830 case 0x10e:
831 s->nfpar1 |= (value & 0xffff) << ((addr - 0x10c) * 8);
832 break;
833 case 0x110:
834 case 0x112:
835 s->nfpar2 |= (value & 0xffff) << ((addr - 0x110) * 8);
836 break;
837 case 0x84:
838 case 0x86:
839 s->rtcsr |= (value & 0xffff) << ((addr - 0x84) * 8);
840 break;
841 case 0x88:
842 case 0x8a:
843 s->rtcnt |= (value & 0xffff) << ((addr - 0x88) * 8);
844 break;
845 case 0x8c:
846 s->rtcor |= (value & 0xffff) << ((addr - 0x8c) * 8);
847 break;
848 default:
849 cpu_abort(s->soc->env,
850 "jz4740_emc_write16 undefined addr " JZ_FMT_plx
851 " value %x \n", addr, value);
852 }
853 }
854
855 static void jz4740_emc_upate_interrupt(struct jz4740_emc_s *s)
856 {
857 qemu_set_irq(s->irq, s->nfints & s->nfinte);
858 }
859
860 static void jz4740_emc_write32(void *opaque, target_phys_addr_t addr,
861 uint32_t value)
862 {
863 struct jz4740_emc_s *s = (struct jz4740_emc_s *) opaque;
864
865 debug_out(DEBUG_EMC, "jz4740_emc_write32 addr %x value %x\n", addr, value);
866 switch (addr)
867 {
868 case 0x104:
869 case 0x11c:
870 case 0x120:
871 case 0x124:
872 case 0x128:
873 JZ4740_RO_REG(addr);
874 break;
875 case 0x0:
876 s->bcr = value;
877 break;
878 case 0x14:
879 s->smcr1 = value & 0xfff77cf;
880 break;
881 case 0x18:
882 s->smcr2 = value & 0xfff77cf;
883 break;
884 case 0x1c:
885 s->smcr3 = value & 0xfff77cf;
886 break;
887 case 0x20:
888 s->smcr4 = value & 0xfff77cf;
889 break;
890 case 0x34:
891 s->sacr1 = value & 0xffff;
892 break;
893 case 0x38:
894 s->sacr2 = value & 0xffff;
895 break;
896 case 0x3c:
897 s->sacr3 = value & 0xffff;
898 break;
899 case 0x40:
900 s->sacr4 = value & 0xffff;
901 break;
902 case 0x50:
903 s->nfcsr = value & 0xffff;
904 break;
905 case 0x100:
906 s->nfeccr = value & 0x1f;
907 if (s->nfeccr & 0x2)
908 {
909 s->nfecc = 0x0;
910 s->nfpar0 = 0x0;
911 s->nfpar1 = 0x0;
912 s->nfpar2 = 0x0;
913 s->nfints = 0x0;
914 s->nfinte = 0x0;
915 s->nferr0 = 0x0;
916 s->nferr1 = 0x0;
917 s->nferr2 = 0x0;
918 s->nferr3 = 0x0;
919 }
920 /*RS*/
921 /*TODO: Real RS error correction */
922 if (s->nfeccr & 0x4)
923 {
924 if ((s->nfeccr & 0x10) && (!(s->nfeccr & 0x8)))
925 {
926 /*decode */
927 s->nfints = 0x8;
928 s->nferr0 = 0x0;
929 s->nferr1 = 0x0;
930 s->nferr2 = 0x0;
931 }
932 if (s->nfeccr & 0x8)
933 {
934 /*encoding */
935 s->nfints = 0x4;
936 s->nfpar0 = 0xffffffff; /*fake value. for debug */
937 s->nfpar1 = 0xffffffff; /*fake value */
938 s->nfpar2 = 0xff; /*fake value */
939 }
940 }
941 else
942 {
943 s->nfecc = 0xffffff;
944 }
945 jz4740_emc_upate_interrupt(s);
946 break;
947 case 0x108:
948 s->nfpar0 = value;
949 break;
950 case 0x10c:
951 s->nfpar1 = value;
952 break;
953 case 0x110:
954 s->nfpar2 = value & 0xff;
955 break;
956 case 0x114:
957 s->nfints = value & 0x1fffffff;
958 jz4740_emc_upate_interrupt(s);
959 break;
960 case 0x118:
961 s->nfinte = value & 0x1f;
962 jz4740_emc_upate_interrupt(s);
963 break;
964 case 0x080:
965 s->dmcr = value & 0x9fbeff7f;
966 break;
967 case 0x90:
968 s->dmar = value & 0xffff;
969 break;
970 default:
971 cpu_abort(s->soc->env,
972 "jz4740_emc_write32 undefined addr " JZ_FMT_plx
973 " value %x \n", addr, value);
974
975 }
976
977 }
978
979 static CPUReadMemoryFunc *jz4740_emc_readfn[] = {
980 jz4740_emc_read8,
981 jz4740_emc_read16,
982 jz4740_emc_read32,
983 };
984
985 static CPUWriteMemoryFunc *jz4740_emc_writefn[] = {
986 jz4740_emc_write8,
987 jz4740_emc_write16,
988 jz4740_emc_write32,
989 };
990
991
992 static struct jz4740_emc_s *jz4740_emc_init(struct jz_state_s *soc,
993 qemu_irq irq)
994 {
995 int iomemtype;
996 struct jz4740_emc_s *s = (struct jz4740_emc_s *) qemu_mallocz(sizeof(*s));
997 s->base = JZ4740_PHYS_BASE(JZ4740_EMC_BASE);
998 s->soc = soc;
999 s->irq = irq;
1000
1001 jz4740_emc_reset(s);
1002
1003 iomemtype =
1004 cpu_register_io_memory(0, jz4740_emc_readfn, jz4740_emc_writefn, s);
1005 cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
1006 return s;
1007
1008 }
1009
1010 struct jz4740_gpio_s
1011 {
1012 qemu_irq irq;
1013 target_phys_addr_t base;
1014 struct jz_state_s *soc;
1015
1016 uint32_t papin[4];
1017 uint32_t padat[4];
1018 uint32_t paim[4];
1019 uint32_t pape[4];
1020 uint32_t pafun[4];
1021 uint32_t pasel[4];
1022 uint32_t padir[4];
1023 uint32_t patrg[4];
1024 uint32_t paflg[4];
1025 };
1026
1027 static void jz4740_gpio_reset(struct jz4740_gpio_s *s)
1028 {
1029 memset(s->papin, 0x0, sizeof(s->papin));
1030 memset(s->padat, 0x0, sizeof(s->padat));
1031 memset(s->paim, 0xffffffff, sizeof(s->paim));
1032 memset(s->pape, 0x0, sizeof(s->pape));
1033 memset(s->pafun, 0x0, sizeof(s->pafun));
1034 memset(s->pasel, 0x0, sizeof(s->pasel));
1035 memset(s->padir, 0x0, sizeof(s->padir));
1036 memset(s->patrg, 0x0, sizeof(s->patrg));
1037 memset(s->paflg, 0x0, sizeof(s->paflg));
1038 }
1039
1040 static uint32_t jz4740_gpio_read(void *opaque, target_phys_addr_t addr)
1041 {
1042 struct jz4740_gpio_s *s = (struct jz4740_gpio_s *) opaque;
1043 uint32_t group;
1044 debug_out(DEBUG_GPIO, "jz4740_gpio_read addr %x\n", addr);
1045
1046 switch (addr)
1047 {
1048 case 0x14:
1049 case 0x114:
1050 case 0x214:
1051 case 0x314:
1052 case 0x18:
1053 case 0x118:
1054 case 0x218:
1055 case 0x318:
1056 case 0x24:
1057 case 0x124:
1058 case 0x224:
1059 case 0x324:
1060 case 0x28:
1061 case 0x128:
1062 case 0x228:
1063 case 0x328:
1064 case 0x34:
1065 case 0x134:
1066 case 0x234:
1067 case 0x334:
1068 case 0x38:
1069 case 0x138:
1070 case 0x238:
1071 case 0x338:
1072 case 0x44:
1073 case 0x144:
1074 case 0x244:
1075 case 0x344:
1076 case 0x48:
1077 case 0x148:
1078 case 0x248:
1079 case 0x348:
1080 case 0x54:
1081 case 0x154:
1082 case 0x254:
1083 case 0x354:
1084 case 0x58:
1085 case 0x158:
1086 case 0x258:
1087 case 0x358:
1088 case 0x64:
1089 case 0x164:
1090 case 0x264:
1091 case 0x364:
1092 case 0x68:
1093 case 0x168:
1094 case 0x268:
1095 case 0x368:
1096 case 0x74:
1097 case 0x174:
1098 case 0x274:
1099 case 0x374:
1100 case 0x78:
1101 case 0x178:
1102 case 0x278:
1103 case 0x378:
1104 case 0x84:
1105 case 0x184:
1106 case 0x284:
1107 case 0x384:
1108 JZ4740_WO_REG(addr);
1109 break;
1110
1111 case 0x0:
1112 case 0x100:
1113 case 0x200:
1114 case 0x300:
1115 group = (addr - 0x0) / 0x100;
1116 if (addr == 0x200)
1117 {
1118 /*GPIO(C) PIN 30 -> NAND FLASH R/B. */
1119 /*FOR NAND FLASH.PIN 30 ----|_____|------ */
1120 s->papin[2] &= 0x40000000;
1121 if (s->papin[2])
1122 s->papin[2] &= ~0x40000000;
1123 else
1124 s->papin[2] |= 0x40000000;
1125 }
1126 return s->papin[group];
1127 case 0x10:
1128 case 0x110:
1129 case 0x210:
1130 case 0x310:
1131 group = (addr - 0x10) / 0x100;
1132 return s->padat[group];
1133 case 0x20:
1134 case 0x120:
1135 case 0x220:
1136 case 0x320:
1137 group = (addr - 0x20) / 0x100;
1138 return s->paim[group];
1139 case 0x30:
1140 case 0x130:
1141 case 0x230:
1142 case 0x330:
1143 group = (addr - 0x30) / 0x100;
1144 return s->pape[group];
1145 case 0x40:
1146 case 0x140:
1147 case 0x240:
1148 case 0x340:
1149 group = (addr - 0x40) / 0x100;
1150 return s->pafun[group];
1151 case 0x50:
1152 case 0x150:
1153 case 0x250:
1154 case 0x350:
1155 group = (addr - 0x50) / 0x100;
1156 return s->pasel[group];
1157 case 0x60:
1158 case 0x160:
1159 case 0x260:
1160 case 0x360:
1161 group = (addr - 0x60) / 0x100;
1162 return s->padir[group];
1163 case 0x70:
1164 case 0x170:
1165 case 0x270:
1166 case 0x370:
1167 group = (addr - 0x70) / 0x100;
1168 return s->patrg[group];
1169 case 0x80:
1170 case 0x180:
1171 case 0x280:
1172 case 0x380:
1173 group = (addr - 0x80) / 0x100;
1174 return s->paflg[group];
1175 default:
1176 cpu_abort(s->soc->env,
1177 "jz4740_gpio_read undefined addr " JZ_FMT_plx " \n", addr);
1178 }
1179 return (0);
1180 }
1181
1182 static void jz4740_gpio_write(void *opaque, target_phys_addr_t addr,
1183 uint32_t value)
1184 {
1185 struct jz4740_gpio_s *s = (struct jz4740_gpio_s *) opaque;
1186 uint32_t group;
1187
1188 debug_out(DEBUG_GPIO, "jz4740_gpio_write addr %x value %x\n", addr, value);
1189
1190 switch (addr)
1191 {
1192 case 0x0:
1193 case 0x100:
1194 case 0x200:
1195 case 0x300:
1196 case 0x10:
1197 case 0x110:
1198 case 0x210:
1199 case 0x310:
1200 case 0x20:
1201 case 0x120:
1202 case 0x220:
1203 case 0x320:
1204 case 0x30:
1205 case 0x130:
1206 case 0x230:
1207 case 0x330:
1208 case 0x40:
1209 case 0x140:
1210 case 0x240:
1211 case 0x340:
1212 case 0x50:
1213 case 0x150:
1214 case 0x250:
1215 case 0x350:
1216 case 0x60:
1217 case 0x160:
1218 case 0x260:
1219 case 0x360:
1220 case 0x70:
1221 case 0x170:
1222 case 0x270:
1223 case 0x370:
1224 case 0x80:
1225 case 0x180:
1226 case 0x280:
1227 case 0x380:
1228 JZ4740_RO_REG(addr);
1229 break;
1230 case 0x14:
1231 case 0x114:
1232 case 0x214:
1233 case 0x314:
1234 group = (addr - 0x14) / 0x100;
1235 s->padat[group] = value;
1236 break;
1237 case 0x18:
1238 case 0x118:
1239 case 0x218:
1240 case 0x318:
1241 group = (addr - 0x18) / 0x100;
1242 s->padat[group] &= ~value;
1243 break;
1244 case 0x24:
1245 case 0x124:
1246 case 0x224:
1247 case 0x324:
1248 group = (addr - 0x24) / 0x100;
1249 s->paim[group] = value;
1250 break;
1251 case 0x28:
1252 case 0x128:
1253 case 0x228:
1254 case 0x328:
1255 group = (addr - 0x28) / 0x100;
1256 s->paim[group] &= ~value;
1257 break;
1258 case 0x34:
1259 case 0x134:
1260 case 0x234:
1261 case 0x334:
1262 group = (addr - 0x34) / 0x100;
1263 s->pape[group] = value;
1264 break;
1265 case 0x38:
1266 case 0x138:
1267 case 0x238:
1268 case 0x338:
1269 group = (addr - 0x38) / 0x100;
1270 s->pape[group] &= ~value;
1271 break;
1272 case 0x44:
1273 case 0x144:
1274 case 0x244:
1275 case 0x344:
1276 group = (addr - 0x44) / 0x100;
1277 s->pafun[group] = value;
1278 break;
1279 case 0x48:
1280 case 0x148:
1281 case 0x248:
1282 case 0x348:
1283 group = (addr - 0x48) / 0x100;
1284 s->pafun[group] &= ~value;
1285 break;
1286 case 0x54:
1287 case 0x154:
1288 case 0x254:
1289 case 0x354:
1290 group = (addr - 0x54) / 0x100;
1291 s->pasel[group] = value;
1292 break;
1293 case 0x58:
1294 case 0x158:
1295 case 0x258:
1296 case 0x358:
1297 group = (addr - 0x58) / 0x100;
1298 s->pasel[group] &= ~value;
1299 break;
1300 case 0x64:
1301 case 0x164:
1302 case 0x264:
1303 case 0x364:
1304 group = (addr - 0x64) / 0x100;
1305 s->padir[group] = value;
1306 break;
1307 case 0x68:
1308 case 0x168:
1309 case 0x268:
1310 case 0x368:
1311 group = (addr - 0x68) / 0x100;
1312 s->padir[group] &= ~value;
1313 break;
1314 case 0x74:
1315 case 0x174:
1316 case 0x274:
1317 case 0x374:
1318 group = (addr - 0x74) / 0x100;
1319 s->patrg[group] = value;
1320 break;
1321 case 0x78:
1322 case 0x178:
1323 case 0x278:
1324 case 0x378:
1325 group = (addr - 0x78) / 0x100;
1326 s->patrg[group] &= ~value;
1327 break;
1328 case 0x84:
1329 case 0x184:
1330 case 0x284:
1331 case 0x384:
1332 group = (addr - 0x74) / 0x100;
1333 s->paflg[group] &= ~value;
1334 break;
1335 default:
1336 cpu_abort(s->soc->env,
1337 "jz4740_gpio_write undefined addr " JZ_FMT_plx
1338 " value %x \n", addr, value);
1339
1340 }
1341
1342
1343 }
1344
1345
1346 static CPUReadMemoryFunc *jz4740_gpio_readfn[] = {
1347 jz4740_badwidth_read32,
1348 jz4740_badwidth_read32,
1349 jz4740_gpio_read,
1350 };
1351
1352 static CPUWriteMemoryFunc *jz4740_gpio_writefn[] = {
1353 jz4740_badwidth_write32,
1354 jz4740_badwidth_write32,
1355 jz4740_gpio_write,
1356 };
1357
1358 static struct jz4740_gpio_s *jz4740_gpio_init(struct jz_state_s *soc,
1359 qemu_irq irq)
1360 {
1361 int iomemtype;
1362 struct jz4740_gpio_s *s = (struct jz4740_gpio_s *) qemu_mallocz(sizeof(*s));
1363 s->base = JZ4740_PHYS_BASE(JZ4740_GPIO_BASE);
1364 s->soc = soc;
1365 s->irq = irq;
1366
1367 jz4740_gpio_reset(s);
1368
1369 iomemtype =
1370 cpu_register_io_memory(0, jz4740_gpio_readfn, jz4740_gpio_writefn, s);
1371 cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
1372 return s;
1373
1374 }
1375
1376 struct jz4740_rtc_s
1377 {
1378 qemu_irq irq;
1379 target_phys_addr_t base;
1380 struct jz_state_s *soc;
1381
1382 QEMUTimer *hz_tm;
1383 //struct tm tm;
1384 //int sec_offset;
1385 int64_t next;
1386
1387 uint32_t rtccr;
1388 uint32_t rtcsr;
1389 uint32_t rtcsar;
1390 uint32_t rtcgr;
1391
1392 uint32_t hcr;
1393 uint32_t hwfcr;
1394 uint32_t hrcr;
1395 uint32_t hwcr;
1396 uint32_t hwrsr;
1397 uint32_t hspr;
1398
1399 };
1400
1401
1402 static void jz4740_rtc_update_interrupt(struct jz4740_rtc_s *s)
1403 {
1404 /* if (((s->rtcsr & 0x40) && (s->rtcsr & 0x20))
1405 || ((s->rtcsr & 0x10) && (s->rtcsr & 0x8)))
1406 qemu_set_irq(s->irq, 1);*/
1407 //else
1408 // qemu_set_irq(s->irq, 0);
1409 }
1410
1411 static inline void jz4740_rtc_start(struct jz4740_rtc_s *s)
1412 {
1413 s->next = +qemu_get_clock(rt_clock);
1414 qemu_mod_timer(s->hz_tm, s->next);
1415 }
1416
1417 static inline void jz4740_rtc_stop(struct jz4740_rtc_s *s)
1418 {
1419 qemu_del_timer(s->hz_tm);
1420 s->next = -qemu_get_clock(rt_clock);
1421 if (s->next < 1)
1422 s->next = 1;
1423 }
1424
1425 static void jz4740_rtc_hz(void *opaque)
1426 {
1427 struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) opaque;
1428
1429 s->next += 1000;
1430 qemu_mod_timer(s->hz_tm, s->next);
1431 if (s->rtccr & 0x1)
1432 {
1433 s->rtcsr++;
1434 s->rtccr |= 0x40;
1435 if (s->rtcsr & 0x4)
1436 {
1437 if (s->rtcsr == s->rtcsar)
1438 s->rtccr |= 0x10;
1439 }
1440 jz4740_rtc_update_interrupt(s);
1441 }
1442 }
1443
1444 static void jz4740_rtc_reset(struct jz4740_rtc_s *s)
1445 {
1446 s->rtccr = 0x81;
1447
1448 s->next = 1000;
1449
1450 /*Maybe rtcsr need to be saved to file */
1451 s->rtcsr = 0;
1452 //s->sec_offset = 0;
1453 //qemu_get_timedate(&s->tm, s->sec_offset);
1454 jz4740_rtc_start(s);
1455
1456 }
1457
1458 static uint32_t jz4740_rtc_read(void *opaque, target_phys_addr_t addr)
1459 {
1460 struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) opaque;
1461
1462 debug_out(DEBUG_RTC, "jz4740_rtc_read addr %x\n", addr);
1463 switch (addr)
1464 {
1465 case 0x0:
1466 return s->rtccr | 0x80;
1467 case 0x4:
1468 return s->rtcsr;
1469 case 0x8:
1470 return s->rtcsar;
1471 case 0xc:
1472 return s->rtcgr;
1473 case 0x20:
1474 return s->hcr;
1475 case 0x24:
1476 return s->hwfcr;
1477 case 0x28:
1478 return s->hrcr;
1479 case 0x2c:
1480 return s->hwcr;
1481 case 0x30:
1482 return s->hwrsr;
1483 case 0x34:
1484 return s->hspr;
1485 default:
1486 cpu_abort(s->soc->env,
1487 "jz4740_rtc_read undefined addr " JZ_FMT_plx "\n", addr);
1488 }
1489
1490 return (0);
1491 }
1492
1493 static void jz4740_rtc_write(void *opaque, target_phys_addr_t addr,
1494 uint32_t value)
1495 {
1496 struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) opaque;
1497
1498 debug_out(DEBUG_RTC, "jz4740_rtc_write addr %x value %x\n", addr, value);
1499
1500 switch (addr)
1501 {
1502 case 0x0:
1503 s->rtccr = value & 0x2d;
1504 if (!value & 0x40)
1505 s->rtccr &= ~0x40;
1506 if (!value & 0x10)
1507 s->rtccr &= ~0x10;
1508 if (s->rtccr & 0x1)
1509 {
1510 //jz4740_rtc_start(s);
1511 jz4740_rtc_update_interrupt(s);
1512 }
1513 else
1514 jz4740_rtc_stop(s);
1515 break;
1516 case 0x4:
1517 s->rtcsr = value;
1518 //s->sec_offset = qemu_timedate_diff(&s->tm);
1519 break;
1520 case 0x8:
1521 s->rtcsar = value;
1522 break;
1523 case 0xc:
1524 s->rtcgr = value & 0x13ffffff;
1525 break;
1526 case 0x20:
1527 s->hcr = value & 0x1;
1528 break;
1529 case 0x24:
1530 s->hwfcr = value & 0xffe0;
1531 break;
1532 case 0x28:
1533 s->hrcr = value & 0xfe0;
1534 break;
1535 case 0x2c:
1536 s->hwcr = value & 0x1;
1537 break;
1538 case 0x30:
1539 s->hwrsr = value & 0x33;
1540 break;
1541 case 0x34:
1542 s->hspr = value;
1543 break;
1544 default:
1545 cpu_abort(s->soc->env,
1546 "jz4740_rtc_write undefined addr " JZ_FMT_plx
1547 " value %x \n", addr, value);
1548 }
1549
1550 }
1551
1552 static CPUReadMemoryFunc *jz4740_rtc_readfn[] = {
1553 jz4740_badwidth_read32,
1554 jz4740_badwidth_read32,
1555 jz4740_rtc_read,
1556 };
1557
1558 static CPUWriteMemoryFunc *jz4740_rtc_writefn[] = {
1559 jz4740_badwidth_write32,
1560 jz4740_badwidth_write32,
1561 jz4740_rtc_write,
1562 };
1563
1564 static struct jz4740_rtc_s *jz4740_rtc_init(struct jz_state_s *soc,
1565 qemu_irq irq)
1566 {
1567 int iomemtype;
1568 struct jz4740_rtc_s *s = (struct jz4740_rtc_s *) qemu_mallocz(sizeof(*s));
1569 s->base = JZ4740_PHYS_BASE(JZ4740_RTC_BASE);
1570 s->soc = soc;
1571 s->irq = irq;
1572
1573 s->hz_tm = qemu_new_timer(rt_clock, jz4740_rtc_hz, s);
1574
1575 jz4740_rtc_reset(s);
1576
1577 iomemtype =
1578 cpu_register_io_memory(0, jz4740_rtc_readfn, jz4740_rtc_writefn, s);
1579 cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
1580 return s;
1581 }
1582
1583 struct jz4740_tcu_s
1584 {
1585 qemu_irq tcu_irq0;
1586 qemu_irq tcu_irq1;
1587 qemu_irq tcu_irq2;
1588
1589 target_phys_addr_t base;
1590 struct jz_state_s *soc;
1591
1592
1593 QEMUTimer *half_timer[8];
1594 QEMUTimer *full_timer[8];
1595 int64_t time[8];
1596
1597 uint32_t tsr;
1598 uint32_t ter;
1599 uint32_t tfr;
1600 uint32_t tmr;
1601
1602 uint32_t tdfr[8];
1603 uint32_t tdhr[8];
1604 uint32_t tcnt[8];
1605 uint32_t tcsr[8];
1606
1607 uint32_t prescale[8];
1608 uint32_t freq[8];
1609 };
1610
1611 static void jz4740_tcu_update_interrupt(struct jz4740_tcu_s *s)
1612 {
1613 //printf("s->tfr %x s->tmr %x \n",s->tfr,s->tmr);
1614 if (((s->tfr & 0x1) & (~(s->tmr & 0x1)))
1615 || ((s->tfr & 0x10000) & (~(s->tmr & 0x10000))))
1616 {
1617 qemu_set_irq(s->tcu_irq0, 1);
1618 }
1619 else
1620 qemu_set_irq(s->tcu_irq0, 0);
1621
1622 if (((s->tfr & 0x2) & (~(s->tmr & 0x2)))
1623 || ((s->tfr & 0x20000) & (~(s->tmr & 0x20000))))
1624 {
1625 qemu_set_irq(s->tcu_irq1, 1);
1626 }
1627 else
1628 qemu_set_irq(s->tcu_irq1, 0);
1629
1630 if (((s->tfr & 0xfc) & (~(s->tmr & 0xfc)))
1631 || ((s->tfr & 0xfc0000) & (~(s->tmr & 0xfc0000))))
1632 {
1633 qemu_set_irq(s->tcu_irq2, 1);
1634 }
1635 else
1636 qemu_set_irq(s->tcu_irq2, 0);
1637
1638 }
1639
1640 #undef TCU_INDEX
1641 #define TCU_INDEX 0
1642 #include "mips_jz_glue.h"
1643 #define TCU_INDEX 1
1644 #include "mips_jz_glue.h"
1645 #define TCU_INDEX 2
1646 #include "mips_jz_glue.h"
1647 #define TCU_INDEX 3
1648 #include "mips_jz_glue.h"
1649 #define TCU_INDEX 4
1650 #include "mips_jz_glue.h"
1651 #define TCU_INDEX 5
1652 #include "mips_jz_glue.h"
1653 #define TCU_INDEX 6
1654 #include "mips_jz_glue.h"
1655 #define TCU_INDEX 7
1656 #include "mips_jz_glue.h"
1657 #undef TCU_INDEX
1658
1659 #define jz4740_tcu_start(s) do { \
1660 jz4740_tcu_start_half0(s); \
1661 jz4740_tcu_start_full0(s); \
1662 jz4740_tcu_start_half1(s); \
1663 jz4740_tcu_start_full1(s); \
1664 jz4740_tcu_start_half2(s); \
1665 jz4740_tcu_start_full2(s); \
1666 jz4740_tcu_start_half3(s); \
1667 jz4740_tcu_start_full3(s); \
1668 jz4740_tcu_start_half4(s); \
1669 jz4740_tcu_start_full4(s); \
1670 jz4740_tcu_start_half5(s); \
1671 jz4740_tcu_start_full5(s); \
1672 jz4740_tcu_start_half6(s); \
1673 jz4740_tcu_start_full6(s); \
1674 jz4740_tcu_start_half7(s); \
1675 jz4740_tcu_start_full7(s); \
1676 }while (0)
1677
1678 static void jz4740_tcu_if_reset(struct jz4740_tcu_s *s)
1679 {
1680 int i;
1681
1682 s->tsr = 0x0;
1683 s->ter = 0x0;
1684 s->tfr = 0x0;
1685 s->tmr = 0x0;
1686 for (i = 0; i < 8; i++)
1687 {
1688 s->tdfr[i] = 0xffff;
1689 s->tdhr[i] = 0x8000;
1690 s->tcnt[i] = 0x0;
1691 s->tcsr[i] = 0x0;
1692 s->half_timer[i] = NULL;
1693 s->full_timer[i] = NULL;
1694 }
1695 }
1696
1697 static void jz4740_tcu_if_write8(void *opaque, target_phys_addr_t addr,
1698 uint32_t value)
1699 {
1700 struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1701
1702 debug_out(DEBUG_TCU, "jz4740_tcu_if_write8 addr %x value %x\n", addr,
1703 value);
1704
1705 switch (addr)
1706 {
1707 case 0x14:
1708 s->ter |= (value & 0xff);
1709 jz4740_tcu_start(s);
1710 break;
1711 case 0x18:
1712 s->ter &= ~(value & 0xff);
1713 jz4740_tcu_start(s);
1714 break;
1715 default:
1716 cpu_abort(s->soc->env,
1717 "jz4740_tcu_if_write8 undefined addr " JZ_FMT_plx
1718 " value %x \n", addr, value);
1719 }
1720
1721 }
1722
1723 static void jz4740_tcu_if_write32(void *opaque, target_phys_addr_t addr,
1724 uint32_t value)
1725 {
1726 struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1727
1728 debug_out(DEBUG_TCU, "jz4740_tcu_if_write32 addr %x value %x\n", addr,
1729 value);
1730
1731 switch (addr)
1732 {
1733 case 0x2c:
1734 s->tsr |= (value & 0x100ff);
1735 jz4740_tcu_start(s);
1736 break;
1737 case 0x3c:
1738 s->tsr &= ~(value & 0x100ff);
1739 jz4740_tcu_start(s);
1740 break;
1741 case 0x24:
1742 s->tfr |= (value & 0xff00ff);
1743 break;
1744 case 0x28:
1745 s->tfr &= ~(value & 0xff00ff);
1746 break;
1747 case 0x34:
1748 s->tmr |= (value & 0xff00ff);
1749 jz4740_tcu_update_interrupt(s);
1750 break;
1751 case 0x38:
1752 s->tmr &= ~(value & 0xff00ff);
1753 jz4740_tcu_update_interrupt(s);
1754 break;
1755 default:
1756 cpu_abort(s->soc->env,
1757 "jz4740_tcu_if_write32 undefined addr " JZ_FMT_plx
1758 " value %x \n", addr, value);
1759
1760 }
1761 }
1762
1763 static uint32_t jz4740_tcu_if_read8(void *opaque, target_phys_addr_t addr)
1764 {
1765 struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1766
1767 debug_out(DEBUG_TCU, "jz4740_tcu_if_read8 addr %x\n", addr);
1768
1769 switch (addr)
1770 {
1771 case 0x10:
1772 return s->ter;
1773 default:
1774 cpu_abort(s->soc->env,
1775 "jz4740_tcu_if_read8 undefined addr " JZ_FMT_plx "\n", addr);
1776 }
1777 return (0);
1778 }
1779
1780 static uint32_t jz4740_tcu_if_read32(void *opaque, target_phys_addr_t addr)
1781 {
1782 struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque;
1783
1784 debug_out(DEBUG_TCU, "jz4740_tcu_if_read32 addr %x\n", addr);
1785
1786 switch (addr)
1787 {
1788 case 0x1c:
1789 return s->tsr;
1790 case 0x20:
1791 return s->tfr;
1792 case 0x30:
1793 return s->tmr;
1794 default:
1795 cpu_abort(s->soc->env,
1796 "jz4740_tcu_if_read32 undefined addr " JZ_FMT_plx "\n", addr);
1797
1798 }
1799 return (0);
1800
1801 }
1802
1803 static CPUReadMemoryFunc *jz4740_tcu_if_readfn[] = {
1804 jz4740_tcu_if_read8,
1805 jz4740_badwidth_read32,
1806 jz4740_tcu_if_read32,
1807 };
1808
1809 static CPUWriteMemoryFunc *jz4740_tcu_if_writefn[] = {
1810 jz4740_tcu_if_write8,
1811 jz4740_badwidth_write32,
1812 jz4740_tcu_if_write32,
1813 };
1814
1815 static struct jz4740_tcu_s *jz4740_tcu_if_init(struct jz_state_s *soc,
1816 qemu_irq tcu_irq0,
1817 qemu_irq tcu_irq1,
1818 qemu_irq tcu_irq2)
1819 {
1820 int iomemtype;
1821 //int i;
1822
1823 struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) qemu_mallocz(sizeof(*s));
1824 s->base = JZ4740_PHYS_BASE(JZ4740_TCU_BASE);
1825 s->soc = soc;
1826 s->tcu_irq0 = tcu_irq0;
1827 s->tcu_irq1 = tcu_irq1;
1828 s->tcu_irq2 = tcu_irq2;
1829
1830 jz4740_tcu_if_reset(s);
1831
1832 iomemtype =
1833 cpu_register_io_memory(0, jz4740_tcu_if_readfn, jz4740_tcu_if_writefn,
1834 s);
1835 cpu_register_physical_memory(s->base, 0x00000040, iomemtype);
1836 return s;
1837
1838 }
1839
1840 static void jz4740_tcu_init(struct jz_state_s *soc,
1841 struct jz4740_tcu_s *s, int timer_index)
1842 {
1843 switch (timer_index)
1844 {
1845 case 0x0:
1846 jz4740_tcu_init0(soc, s);
1847 break;
1848 case 0x1:
1849 jz4740_tcu_init1(soc, s);
1850 break;
1851 case 0x2:
1852 jz4740_tcu_init2(soc, s);
1853 break;
1854 case 0x3:
1855 jz4740_tcu_init3(soc, s);
1856 break;
1857 case 0x4:
1858 jz4740_tcu_init4(soc, s);
1859 break;
1860 case 0x5:
1861 jz4740_tcu_init5(soc, s);
1862 break;
1863 case 0x6:
1864 jz4740_tcu_init6(soc, s);
1865 break;
1866 case 0x7:
1867 jz4740_tcu_init7(soc, s);
1868 break;
1869 default:
1870 cpu_abort(s->soc->env,
1871 "jz4740_tcu_init undefined timer %x \n", timer_index);
1872 }
1873 }
1874
1875 typedef void (*jz4740_lcd_fn_t) (uint8_t * d, const uint8_t * s, int width,
1876 const uint16_t * pal);
1877 struct jz_fb_descriptor
1878 {
1879 uint32_t fdadr; /* Frame descriptor address register */
1880 uint32_t fsadr; /* Frame source address register */
1881 uint32_t fidr; /* Frame ID register */
1882 uint32_t ldcmd; /* Command register */
1883 };
1884
1885 struct jz4740_lcdc_s
1886 {
1887 qemu_irq irq;
1888
1889 target_phys_addr_t base;
1890 struct jz_state_s *soc;
1891
1892 DisplayState *state;
1893 QEMUConsole *console;
1894 jz4740_lcd_fn_t *line_fn_tab;
1895 jz4740_lcd_fn_t line_fn;
1896
1897
1898 uint32_t lcdcfg;
1899 uint32_t lcdvsync;
1900 uint32_t lcdhsync;
1901 uint32_t lcdvat;
1902 uint32_t lcddah;
1903 uint32_t lcddav;
1904 uint32_t lcdps;
1905 uint32_t lcdcls;
1906 uint32_t lcdspl;
1907 uint32_t lcdrev;
1908 uint32_t lcdctrl;
1909 uint32_t lcdstate;
1910 uint32_t lcdiid;
1911 uint32_t lcdda0;
1912 uint32_t lcdsa0;
1913 uint32_t lcdfid0;
1914 uint32_t lcdcmd0;
1915 uint32_t lcdda1;
1916 uint32_t lcdsa1;
1917 uint32_t lcdfid1;
1918 uint32_t lcdcmd1;
1919
1920 uint32_t ena;
1921 uint32_t dis;
1922 uint32_t width;
1923 uint32_t height;
1924 uint32_t bpp; /*bit per second */
1925 uint16_t palette[256];
1926 uint32_t invalidate;
1927
1928 };
1929
1930 /*bit per pixel*/
1931 static const int jz4740_lcd_bpp[0x6] = {
1932 1, 2, 4, 8, 16, 32 /*4740 uses 32 bit for 24bpp */
1933 };
1934
1935 static void jz4740_lcdc_reset(struct jz4740_lcdc_s *s)
1936 {
1937
1938 }
1939
1940 static uint32_t jz4740_lcdc_read(void *opaque, target_phys_addr_t addr)
1941 {
1942 struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
1943
1944 debug_out(DEBUG_LCDC, "jz4740_lcdc_read addr %x \n", addr);
1945 switch (addr)
1946 {
1947 case 0x0:
1948 return s->lcdcfg;
1949 case 0x4:
1950 return s->lcdvsync;
1951 case 0x8:
1952 return s->lcdhsync;
1953 case 0xc:
1954 return s->lcdvat;
1955 case 0x10:
1956 return s->lcddah;
1957 case 0x14:
1958 return s->lcddav;
1959 case 0x18:
1960 return s->lcdps;
1961 case 0x1c:
1962 return s->lcdcls;
1963 case 0x20:
1964 return s->lcdspl;
1965 case 0x24:
1966 return s->lcdrev;
1967 case 0x30:
1968 return s->lcdctrl;
1969 case 0x34:
1970 return s->lcdstate;
1971 case 0x38:
1972 return s->lcdiid;
1973 case 0x40:
1974 return s->lcdda0;
1975 case 0x44:
1976 return s->lcdsa0;
1977 case 0x48:
1978 return s->lcdfid0;
1979 case 0x4c:
1980 return s->lcdcmd0;
1981 case 0x50:
1982 return s->lcdda1;
1983 case 0x54:
1984 return s->lcdsa1;
1985 case 0x58:
1986 return s->lcdfid1;
1987 case 0x5c:
1988 return s->lcdcmd1;
1989 default:
1990 cpu_abort(s->soc->env,
1991 "jz4740_lcdc_read undefined addr " JZ_FMT_plx " \n", addr);
1992
1993 }
1994
1995 }
1996
1997 static void jz4740_lcdc_write(void *opaque, target_phys_addr_t addr,
1998 uint32_t value)
1999 {
2000 struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
2001
2002 debug_out(DEBUG_LCDC, "jz4740_lcdc_write addr %x value %x\n", addr, value);
2003
2004 switch (addr)
2005 {
2006 case 0x44:
2007 case 0x48:
2008 case 0x4c:
2009 JZ4740_RO_REG(addr);
2010 break;
2011 case 0x0:
2012 s->lcdcfg = value & 0x80ffffbf;
2013 break;
2014 case 0x4:
2015 s->lcdvsync = value & 0x7ff07ff;
2016 break;
2017 case 0x8:
2018 s->lcdhsync = value & 0x7ff07ff;
2019 break;
2020 case 0xc:
2021 s->lcdvat = value & 0x7ff07ff;
2022 break;
2023 case 0x10:
2024 s->lcddah = value & 0x7ff07ff;
2025 s->width = (value & 0x7ff) - ((value >> 16) & 0x7ff);
2026 break;
2027 case 0x14:
2028 s->height = (value & 0x7ff) - ((value >> 16) & 0x7ff);
2029 s->lcddav = value & 0x7ff07ff;
2030 break;
2031 case 0x18:
2032 s->lcdps = value & 0x7ff07ff;
2033 break;
2034 case 0x1c:
2035 s->lcdcls = value & 0x7ff07ff;
2036 break;
2037 case 0x20:
2038 s->lcdspl = value & 0x7ff07ff;
2039 break;
2040 case 0x24:
2041 s->lcdrev = value & 0x7ff0000;
2042 break;
2043 case 0x30:
2044 s->lcdctrl = value & 0x3fff3fff;
2045 s->ena = (value & 0x8) >> 3;
2046 s->dis = (value & 0x10) >> 4;
2047 s->bpp = jz4740_lcd_bpp[value & 0x7];
2048 if ((s->bpp == 1))
2049 {
2050 fprintf(stderr, "bpp =1 is not supported\n");
2051 exit(-1);
2052 }
2053 s->line_fn = s->line_fn_tab[value & 0x7];
2054 break;
2055 case 0x34:
2056 s->lcdstate = value & 0xbf;
2057 break;
2058 case 0x38:
2059 s->lcdiid = value;
2060 break;
2061 case 0x40:
2062 s->lcdda0 = value;
2063 break;
2064 case 0x50:
2065 s->lcdda1 = value;
2066 break;
2067 default:
2068 cpu_abort(s->soc->env,
2069 "jz4740_lcdc_write undefined addr " JZ_FMT_plx " value %x \n",
2070 addr, value);
2071 }
2072
2073 }
2074
2075 static CPUReadMemoryFunc *jz4740_lcdc_readfn[] = {
2076 jz4740_badwidth_read32,
2077 jz4740_badwidth_read32,
2078 jz4740_lcdc_read,
2079 };
2080
2081 static CPUWriteMemoryFunc *jz4740_lcdc_writefn[] = {
2082 jz4740_badwidth_write32,
2083 jz4740_badwidth_write32,
2084 jz4740_lcdc_write,
2085 };
2086
2087 #include "pixel_ops.h"
2088 #define JZ4740_LCD_PANEL
2089 #define DEPTH 8
2090 #include "mips_jz_glue.h"
2091 #define DEPTH 15
2092 #include "mips_jz_glue.h"
2093 #define DEPTH 16
2094 #include "mips_jz_glue.h"
2095 #define DEPTH 24
2096 #include "mips_jz_glue.h"
2097 #define DEPTH 32
2098 #include "mips_jz_glue.h"
2099 #undef JZ4740_LCD_PANEL
2100
2101 static void *jz4740_lcd_get_buffer(struct jz4740_lcdc_s *s,
2102 target_phys_addr_t addr)
2103 {
2104 uint32_t pd;
2105
2106 pd = cpu_get_physical_page_desc(addr);
2107 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2108 /* TODO */
2109 cpu_abort(cpu_single_env, "%s: framebuffer outside RAM!\n",
2110 __FUNCTION__);
2111 else
2112 return phys_ram_base +
2113 (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
2114 }
2115
2116 static void jz4740_lcd_update_display(void *opaque)
2117 {
2118 struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
2119
2120 uint8_t *src, *dest;
2121 struct jz_fb_descriptor *fb_des;
2122
2123 int step, linesize;
2124 int y;
2125
2126
2127 if (!s->ena)
2128 return;
2129 if (s->dis)
2130 return;
2131
2132 if (!s->lcdda0)
2133 return;
2134
2135 fb_des = (struct jz_fb_descriptor *) jz4740_lcd_get_buffer(s, s->lcdda0);
2136 s->lcdda0 = fb_des->fdadr;
2137 s->lcdsa0 = fb_des->fsadr;
2138 s->lcdfid0 = fb_des->fidr;
2139 s->lcdcmd0 = fb_des->ldcmd;
2140
2141 src = (uint8_t *) jz4740_lcd_get_buffer(s, fb_des->fsadr);
2142 if (s->lcdcmd0 & (0x1 << 28))
2143 {
2144 /*palette */
2145 memcpy(s->palette, src, sizeof(s->palette));
2146 return;
2147 }
2148
2149 /*frame buffer */
2150
2151 if (s->width != ds_get_width(s->state) ||
2152 s->height != ds_get_height(s->state))
2153 {
2154 qemu_console_resize(s->console, s->width, s->height);
2155 s->invalidate = 1;
2156 }
2157
2158 step = (s->width * s->bpp) >> 3;
2159 dest = ds_get_data(s->state);
2160 linesize = ds_get_linesize(s->state);
2161
2162 //printf("s->width %d s->height %d s->bpp %d linesize %d \n",s->width,s->height ,s->bpp,linesize);
2163
2164 for (y = 0; y < s->height; y++)
2165 {
2166 s->line_fn(dest, src, s->width, s->palette);
2167 //memcpy(dest,src,step);
2168 src += step;
2169 dest += linesize;
2170 }
2171
2172
2173 dpy_update(s->state, 0, 0, s->width, s->height);
2174 s->lcdstate |= 0x20;
2175 if ((s->lcdcmd0 & 0x40000000) && (!(s->lcdctrl & 0x2000)))
2176 qemu_set_irq(s->irq, 1);
2177 }
2178
2179 static inline void jz4740_lcd_invalidate_display(void *opaque)
2180 {
2181 struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) opaque;
2182 s->invalidate = 1;
2183 }
2184
2185 static struct jz4740_lcdc_s *jz4740_lcdc_init(struct jz_state_s *soc,
2186 qemu_irq irq, DisplayState * ds)
2187 {
2188 int iomemtype;
2189
2190 struct jz4740_lcdc_s *s = (struct jz4740_lcdc_s *) qemu_mallocz(sizeof(*s));
2191 s->base = JZ4740_PHYS_BASE(JZ4740_LCD_BASE);
2192 s->soc = soc;
2193 s->irq = irq;
2194 s->state = ds;
2195
2196
2197 jz4740_lcdc_reset(s);
2198
2199 iomemtype =
2200 cpu_register_io_memory(0, jz4740_lcdc_readfn, jz4740_lcdc_writefn, s);
2201 cpu_register_physical_memory(s->base, 0x10000, iomemtype);
2202
2203 s->console = graphic_console_init(s->state, jz4740_lcd_update_display,
2204 jz4740_lcd_invalidate_display,
2205 NULL, NULL, s);
2206 switch (ds_get_bits_per_pixel(s->state))
2207 {
2208 case 0x0:
2209 s->line_fn_tab = qemu_mallocz(sizeof(jz4740_lcd_fn_t) * 6);
2210 break;
2211 case 8:
2212 s->line_fn_tab = jz4740_lcd_draw_fn_8;
2213 break;
2214 case 15:
2215 s->line_fn_tab = jz4740_lcd_draw_fn_15;
2216 break;
2217 case 16:
2218 s->line_fn_tab = jz4740_lcd_draw_fn_16;
2219 break;
2220 case 24:
2221 s->line_fn_tab = jz4740_lcd_draw_fn_24;
2222 break;
2223 case 32:
2224 s->line_fn_tab = jz4740_lcd_draw_fn_32;
2225 break;
2226 default:
2227 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
2228 exit(1);
2229 }
2230
2231 return s;
2232
2233 }
2234
2235 #define JZ4740_DMA_NUM 6
2236 struct jz4740_dma_s
2237 {
2238 qemu_irq irq;
2239
2240 target_phys_addr_t base;
2241 struct jz_state_s *soc;
2242
2243 uint32_t dmac;
2244 uint32_t dirqp;
2245 uint32_t ddr;
2246 uint32_t ddrs;
2247
2248 uint32_t dsa[JZ4740_DMA_NUM];
2249 uint32_t dta[JZ4740_DMA_NUM];
2250 uint32_t dtc[JZ4740_DMA_NUM];
2251 uint32_t drs[JZ4740_DMA_NUM];
2252 uint32_t dcs[JZ4740_DMA_NUM];
2253 uint32_t dcm[JZ4740_DMA_NUM];
2254 uint32_t dda[JZ4740_DMA_NUM];
2255
2256 };
2257
2258 struct jz4740_desc_s
2259 {
2260 uint32_t dcmd; /* DCMD value for the current transfer */
2261 uint32_t dsadr; /* DSAR value for the current transfer */
2262 uint32_t dtadr; /* DTAR value for the current transfer */
2263 uint32_t ddadr; /* Points to the next descriptor + transfer count */
2264 };
2265
2266 static inline void jz4740_dma_transfer(struct jz4740_dma_s *s,
2267 target_phys_addr_t src,
2268 target_phys_addr_t dest, uint32_t len)
2269 {
2270 uint32_t pd_src, pd_dest;
2271 uint8_t *sr, *de;
2272
2273 pd_src = cpu_get_physical_page_desc(src);
2274 if ((pd_src & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2275 /* TODO */
2276 cpu_abort(cpu_single_env, "%s: DMA source address %x outside RAM!\n",
2277 __FUNCTION__, src);
2278 else
2279 sr = phys_ram_base +
2280 (pd_src & TARGET_PAGE_MASK) + (src & ~TARGET_PAGE_MASK);
2281
2282 pd_dest = cpu_get_physical_page_desc(dest);
2283 if ((pd_dest & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2284 /* TODO */
2285 cpu_abort(cpu_single_env,
2286 "%s: DMA destination address %x outside RAM!\n",
2287 __FUNCTION__, dest);
2288 else
2289 de = phys_ram_base +
2290 (pd_dest & TARGET_PAGE_MASK) + (dest & ~TARGET_PAGE_MASK);
2291
2292 memcpy(de, sr, len);
2293 }
2294
2295 static inline uint32_t jz4740_dma_unit_size(struct jz4740_dma_s *s,
2296 uint32_t cmd)
2297 {
2298 switch ((cmd & 0x700) >> 8)
2299 {
2300 case 0x0:
2301 return 4;
2302 case 0x1:
2303 return 1;
2304 case 0x2:
2305 return 2;
2306 case 0x3:
2307 return 16;
2308 case 0x4:
2309 return 32;
2310 }
2311 return (0);
2312 }
2313
2314
2315 /*No-descriptor transfer*/
2316 static inline void jz4740_dma_ndrun(struct jz4740_dma_s *s, int channel)
2317 {
2318 uint32_t len;
2319
2320 len = jz4740_dma_unit_size(s, s->dcs[channel]) * s->dtc[channel];
2321
2322 jz4740_dma_transfer(s, s->dsa[channel], s->dta[channel], len);
2323
2324 /*finish dma transfer */
2325 s->dtc[channel] = 0;
2326 /*set DIR QP */
2327 s->dirqp |= 1 << channel;
2328
2329 /*some cleanup work */
2330 /*clean AR TT GLOBAL AR */
2331 s->dcs[channel] &= 0xffffffe7;
2332 s->dmac &= 0xfffffffb;
2333
2334 if (s->dcm[channel] & 0x2)
2335 qemu_set_irq(s->irq, 1);
2336 }
2337
2338 /*descriptor transfer */
2339 static inline void jz4740_dma_drun(struct jz4740_dma_s *s, int channel)
2340 {
2341 struct jz4740_desc_s *desc;
2342 target_phys_addr_t desc_phy;
2343 uint32_t pd;
2344
2345 desc_phy = s->dda[channel];
2346 if (desc_phy & 0xf)
2347 cpu_abort(s->soc->env,
2348 "jz4740_dma_drun descriptor address " JZ_FMT_plx
2349 " must be 4 bytes aligned \n", desc_phy);
2350
2351 pd = cpu_get_physical_page_desc(desc_phy);
2352 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2353 cpu_abort(cpu_single_env,
2354 "%s: DMA descriptor address " JZ_FMT_plx " outside RAM!\n",
2355 __FUNCTION__, desc_phy);
2356 else
2357 desc = (struct jz4740_desc_s *) (phys_ram_base +
2358 (pd & TARGET_PAGE_MASK) +
2359 (desc_phy & ~TARGET_PAGE_MASK));
2360
2361 if (!desc)
2362 cpu_abort(cpu_single_env,
2363 "%s: DMA descriptor " JZ_FMT_plx " is NULL!\n", __FUNCTION__,
2364 (uint32_t) desc);
2365
2366 while (1)
2367 {
2368 if ((desc->dcmd & 0x8) && (!(desc->dcmd & 0x10)))
2369 {
2370 /*Stop DMA and set DCSN.INV=1 */
2371 s->dcs[channel] |= 1 << 6;
2372 return;
2373 }
2374 jz4740_dma_transfer(s, desc->dtadr, desc->dsadr,
2375 (desc->ddadr & 0xffffff) *
2376 jz4740_dma_unit_size(s, desc->dcmd));
2377
2378 if ((desc->dcmd) & (1 << 3))
2379 /*clear v */
2380 desc->dcmd &= ~(1 << 4);
2381 if (desc->dcmd & 0x1)
2382 /*set DCSN.CT=1 */
2383 s->dcs[channel] |= 0x2;
2384 else
2385 /*set DCSN.TT=1 */
2386 s->dcs[channel] |= 0x8;
2387
2388 if (desc->dcmd & 0x2)
2389 qemu_set_irq(s->irq, 1);
2390
2391 if ((desc->dcmd) & 0x1)
2392 {
2393 /*fetch next descriptor */
2394 desc_phy = s->dda[channel] & 0xfffff000;
2395 desc_phy += (desc->dtadr & 0xff000000) >> 24;
2396 pd = cpu_get_physical_page_desc(desc_phy);
2397 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
2398 cpu_abort(cpu_single_env,
2399 "%s: DMA descriptor address %x outside RAM!\n",
2400 __FUNCTION__, desc_phy);
2401 else
2402 desc = (struct jz4740_desc_s *) (phys_ram_base +
2403 (pd & TARGET_PAGE_MASK)
2404 +
2405 (desc_phy &
2406 ~TARGET_PAGE_MASK));
2407 if (!desc)
2408 cpu_abort(cpu_single_env,
2409 "%s: DMA descriptor %x is NULL!\n",
2410 __FUNCTION__, (uint32_t) desc);
2411 }
2412 else
2413 break;
2414 }
2415 }
2416
2417 static void jz4740_dma_en_channel(struct jz4740_dma_s *s, int channel)
2418 {
2419 if (s->dmac & 0x1)
2420 {
2421 if (s->dcs[channel] & (1 << 31))
2422 {
2423 /*NON DESCRIPTOR */
2424 jz4740_dma_ndrun(s, channel);
2425 }
2426 }
2427 }
2428
2429 static inline void jz4740_dma_en_global(struct jz4740_dma_s *s)
2430 {
2431 int channel;
2432 for (channel = 0; channel < JZ4740_DMA_NUM; channel++)
2433 {
2434 jz4740_dma_en_channel(s, channel);
2435 }
2436 }
2437
2438 static inline void jz4740_dma_en_dbn(struct jz4740_dma_s *s, int channel)
2439 {
2440 if ((s->dmac & 0x1) && (s->dcs[channel] & (1 << 31)))
2441 {
2442 jz4740_dma_drun(s, channel);
2443 }
2444 }
2445
2446 static void jz4740_dma_reset(struct jz4740_dma_s *s)
2447 {
2448
2449 }
2450
2451 static uint32_t jz4740_dma_read(void *opaque, target_phys_addr_t addr)
2452 {
2453 struct jz4740_dma_s *s = (struct jz4740_dma_s *) opaque;
2454 int channel;
2455
2456 debug_out(DEBUG_DMA, "jz4740_dma_read addr %x \n", addr);
2457 switch (addr)
2458 {
2459 case 0x300:
2460 return s->dmac;
2461 case 0x304:
2462 return s->dirqp;
2463 case 0x308:
2464 return s->ddr;
2465 case 0x0:
2466 case 0x20:
2467 case 0x40:
2468 case 0x60:
2469 case 0x80:
2470 case 0xa0:
2471 channel = (addr - 0x0) / 0x20;
2472 return s->dsa[channel];
2473 case 0x4:
2474 case 0x24:
2475 case 0x44:
2476 case 0x64:
2477 case 0x84:
2478 case 0xa4:
2479 channel = (addr - 0x4) / 0x20;
2480 return s->dta[channel];
2481 case 0x8:
2482 case 0x28:
2483 case 0x48:
2484 case 0x68:
2485 case 0x88:
2486 case 0xa8:
2487 channel = (addr - 0x8) / 0x20;
2488 return s->dtc[channel];
2489 case 0xc:
2490 case 0x2c:
2491 case 0x4c:
2492 case 0x6c:
2493 case 0x8c:
2494 case 0xac:
2495 channel = (addr - 0xc) / 0x20;
2496 return s->drs[channel];
2497 case 0x10:
2498 case 0x30:
2499 case 0x50:
2500 case 0x70:
2501 case 0x90:
2502 case 0xb0:
2503 channel = (addr - 0x10) / 0x20;
2504 return s->dcs[channel];
2505 case 0x14:
2506 case 0x34:
2507 case 0x54:
2508 case 0x74:
2509 case 0x94:
2510 case 0xb4:
2511 channel = (addr - 0x14) / 0x20;
2512 return s->dcm[channel];
2513 case 0x18:
2514 case 0x38:
2515 case 0x58:
2516 case 0x78:
2517 case 0x98:
2518 case 0xb8:
2519 channel = (addr - 0x18) / 0x20;
2520 return s->dda[channel];
2521 default:
2522 cpu_abort(s->soc->env,
2523 "jz4740_dma_read undefined addr " JZ_FMT_plx " \n", addr);
2524 }
2525 return (0);
2526 }
2527
2528 static void jz4740_dma_write(void *opaque, target_phys_addr_t addr,
2529 uint32_t value)
2530 {
2531 struct jz4740_dma_s *s = (struct jz4740_dma_s *) opaque;
2532 int channel;
2533
2534 debug_out(DEBUG_DMA, "jz4740_dma_write addr %x value %x \n", addr, value);
2535 switch (addr)
2536 {
2537 case 0x304:
2538 JZ4740_RO_REG(addr);
2539 break;
2540 case 0x300:
2541 s->dmac = value & 0x30d;
2542 if (s->dmac & 0x1)
2543 jz4740_dma_en_global(s);
2544 break;
2545 case 0x308:
2546 case 0x30c:
2547 s->ddr = value & 0xff;
2548 for (channel = 0; channel < JZ4740_DMA_NUM; channel++)
2549 {
2550 if (s->ddr & (1 << channel))
2551 {
2552 jz4740_dma_en_dbn(s, channel);
2553 break;
2554 }
2555 }
2556 break;
2557 case 0x0:
2558 case 0x20:
2559 case 0x40:
2560 case 0x60:
2561 case 0x80:
2562 case 0xa0:
2563 channel = (addr - 0x0) / 0x20;
2564 s->dsa[channel] = value;
2565 break;
2566 case 0x4:
2567 case 0x24:
2568 case 0x44:
2569 case 0x64:
2570 case 0x84:
2571 case 0xa4:
2572 channel = (addr - 0x4) / 0x20;
2573 s->dta[channel] = value;
2574 break;
2575 case 0x8:
2576 case 0x28:
2577 case 0x48:
2578 case 0x68:
2579 case 0x88:
2580 case 0xa8:
2581 channel = (addr - 0x8) / 0x20;
2582 s->dtc[channel] = value;
2583 break;
2584 case 0xc:
2585 case 0x2c:
2586 case 0x4c:
2587 case 0x6c:
2588 case 0x8c:
2589 case 0xac:
2590 channel = (addr - 0xc) / 0x20;
2591 s->drs[channel] = value & 0x10;
2592 if (s->drs[channel] != 0x8)
2593 {
2594 fprintf(stderr, "Only auto request is supproted \n");
2595 }
2596 break;
2597 case 0x10:
2598 case 0x30:
2599 case 0x50:
2600 case 0x70:
2601 case 0x90:
2602 case 0xb0:
2603 channel = (addr - 0x10) / 0x20;
2604 s->dcs[channel] = value & 0x80ff005f;
2605 if (s->dcs[channel] & 0x1)
2606 jz4740_dma_en_channel(s, channel);
2607 break;
2608 case 0x14:
2609 case 0x34:
2610 case 0x54:
2611 case 0x74:
2612 case 0x94:
2613 case 0xb4:
2614 channel = (addr - 0x14) / 0x20;
2615 s->dcm[channel] = value & 0xcff79f;
2616 break;
2617 case 0x18:
2618 case 0x38:
2619 case 0x58:
2620 case 0x78:
2621 case 0x98:
2622 case 0xb8:
2623 channel = (addr - 0x18) / 0x20;
2624 s->dda[channel] = 0xfffffff0;
2625 break;
2626 default:
2627 cpu_abort(s->soc->env,
2628 "jz4740_dma_read undefined addr " JZ_FMT_plx " \n", addr);
2629 }
2630
2631 }
2632
2633 static CPUReadMemoryFunc *jz4740_dma_readfn[] = {
2634 jz4740_badwidth_read32,
2635 jz4740_badwidth_read32,
2636 jz4740_dma_read,
2637 };
2638
2639 static CPUWriteMemoryFunc *jz4740_dma_writefn[] = {
2640 jz4740_badwidth_write32,
2641 jz4740_badwidth_write32,
2642 jz4740_dma_write,
2643 };
2644
2645
2646 static struct jz4740_dma_s *jz4740_dma_init(struct jz_state_s *soc,
2647 qemu_irq irq)
2648 {
2649 int iomemtype;
2650 struct jz4740_dma_s *s = (struct jz4740_dma_s *) qemu_mallocz(sizeof(*s));
2651 s->base = JZ4740_PHYS_BASE(JZ4740_DMAC_BASE);
2652 s->soc = soc;
2653 s->irq = irq;
2654
2655 jz4740_dma_reset(s);
2656
2657 iomemtype =
2658 cpu_register_io_memory(0, jz4740_dma_readfn, jz4740_dma_writefn, s);
2659 cpu_register_physical_memory(s->base, 0x00010000, iomemtype);
2660 return s;
2661
2662 }
2663
2664 #define PEN_DOWN 1
2665 #define PEN_UP 0
2666 struct jz4740_sadc_s
2667 {
2668 qemu_irq irq;
2669
2670 target_phys_addr_t base;
2671 struct jz_state_s *soc;
2672
2673 uint32_t adena;
2674 uint32_t adcfg;
2675 uint32_t adctrl;
2676 uint32_t adstate;
2677 uint32_t adsame;
2678 uint32_t adwait;
2679 uint32_t adtch;
2680 uint32_t adbdat;
2681 uint32_t adsdat;
2682 uint32_t addpin;
2683
2684 uint8_t tchen;
2685 uint8_t ex_in;
2686 uint8_t xyz;
2687 uint8_t snum;
2688
2689 uint16_t x;
2690 uint16_t y;
2691
2692 uint16_t pen_state;
2693 uint8_t read_index;
2694
2695
2696 };
2697
2698 static void jz4740_touchscreen_interrupt(struct jz4740_sadc_s *s)
2699 {
2700 if (!s->tchen)
2701 return;
2702
2703 if ((s->adctrl)&(s->adstate))
2704 {
2705 debug_out(DEBUG_SADC,"irq s->adctrl %x s->adstate %x \n",s->adctrl,s->adstate);
2706 qemu_set_irq(s->irq,1);
2707 }
2708
2709 }
2710
2711 static void jz4740_touchscreen_event(void *opaque,
2712 int x, int y, int z, int buttons_state)
2713 {
2714 struct jz4740_sadc_s *s = opaque;
2715
2716 if (!s->tchen)
2717 return;
2718
2719 s->x = (x*4096)/0x7FFF;
2720 s->y = (y*4096)/0x7FFF;
2721
2722 if ((s->pen_state == PEN_UP)&&(buttons_state==PEN_DOWN))
2723 {
2724 s->adstate |= 0x14;
2725 jz4740_touchscreen_interrupt(s);
2726 }
2727 else if ((s->pen_state == PEN_DOWN)&&(buttons_state==PEN_UP))
2728 {
2729 s->adstate |= 0xc;
2730 jz4740_touchscreen_interrupt(s);
2731 }
2732 s->pen_state = buttons_state;
2733
2734 }
2735
2736 static uint32_t jz4740_sadc_read8(void *opaque, target_phys_addr_t addr)
2737 {
2738 struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
2739
2740 switch (addr)
2741 {
2742 case 0x0:
2743 return s->adena;
2744 case 0x8:
2745 return s->adctrl;
2746 case 0xc:
2747 return s->adstate;
2748 default:
2749 cpu_abort(s->soc->env,
2750 "jz4740_sadc_read8 undefined addr " JZ_FMT_plx " \n", addr);
2751 }
2752 return (0);
2753 }
2754
2755 static uint32_t jz4740_sdac_read16(void *opaque, target_phys_addr_t addr)
2756 {
2757 struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
2758
2759 switch (addr)
2760 {
2761 case 0x10:
2762 return s->adsame;
2763 case 0x14:
2764 return s->adwait;
2765 case 0x1c:
2766 return s->adbdat;
2767 case 0x20:
2768 return s->adsdat;
2769 default:
2770 cpu_abort(s->soc->env,
2771 "jz4740_sdac_read16 undefined addr " JZ_FMT_plx " \n", addr);
2772 }
2773 return (0);
2774 }
2775
2776 static uint32_t jz4740_sdac_read32(void *opaque, target_phys_addr_t addr)
2777 {
2778 struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
2779 switch (addr)
2780 {
2781 case 0x4:
2782 return s->adcfg;
2783 case 0x18:
2784 /*TODO: Other type format*/
2785 if (s->read_index==0)
2786 {
2787 s->read_index ++;
2788 return (((s->x) & 0x7fff) | ((s->y & 0x7ffff) << 16));
2789 }
2790 else
2791 {
2792 s->read_index = 0;
2793 return (0x3fff);
2794 }
2795 default:
2796 cpu_abort(s->soc->env,
2797 "jz4740_sdac_read32 undefined addr " JZ_FMT_plx " \n", addr);
2798 }
2799 return (0);
2800 }
2801
2802 static void jz4740_sadc_write8(void *opaque, target_phys_addr_t addr,
2803 uint32_t value)
2804 {
2805 struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
2806
2807 debug_out(DEBUG_SADC, "jz4740_sadc_write8 addr %x value %x\n", addr, value);
2808
2809 switch (addr)
2810 {
2811 case 0x0:
2812 s->adena = value & 0x7;
2813 s->tchen = value & 0x4;
2814 break;
2815 case 0x8:
2816 s->adctrl = value & 0x1f;
2817 break;
2818 case 0xc:
2819 s->adstate &= ~(value & 0x1f);
2820 break;
2821 default:
2822 cpu_abort(s->soc->env,
2823 "jz4740_sadc_write8 undefined addr " JZ_FMT_plx " value %x \n", addr,value);
2824 }
2825 }
2826
2827 static void jz4740_sadc_write16(void *opaque, target_phys_addr_t addr,
2828 uint32_t value)
2829 {
2830 struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
2831
2832 debug_out(DEBUG_SADC, "jz4740_sadc_write16 addr %x value %x\n", addr, value);
2833
2834 switch (addr)
2835 {
2836 case 0x10:
2837 s->adsame = value & 0xffff;
2838 break;
2839 case 0x14:
2840 s->adsdat = value & 0xffff;
2841 break;
2842 case 0x1c:
2843 s->adbdat = 0x0;
2844 case 0x20:
2845 s->adsdat = 0x0;
2846 default:
2847 cpu_abort(s->soc->env,
2848 "jz4740_sadc_write16 undefined addr " JZ_FMT_plx " value %x \n", addr,value);
2849 }
2850 }
2851
2852 static void jz4740_sadc_write32(void *opaque, target_phys_addr_t addr,
2853 uint32_t value)
2854 {
2855 struct jz4740_sadc_s *s = (struct jz4740_sadc_s *) opaque;
2856
2857
2858 debug_out(DEBUG_SADC, "jz4740_sadc_write32 addr %x value %x\n", addr, value);
2859
2860 switch (addr)
2861 {
2862 case 0x4:
2863 s->adcfg = value & 0xc007ffff;
2864 s->ex_in = (value & 0x40000000)>>30;
2865 s->xyz = (value & 0x6fff)>>13;
2866 s->snum = ((value & 0x1cff)>>10)+1;
2867 break;
2868 case 18:
2869 s->adtch = value & 0x8fff8fff;
2870 break;
2871 default:
2872 cpu_abort(s->soc->env,
2873 "jz4740_sadc_write32 undefined addr " JZ_FMT_plx " value %x \n", addr,value);
2874 }
2875 }
2876
2877 static void jz4740_sadc_reset(struct jz4740_sadc_s *s)
2878 {
2879 s->adcfg = 0x0002002c;
2880 s->tchen = 0;
2881 s->snum = 1;
2882 s->xyz = 0;
2883 s->ex_in = 0;
2884 }
2885
2886 static CPUReadMemoryFunc *jz4740_sadc_readfn[] = {
2887 jz4740_sadc_read8,
2888 jz4740_sdac_read16,
2889 jz4740_sdac_read32,
2890 };
2891
2892 static CPUWriteMemoryFunc *jz4740_sadc_writefn[] = {
2893 jz4740_sadc_write8,
2894 jz4740_sadc_write16,
2895 jz4740_sadc_write32,
2896 };
2897
2898 static struct jz4740_sadc_s *jz4740_sadc_init(struct jz_state_s *soc,
2899 qemu_irq irq)
2900 {
2901 int iomemtype;
2902 struct jz4740_sadc_s *s;
2903
2904 s = (struct jz4740_sadc_s *)
2905 qemu_mallocz(sizeof(struct jz4740_sadc_s));
2906 s->base = JZ4740_PHYS_BASE(JZ4740_SADC_BASE);
2907 s->irq = irq;
2908 s->soc = soc;
2909
2910 qemu_add_mouse_event_handler(jz4740_touchscreen_event, s, 1,
2911 "QEMU JZ4740 Touchscreen");
2912
2913 jz4740_sadc_reset(s);
2914
2915 iomemtype =
2916 cpu_register_io_memory(0, jz4740_sadc_readfn, jz4740_sadc_writefn, s);
2917 cpu_register_physical_memory(s->base, 0x00001000, iomemtype);
2918 return s;
2919 }
2920
2921 static void jz4740_cpu_reset(void *opaque)
2922 {
2923 fprintf(stderr, "%s: UNIMPLEMENTED!", __FUNCTION__);
2924 }
2925
2926 struct jz_state_s *jz4740_init(unsigned long sdram_size,
2927 uint32_t osc_extal_freq, DisplayState * ds)
2928 {
2929 struct jz_state_s *s = (struct jz_state_s *)
2930 qemu_mallocz(sizeof(struct jz_state_s));
2931 ram_addr_t sram_base, sdram_base;
2932 qemu_irq *intc;
2933
2934 s->mpu_model = jz4740;
2935 s->env = cpu_init("jz4740");
2936
2937 if (!s->env)
2938 {
2939 fprintf(stderr, "Unable to find CPU definition\n");
2940 exit(1);
2941 }
2942
2943 debug_init();
2944 qemu_register_reset(jz4740_cpu_reset, s->env);
2945
2946 s->sdram_size = sdram_size;
2947 s->sram_size = JZ4740_SRAM_SIZE;
2948
2949 /* Clocks */
2950 jz_clk_init(s, osc_extal_freq);
2951
2952 /*map sram to 0x80000000 and sdram to 0x80004000 */
2953 sram_base = qemu_ram_alloc(s->sram_size);
2954 cpu_register_physical_memory(0x0, s->sram_size, (sram_base | IO_MEM_RAM));
2955 sdram_base = qemu_ram_alloc(s->sdram_size);
2956 cpu_register_physical_memory(JZ4740_SRAM_SIZE, s->sdram_size,
2957 (sdram_base | IO_MEM_RAM));
2958
2959 /* Init internal devices */
2960 cpu_mips_irq_init_cpu(s->env);
2961 cpu_mips_clock_init(s->env);
2962
2963
2964 /* Clocks */
2965 jz_clk_init(s, osc_extal_freq);
2966
2967 intc = jz4740_intc_init(s, s->env->irq[2]);
2968 s->cpm = jz4740_cpm_init(s);
2969 s->emc = jz4740_emc_init(s, intc[2]);
2970 s->gpio = jz4740_gpio_init(s, intc[25]);
2971 s->rtc = jz4740_rtc_init(s, intc[15]);
2972 s->tcu = jz4740_tcu_if_init(s, intc[23], intc[22], intc[21]);
2973 jz4740_tcu_init(s, s->tcu, 0);
2974 s->lcdc = jz4740_lcdc_init(s, intc[30], ds);
2975 s->dma = jz4740_dma_init(s, intc[20]);
2976 s->sadc = jz4740_sadc_init(s,intc[12]);
2977
2978 if (serial_hds[0])
2979 serial_mm_init(0x10030000, 2, intc[9], 57600, serial_hds[0], 1);
2980
2981 return s;
2982 }
jz4740 based target emulation