hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "nvram.h"
  29 #include "pc.h"
  30 #include "sysemu.h"
  31 #include "net.h"
  32 #include "isa.h"
  33 #include "pci.h"
  34 #include "boards.h"
  35 #include "fw_cfg.h"
  36
  37 #define MAX_IDE_BUS 2
  38 #define VGA_BIOS_SIZE 65536
  39 #define CFG_ADDR 0xf0000510
  40
  41 enum {
  42     ARCH_PREP = 0,
  43     ARCH_MAC99,
  44     ARCH_HEATHROW,
  45 };
  46
  47 /* temporary frame buffer OSI calls for the video.x driver. The right
  48    solution is to modify the driver to use VGA PCI I/Os */
  49 /* XXX: to be removed. This is no way related to emulation */
  50 static int vga_osi_call (CPUState *env)
  51 {
  52     static int vga_vbl_enabled;
  53     int linesize;
  54
  55     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  56
  57     /* same handler as PearPC, coming from the original MOL video
  58        driver. */
  59     switch(env->gpr[5]) {
  60     case 4:
  61         break;
  62     case 28: /* set_vmode */
  63         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  64             env->gpr[3] = 1;
  65         else
  66             env->gpr[3] = 0;
  67         break;
  68     case 29: /* get_vmode_info */
  69         if (env->gpr[6] != 0) {
  70             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  71                 env->gpr[3] = 1;
  72                 break;
  73             }
  74         }
  75         env->gpr[3] = 0;
  76         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  77         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  78         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  79         env->gpr[7] = 85 << 16; /* refresh rate */
  80         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  81         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  82         linesize = (linesize + 3) & ~3;
  83         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  84         break;
  85     case 31: /* set_video power */
  86         env->gpr[3] = 0;
  87         break;
  88     case 39: /* video_ctrl */
  89         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  90             vga_vbl_enabled = env->gpr[6];
  91         env->gpr[3] = 0;
  92         break;
  93     case 47:
  94         break;
  95     case 59: /* set_color */
  96         /* R6 = index, R7 = RGB */
  97         env->gpr[3] = 0;
  98         break;
  99     case 64: /* get color */
 100         /* R6 = index */
 101         env->gpr[3] = 0;
 102         break;
 103     case 116: /* set hwcursor */
 104         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 105         break;
 106     default:
 107         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
 108                 ppc_dump_gpr(env, 5));
 109         break;
 110     }
 111
 112     return 1; /* osi_call handled */
 113 }
 114
 115 static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
 116                                const char *boot_device, DisplayState *ds,
 117                                const char *kernel_filename,
 118                                const char *kernel_cmdline,
 119                                const char *initrd_filename,
 120                                const char *cpu_model)
 121 {
 122     CPUState *env = NULL, *envs[MAX_CPUS];
 123     char buf[1024];
 124     qemu_irq *pic, **heathrow_irqs;
 125     nvram_t nvram;
 126     m48t59_t *m48t59;
 127     int linux_boot, i;
 128     ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
 129     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 130     PCIBus *pci_bus;
 131     MacIONVRAMState *nvr;
 132     int vga_bios_size, bios_size;
 133     qemu_irq *dummy_irq;
 134     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 135     int ide_mem_index[2];
 136     int ppc_boot_device;
 137     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 138     int index;
 139     void *fw_cfg;
 140
 141     linux_boot = (kernel_filename != NULL);
 142
 143     /* init CPUs */
 144     if (cpu_model == NULL)
 145         cpu_model = "G3";
 146     for (i = 0; i < smp_cpus; i++) {
 147         env = cpu_init(cpu_model);
 148         if (!env) {
 149             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 150             exit(1);
 151         }
 152         /* Set time-base frequency to 100 Mhz */
 153         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 154         env->osi_call = vga_osi_call;
 155         qemu_register_reset(&cpu_ppc_reset, env);
 156         envs[i] = env;
 157     }
 158     if (env->nip < 0xFFF80000) {
 159         /* Special test for PowerPC 601:
 160          * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
 161          * But the NVRAM is located at 0xFFF04000...
 162          */
 163         cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
 164     }
 165
 166     /* allocate RAM */
 167     ram_offset = qemu_ram_alloc(ram_size);
 168     cpu_register_physical_memory(0, ram_size, ram_offset);
 169
 170     /* allocate VGA RAM */
 171     vga_ram_offset = qemu_ram_alloc(vga_ram_size);
 172
 173     /* allocate and load BIOS */
 174     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 175     if (bios_name == NULL)
 176         bios_name = PROM_FILENAME;
 177     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 178     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 179
 180     /* Load OpenBIOS (ELF) */
 181     bios_size = load_elf(buf, 0, NULL, NULL, NULL);
 182     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 183         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 184         exit(1);
 185     }
 186
 187     /* allocate and load VGA BIOS */
 188     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 189     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 190     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 191     if (vga_bios_size < 0) {
 192         /* if no bios is present, we can still work */
 193         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 194         vga_bios_size = 0;
 195     } else {
 196         /* set a specific header (XXX: find real Apple format for NDRV
 197            drivers) */
 198         phys_ram_base[vga_bios_offset] = 'N';
 199         phys_ram_base[vga_bios_offset + 1] = 'D';
 200         phys_ram_base[vga_bios_offset + 2] = 'R';
 201         phys_ram_base[vga_bios_offset + 3] = 'V';
 202         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 203                      vga_bios_size);
 204         vga_bios_size += 8;
 205     }
 206
 207     if (linux_boot) {
 208         kernel_base = KERNEL_LOAD_ADDR;
 209         /* now we can load the kernel */
 210         kernel_size = load_elf(kernel_filename, kernel_base - 0xc0000000ULL,
 211                                NULL, NULL, NULL);
 212         if (kernel_size < 0)
 213             kernel_size = load_aout(kernel_filename, kernel_base,
 214                                     ram_size - kernel_base);
 215         if (kernel_size < 0)
 216             kernel_size = load_image_targphys(kernel_filename,
 217                                               kernel_base,
 218                                               ram_size - kernel_base);
 219         if (kernel_size < 0) {
 220             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 221                       kernel_filename);
 222             exit(1);
 223         }
 224         /* load initrd */
 225         if (initrd_filename) {
 226             initrd_base = INITRD_LOAD_ADDR;
 227             initrd_size = load_image(initrd_filename,
 228                                      phys_ram_base + initrd_base);
 229             if (initrd_size < 0) {
 230                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 231                           initrd_filename);
 232                 exit(1);
 233             }
 234         } else {
 235             initrd_base = 0;
 236             initrd_size = 0;
 237         }
 238         ppc_boot_device = 'm';
 239     } else {
 240         kernel_base = 0;
 241         kernel_size = 0;
 242         initrd_base = 0;
 243         initrd_size = 0;
 244         ppc_boot_device = '\0';
 245         for (i = 0; boot_device[i] != '\0'; i++) {
 246             /* TOFIX: for now, the second IDE channel is not properly
 247              *        used by OHW. The Mac floppy disk are not emulated.
 248              *        For now, OHW cannot boot from the network.
 249              */
 250 #if 0
 251             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 252                 ppc_boot_device = boot_device[i];
 253                 break;
 254             }
 255 #else
 256             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 257                 ppc_boot_device = boot_device[i];
 258                 break;
 259             }
 260 #endif
 261         }
 262         if (ppc_boot_device == '\0') {
 263             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 264             exit(1);
 265         }
 266     }
 267
 268     isa_mem_base = 0x80000000;
 269
 270     /* Register 2 MB of ISA IO space */
 271     isa_mmio_init(0xfe000000, 0x00200000);
 272
 273     /* XXX: we register only 1 output pin for heathrow PIC */
 274     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 275     heathrow_irqs[0] =
 276         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 277     /* Connect the heathrow PIC outputs to the 6xx bus */
 278     for (i = 0; i < smp_cpus; i++) {
 279         switch (PPC_INPUT(env)) {
 280         case PPC_FLAGS_INPUT_6xx:
 281             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 282             heathrow_irqs[i][0] =
 283                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 284             break;
 285         default:
 286             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 287             exit(1);
 288         }
 289     }
 290
 291     /* init basic PC hardware */
 292     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 293         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 294         exit(1);
 295     }
 296     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 297     pci_bus = pci_grackle_init(0xfec00000, pic);
 298     pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
 299                  vga_ram_offset, vga_ram_size,
 300                  vga_bios_offset, vga_bios_size);
 301
 302     /* XXX: suppress that */
 303     dummy_irq = i8259_init(NULL);
 304
 305     /* XXX: use Mac Serial port */
 306     serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
 307
 308     for(i = 0; i < nb_nics; i++) {
 309         if (!nd_table[i].model)
 310             nd_table[i].model = "ne2k_pci";
 311         pci_nic_init(pci_bus, &nd_table[i], -1);
 312     }
 313
 314     /* First IDE channel is a CMD646 on the PCI bus */
 315
 316     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 317         fprintf(stderr, "qemu: too many IDE bus\n");
 318         exit(1);
 319     }
 320     index = drive_get_index(IF_IDE, 0, 0);
 321     if (index == -1)
 322         hd[0] = NULL;
 323     else
 324         hd[0] =  drives_table[index].bdrv;
 325     index = drive_get_index(IF_IDE, 0, 1);
 326     if (index == -1)
 327         hd[1] = NULL;
 328     else
 329         hd[1] =  drives_table[index].bdrv;
 330     hd[3] = hd[2] = NULL;
 331     pci_cmd646_ide_init(pci_bus, hd, 0);
 332
 333     /* Second IDE channel is a MAC IDE on the MacIO bus */
 334     index = drive_get_index(IF_IDE, 1, 0);
 335     if (index == -1)
 336         hd[0] = NULL;
 337     else
 338         hd[0] =  drives_table[index].bdrv;
 339     index = drive_get_index(IF_IDE, 1, 1);
 340     if (index == -1)
 341         hd[1] = NULL;
 342     else
 343         hd[1] =  drives_table[index].bdrv;
 344     ide_mem_index[0] = -1;
 345     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
 346
 347     /* cuda also initialize ADB */
 348     cuda_init(&cuda_mem_index, pic[0x12]);
 349
 350     adb_kbd_init(&adb_bus);
 351     adb_mouse_init(&adb_bus);
 352
 353     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
 354     pmac_format_nvram_partition(nvr, 0x2000);
 355
 356     dbdma_init(&dbdma_mem_index);
 357
 358     macio_init(pci_bus, 0x0010, 1, pic_mem_index, dbdma_mem_index,
 359                cuda_mem_index, nvr, 2, ide_mem_index);
 360
 361     if (usb_enabled) {
 362         usb_ohci_init_pci(pci_bus, 3, -1);
 363     }
 364
 365     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 366         graphic_depth = 15;
 367
 368     m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
 369     nvram.opaque = m48t59;
 370     nvram.read_fn = &m48t59_read;
 371     nvram.write_fn = &m48t59_write;
 372     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
 373                          ppc_boot_device, kernel_base, kernel_size,
 374                          kernel_cmdline,
 375                          initrd_base, initrd_size,
 376                          /* XXX: need an option to load a NVRAM image */
 377                          0,
 378                          graphic_width, graphic_height, graphic_depth);
 379     /* No PCI init: the BIOS will do it */
 380
 381     /* Special port to get debug messages from Open-Firmware */
 382     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 383
 384     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 385     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 386     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 387     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 388 }
 389
 390 QEMUMachine heathrow_machine = {
 391     .name = "g3beige",
 392     .desc = "Heathrow based PowerMAC",
 393     .init = ppc_heathrow_init,
 394     .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE,
 395     .max_cpus = MAX_CPUS,
 396 };