hw/s3c.h

   1 /*
   2  * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
   3  *
   4  * Copyright (c) 2007 OpenMoko, Inc.
   5  * Author: Andrzej Zaborowski <andrew@openedhand.com>
   6  *
   7  * This code is licenced under the GNU GPL v2.
   8  */
   9 #ifndef S3C_H
  10 # define S3C_H  "s3c.h"
  11
  12 #include "qemu-common.h"
  13 #include "flash.h"
  14 #include "sd.h"
  15 #include "sysbus.h"
  16
  17 #define S3C_CPU_2410    0x32410002
  18 #define S3C_CPU_2440    0x32440001
  19
  20 /* Interrupt numbers */
  21 # define S3C_PIC_EINT0  0
  22 # define S3C_PIC_EINT1  1
  23 # define S3C_PIC_EINT2  2
  24 # define S3C_PIC_EINT3  3
  25 # define S3C_PIC_EINT4  4
  26 # define S3C_PIC_EINT8  5
  27 # define S3C_PIC_WDT    9
  28 # define S3C_PIC_TIMER0 10
  29 # define S3C_PIC_TIMER1 11
  30 # define S3C_PIC_TIMER2 12
  31 # define S3C_PIC_TIMER3 13
  32 # define S3C_PIC_TIMER4 14
  33 # define S3C_PIC_UART2  15
  34 # define S3C_PIC_LCD    16
  35 # define S3C_PIC_DMA0   17
  36 # define S3C_PIC_DMA1   18
  37 # define S3C_PIC_DMA2   19
  38 # define S3C_PIC_DMA3   20
  39 # define S3C_PIC_SDI    21
  40 # define S3C_PIC_SPI0   22
  41 # define S3C_PIC_UART1  23
  42 # define S3C_PIC_USBD   25
  43 # define S3C_PIC_USBH   26
  44 # define S3C_PIC_IIC    27
  45 # define S3C_PIC_UART0  28
  46 # define S3C_PIC_SPI1   29
  47 # define S3C_PIC_RTC    30
  48 # define S3C_PIC_ADC    31
  49 /* "Sub source" interrupt numbers */
  50 # define S3C_PICS_RXD0  32
  51 # define S3C_PICS_TXD0  33
  52 # define S3C_PICS_ERR0  34
  53 # define S3C_PICS_RXD1  35
  54 # define S3C_PICS_TXD1  36
  55 # define S3C_PICS_ERR1  37
  56 # define S3C_PICS_RXD2  38
  57 # define S3C_PICS_TXD2  39
  58 # define S3C_PICS_ERR2  40
  59 # define S3C_PICS_TC    41
  60 # define S3C_PICS_ADC   42
  61
  62 # define S3C_PIC_MAX    43
  63 /* External interrupt numbers */
  64 # define S3C_EINT(n)    ((n >= 8) ? (6 << 5) | (n - 8) : (5 << 5) | n)
  65
  66 /* DMA requests */
  67 # define S3C_RQ_nXDREQ0 0x00
  68 # define S3C_RQ_nXDREQ1 0x10
  69 # define S3C_RQ_I2SSDO  0x20
  70 # define S3C_RQ_UART2   0x30
  71 # define S3C_RQ_UART0   0x01
  72 # define S3C_RQ_UART1   0x11
  73 # define S3C_RQ_I2SSDI0 0x21
  74 # define S3C_RQ_SDI0    0x31
  75 # define S3C_RQ_SDI1    0x02
  76 # define S3C_RQ_I2SSDI1 0x12
  77 # define S3C_RQ_SDI2    0x22
  78 # define S3C_RQ_SPI1    0x32
  79 # define S3C_RQ_TIMER0  0x03
  80 # define S3C_RQ_SPI0    0x13
  81 # define S3C_RQ_TIMER1  0x23
  82 # define S3C_RQ_TIMER2  0x33
  83 # define S3C_RQ_USB_EP1 0x04
  84 # define S3C_RQ_USB_EP2 0x14
  85 # define S3C_RQ_USB_EP3 0x24
  86 # define S3C_RQ_USB_EP4 0x34
  87
  88 # define S3C_RQ_MAX     0x35
  89
  90 /* I/O port numbers */
  91 # define S3C_GP(b, n)   (((b) << 5) | n)
  92 # define S3C_GPA(n)     S3C_GP(0, n)
  93 # define S3C_GPB(n)     S3C_GP(1, n)
  94 # define S3C_GPC(n)     S3C_GP(2, n)
  95 # define S3C_GPD(n)     S3C_GP(3, n)
  96 # define S3C_GPE(n)     S3C_GP(4, n)
  97 # define S3C_GPF(n)     S3C_GP(5, n)
  98 # define S3C_GPG(n)     S3C_GP(6, n)
  99 # define S3C_GPH(n)     S3C_GP(7, n)
 100 # define S3C_GP_MAX     S3C_GP(8, 0)
 101
 102 # define S3C_RAM_BASE   0x30000000
 103 # define S3C_SRAM_BASE_NORBOOT  0x40000000
 104 # define S3C_SRAM_BASE_NANDBOOT 0x00000000
 105 # define S3C_SRAM_SIZE  0x00001000
 106
 107 # define S3C_XTAL_FREQ  32768           /* Hz */
 108
 109 /* s3c2410.c */
 110 struct s3c_pic_state_s;
 111 struct s3c_pic_state_s *s3c_pic_init(target_phys_addr_t base,
 112                 qemu_irq *arm_pic);
 113 qemu_irq *s3c_pic_get(struct s3c_pic_state_s *s);
 114
 115 struct s3c_dma_state_s;
 116 struct s3c_dma_state_s *s3c_dma_init(target_phys_addr_t base, qemu_irq *pic);
 117 qemu_irq *s3c_dma_get(struct s3c_dma_state_s *s);
 118
 119 /* GPIO TODO: remove this out, replace with qemu_irq or sumpthin */
 120 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
 121
 122 struct s3c_freq_s;
 123 struct s3c_timers_state_s;
 124 struct s3c_timers_state_s *s3c_timers_init(struct s3c_freq_s * freq,
 125                                 target_phys_addr_t base, qemu_irq *pic, qemu_irq *dma);
 126 void s3c_timers_cmp_handler_set(void *opaque, int line,
 127                 gpio_handler_t handler, void *cmp_opaque);
 128
 129 struct s3c_freq_s;
 130 struct s3c_uart_state_s;
 131 struct s3c_uart_state_s *s3c_uart_init(struct s3c_freq_s * freq, target_phys_addr_t base,
 132                 qemu_irq *irqs, qemu_irq *dma);
 133 void s3c_uart_attach(struct s3c_uart_state_s *s, CharDriverState *chr);
 134
 135 struct s3c_adc_state_s;
 136 struct s3c_adc_state_s *s3c_adc_init(target_phys_addr_t base, qemu_irq irq,
 137                 qemu_irq tcirq);
 138 void s3c_adc_setscale(struct s3c_adc_state_s *adc, const int m[]);
 139
 140 struct s3c_i2c_state_s;
 141 //struct s3c_i2c_state_s *s3c_i2c_init(target_phys_addr_t base, qemu_irq irq);
 142 void s3c_i2c_init(SysBusDevice * dev);
 143 i2c_bus *s3c_i2c_bus(struct s3c_i2c_state_s *s);
 144
 145 struct s3c_i2s_state_s;
 146 struct s3c_i2s_state_s *s3c_i2s_init(target_phys_addr_t base, qemu_irq *dma);
 147
 148 struct s3c_freq_s;
 149 struct s3c_wdt_state_s;
 150 struct s3c_wdt_state_s *s3c_wdt_init(struct s3c_freq_s * freq, target_phys_addr_t base, qemu_irq irq);
 151
 152 /* s3c24xx_gpio.c */
 153 struct s3c_gpio_state_s;
 154 struct s3c_gpio_state_s *s3c_gpio_init(target_phys_addr_t base, qemu_irq *pic, uint32_t cpu_id);
 155 qemu_irq *s3c_gpio_in_get(struct s3c_gpio_state_s *s);
 156 void s3c_gpio_out_set(struct s3c_gpio_state_s *s, int line, qemu_irq handler);
 157 void s3c_gpio_setpwrstat(struct s3c_gpio_state_s *s, int stat);
 158 void s3c_gpio_reset(struct s3c_gpio_state_s *s);
 159 void s3c_gpio_set_dat(struct s3c_gpio_state_s *s, int gpio, int level);
 160
 161 /* s3c24xx_lcd.c */
 162 struct s3c_lcd_state_s;
 163 struct s3c_lcd_state_s *s3c_lcd_init(target_phys_addr_t base,
 164                 qemu_irq irq);
 165 void s3c_lcd_reset(struct s3c_lcd_state_s *s);
 166
 167 /* s3c24xx_mmci.c */
 168 struct s3c_mmci_state_s;
 169 struct s3c_mmci_state_s *s3c_mmci_init(target_phys_addr_t base, uint32_t cpu_id,
 170                 SDState *mmc, qemu_irq irq, qemu_irq *dma);
 171 void s3c_mmci_reset(struct s3c_mmci_state_s *s);
 172
 173 /* s3c24xx_rtc.c */
 174 struct s3c_rtc_state_s;
 175 struct s3c_rtc_state_s *s3c_rtc_init(target_phys_addr_t base, qemu_irq irq);
 176 void s3c_rtc_reset(struct s3c_rtc_state_s *s);
 177
 178 /* s3c24xx_udc.c */
 179 struct s3c_udc_state_s;
 180 struct s3c_udc_state_s *s3c_udc_init(target_phys_addr_t base, qemu_irq irq,
 181                 qemu_irq *dma);
 182 void s3c_udc_reset(struct s3c_udc_state_s *s);
 183
 184 struct s3c_nand_driver_s {
 185         void (*reset)(void * opaque);
 186         void (*setwp)(void * opaque, int wp);
 187         void (*reg)(void * opaque, NANDFlashState *chip);
 188 };
 189
 190 /* s3c2410_nand.c */
 191 struct s3c_nand_driver_s * s3c2410_nand_init(void);
 192 /* s3c2440_nand.c */
 193 struct s3c_nand_driver_s * s3c2440_nand_init(void);
 194
 195 /* s3c2410.c */
 196 struct s3c_spi_state_s;
 197 struct s3c_spi_state_s *s3c_spi_init(target_phys_addr_t base,
 198                 qemu_irq irq0, qemu_irq drq0, qemu_irq irq1, qemu_irq drq1,
 199                 struct s3c_gpio_state_s *gpio);
 200 void s3c_spi_attach(struct s3c_spi_state_s *s, int ch,
 201                 uint8_t (*txrx)(void *opaque, uint8_t value),
 202                 uint8_t (*btxrx)(void *opaque, uint8_t value), void *opaque);
 203
 204 struct s3c_freq_s {
 205         uint32_t        xtal;   /* 16 or 12Mhz : Set in init()*/
 206         /* These are recalculated when the guest code changes the clock registers */
 207         uint32_t        clk;    /* CPU clock */
 208         uint32_t        hclk;   /* SDRAM clock */
 209         uint32_t        pclk;   /* peripheral clock */
 210         uint32_t        uclk;
 211 };
 212
 213 struct s3c_state_s {
 214     CPUState *env;
 215     struct s3c_freq_s   clock;
 216     uint32_t cpu_id;
 217     qemu_irq *irq;
 218     qemu_irq *drq;
 219     struct s3c_pic_state_s *pic;
 220     struct s3c_dma_state_s *dma;
 221     struct s3c_gpio_state_s *io;
 222     struct s3c_lcd_state_s *lcd;
 223     struct s3c_timers_state_s *timers;
 224     struct s3c_uart_state_s *uart[3];
 225     struct s3c_mmci_state_s *mmci;
 226     struct s3c_adc_state_s *adc;
 227     struct s3c_i2c_state_s *i2c;
 228     struct s3c_i2s_state_s *i2s;
 229     struct s3c_rtc_state_s *rtc;
 230     struct s3c_spi_state_s *spi;
 231     struct s3c_udc_state_s *udc;
 232     struct s3c_wdt_state_s *wdt;
 233     struct s3c_nand_driver_s *nand;
 234
 235     /* Memory controller */
 236     target_phys_addr_t mc_base;
 237     uint32_t mc_regs[13];
 238
 239     /* Clock & power management */
 240     target_phys_addr_t clkpwr_base;
 241     uint32_t clkpwr_regs[6 + 1];        // 6 2410. 1 2440
 242 };
 243
 244 /* s3c2410.c */
 245 struct s3c_state_s *s3c24xx_init(uint32_t cpu_id, uint32_t xtal, unsigned int sdram_size, uint32_t sram_address,
 246                 SDState *mmc);
 247
 248
 249 struct s3c_i2s_state_s { /* XXX move to .c */
 250     target_phys_addr_t base;
 251     qemu_irq *dma;
 252     void (*data_req)(void *, int, int);
 253
 254     uint16_t control;
 255     uint16_t mode;
 256     uint16_t prescaler;
 257     uint16_t fcontrol;
 258
 259     int tx_en;
 260     int rx_en;
 261     int tx_len;
 262     int rx_len;
 263     void (*codec_out)(void *, uint32_t);
 264     uint32_t (*codec_in)(void *);
 265     void *opaque;
 266
 267     uint16_t buffer;
 268     int cycle;
 269 };
 270
 271 #endif  /* S3C_H */