hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31
  32 struct PCIBus {
  33     int bus_num;
  34     int devfn_min;
  35     pci_set_irq_fn set_irq;
  36     pci_map_irq_fn map_irq;
  37     uint32_t config_reg; /* XXX: suppress */
  38     /* low level pic */
  39     SetIRQFunc *low_set_irq;
  40     qemu_irq *irq_opaque;
  41     PCIDevice *devices[256];
  42     PCIDevice *parent_dev;
  43     PCIBus *next;
  44     /* The bus IRQ state is the logical OR of the connected devices.
  45        Keep a count of the number of devices with raised IRQs.  */
  46     int nirq;
  47     int irq_count[];
  48 };
  49
  50 static void pci_update_mappings(PCIDevice *d);
  51 static void pci_set_irq(void *opaque, int irq_num, int level);
  52
  53 target_phys_addr_t pci_mem_base;
  54 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  55 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  56 static int pci_irq_index;
  57 static PCIBus *first_bus;
  58
  59 static void pcibus_save(QEMUFile *f, void *opaque)
  60 {
  61     PCIBus *bus = (PCIBus *)opaque;
  62     int i;
  63
  64     qemu_put_be32(f, bus->nirq);
  65     for (i = 0; i < bus->nirq; i++)
  66         qemu_put_be32(f, bus->irq_count[i]);
  67 }
  68
  69 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  70 {
  71     PCIBus *bus = (PCIBus *)opaque;
  72     int i, nirq;
  73
  74     if (version_id != 1)
  75         return -EINVAL;
  76
  77     nirq = qemu_get_be32(f);
  78     if (bus->nirq != nirq) {
  79         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  80                 nirq, bus->nirq);
  81         return -EINVAL;
  82     }
  83
  84     for (i = 0; i < nirq; i++)
  85         bus->irq_count[i] = qemu_get_be32(f);
  86
  87     return 0;
  88 }
  89
  90 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  91                          qemu_irq *pic, int devfn_min, int nirq)
  92 {
  93     PCIBus *bus;
  94     static int nbus = 0;
  95
  96     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  97     bus->set_irq = set_irq;
  98     bus->map_irq = map_irq;
  99     bus->irq_opaque = pic;
 100     bus->devfn_min = devfn_min;
 101     bus->nirq = nirq;
 102     bus->next = first_bus;
 103     first_bus = bus;
 104     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 105     return bus;
 106 }
 107
 108 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 109 {
 110     PCIBus *bus;
 111     bus = qemu_mallocz(sizeof(PCIBus));
 112     bus->map_irq = map_irq;
 113     bus->parent_dev = dev;
 114     bus->next = dev->bus->next;
 115     dev->bus->next = bus;
 116     return bus;
 117 }
 118
 119 int pci_bus_num(PCIBus *s)
 120 {
 121     return s->bus_num;
 122 }
 123
 124 void pci_device_save(PCIDevice *s, QEMUFile *f)
 125 {
 126     int i;
 127
 128     qemu_put_be32(f, 2); /* PCI device version */
 129     qemu_put_buffer(f, s->config, 256);
 130     for (i = 0; i < 4; i++)
 131         qemu_put_be32(f, s->irq_state[i]);
 132 }
 133
 134 int pci_device_load(PCIDevice *s, QEMUFile *f)
 135 {
 136     uint32_t version_id;
 137     int i;
 138
 139     version_id = qemu_get_be32(f);
 140     if (version_id > 2)
 141         return -EINVAL;
 142     qemu_get_buffer(f, s->config, 256);
 143     pci_update_mappings(s);
 144
 145     if (version_id >= 2)
 146         for (i = 0; i < 4; i ++)
 147             s->irq_state[i] = qemu_get_be32(f);
 148
 149     return 0;
 150 }
 151
 152 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 153 {
 154     uint16_t *id;
 155
 156     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 157     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 158     id[1] = cpu_to_le16(pci_default_sub_device_id);
 159     return 0;
 160 }
 161
 162 /*
 163  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 164  */
 165 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 166 {
 167     const char *p;
 168     char *e;
 169     unsigned long val;
 170     unsigned long dom = 0, bus = 0;
 171     unsigned slot = 0;
 172
 173     p = addr;
 174     val = strtoul(p, &e, 16);
 175     if (e == p)
 176         return -1;
 177     if (*e == ':') {
 178         bus = val;
 179         p = e + 1;
 180         val = strtoul(p, &e, 16);
 181         if (e == p)
 182             return -1;
 183         if (*e == ':') {
 184             dom = bus;
 185             bus = val;
 186             p = e + 1;
 187             val = strtoul(p, &e, 16);
 188             if (e == p)
 189                 return -1;
 190         }
 191     }
 192
 193     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 194         return -1;
 195
 196     slot = val;
 197
 198     if (*e)
 199         return -1;
 200
 201     /* Note: QEMU doesn't implement domains other than 0 */
 202     if (dom != 0 || pci_find_bus(bus) == NULL)
 203         return -1;
 204
 205     *domp = dom;
 206     *busp = bus;
 207     *slotp = slot;
 208     return 0;
 209 }
 210
 211 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 212 {
 213     char devaddr[32];
 214
 215     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 216         return -1;
 217
 218     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 219 }
 220
 221 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 222 {
 223     char devaddr[32];
 224
 225     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 226         return -1;
 227
 228     if (!strcmp(devaddr, "auto")) {
 229         *domp = *busp = 0;
 230         *slotp = -1;
 231         /* want to support dom/bus auto-assign at some point */
 232         return 0;
 233     }
 234
 235     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 236 }
 237
 238 /* -1 for devfn means auto assign */
 239 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 240                                          const char *name, int devfn,
 241                                          PCIConfigReadFunc *config_read,
 242                                          PCIConfigWriteFunc *config_write)
 243 {
 244     if (pci_irq_index >= PCI_DEVICES_MAX)
 245         return NULL;
 246
 247     if (devfn < 0) {
 248         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 249             if (!bus->devices[devfn])
 250                 goto found;
 251         }
 252         return NULL;
 253     found: ;
 254     }
 255     pci_dev->bus = bus;
 256     pci_dev->devfn = devfn;
 257     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 258     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 259     pci_set_default_subsystem_id(pci_dev);
 260
 261     if (!config_read)
 262         config_read = pci_default_read_config;
 263     if (!config_write)
 264         config_write = pci_default_write_config;
 265     pci_dev->config_read = config_read;
 266     pci_dev->config_write = config_write;
 267     pci_dev->irq_index = pci_irq_index++;
 268     bus->devices[devfn] = pci_dev;
 269     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 270     return pci_dev;
 271 }
 272
 273 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 274                                int instance_size, int devfn,
 275                                PCIConfigReadFunc *config_read,
 276                                PCIConfigWriteFunc *config_write)
 277 {
 278     PCIDevice *pci_dev;
 279
 280     pci_dev = qemu_mallocz(instance_size);
 281     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 282                                      config_read, config_write);
 283     return pci_dev;
 284 }
 285 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 286 {
 287     return addr + pci_mem_base;
 288 }
 289
 290 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 291 {
 292     PCIIORegion *r;
 293     int i;
 294
 295     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 296         r = &pci_dev->io_regions[i];
 297         if (!r->size || r->addr == -1)
 298             continue;
 299         if (r->type == PCI_ADDRESS_SPACE_IO) {
 300             isa_unassign_ioport(r->addr, r->size);
 301         } else {
 302             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 303                                                      r->size,
 304                                                      IO_MEM_UNASSIGNED);
 305         }
 306     }
 307 }
 308
 309 int pci_unregister_device(PCIDevice *pci_dev)
 310 {
 311     int ret = 0;
 312
 313     if (pci_dev->unregister)
 314         ret = pci_dev->unregister(pci_dev);
 315     if (ret)
 316         return ret;
 317
 318     pci_unregister_io_regions(pci_dev);
 319
 320     qemu_free_irqs(pci_dev->irq);
 321     pci_irq_index--;
 322     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 323     qemu_free(pci_dev);
 324     return 0;
 325 }
 326
 327 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 328                             uint32_t size, int type,
 329                             PCIMapIORegionFunc *map_func)
 330 {
 331     PCIIORegion *r;
 332     uint32_t addr;
 333
 334     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 335         return;
 336
 337     if (size & (size-1)) {
 338         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 339                     "type=0x%x, size=0x%x\n", type, size);
 340         exit(1);
 341     }
 342
 343     r = &pci_dev->io_regions[region_num];
 344     r->addr = -1;
 345     r->size = size;
 346     r->type = type;
 347     r->map_func = map_func;
 348     if (region_num == PCI_ROM_SLOT) {
 349         addr = 0x30;
 350     } else {
 351         addr = 0x10 + region_num * 4;
 352     }
 353     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 354 }
 355
 356 static void pci_update_mappings(PCIDevice *d)
 357 {
 358     PCIIORegion *r;
 359     int cmd, i;
 360     uint32_t last_addr, new_addr, config_ofs;
 361
 362     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 363     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 364         r = &d->io_regions[i];
 365         if (i == PCI_ROM_SLOT) {
 366             config_ofs = 0x30;
 367         } else {
 368             config_ofs = 0x10 + i * 4;
 369         }
 370         if (r->size != 0) {
 371             if (r->type & PCI_ADDRESS_SPACE_IO) {
 372                 if (cmd & PCI_COMMAND_IO) {
 373                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 374                                                          config_ofs));
 375                     new_addr = new_addr & ~(r->size - 1);
 376                     last_addr = new_addr + r->size - 1;
 377                     /* NOTE: we have only 64K ioports on PC */
 378                     if (last_addr <= new_addr || new_addr == 0 ||
 379                         last_addr >= 0x10000) {
 380                         new_addr = -1;
 381                     }
 382                 } else {
 383                     new_addr = -1;
 384                 }
 385             } else {
 386                 if (cmd & PCI_COMMAND_MEMORY) {
 387                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 388                                                          config_ofs));
 389                     /* the ROM slot has a specific enable bit */
 390                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 391                         goto no_mem_map;
 392                     new_addr = new_addr & ~(r->size - 1);
 393                     last_addr = new_addr + r->size - 1;
 394                     /* NOTE: we do not support wrapping */
 395                     /* XXX: as we cannot support really dynamic
 396                        mappings, we handle specific values as invalid
 397                        mappings. */
 398                     if (last_addr <= new_addr || new_addr == 0 ||
 399                         last_addr == -1) {
 400                         new_addr = -1;
 401                     }
 402                 } else {
 403                 no_mem_map:
 404                     new_addr = -1;
 405                 }
 406             }
 407             /* now do the real mapping */
 408             if (new_addr != r->addr) {
 409                 if (r->addr != -1) {
 410                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 411                         int class;
 412                         /* NOTE: specific hack for IDE in PC case:
 413                            only one byte must be mapped. */
 414                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 415                         if (class == 0x0101 && r->size == 4) {
 416                             isa_unassign_ioport(r->addr + 2, 1);
 417                         } else {
 418                             isa_unassign_ioport(r->addr, r->size);
 419                         }
 420                     } else {
 421                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 422                                                      r->size,
 423                                                      IO_MEM_UNASSIGNED);
 424                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 425                     }
 426                 }
 427                 r->addr = new_addr;
 428                 if (r->addr != -1) {
 429                     r->map_func(d, i, r->addr, r->size, r->type);
 430                 }
 431             }
 432         }
 433     }
 434 }
 435
 436 uint32_t pci_default_read_config(PCIDevice *d,
 437                                  uint32_t address, int len)
 438 {
 439     uint32_t val;
 440
 441     switch(len) {
 442     default:
 443     case 4:
 444         if (address <= 0xfc) {
 445             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 446             break;
 447         }
 448         /* fall through */
 449     case 2:
 450         if (address <= 0xfe) {
 451             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 452             break;
 453         }
 454         /* fall through */
 455     case 1:
 456         val = d->config[address];
 457         break;
 458     }
 459     return val;
 460 }
 461
 462 void pci_default_write_config(PCIDevice *d,
 463                               uint32_t address, uint32_t val, int len)
 464 {
 465     int can_write, i;
 466     uint32_t end, addr;
 467
 468     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 469                      (address >= 0x30 && address < 0x34))) {
 470         PCIIORegion *r;
 471         int reg;
 472
 473         if ( address >= 0x30 ) {
 474             reg = PCI_ROM_SLOT;
 475         }else{
 476             reg = (address - 0x10) >> 2;
 477         }
 478         r = &d->io_regions[reg];
 479         if (r->size == 0)
 480             goto default_config;
 481         /* compute the stored value */
 482         if (reg == PCI_ROM_SLOT) {
 483             /* keep ROM enable bit */
 484             val &= (~(r->size - 1)) | 1;
 485         } else {
 486             val &= ~(r->size - 1);
 487             val |= r->type;
 488         }
 489         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 490         pci_update_mappings(d);
 491         return;
 492     }
 493  default_config:
 494     /* not efficient, but simple */
 495     addr = address;
 496     for(i = 0; i < len; i++) {
 497         /* default read/write accesses */
 498         switch(d->config[0x0e]) {
 499         case 0x00:
 500         case 0x80:
 501             switch(addr) {
 502             case 0x00:
 503             case 0x01:
 504             case 0x02:
 505             case 0x03:
 506             case 0x06:
 507             case 0x07:
 508             case 0x08:
 509             case 0x09:
 510             case 0x0a:
 511             case 0x0b:
 512             case 0x0e:
 513             case 0x10 ... 0x27: /* base */
 514             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 515             case 0x30 ... 0x33: /* rom */
 516             case 0x3d:
 517                 can_write = 0;
 518                 break;
 519             default:
 520                 can_write = 1;
 521                 break;
 522             }
 523             break;
 524         default:
 525         case 0x01:
 526             switch(addr) {
 527             case 0x00:
 528             case 0x01:
 529             case 0x02:
 530             case 0x03:
 531             case 0x06:
 532             case 0x07:
 533             case 0x08:
 534             case 0x09:
 535             case 0x0a:
 536             case 0x0b:
 537             case 0x0e:
 538             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 539             case 0x38 ... 0x3b: /* rom */
 540             case 0x3d:
 541                 can_write = 0;
 542                 break;
 543             default:
 544                 can_write = 1;
 545                 break;
 546             }
 547             break;
 548         }
 549         if (can_write) {
 550             /* Mask out writes to reserved bits in registers */
 551             switch (addr) {
 552             case 0x05:
 553                 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
 554                 break;
 555             case 0x06:
 556                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
 557                 break;
 558             case 0x07:
 559                 val &= ~PCI_STATUS_RESERVED_MASK_HI;
 560                 break;
 561             }
 562             d->config[addr] = val;
 563         }
 564         if (++addr > 0xff)
 565                 break;
 566         val >>= 8;
 567     }
 568
 569     end = address + len;
 570     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 571         /* if the command register is modified, we must modify the mappings */
 572         pci_update_mappings(d);
 573     }
 574 }
 575
 576 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 577 {
 578     PCIBus *s = opaque;
 579     PCIDevice *pci_dev;
 580     int config_addr, bus_num;
 581
 582 #if defined(DEBUG_PCI) && 0
 583     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 584            addr, val, len);
 585 #endif
 586     bus_num = (addr >> 16) & 0xff;
 587     while (s && s->bus_num != bus_num)
 588         s = s->next;
 589     if (!s)
 590         return;
 591     pci_dev = s->devices[(addr >> 8) & 0xff];
 592     if (!pci_dev)
 593         return;
 594     config_addr = addr & 0xff;
 595 #if defined(DEBUG_PCI)
 596     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 597            pci_dev->name, config_addr, val, len);
 598 #endif
 599     pci_dev->config_write(pci_dev, config_addr, val, len);
 600 }
 601
 602 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 603 {
 604     PCIBus *s = opaque;
 605     PCIDevice *pci_dev;
 606     int config_addr, bus_num;
 607     uint32_t val;
 608
 609     bus_num = (addr >> 16) & 0xff;
 610     while (s && s->bus_num != bus_num)
 611         s= s->next;
 612     if (!s)
 613         goto fail;
 614     pci_dev = s->devices[(addr >> 8) & 0xff];
 615     if (!pci_dev) {
 616     fail:
 617         switch(len) {
 618         case 1:
 619             val = 0xff;
 620             break;
 621         case 2:
 622             val = 0xffff;
 623             break;
 624         default:
 625         case 4:
 626             val = 0xffffffff;
 627             break;
 628         }
 629         goto the_end;
 630     }
 631     config_addr = addr & 0xff;
 632     val = pci_dev->config_read(pci_dev, config_addr, len);
 633 #if defined(DEBUG_PCI)
 634     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 635            pci_dev->name, config_addr, val, len);
 636 #endif
 637  the_end:
 638 #if defined(DEBUG_PCI) && 0
 639     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 640            addr, val, len);
 641 #endif
 642     return val;
 643 }
 644
 645 /***********************************************************/
 646 /* generic PCI irq support */
 647
 648 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 649 static void pci_set_irq(void *opaque, int irq_num, int level)
 650 {
 651     PCIDevice *pci_dev = (PCIDevice *)opaque;
 652     PCIBus *bus;
 653     int change;
 654
 655     change = level - pci_dev->irq_state[irq_num];
 656     if (!change)
 657         return;
 658
 659     pci_dev->irq_state[irq_num] = level;
 660     for (;;) {
 661         bus = pci_dev->bus;
 662         irq_num = bus->map_irq(pci_dev, irq_num);
 663         if (bus->set_irq)
 664             break;
 665         pci_dev = bus->parent_dev;
 666     }
 667     bus->irq_count[irq_num] += change;
 668     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 669 }
 670
 671 /***********************************************************/
 672 /* monitor info on PCI */
 673
 674 typedef struct {
 675     uint16_t class;
 676     const char *desc;
 677 } pci_class_desc;
 678
 679 static const pci_class_desc pci_class_descriptions[] =
 680 {
 681     { 0x0100, "SCSI controller"},
 682     { 0x0101, "IDE controller"},
 683     { 0x0102, "Floppy controller"},
 684     { 0x0103, "IPI controller"},
 685     { 0x0104, "RAID controller"},
 686     { 0x0106, "SATA controller"},
 687     { 0x0107, "SAS controller"},
 688     { 0x0180, "Storage controller"},
 689     { 0x0200, "Ethernet controller"},
 690     { 0x0201, "Token Ring controller"},
 691     { 0x0202, "FDDI controller"},
 692     { 0x0203, "ATM controller"},
 693     { 0x0280, "Network controller"},
 694     { 0x0300, "VGA controller"},
 695     { 0x0301, "XGA controller"},
 696     { 0x0302, "3D controller"},
 697     { 0x0380, "Display controller"},
 698     { 0x0400, "Video controller"},
 699     { 0x0401, "Audio controller"},
 700     { 0x0402, "Phone"},
 701     { 0x0480, "Multimedia controller"},
 702     { 0x0500, "RAM controller"},
 703     { 0x0501, "Flash controller"},
 704     { 0x0580, "Memory controller"},
 705     { 0x0600, "Host bridge"},
 706     { 0x0601, "ISA bridge"},
 707     { 0x0602, "EISA bridge"},
 708     { 0x0603, "MC bridge"},
 709     { 0x0604, "PCI bridge"},
 710     { 0x0605, "PCMCIA bridge"},
 711     { 0x0606, "NUBUS bridge"},
 712     { 0x0607, "CARDBUS bridge"},
 713     { 0x0608, "RACEWAY bridge"},
 714     { 0x0680, "Bridge"},
 715     { 0x0c03, "USB controller"},
 716     { 0, NULL}
 717 };
 718
 719 static void pci_info_device(PCIDevice *d)
 720 {
 721     Monitor *mon = cur_mon;
 722     int i, class;
 723     PCIIORegion *r;
 724     const pci_class_desc *desc;
 725
 726     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 727                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 728     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 729     monitor_printf(mon, "    ");
 730     desc = pci_class_descriptions;
 731     while (desc->desc && class != desc->class)
 732         desc++;
 733     if (desc->desc) {
 734         monitor_printf(mon, "%s", desc->desc);
 735     } else {
 736         monitor_printf(mon, "Class %04x", class);
 737     }
 738     monitor_printf(mon, ": PCI device %04x:%04x\n",
 739            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 740            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 741
 742     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 743         monitor_printf(mon, "      IRQ %d.\n",
 744                        d->config[PCI_INTERRUPT_LINE]);
 745     }
 746     if (class == 0x0604) {
 747         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 748     }
 749     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 750         r = &d->io_regions[i];
 751         if (r->size != 0) {
 752             monitor_printf(mon, "      BAR%d: ", i);
 753             if (r->type & PCI_ADDRESS_SPACE_IO) {
 754                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 755                                r->addr, r->addr + r->size - 1);
 756             } else {
 757                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 758                                r->addr, r->addr + r->size - 1);
 759             }
 760         }
 761     }
 762     if (class == 0x0604 && d->config[0x19] != 0) {
 763         pci_for_each_device(d->config[0x19], pci_info_device);
 764     }
 765 }
 766
 767 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 768 {
 769     PCIBus *bus = first_bus;
 770     PCIDevice *d;
 771     int devfn;
 772
 773     while (bus && bus->bus_num != bus_num)
 774         bus = bus->next;
 775     if (bus) {
 776         for(devfn = 0; devfn < 256; devfn++) {
 777             d = bus->devices[devfn];
 778             if (d)
 779                 fn(d);
 780         }
 781     }
 782 }
 783
 784 void pci_info(Monitor *mon)
 785 {
 786     pci_for_each_device(0, pci_info_device);
 787 }
 788
 789 static const char * const pci_nic_models[] = {
 790     "ne2k_pci",
 791     "i82551",
 792     "i82557b",
 793     "i82559er",
 794     "rtl8139",
 795     "e1000",
 796     "pcnet",
 797     "virtio",
 798     NULL
 799 };
 800
 801 static const char * const pci_nic_names[] = {
 802     "ne2k_pci",
 803     "i82551",
 804     "i82557b",
 805     "i82559er",
 806     "rtl8139",
 807     "e1000",
 808     "pcnet",
 809     "virtio-net-pci",
 810     NULL
 811 };
 812
 813 /* Initialize a PCI NIC.  */
 814 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 815                   const char *default_model)
 816 {
 817     DeviceState *dev;
 818     int i;
 819
 820     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 821
 822     for (i = 0; pci_nic_models[i]; i++) {
 823         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 824             dev = qdev_create(bus, pci_nic_names[i]);
 825             qdev_set_prop_int(dev, "devfn", devfn);
 826             qdev_set_netdev(dev, nd);
 827             qdev_init(dev);
 828             nd->private = dev;
 829             return (PCIDevice *)dev;
 830         }
 831     }
 832
 833     return NULL;
 834 }
 835
 836 typedef struct {
 837     PCIDevice dev;
 838     PCIBus *bus;
 839 } PCIBridge;
 840
 841 static void pci_bridge_write_config(PCIDevice *d,
 842                              uint32_t address, uint32_t val, int len)
 843 {
 844     PCIBridge *s = (PCIBridge *)d;
 845
 846     if (address == 0x19 || (address == 0x18 && len > 1)) {
 847         if (address == 0x19)
 848             s->bus->bus_num = val & 0xff;
 849         else
 850             s->bus->bus_num = (val >> 8) & 0xff;
 851 #if defined(DEBUG_PCI)
 852         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 853 #endif
 854     }
 855     pci_default_write_config(d, address, val, len);
 856 }
 857
 858 PCIBus *pci_find_bus(int bus_num)
 859 {
 860     PCIBus *bus = first_bus;
 861
 862     while (bus && bus->bus_num != bus_num)
 863         bus = bus->next;
 864
 865     return bus;
 866 }
 867
 868 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 869 {
 870     PCIBus *bus = pci_find_bus(bus_num);
 871
 872     if (!bus)
 873         return NULL;
 874
 875     return bus->devices[PCI_DEVFN(slot, function)];
 876 }
 877
 878 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 879                         pci_map_irq_fn map_irq, const char *name)
 880 {
 881     PCIBridge *s;
 882     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 883                                          devfn, NULL, pci_bridge_write_config);
 884
 885     pci_config_set_vendor_id(s->dev.config, vid);
 886     pci_config_set_device_id(s->dev.config, did);
 887
 888     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 889     s->dev.config[0x05] = 0x00;
 890     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 891     s->dev.config[0x07] = 0x00; // status = fast devsel
 892     s->dev.config[0x08] = 0x00; // revision
 893     s->dev.config[0x09] = 0x00; // programming i/f
 894     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 895     s->dev.config[0x0D] = 0x10; // latency_timer
 896     s->dev.config[PCI_HEADER_TYPE] =
 897         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 898     s->dev.config[0x1E] = 0xa0; // secondary status
 899
 900     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 901     return s->bus;
 902 }
 903
 904 static void pci_qdev_init(DeviceState *qdev, void *opaque)
 905 {
 906     PCIDevice *pci_dev = (PCIDevice *)qdev;
 907     pci_qdev_initfn init;
 908     PCIBus *bus;
 909     int devfn;
 910
 911     init = opaque;
 912     bus = qdev_get_bus(qdev);
 913     devfn = qdev_get_prop_int(qdev, "devfn", -1);
 914     pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
 915                                      NULL, NULL);//FIXME:config_read, config_write);
 916     assert(pci_dev);
 917     init(pci_dev);
 918 }
 919
 920 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
 921 {
 922     qdev_register(name, size, pci_qdev_init, init);
 923 }
 924
 925 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 926 {
 927     DeviceState *dev;
 928
 929     dev = qdev_create(bus, name);
 930     qdev_set_prop_int(dev, "devfn", devfn);
 931     qdev_init(dev);
 932
 933     return (PCIDevice *)dev;
 934 }