2 * Samsung S3C24xx series LCD controller.
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
6 * With: Michel Pollet <buserror@gmail.com>
8 * This code is licenced under the GNU GPL v2.
14 #include "framebuffer.h"
17 struct s3c_lcd_state_s
{
18 target_phys_addr_t base
;
35 uint16_t raw_pal
[0x100];
43 uint32_t palette
[0x100];
51 static void s3c_lcd_update(struct s3c_lcd_state_s
*s
)
53 s
->intpnd
|= s
->srcpnd
& ~s
->intmsk
;
54 qemu_set_irq(s
->irq
, !!s
->intpnd
);
57 void s3c_lcd_reset(struct s3c_lcd_state_s
*s
)
65 s
->con
[0] = 0x00000000;
66 s
->con
[1] = 0x00000000;
67 s
->con
[2] = 0x00000000;
68 s
->con
[3] = 0x00000000;
69 s
->con
[4] = 0x00000000;
70 s
->saddr
[0] = 0x00000000;
71 s
->saddr
[1] = 0x00000000;
72 s
->saddr
[2] = 0x00000000;
76 s
->dithmode
= 0x00000;
85 #define S3C_LCDCON1 0x00 /* LCD Control register 1 */
86 #define S3C_LCDCON2 0x04 /* LCD Control register 2 */
87 #define S3C_LCDCON3 0x08 /* LCD Control register 3 */
88 #define S3C_LCDCON4 0x0c /* LCD Control register 4 */
89 #define S3C_LCDCON5 0x10 /* LCD Control register 5 */
90 #define S3C_LCDSADDR1 0x14 /* Framebuffer Start Address 1 register */
91 #define S3C_LCDSADDR2 0x18 /* Framebuffer Start Address 2 register */
92 #define S3C_LCDSADDR3 0x1c /* Framebuffer Start Address 3 register */
93 #define S3C_REDLUT 0x20 /* Red Lookup Table register */
94 #define S3C_GREENLUT 0x24 /* Green Lookup Table register */
95 #define S3C_BLUELUT 0x28 /* Blue Lookup Table register */
96 #define S3C_DITHMODE 0x4c /* Dithering Mode register */
97 #define S3C_TPAL 0x50 /* Temporary Palette register */
98 #define S3C_LCDINTPND 0x54 /* LCD Interrupt Pending register */
99 #define S3C_LCDSRCPND 0x58 /* LCD Interrupt Source Pending register */
100 #define S3C_LCDINTMSK 0x5c /* LCD Interrupt Mask register */
101 #define S3C_LPCSEL 0x60 /* LPC3600 Control register */
103 #define S3C_PALETTE 0x400 /* Palette IO start offset */
104 #define S3C_PALETTEEND 0x5ff /* Palette IO end offset */
106 static uint32_t s3c_lcd_read(void *opaque
, target_phys_addr_t addr
)
108 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
112 return s
->con
[0]; /* XXX Return random LINECNT? */
120 return s
->con
[4]; /* XXX Return random STATUS? */
145 case S3C_PALETTE
... S3C_PALETTEEND
:
146 /* XXX assuming 16bit access */
147 return s
->raw_pal
[(addr
- S3C_PALETTE
) >> 1];
149 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
155 static void s3c_lcd_write(void *opaque
, target_phys_addr_t addr
,
158 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
162 s
->con
[0] = value
& 0x0003ffff;
163 s
->enable
= value
& 1;
164 s
->bpp
= (value
>> 1) & 0xf;
177 s
->con
[3] = value
& 0xffff;
180 s
->con
[4] = value
& 0x1fff;
181 s
->frm565
= (value
>> 11) & 1;
182 s
->msb
= (value
>> 12) & 1;
222 s
->intpnd
= value
& 3;
225 s
->srcpnd
= value
& 3;
228 s
->intmsk
= value
& 7;
232 s
->lpcsel
= (value
& 3) | 4;
234 printf("%s: attempt to enable LPC3600\n", __FUNCTION__
);
236 case S3C_PALETTE
... S3C_PALETTEEND
:
237 /* XXX assuming 16bit access */
238 s
->raw_pal
[(addr
- S3C_PALETTE
) >> 1] = value
;
241 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
245 static CPUReadMemoryFunc
*s3c_lcd_readfn
[] = {
251 static CPUWriteMemoryFunc
*s3c_lcd_writefn
[] = {
257 static inline void s3c_lcd_resize(struct s3c_lcd_state_s
*s
)
259 int new_width
, new_height
;
260 new_height
= ((s
->con
[1] >> 14) & 0x3ff) + 1;
261 new_width
= ((s
->con
[2] >> 8) & 0x7ff) + 1;
262 if (s
->width
!= new_width
|| s
->height
!= new_height
) {
263 s
->width
= new_width
;
264 s
->height
= new_height
;
265 // dpy_resize(s->ds, s->width, s->height);
266 qemu_console_resize(s
->ds
, s
->width
, s
->height
);
272 uint32_t s3c_rgb_to_pixel8(unsigned int r
, unsigned int g
, unsigned b
)
274 return ((r
>> 5) << 5) | ((g
>> 5) << 2) | (b
>> 6);
278 uint32_t s3c_rgb_to_pixel15(unsigned int r
, unsigned int g
, unsigned b
)
280 return ((r
>> 3) << 10) | ((g
>> 3) << 5) | (b
>> 3);
284 uint32_t s3c_rgb_to_pixel16(unsigned int r
, unsigned int g
, unsigned b
)
286 return ((r
>> 3) << 11) | ((g
>> 2) << 5) | (b
>> 3);
290 uint32_t s3c_rgb_to_pixel24(unsigned int r
, unsigned int g
, unsigned b
)
292 return (r
<< 16) | (g
<< 8) | b
;
296 uint32_t s3c_rgb_to_pixel32(unsigned int r
, unsigned int g
, unsigned b
)
298 return (r
<< 16) | (g
<< 8) | b
;
301 static inline uint32_t s3c_rgb(struct s3c_lcd_state_s
*s
,
302 unsigned int r
, unsigned int g
, unsigned b
)
304 switch (ds_get_bits_per_pixel(s
->ds
)) {
306 return s3c_rgb_to_pixel32(r
<< 2, g
<< 2, b
<< 2);
308 return s3c_rgb_to_pixel15(r
<< 2, g
<< 2, b
<< 2);
310 return s3c_rgb_to_pixel16(r
<< 2, g
<< 2, b
<< 2);
312 return s3c_rgb_to_pixel24(r
<< 2, g
<< 2, b
<< 2);
314 return s3c_rgb_to_pixel32(r
<< 2, g
<< 2, b
<< 2);
316 fprintf(stderr
, "%s: Bad color depth\n", __FUNCTION__
);
321 static void s3c_lcd_palette_load(struct s3c_lcd_state_s
*s
)
328 s
->src_width
= s
->width
>> 3;
329 s
->fn
= s
->line_fn
[0];
334 s
->src_width
= s
->width
>> 2;
335 s
->fn
= s
->line_fn
[1];
340 s
->src_width
= s
->width
>> 1;
341 s
->fn
= s
->line_fn
[2];
346 s
->src_width
= s
->width
>> 0;
347 s
->fn
= s
->line_fn
[3];
350 s
->src_width
= (s
->width
* 3) >> 1;
351 s
->fn
= s
->line_fn
[4];
354 s
->src_width
= s
->width
<< 1;
356 s
->fn
= s
->line_fn
[5];
358 s
->fn
= s
->line_fn
[6];
361 s
->src_width
= s
->width
<< 2;
362 s
->fn
= s
->line_fn
[7];
368 for (i
= 0; i
< n
; i
++)
370 s
->palette
[i
] = s3c_rgb(s
,
371 (s
->raw_pal
[i
] >> 10) & 0x3e,
372 (s
->raw_pal
[i
] >> 5) & 0x3f,
373 (s
->raw_pal
[i
] << 1) & 0x3e);
375 s
->palette
[i
] = s3c_rgb(s
,
376 ((s
->raw_pal
[i
] >> 10) & 0x3e) | (s
->raw_pal
[i
] & 1),
377 ((s
->raw_pal
[i
] >> 6) & 0x3e) | (s
->raw_pal
[i
] & 1),
378 s
->raw_pal
[i
] & 0x3f);
380 for (i
= 0; i
< n
; i
++)
382 s
->palette
[i
] = s3c_rgb(s
,
383 ((s
->r
>> (i
* 4)) & 0xf) << 2,
384 ((s
->g
>> (i
* 4)) & 0xf) << 2,
385 ((s
->b
>> (i
* 4)) & 0xf) << 2);
387 s
->palette
[i
] = s3c_rgb(s
,
388 ((s
->r
>> (((i
>> 5) & 7) * 4)) & 0xf) << 2,
389 ((s
->g
>> (((i
>> 2) & 7) * 4)) & 0xf) << 2,
390 ((s
->b
>> ((i
& 3) * 4)) & 0xf) << 2);
394 static void s3c_update_display(void *opaque
)
396 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
397 int src_width
, dest_width
;
403 if (s
->invalidatep
) {
404 s3c_lcd_palette_load(s
);
408 addr
= s
->saddr
[0]<<1;
410 src_width
= s
->src_width
;
411 dest_width
= s
->width
* s
->dest_width
;
414 framebuffer_update_display(s
->ds
,
415 addr
, s
->width
, s
->height
,
416 src_width
, dest_width
, s
->dest_width
,
421 s
->srcpnd
|= (1 << 1); /* INT_FrSyn */
424 dpy_update(s
->ds
, 0, first
, s
->width
, last
- first
+ 1);
429 static void s3c_invalidate_display(void *opaque
)
431 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
435 static void s3c_screen_dump(void *opaque
, const char *filename
)
441 #include "s3c24xx_template.h"
443 #include "s3c24xx_template.h"
445 #include "s3c24xx_template.h"
447 #include "s3c24xx_template.h"
449 #include "s3c24xx_template.h"
451 static void s3c_lcd_save(QEMUFile
*f
, void *opaque
)
453 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
455 for (i
= 0; i
< 5; i
++)
456 qemu_put_be32s(f
, &s
->con
[i
]);
457 for (i
= 0; i
< 3; i
++)
458 qemu_put_be32s(f
, &s
->saddr
[i
]);
459 qemu_put_be32s(f
, &s
->r
);
460 qemu_put_be32s(f
, &s
->g
);
461 qemu_put_be16s(f
, &s
->b
);
462 qemu_put_be32s(f
, &s
->dithmode
);
463 qemu_put_be32s(f
, &s
->tpal
);
464 qemu_put_8s(f
, &s
->intpnd
);
465 qemu_put_8s(f
, &s
->srcpnd
);
466 qemu_put_8s(f
, &s
->intmsk
);
467 qemu_put_8s(f
, &s
->lpcsel
);
468 for (i
= 0; i
< 0x100; i
++)
469 qemu_put_be16s(f
, &s
->raw_pal
[i
]);
472 static int s3c_lcd_load(QEMUFile
*f
, void *opaque
, int version_id
)
474 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*) opaque
;
476 for (i
= 0; i
< 5; i
++)
477 qemu_get_be32s(f
, &s
->con
[i
]);
478 for (i
= 0; i
< 3; i
++)
479 qemu_get_be32s(f
, &s
->saddr
[i
]);
480 qemu_get_be32s(f
, &s
->r
);
481 qemu_get_be32s(f
, &s
->g
);
482 qemu_get_be16s(f
, &s
->b
);
483 qemu_get_be32s(f
, &s
->dithmode
);
484 qemu_get_be32s(f
, &s
->tpal
);
485 qemu_get_8s(f
, &s
->intpnd
);
486 qemu_get_8s(f
, &s
->srcpnd
);
487 qemu_get_8s(f
, &s
->intmsk
);
488 qemu_get_8s(f
, &s
->lpcsel
);
494 s
->bpp
= (s
->con
[0] >> 1) & 0xf;
495 s
->enable
= s
->con
[0] & 1;
496 s
->msb
= (s
->con
[4] >> 12) & 1;
497 s
->frm565
= (s
->con
[4] >> 11) & 1;
499 for (i
= 0; i
< 0x100; i
++)
500 qemu_get_be16s(f
, &s
->raw_pal
[i
]);
505 struct s3c_lcd_state_s
*s3c_lcd_init(target_phys_addr_t base
,
509 struct s3c_lcd_state_s
*s
= (struct s3c_lcd_state_s
*)
510 qemu_mallocz(sizeof(struct s3c_lcd_state_s
));
517 s
->ds
= graphic_console_init(
519 s3c_invalidate_display
,
520 s3c_screen_dump
, NULL
, s
);
522 iomemtype
= cpu_register_io_memory(0, s3c_lcd_readfn
,
524 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
526 register_savevm("s3c24xx_lcd", 0, 0, s3c_lcd_save
, s3c_lcd_load
, s
);
528 switch (ds_get_bits_per_pixel(s
->ds
)) {
533 s
->line_fn
= s3c_draw_fn_8
;
537 s
->line_fn
= s3c_draw_fn_15
;
541 s
->line_fn
= s3c_draw_fn_16
;
545 s
->line_fn
= s3c_draw_fn_24
;
549 s
->line_fn
= s3c_draw_fn_32
;
553 fprintf(stderr
, "%s: Bad color depth\n", __FUNCTION__
);