hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "fdc.h"
  27 #include "pci.h"
  28 #include "block.h"
  29 #include "sysemu.h"
  30 #include "audio/audio.h"
  31 #include "net.h"
  32 #include "smbus.h"
  33 #include "boards.h"
  34 #include "monitor.h"
  35 #include "fw_cfg.h"
  36 #include "hpet_emul.h"
  37 #include "watchdog.h"
  38 #include "smbios.h"
  39
  40 /* output Bochs bios info messages */
  41 //#define DEBUG_BIOS
  42
  43 #define BIOS_FILENAME "bios.bin"
  44 #define VGABIOS_FILENAME "vgabios.bin"
  45 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
  46
  47 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  48
  49 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  50 #define ACPI_DATA_SIZE       0x10000
  51 #define BIOS_CFG_IOPORT 0x510
  52 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  53 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  54
  55 #define MAX_IDE_BUS 2
  56
  57 static fdctrl_t *floppy_controller;
  58 static RTCState *rtc_state;
  59 static PITState *pit;
  60 static IOAPICState *ioapic;
  61 static PCIDevice *i440fx_state;
  62
  63 typedef struct rom_reset_data {
  64     uint8_t *data;
  65     target_phys_addr_t addr;
  66     unsigned size;
  67 } RomResetData;
  68
  69 static void option_rom_reset(void *_rrd)
  70 {
  71     RomResetData *rrd = _rrd;
  72
  73     cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
  74 }
  75
  76 static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
  77 {
  78     RomResetData *rrd = qemu_malloc(sizeof *rrd);
  79
  80     rrd->data = qemu_malloc(size);
  81     cpu_physical_memory_read(addr, rrd->data, size);
  82     rrd->addr = addr;
  83     rrd->size = size;
  84     qemu_register_reset(option_rom_reset, rrd);
  85 }
  86
  87 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  88 {
  89 }
  90
  91 /* MSDOS compatibility mode FPU exception support */
  92 static qemu_irq ferr_irq;
  93 /* XXX: add IGNNE support */
  94 void cpu_set_ferr(CPUX86State *s)
  95 {
  96     qemu_irq_raise(ferr_irq);
  97 }
  98
  99 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 100 {
 101     qemu_irq_lower(ferr_irq);
 102 }
 103
 104 /* TSC handling */
 105 uint64_t cpu_get_tsc(CPUX86State *env)
 106 {
 107     /* Note: when using kqemu, it is more logical to return the host TSC
 108        because kqemu does not trap the RDTSC instruction for
 109        performance reasons */
 110 #ifdef CONFIG_KQEMU
 111     if (env->kqemu_enabled) {
 112         return cpu_get_real_ticks();
 113     } else
 114 #endif
 115     {
 116         return cpu_get_ticks();
 117     }
 118 }
 119
 120 /* SMM support */
 121 void cpu_smm_update(CPUState *env)
 122 {
 123     if (i440fx_state && env == first_cpu)
 124         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
 125 }
 126
 127
 128 /* IRQ handling */
 129 int cpu_get_pic_interrupt(CPUState *env)
 130 {
 131     int intno;
 132
 133     intno = apic_get_interrupt(env);
 134     if (intno >= 0) {
 135         /* set irq request if a PIC irq is still pending */
 136         /* XXX: improve that */
 137         pic_update_irq(isa_pic);
 138         return intno;
 139     }
 140     /* read the irq from the PIC */
 141     if (!apic_accept_pic_intr(env))
 142         return -1;
 143
 144     intno = pic_read_irq(isa_pic);
 145     return intno;
 146 }
 147
 148 static void pic_irq_request(void *opaque, int irq, int level)
 149 {
 150     CPUState *env = first_cpu;
 151
 152     if (env->apic_state) {
 153         while (env) {
 154             if (apic_accept_pic_intr(env))
 155                 apic_deliver_pic_intr(env, level);
 156             env = env->next_cpu;
 157         }
 158     } else {
 159         if (level)
 160             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 161         else
 162             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 163     }
 164 }
 165
 166 /* PC cmos mappings */
 167
 168 #define REG_EQUIPMENT_BYTE          0x14
 169
 170 static int cmos_get_fd_drive_type(int fd0)
 171 {
 172     int val;
 173
 174     switch (fd0) {
 175     case 0:
 176         /* 1.44 Mb 3"5 drive */
 177         val = 4;
 178         break;
 179     case 1:
 180         /* 2.88 Mb 3"5 drive */
 181         val = 5;
 182         break;
 183     case 2:
 184         /* 1.2 Mb 5"5 drive */
 185         val = 2;
 186         break;
 187     default:
 188         val = 0;
 189         break;
 190     }
 191     return val;
 192 }
 193
 194 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 195 {
 196     RTCState *s = rtc_state;
 197     int cylinders, heads, sectors;
 198     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 199     rtc_set_memory(s, type_ofs, 47);
 200     rtc_set_memory(s, info_ofs, cylinders);
 201     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 202     rtc_set_memory(s, info_ofs + 2, heads);
 203     rtc_set_memory(s, info_ofs + 3, 0xff);
 204     rtc_set_memory(s, info_ofs + 4, 0xff);
 205     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 206     rtc_set_memory(s, info_ofs + 6, cylinders);
 207     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 208     rtc_set_memory(s, info_ofs + 8, sectors);
 209 }
 210
 211 /* convert boot_device letter to something recognizable by the bios */
 212 static int boot_device2nibble(char boot_device)
 213 {
 214     switch(boot_device) {
 215     case 'a':
 216     case 'b':
 217         return 0x01; /* floppy boot */
 218     case 'c':
 219         return 0x02; /* hard drive boot */
 220     case 'd':
 221         return 0x03; /* CD-ROM boot */
 222     case 'n':
 223         return 0x04; /* Network boot */
 224     }
 225     return 0;
 226 }
 227
 228 /* copy/pasted from cmos_init, should be made a general function
 229  and used there as well */
 230 static int pc_boot_set(void *opaque, const char *boot_device)
 231 {
 232     Monitor *mon = cur_mon;
 233 #define PC_MAX_BOOT_DEVICES 3
 234     RTCState *s = (RTCState *)opaque;
 235     int nbds, bds[3] = { 0, };
 236     int i;
 237
 238     nbds = strlen(boot_device);
 239     if (nbds > PC_MAX_BOOT_DEVICES) {
 240         monitor_printf(mon, "Too many boot devices for PC\n");
 241         return(1);
 242     }
 243     for (i = 0; i < nbds; i++) {
 244         bds[i] = boot_device2nibble(boot_device[i]);
 245         if (bds[i] == 0) {
 246             monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
 247                            boot_device[i]);
 248             return(1);
 249         }
 250     }
 251     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 252     rtc_set_memory(s, 0x38, (bds[2] << 4));
 253     return(0);
 254 }
 255
 256 /* hd_table must contain 4 block drivers */
 257 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 258                       const char *boot_device, BlockDriverState **hd_table)
 259 {
 260     RTCState *s = rtc_state;
 261     int nbds, bds[3] = { 0, };
 262     int val;
 263     int fd0, fd1, nb;
 264     int i;
 265
 266     /* various important CMOS locations needed by PC/Bochs bios */
 267
 268     /* memory size */
 269     val = 640; /* base memory in K */
 270     rtc_set_memory(s, 0x15, val);
 271     rtc_set_memory(s, 0x16, val >> 8);
 272
 273     val = (ram_size / 1024) - 1024;
 274     if (val > 65535)
 275         val = 65535;
 276     rtc_set_memory(s, 0x17, val);
 277     rtc_set_memory(s, 0x18, val >> 8);
 278     rtc_set_memory(s, 0x30, val);
 279     rtc_set_memory(s, 0x31, val >> 8);
 280
 281     if (above_4g_mem_size) {
 282         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 283         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 284         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 285     }
 286
 287     if (ram_size > (16 * 1024 * 1024))
 288         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 289     else
 290         val = 0;
 291     if (val > 65535)
 292         val = 65535;
 293     rtc_set_memory(s, 0x34, val);
 294     rtc_set_memory(s, 0x35, val >> 8);
 295
 296     /* set the number of CPU */
 297     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 298
 299     /* set boot devices, and disable floppy signature check if requested */
 300 #define PC_MAX_BOOT_DEVICES 3
 301     nbds = strlen(boot_device);
 302     if (nbds > PC_MAX_BOOT_DEVICES) {
 303         fprintf(stderr, "Too many boot devices for PC\n");
 304         exit(1);
 305     }
 306     for (i = 0; i < nbds; i++) {
 307         bds[i] = boot_device2nibble(boot_device[i]);
 308         if (bds[i] == 0) {
 309             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 310                     boot_device[i]);
 311             exit(1);
 312         }
 313     }
 314     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 315     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 316
 317     /* floppy type */
 318
 319     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 320     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 321
 322     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 323     rtc_set_memory(s, 0x10, val);
 324
 325     val = 0;
 326     nb = 0;
 327     if (fd0 < 3)
 328         nb++;
 329     if (fd1 < 3)
 330         nb++;
 331     switch (nb) {
 332     case 0:
 333         break;
 334     case 1:
 335         val |= 0x01; /* 1 drive, ready for boot */
 336         break;
 337     case 2:
 338         val |= 0x41; /* 2 drives, ready for boot */
 339         break;
 340     }
 341     val |= 0x02; /* FPU is there */
 342     val |= 0x04; /* PS/2 mouse installed */
 343     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 344
 345     /* hard drives */
 346
 347     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 348     if (hd_table[0])
 349         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 350     if (hd_table[1])
 351         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 352
 353     val = 0;
 354     for (i = 0; i < 4; i++) {
 355         if (hd_table[i]) {
 356             int cylinders, heads, sectors, translation;
 357             /* NOTE: bdrv_get_geometry_hint() returns the physical
 358                 geometry.  It is always such that: 1 <= sects <= 63, 1
 359                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 360                 geometry can be different if a translation is done. */
 361             translation = bdrv_get_translation_hint(hd_table[i]);
 362             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 363                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 364                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 365                     /* No translation. */
 366                     translation = 0;
 367                 } else {
 368                     /* LBA translation. */
 369                     translation = 1;
 370                 }
 371             } else {
 372                 translation--;
 373             }
 374             val |= translation << (i * 2);
 375         }
 376     }
 377     rtc_set_memory(s, 0x39, val);
 378 }
 379
 380 void ioport_set_a20(int enable)
 381 {
 382     /* XXX: send to all CPUs ? */
 383     cpu_x86_set_a20(first_cpu, enable);
 384 }
 385
 386 int ioport_get_a20(void)
 387 {
 388     return ((first_cpu->a20_mask >> 20) & 1);
 389 }
 390
 391 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 392 {
 393     ioport_set_a20((val >> 1) & 1);
 394     /* XXX: bit 0 is fast reset */
 395 }
 396
 397 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 398 {
 399     return ioport_get_a20() << 1;
 400 }
 401
 402 /***********************************************************/
 403 /* Bochs BIOS debug ports */
 404
 405 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 406 {
 407     static const char shutdown_str[8] = "Shutdown";
 408     static int shutdown_index = 0;
 409
 410     switch(addr) {
 411         /* Bochs BIOS messages */
 412     case 0x400:
 413     case 0x401:
 414         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 415         exit(1);
 416     case 0x402:
 417     case 0x403:
 418 #ifdef DEBUG_BIOS
 419         fprintf(stderr, "%c", val);
 420 #endif
 421         break;
 422     case 0x8900:
 423         /* same as Bochs power off */
 424         if (val == shutdown_str[shutdown_index]) {
 425             shutdown_index++;
 426             if (shutdown_index == 8) {
 427                 shutdown_index = 0;
 428                 qemu_system_shutdown_request();
 429             }
 430         } else {
 431             shutdown_index = 0;
 432         }
 433         break;
 434
 435         /* LGPL'ed VGA BIOS messages */
 436     case 0x501:
 437     case 0x502:
 438         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 439         exit(1);
 440     case 0x500:
 441     case 0x503:
 442 #ifdef DEBUG_BIOS
 443         fprintf(stderr, "%c", val);
 444 #endif
 445         break;
 446     }
 447 }
 448
 449 extern uint64_t node_cpumask[MAX_NODES];
 450
 451 static void bochs_bios_init(void)
 452 {
 453     void *fw_cfg;
 454     uint8_t *smbios_table;
 455     size_t smbios_len;
 456     uint64_t *numa_fw_cfg;
 457     int i, j;
 458
 459     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 460     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 461     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 462     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 463     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 464
 465     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 466     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 467     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 468     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 469
 470     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 471     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 472     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 473     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 474                      acpi_tables_len);
 475
 476     smbios_table = smbios_get_table(&smbios_len);
 477     if (smbios_table)
 478         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 479                          smbios_table, smbios_len);
 480
 481     /* allocate memory for the NUMA channel: one (64bit) word for the number
 482      * of nodes, one word for each VCPU->node and one word for each node to
 483      * hold the amount of memory.
 484      */
 485     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 486     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 487     for (i = 0; i < smp_cpus; i++) {
 488         for (j = 0; j < nb_numa_nodes; j++) {
 489             if (node_cpumask[j] & (1 << i)) {
 490                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 491                 break;
 492             }
 493         }
 494     }
 495     for (i = 0; i < nb_numa_nodes; i++) {
 496         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 497     }
 498     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 499                      (1 + smp_cpus + nb_numa_nodes) * 8);
 500 }
 501
 502 /* Generate an initial boot sector which sets state and jump to
 503    a specified vector */
 504 static void generate_bootsect(target_phys_addr_t option_rom,
 505                               uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
 506 {
 507     uint8_t rom[512], *p, *reloc;
 508     uint8_t sum;
 509     int i;
 510
 511     memset(rom, 0, sizeof(rom));
 512
 513     p = rom;
 514     /* Make sure we have an option rom signature */
 515     *p++ = 0x55;
 516     *p++ = 0xaa;
 517
 518     /* ROM size in sectors*/
 519     *p++ = 1;
 520
 521     /* Hook int19 */
 522
 523     *p++ = 0x50;                /* push ax */
 524     *p++ = 0x1e;                /* push ds */
 525     *p++ = 0x31; *p++ = 0xc0;   /* xor ax, ax */
 526     *p++ = 0x8e; *p++ = 0xd8;   /* mov ax, ds */
 527
 528     *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
 529     *p++ = 0x64; *p++ = 0x00;
 530     reloc = p;
 531     *p++ = 0x00; *p++ = 0x00;
 532
 533     *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
 534     *p++ = 0x66; *p++ = 0x00;
 535
 536     *p++ = 0x1f;                /* pop ds */
 537     *p++ = 0x58;                /* pop ax */
 538     *p++ = 0xcb;                /* lret */
 539
 540     /* Actual code */
 541     *reloc = (p - rom);
 542
 543     *p++ = 0xfa;                /* CLI */
 544     *p++ = 0xfc;                /* CLD */
 545
 546     for (i = 0; i < 6; i++) {
 547         if (i == 1)             /* Skip CS */
 548             continue;
 549
 550         *p++ = 0xb8;            /* MOV AX,imm16 */
 551         *p++ = segs[i];
 552         *p++ = segs[i] >> 8;
 553         *p++ = 0x8e;            /* MOV <seg>,AX */
 554         *p++ = 0xc0 + (i << 3);
 555     }
 556
 557     for (i = 0; i < 8; i++) {
 558         *p++ = 0x66;            /* 32-bit operand size */
 559         *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
 560         *p++ = gpr[i];
 561         *p++ = gpr[i] >> 8;
 562         *p++ = gpr[i] >> 16;
 563         *p++ = gpr[i] >> 24;
 564     }
 565
 566     *p++ = 0xea;                /* JMP FAR */
 567     *p++ = ip;                  /* IP */
 568     *p++ = ip >> 8;
 569     *p++ = segs[1];             /* CS */
 570     *p++ = segs[1] >> 8;
 571
 572     /* sign rom */
 573     sum = 0;
 574     for (i = 0; i < (sizeof(rom) - 1); i++)
 575         sum += rom[i];
 576     rom[sizeof(rom) - 1] = -sum;
 577
 578     cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
 579     option_rom_setup_reset(option_rom, sizeof (rom));
 580 }
 581
 582 static long get_file_size(FILE *f)
 583 {
 584     long where, size;
 585
 586     /* XXX: on Unix systems, using fstat() probably makes more sense */
 587
 588     where = ftell(f);
 589     fseek(f, 0, SEEK_END);
 590     size = ftell(f);
 591     fseek(f, where, SEEK_SET);
 592
 593     return size;
 594 }
 595
 596 static void load_linux(target_phys_addr_t option_rom,
 597                        const char *kernel_filename,
 598                        const char *initrd_filename,
 599                        const char *kernel_cmdline)
 600 {
 601     uint16_t protocol;
 602     uint32_t gpr[8];
 603     uint16_t seg[6];
 604     uint16_t real_seg;
 605     int setup_size, kernel_size, initrd_size, cmdline_size;
 606     uint32_t initrd_max;
 607     uint8_t header[1024];
 608     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
 609     FILE *f, *fi;
 610
 611     /* Align to 16 bytes as a paranoia measure */
 612     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 613
 614     /* load the kernel header */
 615     f = fopen(kernel_filename, "rb");
 616     if (!f || !(kernel_size = get_file_size(f)) ||
 617         fread(header, 1, 1024, f) != 1024) {
 618         fprintf(stderr, "qemu: could not load kernel '%s'\n",
 619                 kernel_filename);
 620         exit(1);
 621     }
 622
 623     /* kernel protocol version */
 624 #if 0
 625     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 626 #endif
 627     if (ldl_p(header+0x202) == 0x53726448)
 628         protocol = lduw_p(header+0x206);
 629     else
 630         protocol = 0;
 631
 632     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 633         /* Low kernel */
 634         real_addr    = 0x90000;
 635         cmdline_addr = 0x9a000 - cmdline_size;
 636         prot_addr    = 0x10000;
 637     } else if (protocol < 0x202) {
 638         /* High but ancient kernel */
 639         real_addr    = 0x90000;
 640         cmdline_addr = 0x9a000 - cmdline_size;
 641         prot_addr    = 0x100000;
 642     } else {
 643         /* High and recent kernel */
 644         real_addr    = 0x10000;
 645         cmdline_addr = 0x20000;
 646         prot_addr    = 0x100000;
 647     }
 648
 649 #if 0
 650     fprintf(stderr,
 651             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 652             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 653             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 654             real_addr,
 655             cmdline_addr,
 656             prot_addr);
 657 #endif
 658
 659     /* highest address for loading the initrd */
 660     if (protocol >= 0x203)
 661         initrd_max = ldl_p(header+0x22c);
 662     else
 663         initrd_max = 0x37ffffff;
 664
 665     if (initrd_max >= ram_size-ACPI_DATA_SIZE)
 666         initrd_max = ram_size-ACPI_DATA_SIZE-1;
 667
 668     /* kernel command line */
 669     pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
 670
 671     if (protocol >= 0x202) {
 672         stl_p(header+0x228, cmdline_addr);
 673     } else {
 674         stw_p(header+0x20, 0xA33F);
 675         stw_p(header+0x22, cmdline_addr-real_addr);
 676     }
 677
 678     /* loader type */
 679     /* High nybble = B reserved for Qemu; low nybble is revision number.
 680        If this code is substantially changed, you may want to consider
 681        incrementing the revision. */
 682     if (protocol >= 0x200)
 683         header[0x210] = 0xB0;
 684
 685     /* heap */
 686     if (protocol >= 0x201) {
 687         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 688         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 689     }
 690
 691     /* load initrd */
 692     if (initrd_filename) {
 693         if (protocol < 0x200) {
 694             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 695             exit(1);
 696         }
 697
 698         fi = fopen(initrd_filename, "rb");
 699         if (!fi) {
 700             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 701                     initrd_filename);
 702             exit(1);
 703         }
 704
 705         initrd_size = get_file_size(fi);
 706         initrd_addr = (initrd_max-initrd_size) & ~4095;
 707
 708         fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
 709                 "\n", initrd_size, initrd_addr);
 710
 711         if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
 712             fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
 713                     initrd_filename);
 714             exit(1);
 715         }
 716         fclose(fi);
 717
 718         stl_p(header+0x218, initrd_addr);
 719         stl_p(header+0x21c, initrd_size);
 720     }
 721
 722     /* store the finalized header and load the rest of the kernel */
 723     cpu_physical_memory_write(real_addr, header, 1024);
 724
 725     setup_size = header[0x1f1];
 726     if (setup_size == 0)
 727         setup_size = 4;
 728
 729     setup_size = (setup_size+1)*512;
 730     kernel_size -= setup_size;  /* Size of protected-mode code */
 731
 732     if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
 733         !fread_targphys_ok(prot_addr, kernel_size, f)) {
 734         fprintf(stderr, "qemu: read error on kernel '%s'\n",
 735                 kernel_filename);
 736         exit(1);
 737     }
 738     fclose(f);
 739
 740     /* generate bootsector to set up the initial register state */
 741     real_seg = real_addr >> 4;
 742     seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
 743     seg[1] = real_seg+0x20;     /* CS */
 744     memset(gpr, 0, sizeof gpr);
 745     gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
 746
 747     option_rom_setup_reset(real_addr, setup_size);
 748     option_rom_setup_reset(prot_addr, kernel_size);
 749     option_rom_setup_reset(cmdline_addr, cmdline_size);
 750     if (initrd_filename)
 751         option_rom_setup_reset(initrd_addr, initrd_size);
 752
 753     generate_bootsect(option_rom, gpr, seg, 0);
 754 }
 755
 756 static void main_cpu_reset(void *opaque)
 757 {
 758     CPUState *env = opaque;
 759     cpu_reset(env);
 760 }
 761
 762 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 763 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 764 static const int ide_irq[2] = { 14, 15 };
 765
 766 #define NE2000_NB_MAX 6
 767
 768 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 769 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 770
 771 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 772 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 773
 774 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 775 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 776
 777 #ifdef HAS_AUDIO
 778 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 779 {
 780     struct soundhw *c;
 781     int audio_enabled = 0;
 782
 783     for (c = soundhw; !audio_enabled && c->name; ++c) {
 784         audio_enabled = c->enabled;
 785     }
 786
 787     if (audio_enabled) {
 788         for (c = soundhw; c->name; ++c) {
 789             if (c->enabled) {
 790                 if (c->isa) {
 791                     c->init.init_isa(pic);
 792                 } else {
 793                     if (pci_bus) {
 794                         c->init.init_pci(pci_bus);
 795                     }
 796                 }
 797             }
 798         }
 799     }
 800 }
 801 #endif
 802
 803 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 804 {
 805     static int nb_ne2k = 0;
 806
 807     if (nb_ne2k == NE2000_NB_MAX)
 808         return;
 809     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 810     nb_ne2k++;
 811 }
 812
 813 static int load_option_rom(const char *oprom, target_phys_addr_t start,
 814                            target_phys_addr_t end)
 815 {
 816         int size;
 817
 818         size = get_image_size(oprom);
 819         if (size > 0 && start + size > end) {
 820             fprintf(stderr, "Not enough space to load option rom '%s'\n",
 821                     oprom);
 822             exit(1);
 823         }
 824         size = load_image_targphys(oprom, start, end - start);
 825         if (size < 0) {
 826             fprintf(stderr, "Could not load option rom '%s'\n", oprom);
 827             exit(1);
 828         }
 829         /* Round up optiom rom size to the next 2k boundary */
 830         size = (size + 2047) & ~2047;
 831         option_rom_setup_reset(start, size);
 832         return size;
 833 }
 834
 835 /* PC hardware initialisation */
 836 static void pc_init1(ram_addr_t ram_size,
 837                      const char *boot_device,
 838                      const char *kernel_filename, const char *kernel_cmdline,
 839                      const char *initrd_filename,
 840                      int pci_enabled, const char *cpu_model)
 841 {
 842     char buf[1024];
 843     int ret, linux_boot, i;
 844     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 845     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 846     int bios_size, isa_bios_size, oprom_area_size;
 847     PCIBus *pci_bus;
 848     int piix3_devfn = -1;
 849     CPUState *env;
 850     qemu_irq *cpu_irq;
 851     qemu_irq *i8259;
 852     int index;
 853     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 854     BlockDriverState *fd[MAX_FD];
 855     int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
 856
 857     if (ram_size >= 0xe0000000 ) {
 858         above_4g_mem_size = ram_size - 0xe0000000;
 859         below_4g_mem_size = 0xe0000000;
 860     } else {
 861         below_4g_mem_size = ram_size;
 862     }
 863
 864     linux_boot = (kernel_filename != NULL);
 865
 866     /* init CPUs */
 867     if (cpu_model == NULL) {
 868 #ifdef TARGET_X86_64
 869         cpu_model = "qemu64";
 870 #else
 871         cpu_model = "qemu32";
 872 #endif
 873     }
 874
 875     for(i = 0; i < smp_cpus; i++) {
 876         env = cpu_init(cpu_model);
 877         if (!env) {
 878             fprintf(stderr, "Unable to find x86 CPU definition\n");
 879             exit(1);
 880         }
 881         if (i != 0)
 882             env->halted = 1;
 883         if (smp_cpus > 1) {
 884             /* XXX: enable it in all cases */
 885             env->cpuid_features |= CPUID_APIC;
 886         }
 887         qemu_register_reset(main_cpu_reset, env);
 888         if (pci_enabled) {
 889             apic_init(env);
 890         }
 891     }
 892
 893     vmport_init();
 894
 895     /* allocate RAM */
 896     ram_addr = qemu_ram_alloc(0xa0000);
 897     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 898
 899     /* Allocate, even though we won't register, so we don't break the
 900      * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
 901      * and some bios areas, which will be registered later
 902      */
 903     ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
 904     ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
 905     cpu_register_physical_memory(0x100000,
 906                  below_4g_mem_size - 0x100000,
 907                  ram_addr);
 908
 909     /* above 4giga memory allocation */
 910     if (above_4g_mem_size > 0) {
 911 #if TARGET_PHYS_ADDR_BITS == 32
 912         hw_error("To much RAM for 32-bit physical address");
 913 #else
 914         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 915         cpu_register_physical_memory(0x100000000ULL,
 916                                      above_4g_mem_size,
 917                                      ram_addr);
 918 #endif
 919     }
 920
 921
 922     /* BIOS load */
 923     if (bios_name == NULL)
 924         bios_name = BIOS_FILENAME;
 925     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 926     bios_size = get_image_size(buf);
 927     if (bios_size <= 0 ||
 928         (bios_size % 65536) != 0) {
 929         goto bios_error;
 930     }
 931     bios_offset = qemu_ram_alloc(bios_size);
 932     ret = load_image(buf, qemu_get_ram_ptr(bios_offset));
 933     if (ret != bios_size) {
 934     bios_error:
 935         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
 936         exit(1);
 937     }
 938     /* map the last 128KB of the BIOS in ISA space */
 939     isa_bios_size = bios_size;
 940     if (isa_bios_size > (128 * 1024))
 941         isa_bios_size = 128 * 1024;
 942     cpu_register_physical_memory(0x100000 - isa_bios_size,
 943                                  isa_bios_size,
 944                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 945
 946
 947
 948     option_rom_offset = qemu_ram_alloc(0x20000);
 949     oprom_area_size = 0;
 950     cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
 951
 952     if (using_vga) {
 953         /* VGA BIOS load */
 954         if (cirrus_vga_enabled) {
 955             snprintf(buf, sizeof(buf), "%s/%s", bios_dir,
 956                      VGABIOS_CIRRUS_FILENAME);
 957         } else {
 958             snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 959         }
 960         oprom_area_size = load_option_rom(buf, 0xc0000, 0xe0000);
 961     }
 962     /* Although video roms can grow larger than 0x8000, the area between
 963      * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
 964      * for any other kind of option rom inside this area */
 965     if (oprom_area_size < 0x8000)
 966         oprom_area_size = 0x8000;
 967
 968     if (linux_boot) {
 969         load_linux(0xc0000 + oprom_area_size,
 970                    kernel_filename, initrd_filename, kernel_cmdline);
 971         oprom_area_size += 2048;
 972     }
 973
 974     for (i = 0; i < nb_option_roms; i++) {
 975         oprom_area_size += load_option_rom(option_rom[i],
 976                                            0xc0000 + oprom_area_size, 0xe0000);
 977     }
 978
 979     /* map all the bios at the top of memory */
 980     cpu_register_physical_memory((uint32_t)(-bios_size),
 981                                  bios_size, bios_offset | IO_MEM_ROM);
 982
 983     bochs_bios_init();
 984
 985     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 986     i8259 = i8259_init(cpu_irq[0]);
 987     ferr_irq = i8259[13];
 988
 989     if (pci_enabled) {
 990         pci_bus = i440fx_init(&i440fx_state, i8259);
 991         piix3_devfn = piix3_init(pci_bus, -1);
 992     } else {
 993         pci_bus = NULL;
 994     }
 995
 996     /* init basic PC hardware */
 997     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 998
 999     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1000
1001     if (cirrus_vga_enabled) {
1002         if (pci_enabled) {
1003             pci_cirrus_vga_init(pci_bus);
1004         } else {
1005             isa_cirrus_vga_init();
1006         }
1007     } else if (vmsvga_enabled) {
1008         if (pci_enabled)
1009             pci_vmsvga_init(pci_bus);
1010         else
1011             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1012     } else if (std_vga_enabled) {
1013         if (pci_enabled) {
1014             pci_vga_init(pci_bus, 0, 0);
1015         } else {
1016             isa_vga_init();
1017         }
1018     }
1019
1020     rtc_state = rtc_init(0x70, i8259[8], 2000);
1021
1022     qemu_register_boot_set(pc_boot_set, rtc_state);
1023
1024     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1025     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1026
1027     if (pci_enabled) {
1028         ioapic = ioapic_init();
1029     }
1030     pit = pit_init(0x40, i8259[0]);
1031     pcspk_init(pit);
1032     if (!no_hpet) {
1033         hpet_init(i8259);
1034     }
1035     if (pci_enabled) {
1036         pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1037     }
1038
1039     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1040         if (serial_hds[i]) {
1041             serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1042                         serial_hds[i]);
1043         }
1044     }
1045
1046     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1047         if (parallel_hds[i]) {
1048             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1049                           parallel_hds[i]);
1050         }
1051     }
1052
1053     watchdog_pc_init(pci_bus);
1054
1055     for(i = 0; i < nb_nics; i++) {
1056         NICInfo *nd = &nd_table[i];
1057
1058         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1059             pc_init_ne2k_isa(nd, i8259);
1060         else
1061             pci_nic_init(pci_bus, nd, -1, "ne2k_pci");
1062     }
1063
1064     qemu_system_hot_add_init();
1065
1066     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1067         fprintf(stderr, "qemu: too many IDE bus\n");
1068         exit(1);
1069     }
1070
1071     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1072         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1073         if (index != -1)
1074             hd[i] = drives_table[index].bdrv;
1075         else
1076             hd[i] = NULL;
1077     }
1078
1079     if (pci_enabled) {
1080         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1081     } else {
1082         for(i = 0; i < MAX_IDE_BUS; i++) {
1083             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1084                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1085         }
1086     }
1087
1088     i8042_init(i8259[1], i8259[12], 0x60);
1089     DMA_init(0);
1090 #ifdef HAS_AUDIO
1091     audio_init(pci_enabled ? pci_bus : NULL, i8259);
1092 #endif
1093
1094     for(i = 0; i < MAX_FD; i++) {
1095         index = drive_get_index(IF_FLOPPY, 0, i);
1096         if (index != -1)
1097             fd[i] = drives_table[index].bdrv;
1098         else
1099             fd[i] = NULL;
1100     }
1101     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1102
1103     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1104
1105     if (pci_enabled && usb_enabled) {
1106         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1107     }
1108
1109     if (pci_enabled && acpi_enabled) {
1110         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1111         i2c_bus *smbus;
1112
1113         /* TODO: Populate SPD eeprom data.  */
1114         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1115         for (i = 0; i < 8; i++) {
1116             DeviceState *eeprom;
1117             eeprom = qdev_create(smbus, "smbus-eeprom");
1118             qdev_set_prop_int(eeprom, "address", 0x50 + i);
1119             qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
1120             qdev_init(eeprom);
1121         }
1122     }
1123
1124     if (i440fx_state) {
1125         i440fx_init_memory_mappings(i440fx_state);
1126     }
1127
1128     if (pci_enabled) {
1129         int max_bus;
1130         int bus;
1131
1132         max_bus = drive_get_max_bus(IF_SCSI);
1133         for (bus = 0; bus <= max_bus; bus++) {
1134             pci_create_simple(pci_bus, -1, "lsi53c895a");
1135         }
1136     }
1137
1138     /* Add virtio block devices */
1139     if (pci_enabled) {
1140         int index;
1141         int unit_id = 0;
1142
1143         while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1144             pci_create_simple(pci_bus, -1, "virtio-blk-pci");
1145             unit_id++;
1146         }
1147     }
1148
1149     /* Add virtio balloon device */
1150     if (pci_enabled) {
1151         pci_create_simple(pci_bus, -1, "virtio-balloon-pci");
1152     }
1153
1154     /* Add virtio console devices */
1155     if (pci_enabled) {
1156         for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1157             if (virtcon_hds[i]) {
1158                 pci_create_simple(pci_bus, -1, "virtio-console-pci");
1159             }
1160         }
1161     }
1162 }
1163
1164 static void pc_init_pci(ram_addr_t ram_size,
1165                         const char *boot_device,
1166                         const char *kernel_filename,
1167                         const char *kernel_cmdline,
1168                         const char *initrd_filename,
1169                         const char *cpu_model)
1170 {
1171     pc_init1(ram_size, boot_device,
1172              kernel_filename, kernel_cmdline,
1173              initrd_filename, 1, cpu_model);
1174 }
1175
1176 static void pc_init_isa(ram_addr_t ram_size,
1177                         const char *boot_device,
1178                         const char *kernel_filename,
1179                         const char *kernel_cmdline,
1180                         const char *initrd_filename,
1181                         const char *cpu_model)
1182 {
1183     pc_init1(ram_size, boot_device,
1184              kernel_filename, kernel_cmdline,
1185              initrd_filename, 0, cpu_model);
1186 }
1187
1188 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1189    BIOS will read it and start S3 resume at POST Entry */
1190 void cmos_set_s3_resume(void)
1191 {
1192     if (rtc_state)
1193         rtc_set_memory(rtc_state, 0xF, 0xFE);
1194 }
1195
1196 QEMUMachine pc_machine = {
1197     .name = "pc",
1198     .desc = "Standard PC",
1199     .init = pc_init_pci,
1200     .max_cpus = 255,
1201 };
1202
1203 QEMUMachine isapc_machine = {
1204     .name = "isapc",
1205     .desc = "ISA-only PC",
1206     .init = pc_init_isa,
1207     .max_cpus = 1,
1208 };