2 * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
6 * With: Michel Pollet <buserror@gmail.com>
8 * This code is licenced under the GNU GPL v2.
12 #include "qemu-timer.h"
13 #include "qemu-char.h"
22 /* Interrupt controller */
23 struct s3c_pic_state_s
{
24 target_phys_addr_t base
;
38 static void s3c_pic_update(struct s3c_pic_state_s
*s
)
40 qemu_set_irq(s
->parent_pic
[ARM_PIC_CPU_FIQ
],
41 s
->srcpnd
& s
->intmod
);
42 qemu_set_irq(s
->parent_pic
[ARM_PIC_CPU_IRQ
],
43 s
->intpnd
& ~s
->intmsk
& ~s
->intmod
);
47 * Performs interrupt arbitration and notifies the CPU.
49 * Since it's a complex logic which cannot be relied on by the OS
50 * anyway - first because real hardware doesn't do it accurately,
51 * second because it only matters when interrupts occur at the
52 * same time which normally can't be predicted - we use a simpler
53 * version for non-debug runs.
56 static const uint32_t s3c_arbmsk
[6] = {
65 # define S3C_ARB_SEL(i) ((s->priority >> (7 + (i << 1))) & 3)
66 # define S3C_ARB_MODE(i) ((s->priority >> i) & 1)
67 # define S3C_ARB_SEL_SET(i, v) \
68 s->priority &= ~(3 << (7 + (i << 1))); \
69 s->priority |= v << (7 + (i << 1));
71 static void s3c_pic_arbitrate(struct s3c_pic_state_s
*s
)
73 uint32_t pnd
= s
->srcpnd
& ~s
->intmsk
& ~s
->intmod
;
75 if (s
->intpnd
|| !pnd
) {
80 if (pnd
& s3c_arbmsk
[0]) {
83 } else if (pnd
& 0x0ffffff0) {
86 if (!(pnd
& s3c_arbmsk
[1 + (i
& 3)]))
87 if (!(pnd
& s3c_arbmsk
[1 + (++ i
& 3)]))
88 if (!(pnd
& s3c_arbmsk
[1 + (++ i
& 3)]))
92 S3C_ARB_SEL_SET(6, ((i
+ 1) & 3));
93 offset
= (i
& 3) * 6 + 4;
94 if (pnd
& (1 << offset
))
96 else if (!(pnd
& (0x1f << offset
))) {
108 i
= S3C_ARB_SEL(arb
);
110 if (!(pnd
& (1 << (i
& 3))))
111 if (!(pnd
& (1 << (++ i
& 3))))
112 if (!(pnd
& (1 << (++ i
& 3))))
115 if (S3C_ARB_MODE(arb
))
116 S3C_ARB_SEL_SET(arb
, ((i
+ 1) & 3));
119 s
->intoffset
= offset
;
120 s
->intpnd
= 1 << offset
;
124 inline static void s3c_pic_arbitrate(struct s3c_pic_state_s
*s
)
126 uint32_t pnd
= s
->srcpnd
& ~s
->intmsk
& ~s
->intmod
;
127 if (pnd
&& !s
->intpnd
)
128 s
->intpnd
= 1 << (s
->intoffset
= ffs(pnd
) - 1);
133 static const int s3c_sub_src_map
[] = {
134 [S3C_PICS_RXD0
& 31] = S3C_PIC_UART0
,
135 [S3C_PICS_TXD0
& 31] = S3C_PIC_UART0
,
136 [S3C_PICS_ERR0
& 31] = S3C_PIC_UART0
,
137 [S3C_PICS_RXD1
& 31] = S3C_PIC_UART1
,
138 [S3C_PICS_TXD1
& 31] = S3C_PIC_UART1
,
139 [S3C_PICS_ERR1
& 31] = S3C_PIC_UART1
,
140 [S3C_PICS_RXD2
& 31] = S3C_PIC_UART2
,
141 [S3C_PICS_TXD2
& 31] = S3C_PIC_UART2
,
142 [S3C_PICS_ERR2
& 31] = S3C_PIC_UART2
,
143 [S3C_PICS_TC
& 31] = S3C_PIC_ADC
,
144 [S3C_PICS_ADC
& 31] = S3C_PIC_ADC
,
147 static void s3c_pic_subupdate(struct s3c_pic_state_s
*s
)
150 const int *sub
= &s3c_sub_src_map
[-1];
151 uint32_t pnd
= s
->subsrcpnd
& ~s
->intsubmsk
;
152 while ((next
= ffs(pnd
))) {
155 s
->srcpnd
|= 1 << *sub
;
157 s3c_pic_arbitrate(s
);
160 static void s3c_pic_set_irq(void *opaque
, int irq
, int req
)
162 struct s3c_pic_state_s
*s
= (struct s3c_pic_state_s
*) opaque
;
164 /* This interrupt controller doesn't clear any request signals
165 * or register bits automatically. */
171 s
->subsrcpnd
|= 1 << irq
;
172 if (s
->intsubmsk
& (1 << irq
))
175 irq
= s3c_sub_src_map
[irq
];
177 s
->srcpnd
|= (mask
= 1 << irq
);
180 if (s
->intmod
& mask
)
181 qemu_irq_raise(s
->parent_pic
[ARM_PIC_CPU_FIQ
]);
182 else if (!s
->intpnd
&& !(s
->intmsk
& mask
)) {
184 s3c_pic_arbitrate(s
);
188 qemu_irq_raise(s
->parent_pic
[ARM_PIC_CPU_IRQ
]);
193 static void s3c_pic_reset(struct s3c_pic_state_s
*s
)
197 s
->intmsk
= 0xffffffff;
202 s
->intsubmsk
= 0x7ff;
206 #define S3C_SRCPND 0x00 /* Source Pending register */
207 #define S3C_INTMOD 0x04 /* Source Mode register */
208 #define S3C_INTMSK 0x08 /* Interrupt Mask register */
209 #define S3C_PRIORITY 0x0c /* Priority register */
210 #define S3C_INTPND 0x10 /* Interrupt Pending register */
211 #define S3C_INTOFFSET 0x14 /* Interrupt Offset register */
212 #define S3C_SUBSRCPND 0x18 /* Sub Source Pending register */
213 #define S3C_INTSUBMSK 0x1c /* Interrupt Sub Mask register */
215 static uint32_t s3c_pic_read(void *opaque
, target_phys_addr_t addr
)
217 struct s3c_pic_state_s
*s
= (struct s3c_pic_state_s
*) opaque
;
237 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
243 static void s3c_pic_write(void *opaque
, target_phys_addr_t addr
,
246 struct s3c_pic_state_s
*s
= (struct s3c_pic_state_s
*) opaque
;
251 if (value
& s
->intmod
)
255 if (s
->intpnd
& value
) {
258 s3c_pic_arbitrate(s
);
263 if (s
->intpnd
& value
) {
267 s3c_pic_arbitrate(s
);
276 s
->subsrcpnd
&= ~value
;
279 s
->intsubmsk
= value
;
280 s3c_pic_subupdate(s
);
283 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
287 static CPUReadMemoryFunc
*s3c_pic_readfn
[] = {
293 static CPUWriteMemoryFunc
*s3c_pic_writefn
[] = {
299 static void s3c_pic_save(QEMUFile
*f
, void *opaque
)
301 struct s3c_pic_state_s
*s
= (struct s3c_pic_state_s
*) opaque
;
302 qemu_put_be32s(f
, &s
->srcpnd
);
303 qemu_put_be32s(f
, &s
->intpnd
);
304 qemu_put_be32s(f
, &s
->intmsk
);
305 qemu_put_be32s(f
, &s
->intmod
);
306 qemu_put_be32s(f
, &s
->priority
);
307 qemu_put_be32s(f
, &s
->subsrcpnd
);
308 qemu_put_be32s(f
, &s
->intsubmsk
);
309 qemu_put_be32(f
, s
->intoffset
);
312 static int s3c_pic_load(QEMUFile
*f
, void *opaque
, int version_id
)
314 struct s3c_pic_state_s
*s
= (struct s3c_pic_state_s
*) opaque
;
315 qemu_get_be32s(f
, &s
->srcpnd
);
316 qemu_get_be32s(f
, &s
->intpnd
);
317 qemu_get_be32s(f
, &s
->intmsk
);
318 qemu_get_be32s(f
, &s
->intmod
);
319 qemu_get_be32s(f
, &s
->priority
);
320 qemu_get_be32s(f
, &s
->subsrcpnd
);
321 qemu_get_be32s(f
, &s
->intsubmsk
);
322 s
->intoffset
= qemu_get_be32(f
);
327 struct s3c_pic_state_s
*s3c_pic_init(target_phys_addr_t base
,
331 struct s3c_pic_state_s
*s
= (struct s3c_pic_state_s
*)
332 qemu_mallocz(sizeof(struct s3c_pic_state_s
));
335 s
->parent_pic
= arm_pic
;
336 s
->irqs
= qemu_allocate_irqs(s3c_pic_set_irq
, s
, S3C_PIC_MAX
);
340 iomemtype
= cpu_register_io_memory(0, s3c_pic_readfn
,
342 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
344 register_savevm("s3c24xx_pic", 0, 0, s3c_pic_save
, s3c_pic_load
, s
);
349 qemu_irq
*s3c_pic_get(struct s3c_pic_state_s
*s
)
354 /* Memory controller */
355 #define S3C_BWSCON 0x00 /* Bus Width & Wait Control register */
356 #define S3C_BANKCON0 0x04 /* Bank 0 Control register */
357 #define S3C_BANKCON1 0x08 /* Bank 1 Control register */
358 #define S3C_BANKCON2 0x0c /* Bank 2 Control register */
359 #define S3C_BANKCON3 0x10 /* Bank 3 Control register */
360 #define S3C_BANKCON4 0x14 /* Bank 4 Control register */
361 #define S3C_BANKCON5 0x18 /* Bank 5 Control register */
362 #define S3C_BANKCON6 0x1c /* Bank 6 Control register */
363 #define S3C_BANKCON7 0x20 /* Bank 7 Control register */
364 #define S3C_REFRESH 0x24 /* SDRAM Refresh Control register */
365 #define S3C_BANKSIZE 0x28 /* Flexible Bank Size register */
366 #define S3C_MRSRB6 0x2c /* Bank 6 Mode Set register */
367 #define S3C_MRSRB7 0x30 /* Bank 6 Mode Set register */
369 static void s3c_mc_reset(struct s3c_state_s
*s
)
371 s
->mc_regs
[S3C_BWSCON
>> 2] = 0x0000000;
372 s
->mc_regs
[S3C_BANKCON0
>> 2] = 0x0700;
373 s
->mc_regs
[S3C_BANKCON1
>> 2] = 0x0700;
374 s
->mc_regs
[S3C_BANKCON2
>> 2] = 0x0700;
375 s
->mc_regs
[S3C_BANKCON3
>> 2] = 0x0700;
376 s
->mc_regs
[S3C_BANKCON4
>> 2] = 0x0700;
377 s
->mc_regs
[S3C_BANKCON5
>> 2] = 0x0700;
378 s
->mc_regs
[S3C_BANKCON6
>> 2] = 0x18008;
379 s
->mc_regs
[S3C_BANKCON7
>> 2] = 0x18008;
380 s
->mc_regs
[S3C_REFRESH
>> 2] = 0xac0000;
381 s
->mc_regs
[S3C_BANKSIZE
>> 2] = 0x2;
382 s
->mc_regs
[S3C_MRSRB6
>> 2] = 0x00;
383 s
->mc_regs
[S3C_MRSRB7
>> 2] = 0x00;
386 static uint32_t s3c_mc_read(void *opaque
, target_phys_addr_t addr
)
388 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
391 case S3C_BWSCON
... S3C_MRSRB7
:
392 return s
->mc_regs
[addr
>> 2];
394 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
400 static void s3c_mc_write(void *opaque
, target_phys_addr_t addr
,
403 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
406 case S3C_BWSCON
... S3C_MRSRB7
:
407 s
->mc_regs
[addr
>> 2] = value
;
410 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
414 static CPUReadMemoryFunc
*s3c_mc_readfn
[] = {
420 static CPUWriteMemoryFunc
*s3c_mc_writefn
[] = {
426 static void s3c_mc_save(QEMUFile
*f
, void *opaque
)
428 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
430 for (i
= 0; i
< 13; i
++)
431 qemu_put_be32s(f
, &s
->mc_regs
[i
]);
434 static int s3c_mc_load(QEMUFile
*f
, void *opaque
, int version_id
)
436 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
438 for (i
= 0; i
< 13; i
++)
439 qemu_get_be32s(f
, &s
->mc_regs
[i
]);
443 /* Clock & power management */
444 #define S3C_LOCKTIME 0x00 /* PLL Lock Time Count register */
445 #define S3C_MPLLCON 0x04 /* MPLL Configuration register */
446 #define S3C_UPLLCON 0x08 /* UPLL Configuration register */
447 #define S3C_CLKCON 0x0c /* Clock Generator Control register */
448 #define S3C_CLKSLOW 0x10 /* Slow Clock Control register */
449 #define S3C_CLKDIVN 0x14 /* Clock Divider Control register */
451 #define S3C2440_CAMDIVN 0x18 /* Camera Clock Divider register */
453 static void s3c_clkpwr_update(struct s3c_state_s
*s
)
455 uint32_t mpll
[2] = { s
->clkpwr_regs
[S3C_MPLLCON
>> 2], s
->clkpwr_regs
[S3C_UPLLCON
>> 2] };
459 for (i
= 0; i
< 2; i
++) {
460 uint32_t mdiv
= ((mpll
[i
] >> 12) & 0xff) + 8,
461 pdiv
= ((mpll
[i
] >> 4) & 0x3f) + 2,
462 sdiv
= (mpll
[i
]) & 0x3;
463 clk
[i
] = (mdiv
* s
->clock
.xtal
* 2) / (pdiv
* (1 << sdiv
));
466 s
->clock
.clk
= clk
[0];
467 uint32_t ratio
= s
->clkpwr_regs
[S3C_CLKDIVN
>> 2];
469 switch( (ratio
& 0x6) >> 1 ) {
471 s
->clock
.hclk
= s
->clock
.clk
;
474 s
->clock
.hclk
= s
->clock
.clk
/2;
477 s
->clock
.hclk
= s
->clock
.clk
/4;
480 s
->clock
.hclk
= s
->clock
.clk
/3;
483 switch ( ratio
&0x1) {
485 s
->clock
.pclk
= s
->clock
.hclk
;
488 s
->clock
.pclk
= s
->clock
.hclk
/2;
491 s
->clock
.uclk
= clk
[1] / 2;
493 printf("S3C: CLK=%d HCLK=%d PCLK=%d UCLK=%d\n",
494 s
->clock
.clk
/MHZ
, s
->clock
.hclk
/MHZ
, s
->clock
.pclk
/MHZ
,
498 static void s3c_clkpwr_reset(struct s3c_state_s
*s
)
500 s
->clkpwr_regs
[S3C_LOCKTIME
>> 2] = 0x00ffffff;
501 s
->clkpwr_regs
[S3C_MPLLCON
>> 2] = 0x0005c080;
502 s
->clkpwr_regs
[S3C_UPLLCON
>> 2] = 0x00028080;
503 s
->clkpwr_regs
[S3C_CLKCON
>> 2] = 0x0007fff0;
504 s
->clkpwr_regs
[S3C_CLKSLOW
>> 2] = 0x00000004;
505 s
->clkpwr_regs
[S3C_CLKDIVN
>> 2] = 0x00000000;
506 s
->clkpwr_regs
[S3C2440_CAMDIVN
>> 2] = 0x00000000;
507 s3c_clkpwr_update(s
);
510 static uint32_t s3c_clkpwr_read(void *opaque
, target_phys_addr_t addr
)
512 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
515 case S3C_LOCKTIME
... S3C_CLKDIVN
:
516 return s
->clkpwr_regs
[addr
>> 2];
517 case S3C2440_CAMDIVN
:
518 if (s
->cpu_id
== S3C_CPU_2440
)
519 return s
->clkpwr_regs
[addr
>> 2];
521 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
527 static void s3c_clkpwr_write(void *opaque
, target_phys_addr_t addr
,
530 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
537 s
->clkpwr_regs
[addr
>> 2] = value
;
538 if (addr
!= S3C_LOCKTIME
)
539 s3c_clkpwr_update(s
);
542 if (value
& (1 << 3)) {
543 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
544 printf("%s: processor powered off\n", __FUNCTION__
);
545 s3c_gpio_setpwrstat(s
->io
, 2);
548 s
->env
->regs
[15] = 0; /* XXX */
551 if (value
& (1 << 2)) /* Normal IDLE mode */
552 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
553 if ((s
->clkpwr_regs
[addr
>> 2] ^ value
) & 1)
554 printf("%s: SPECIAL mode %s\n", __FUNCTION__
,
555 (value
& 1) ? "on" : "off");
556 s
->clkpwr_regs
[addr
>> 2] = value
;
559 if ((s
->clkpwr_regs
[addr
>> 2] ^ value
) & (1 << 4))
560 printf("%s: SLOW mode %s\n", __FUNCTION__
,
561 (value
& (1 << 4)) ? "on" : "off");
562 s
->clkpwr_regs
[addr
>> 2] = value
;
564 case S3C2440_CAMDIVN
:
565 if (s
->cpu_id
== S3C_CPU_2440
) {
566 s
->clkpwr_regs
[addr
>> 2] = value
;
570 printf("%s: Bad register 0x%x (cpu %08x)\n", __FUNCTION__
, /*(unsigned long)*/addr
, s
->cpu_id
);
574 static CPUReadMemoryFunc
*s3c_clkpwr_readfn
[] = {
580 static CPUWriteMemoryFunc
*s3c_clkpwr_writefn
[] = {
586 static void s3c_clkpwr_save(QEMUFile
*f
, void *opaque
)
588 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
590 for (i
= 0; i
< 7; i
++)
591 qemu_put_be32s(f
, &s
->clkpwr_regs
[i
]);
594 static int s3c_clkpwr_load(QEMUFile
*f
, void *opaque
, int version_id
)
596 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
598 for (i
= 0; i
< 7; i
++)
599 qemu_get_be32s(f
, &s
->clkpwr_regs
[i
]);
604 #define S3C_DMA_CH_N 4
606 struct s3c_dma_ch_state_s
;
607 struct s3c_dma_state_s
{ /* Modelled as an interrupt controller */
608 target_phys_addr_t base
;
610 struct s3c_dma_ch_state_s
{
626 static inline void s3c_dma_ch_run(struct s3c_dma_state_s
*s
,
627 struct s3c_dma_ch_state_s
*ch
)
631 width
= 1 << ((ch
->con
>> 20) & 3); /* DSZ */
632 burst
= (ch
->con
& (1 << 28)) ? 4 : 1; /* TSZ */
634 while (!ch
->running
&& ch
->curr_tc
> 0 && ch
->req
&&
635 (ch
->mask
& (1 << 1))) { /* ON_OFF */
636 if (width
> sizeof(buffer
)) {
637 printf("%s: wrong access width\n", __FUNCTION__
);
641 while (ch
->curr_tc
--) {
642 for (t
= 0; t
< burst
; t
++) {
643 cpu_physical_memory_read(ch
->csrc
, buffer
, width
);
644 cpu_physical_memory_write(ch
->cdst
, buffer
, width
);
646 if (!(ch
->isrcc
& 1)) /* INT */
648 if (!(ch
->idstc
& 1)) /* INT */
652 if (!(ch
->con
& (1 << 27)) && !ch
->req
) /* SERVMODE */
657 if (!(ch
->con
& (1 << 23))) { /* SWHW_SEL */
661 if (ch
->curr_tc
<= 0) {
662 if (ch
->con
& (1 << 22)) /* RELOAD */
663 ch
->mask
&= ~(1 << 1); /* ON_OFF */
665 if (!(ch
->con
& (1 << 23))) { /* SWHW_SEL */
666 printf("%s: auto-reload software controlled transfer\n",
670 ch
->csrc
= ch
->isrc
; /* S_ADDR */
671 ch
->cdst
= ch
->idst
; /* D_ADDR */
672 ch
->curr_tc
= ch
->con
& 0xfffff; /* TC */
673 ch
->con
|= 1 << 22; /* ON_OFF */
676 if (ch
->con
& (1 << 31)) /* DMD_HS */
679 if (ch
->con
& (1 << 29)) { /* INT */
680 qemu_irq_raise(ch
->intr
);
681 /* Give the system a chance to respond. */
688 static void s3c_dma_reset(struct s3c_dma_state_s
*s
)
691 for (i
= 0; i
< S3C_DMA_CH_N
; i
++) {
692 s
->ch
[i
].curr_tc
= 0;
706 static void s3c_dma_dreq(void *opaque
, int line
, int req
)
708 struct s3c_dma_state_s
*s
= (struct s3c_dma_state_s
*) opaque
;
709 struct s3c_dma_ch_state_s
*ch
= &s
->ch
[line
>> 4];
711 if (ch
->con
& (1 << 23)) /* SWHW_SEL */
712 if (((ch
->con
>> 24) & 7) == (line
& 7)) { /* HWSRCSEL */
714 s3c_dma_ch_run(s
, ch
);
718 #define S3C_DISRC 0x00 /* DMA Initial Source register */
719 #define S3C_DISRCC 0x04 /* DMA Initial Source Control register */
720 #define S3C_DIDST 0x08 /* DMA Initial Destination register */
721 #define S3C_DIDSTC 0x0c /* DMA Initial Destination Control register */
722 #define S3C_DCON 0x10 /* DMA Control register */
723 #define S3C_DSTAT 0x14 /* DMA Count register */
724 #define S3C_DCSRC 0x18 /* DMA Current Source register */
725 #define S3C_DCDST 0x1c /* DMA Current Destination register */
726 #define S3C_DMASKTRIG 0x20 /* DMA Mask Trigger register */
728 static uint32_t s3c_dma_read(void *opaque
, target_phys_addr_t addr
)
730 struct s3c_dma_state_s
*s
= (struct s3c_dma_state_s
*) opaque
;
731 struct s3c_dma_ch_state_s
*ch
= 0;
733 if (addr
>= 0 && addr
<= (S3C_DMA_CH_N
<< 6)) {
734 ch
= &s
->ch
[addr
>> 6];
758 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
764 static void s3c_dma_write(void *opaque
, target_phys_addr_t addr
,
767 struct s3c_dma_state_s
*s
= (struct s3c_dma_state_s
*) opaque
;
768 struct s3c_dma_ch_state_s
*ch
= 0;
770 if (addr
>= 0 && addr
<= (S3C_DMA_CH_N
<< 6)) {
771 ch
= &s
->ch
[addr
>> 6];
792 if (~ch
->mask
& value
& (1 << 1)) { /* ON_OFF */
793 ch
->curr_tc
= ch
->con
& 0xfffff; /* TC */
794 ch
->csrc
= ch
->isrc
; /* S_ADDR */
795 ch
->cdst
= ch
->idst
; /* D_ADDR */
799 if (value
& (1 << 2)) { /* STOP */
800 ch
->mask
&= ~(3 << 1); /* ON_OFF */
801 } else if (!(ch
->con
& (1 << 23))) { /* SWHW_SEL */
802 ch
->req
= value
& 1; /* SW_TRIG */
803 s3c_dma_ch_run(s
, ch
);
807 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
811 static CPUReadMemoryFunc
*s3c_dma_readfn
[] = {
817 static CPUWriteMemoryFunc
*s3c_dma_writefn
[] = {
823 static void s3c_dma_save(QEMUFile
*f
, void *opaque
)
825 struct s3c_dma_state_s
*s
= (struct s3c_dma_state_s
*) opaque
;
827 for (i
= 0; i
< S3C_DMA_CH_N
; i
++) {
828 qemu_put_be32(f
, s
->ch
[i
].curr_tc
);
829 qemu_put_be32(f
, s
->ch
[i
].req
);
830 qemu_put_be32s(f
, &s
->ch
[i
].con
);
831 qemu_put_be32s(f
, &s
->ch
[i
].isrc
);
832 qemu_put_be32s(f
, &s
->ch
[i
].isrcc
);
833 qemu_put_be32s(f
, &s
->ch
[i
].idst
);
834 qemu_put_be32s(f
, &s
->ch
[i
].idstc
);
835 qemu_put_be32s(f
, &s
->ch
[i
].csrc
);
836 qemu_put_be32s(f
, &s
->ch
[i
].cdst
);
837 qemu_put_be32s(f
, &s
->ch
[i
].mask
);
841 static int s3c_dma_load(QEMUFile
*f
, void *opaque
, int version_id
)
843 struct s3c_dma_state_s
*s
= (struct s3c_dma_state_s
*) opaque
;
845 for (i
= 0; i
< S3C_DMA_CH_N
; i
++) {
846 s
->ch
[i
].curr_tc
= qemu_get_be32(f
);
847 s
->ch
[i
].req
= qemu_get_be32(f
);
848 qemu_get_be32s(f
, &s
->ch
[i
].con
);
849 qemu_get_be32s(f
, &s
->ch
[i
].isrc
);
850 qemu_get_be32s(f
, &s
->ch
[i
].isrcc
);
851 qemu_get_be32s(f
, &s
->ch
[i
].idst
);
852 qemu_get_be32s(f
, &s
->ch
[i
].idstc
);
853 qemu_get_be32s(f
, &s
->ch
[i
].csrc
);
854 qemu_get_be32s(f
, &s
->ch
[i
].cdst
);
855 qemu_get_be32s(f
, &s
->ch
[i
].mask
);
860 struct s3c_dma_state_s
*s3c_dma_init(target_phys_addr_t base
, qemu_irq
*pic
)
863 struct s3c_dma_state_s
*s
= (struct s3c_dma_state_s
*)
864 qemu_mallocz(sizeof(struct s3c_dma_state_s
));
867 s
->ch
[0].intr
= pic
[0];
868 s
->ch
[1].intr
= pic
[1];
869 s
->ch
[2].intr
= pic
[2];
870 s
->ch
[3].intr
= pic
[3];
871 s
->drqs
= qemu_allocate_irqs(s3c_dma_dreq
, s
, S3C_RQ_MAX
);
875 iomemtype
= cpu_register_io_memory(0, s3c_dma_readfn
,
877 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
879 register_savevm("s3c24xx_dma", 0, 0, s3c_dma_save
, s3c_dma_load
, s
);
884 qemu_irq
*s3c_dma_get(struct s3c_dma_state_s
*s
)
889 /* PWM timers controller */
890 struct s3c_timer_state_s
;
891 struct s3c_timers_state_s
{
892 struct s3c_freq_s
* freq
;
893 target_phys_addr_t base
;
896 struct s3c_timer_state_s
{
898 struct s3c_timers_state_s
*s
;
905 gpio_handler_t cmp_cb
;
909 uint16_t compareb
[4];
915 static const int s3c_tm_bits
[] = { 0, 8, 12, 16, 20 };
917 static uint16_t s3c_timers_get(struct s3c_timers_state_s
*s
, int tm
)
920 if (!s
->timer
[tm
].running
)
921 return s
->timer
[tm
].count
;
923 elapsed
= muldiv64(qemu_get_clock(vm_clock
) - s
->timer
[tm
].reload
,
924 s
->timer
[tm
].divider
, ticks_per_sec
);
925 if (unlikely(elapsed
> s
->timer
[tm
].count
))
926 return s
->timer
[tm
].count
;
928 return s
->timer
[tm
].count
- elapsed
;
931 static void s3c_timers_stop(struct s3c_timers_state_s
*s
, int tm
)
933 s
->timer
[tm
].count
= s3c_timers_get(s
, tm
);
934 s
->timer
[tm
].running
= 0;
937 static void s3c_timers_start(struct s3c_timers_state_s
*s
, int tm
)
939 if (s
->timer
[tm
].running
)
942 s
->timer
[tm
].divider
= s
->freq
->pclk
>>
943 (((s
->config
[1] >> (tm
* 4)) & 3) + 1);
945 s
->timer
[tm
].divider
/= ((s
->config
[0] >> 0) & 0xff) + 1;
947 s
->timer
[tm
].divider
/= ((s
->config
[0] >> 8) & 0xff) + 1;
948 s
->timer
[tm
].running
= 1;
949 s
->timer
[tm
].reload
= qemu_get_clock(vm_clock
);
950 qemu_mod_timer(s
->timer
[tm
].t
,
951 s
->timer
[tm
].reload
+ muldiv64(s
->timer
[tm
].count
,
952 ticks_per_sec
, s
->timer
[tm
].divider
));
955 static void s3c_timers_reset(struct s3c_timers_state_s
*s
)
958 s
->config
[0] = 0x00000000;
959 s
->config
[1] = 0x00000000;
960 s
->control
= 0x00000000;
962 for (i
= 0; i
< 5; i
++) {
963 if (s
->timer
[i
].running
)
964 s3c_timers_stop(s
, i
);
965 s
->countb
[i
] = 0x0000;
966 s
->timer
[i
].count
= 0;
968 for (i
= 0; i
< 4; i
++)
969 s
->compareb
[i
] = 0x0000;
972 static void s3c_timers_tick(void *opaque
)
974 struct s3c_timer_state_s
*t
= (struct s3c_timer_state_s
*) opaque
;
975 struct s3c_timers_state_s
*s
= t
->s
;
979 if (((s
->config
[1] >> 20) & 0xf) == t
->n
+ 1) {
980 qemu_irq_raise(s
->dma
[S3C_RQ_TIMER0
]); /* TODO */
981 qemu_irq_raise(s
->dma
[S3C_RQ_TIMER1
]);
982 qemu_irq_raise(s
->dma
[S3C_RQ_TIMER2
]);
984 qemu_irq_raise(t
->irq
);
989 if (s
->control
& (1 << ((t
->n
== 4) ? 22 : (s3c_tm_bits
[t
->n
] + 3)))) {
991 t
->count
= s
->countb
[t
->n
];
992 s3c_timers_start(s
, t
->n
);
994 s
->control
&= ~(1 << s3c_tm_bits
[t
->n
]);
997 #define S3C_TCFG0 0x00 /* Timer Configuration register 0 */
998 #define S3C_TCFG1 0x04 /* Timer Configuration register 1 */
999 #define S3C_TCON 0x08 /* Timer Control register */
1000 #define S3C_TCNTB0 0x0c /* Timer 0 Count Buffer register */
1001 #define S3C_TCMPB0 0x10 /* Timer 0 Compare Buffer register */
1002 #define S3C_TCNTO0 0x14 /* Timer 0 Count Observation register */
1003 #define S3C_TCNTB1 0x18 /* Timer 1 Count Buffer register */
1004 #define S3C_TCMPB1 0x1c /* Timer 1 Compare Buffer register */
1005 #define S3C_TCNTO1 0x20 /* Timer 1 Count Observation register */
1006 #define S3C_TCNTB2 0x24 /* Timer 2 Count Buffer register */
1007 #define S3C_TCMPB2 0x28 /* Timer 2 Compare Buffer register */
1008 #define S3C_TCNTO2 0x2c /* Timer 2 Count Observation register */
1009 #define S3C_TCNTB3 0x30 /* Timer 3 Count Buffer register */
1010 #define S3C_TCMPB3 0x34 /* Timer 3 Compare Buffer register */
1011 #define S3C_TCNTO3 0x38 /* Timer 3 Count Observation register */
1012 #define S3C_TCNTB4 0x3c /* Timer 4 Count Buffer register */
1013 #define S3C_TCNTO4 0x40 /* Timer 4 Count Observation register */
1015 static uint32_t s3c_timers_read(void *opaque
, target_phys_addr_t addr
)
1017 struct s3c_timers_state_s
*s
= (struct s3c_timers_state_s
*) opaque
;
1022 return s
->config
[0];
1024 return s
->config
[1];
1027 case S3C_TCMPB3
: tm
++;
1028 case S3C_TCMPB2
: tm
++;
1029 case S3C_TCMPB1
: tm
++;
1031 return s
->compareb
[tm
];
1032 case S3C_TCNTB4
: tm
++;
1033 case S3C_TCNTB3
: tm
++;
1034 case S3C_TCNTB2
: tm
++;
1035 case S3C_TCNTB1
: tm
++;
1037 return s
->countb
[tm
];
1038 case S3C_TCNTO4
: tm
++;
1039 case S3C_TCNTO3
: tm
++;
1040 case S3C_TCNTO2
: tm
++;
1041 case S3C_TCNTO1
: tm
++;
1043 return s3c_timers_get(s
, tm
);
1045 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1051 static void s3c_timers_write(void *opaque
, target_phys_addr_t addr
,
1054 struct s3c_timers_state_s
*s
= (struct s3c_timers_state_s
*) opaque
;
1059 s
->config
[0] = value
& 0x00ffffff;
1062 s
->config
[1] = value
& 0x00ffffff;
1065 for (tm
= 0; tm
< 5; tm
++) {
1066 if (value
& (2 << (s3c_tm_bits
[tm
]))) {
1067 if (s
->timer
[tm
].running
) {
1068 s3c_timers_stop(s
, tm
);
1069 s
->timer
[tm
].count
= s
->countb
[tm
];
1070 s3c_timers_start(s
, tm
);
1072 s
->timer
[tm
].count
= s
->countb
[tm
];
1074 if (((value
>> s3c_tm_bits
[tm
]) & 1) ^ s
->timer
[tm
].running
) {
1075 if (s
->timer
[tm
].running
)
1076 s3c_timers_stop(s
, tm
);
1078 s3c_timers_start(s
, tm
);
1082 s
->control
= value
& 0x007fff1f;
1084 case S3C_TCMPB3
: tm
++;
1085 case S3C_TCMPB2
: tm
++;
1086 case S3C_TCMPB1
: tm
++;
1088 s
->compareb
[tm
] = value
& 0xffff;
1089 if (s
->timer
[tm
].cmp_cb
)
1090 s
->timer
[tm
].cmp_cb(tm
, s
->compareb
[tm
], s
->timer
[tm
].cmp_opaque
);
1092 case S3C_TCNTB4
: tm
++;
1093 case S3C_TCNTB3
: tm
++;
1094 case S3C_TCNTB2
: tm
++;
1095 case S3C_TCNTB1
: tm
++;
1097 s
->countb
[tm
] = value
& 0xffff;
1100 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1104 static CPUReadMemoryFunc
*s3c_timers_readfn
[] = {
1110 static CPUWriteMemoryFunc
*s3c_timers_writefn
[] = {
1116 static void s3c_timers_save(QEMUFile
*f
, void *opaque
)
1118 struct s3c_timers_state_s
*s
= (struct s3c_timers_state_s
*) opaque
;
1120 for (i
= 0; i
< 5; i
++) {
1121 qemu_put_be32(f
, s
->timer
[i
].running
);
1122 qemu_put_be32s(f
, &s
->timer
[i
].divider
);
1123 qemu_put_be16(f
, s3c_timers_get(s
, i
));
1124 qemu_put_sbe64s(f
, &s
->timer
[i
].reload
);
1127 for (i
= 0; i
< 4; i
++)
1128 qemu_put_be16s(f
, &s
->compareb
[i
]);
1129 for (i
= 0; i
< 5; i
++)
1130 qemu_put_be16s(f
, &s
->countb
[i
]);
1131 for (i
= 0; i
< 2; i
++)
1132 qemu_put_be32s(f
, &s
->config
[i
]);
1133 qemu_put_be32s(f
, &s
->control
);
1136 static int s3c_timers_load(QEMUFile
*f
, void *opaque
, int version_id
)
1138 struct s3c_timers_state_s
*s
= (struct s3c_timers_state_s
*) opaque
;
1140 for (i
= 0; i
< 5; i
++) {
1141 s
->timer
[i
].running
= 0;
1142 running
[i
] = qemu_get_be32(f
);
1143 qemu_get_be32s(f
, &s
->timer
[i
].divider
);
1144 qemu_get_be16s(f
, &s
->timer
[i
].count
);
1145 qemu_get_sbe64s(f
, &s
->timer
[i
].reload
);
1148 for (i
= 0; i
< 4; i
++)
1149 qemu_get_be16s(f
, &s
->compareb
[i
]);
1150 for (i
= 0; i
< 5; i
++)
1151 qemu_get_be16s(f
, &s
->countb
[i
]);
1152 for (i
= 0; i
< 2; i
++)
1153 qemu_get_be32s(f
, &s
->config
[i
]);
1154 qemu_get_be32s(f
, &s
->control
);
1156 for (i
= 0; i
< 5; i
++)
1158 s3c_timers_start(s
, i
);
1163 struct s3c_timers_state_s
*s3c_timers_init(struct s3c_freq_s
* freq
, target_phys_addr_t base
,
1164 qemu_irq
*pic
, qemu_irq
*dma
)
1167 struct s3c_timers_state_s
*s
= (struct s3c_timers_state_s
*)
1168 qemu_mallocz(sizeof(struct s3c_timers_state_s
));
1174 s3c_timers_reset(s
);
1176 for (i
= 0; i
< 5; i
++) {
1177 s
->timer
[i
].t
= qemu_new_timer(vm_clock
,
1178 s3c_timers_tick
, &s
->timer
[i
]);
1181 s
->timer
[i
].cmp_cb
= 0;
1182 s
->timer
[i
].irq
= pic
[i
];
1185 iomemtype
= cpu_register_io_memory(0, s3c_timers_readfn
,
1186 s3c_timers_writefn
, s
);
1187 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
1189 register_savevm("s3c24xx_timers", 0, 0,
1190 s3c_timers_save
, s3c_timers_load
, s
);
1195 void s3c_timers_cmp_handler_set(void *opaque
, int line
,
1196 gpio_handler_t handler
, void *cmp_opaque
)
1198 struct s3c_timers_state_s
*s
= (struct s3c_timers_state_s
*) opaque
;
1199 if (line
> 4 || line
< 0) {
1200 printf("%s: Bad timer number %i.\n", __FUNCTION__
, line
);
1203 s
->timer
[line
].cmp_cb
= handler
;
1204 s
->timer
[line
].cmp_opaque
= cmp_opaque
;
1208 struct s3c_uart_state_s
{
1209 struct s3c_freq_s
* freq
;
1210 target_phys_addr_t base
;
1217 #define UART_MAX_CHR 4
1219 CharDriverState
*chr
[UART_MAX_CHR
];
1229 static void s3c_uart_reset(struct s3c_uart_state_s
*s
)
1234 s
->control
= 0x0000;
1241 static void s3c_uart_err(struct s3c_uart_state_s
*s
, int err
)
1244 if (s
->control
& (1 << 6))
1245 qemu_irq_raise(s
->irq
[2]);
1248 inline static void s3c_uart_full(struct s3c_uart_state_s
*s
, int pulse
)
1250 if (s
->fcontrol
& 1) /* FIFOEnable */
1251 if (s
->rxlen
< (((s
->fcontrol
>> 4) & 3) + 1) * 4) {
1252 if (((s
->control
>> 0) & 3) != 1 || /* ReceiveMode */
1255 if (!(s
->control
& (1 << 7))) /* RxTimeOutEnable */
1257 /* When the Rx FIFO trigger level is not reached, the interrupt
1258 * is generated anyway, just after a small timeout instead of
1262 switch ((s
->control
>> 0) & 3) { /* ReceiveMode */
1264 if ((s
->control
& (1 << 8)) || pulse
) /* RxInterruptType */
1265 qemu_irq_raise(s
->irq
[0]);
1269 qemu_irq_raise(s
->dma
[0]);
1274 inline static void s3c_uart_empty(struct s3c_uart_state_s
*s
, int pulse
)
1276 switch ((s
->control
>> 2) & 3) { /* TransmitMode */
1278 if ((s
->control
& (1 << 9)) || pulse
) /* TxInterruptType */
1279 qemu_irq_raise(s
->irq
[1]);
1283 qemu_irq_raise(s
->dma
[0]);
1288 inline static void s3c_uart_update(struct s3c_uart_state_s
*s
)
1290 s3c_uart_empty(s
, 0);
1291 s3c_uart_full(s
, 0);
1294 static void s3c_uart_params_update(struct s3c_uart_state_s
*s
)
1296 QEMUSerialSetParams ssp
;
1301 /* XXX Calculate PCLK frequency from clock manager registers */
1302 ssp
.speed
= (s
->freq
->pclk
>> 4) / (s
->brdiv
+ 1);
1304 switch ((s
->lcontrol
>> 3) & 7) {
1317 ssp
.data_bits
= 5 + (s
->lcontrol
& 3);
1319 ssp
.stop_bits
= (s
->lcontrol
& (1 << 2)) ? 2 : 1;
1321 for (i
= 0; i
< s
->chr_num
; i
++)
1322 qemu_chr_ioctl(s
->chr
[i
], CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1325 static int s3c_uart_is_empty(void *opaque
)
1327 struct s3c_uart_state_s
*s
= (struct s3c_uart_state_s
*) opaque
;
1328 if (s
->fcontrol
& 1) /* FIFOEnable */
1329 return 16 - s
->rxlen
;
1331 return 1 - s
->rxlen
;
1334 static void s3c_uart_rx(void *opaque
, const uint8_t *buf
, int size
)
1336 struct s3c_uart_state_s
*s
= (struct s3c_uart_state_s
*) opaque
;
1338 if (s
->fcontrol
& 1) { /* FIFOEnable */
1339 if (s
->rxlen
+ size
> 16) {
1340 size
= 16 - s
->rxlen
;
1344 left
= 16 - ((s
->rxstart
+ s
->rxlen
) & 15);
1346 memcpy(s
->rxfifo
+ ((s
->rxstart
+ s
->rxlen
) & 15), buf
, left
);
1347 memcpy(s
->rxfifo
, buf
+ left
, size
- left
);
1349 memcpy(s
->rxfifo
+ ((s
->rxstart
+ s
->rxlen
) & 15), buf
, size
);
1352 if (s
->rxlen
+ size
> 1)
1357 s3c_uart_full(s
, 1);
1360 /* S3C2410 UART doesn't seem to understand break conditions. */
1361 static void s3c_uart_event(void *opaque
, int event
)
1365 #define S3C_ULCON 0x00 /* UART Line Control register */
1366 #define S3C_UCON 0x04 /* UART Control register */
1367 #define S3C_UFCON 0x08 /* UART FIFO Control register */
1368 #define S3C_UMCON 0x0c /* UART Modem Control register */
1369 #define S3C_UTRSTAT 0x10 /* UART Tx/Rx Status register */
1370 #define S3C_UERSTAT 0x14 /* UART Error Status register */
1371 #define S3C_UFSTAT 0x18 /* UART FIFO Status register */
1372 #define S3C_UMSTAT 0x1c /* UART Modem Status register */
1373 #define S3C_UTXH 0x20 /* UART Transmit Buffer register */
1374 #define S3C_URXH 0x24 /* UART Receive Buffer register */
1375 #define S3C_UBRDIV 0x28 /* UART Baud Rate Divisor register */
1377 static uint32_t s3c_uart_read(void *opaque
, target_phys_addr_t addr
)
1379 struct s3c_uart_state_s
*s
= (struct s3c_uart_state_s
*) opaque
;
1392 return 6 | !!s
->rxlen
;
1394 /* XXX: UERSTAT[3] is Reserved but Linux thinks it is BREAK */
1401 return s
->rxlen
? s
->rxlen
| (1 << 8) : 0;
1405 case S3C_UTXH
: /* why this is called by u-boot is not clear */
1411 if (s
->fcontrol
& 1) { /* FIFOEnable */
1412 ret
= s
->rxfifo
[s
->rxstart
++];
1422 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1428 static void s3c_uart_write(void *opaque
, target_phys_addr_t addr
,
1431 struct s3c_uart_state_s
*s
= (struct s3c_uart_state_s
*) opaque
;
1437 if ((s
->lcontrol
^ value
) & (1 << 6))
1438 printf("%s: UART Infra-red mode %s\n", __FUNCTION__
,
1439 (value
& (1 << 6)) ? "on" : "off");
1440 s
->lcontrol
= value
;
1441 s3c_uart_params_update(s
);
1445 /* XXX: UCON[4] is Reserved but Linux thinks it is BREAK */
1446 if ((s
->control
^ value
) & (1 << 5))
1447 printf("%s: UART loopback test mode %s\n", __FUNCTION__
,
1448 (value
& (1 << 5)) ? "on" : "off");
1449 s
->control
= value
& 0x7ef;
1453 if (value
& (1 << 1)) /* RxReset */
1455 s
->fcontrol
= value
& 0xf1;
1459 #ifdef CONFIG_S3C_MODEM /* not handled, openmoko modem.c not imported */
1460 if ((s
->mcontrol
^ value
) & (1 << 4)) {
1461 int afc
= (value
>> 4) & 1;
1462 for (i
= 0; i
< s
->chr_num
; i
++)
1463 qemu_chr_ioctl(s
->chr
[i
], CHR_IOCTL_MODEM_HANDSHAKE
, &afc
);
1466 s
->mcontrol
= value
& 0x11;
1471 for (i
= 0; i
< s
->chr_num
; i
++)
1472 qemu_chr_write(s
->chr
[i
], &ch
, 1);
1473 s3c_uart_empty(s
, 1);
1477 s
->brdiv
= value
& 0xffff;
1478 s3c_uart_params_update(s
);
1482 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1486 static CPUReadMemoryFunc
*s3c_uart_readfn
[] = {
1492 static CPUWriteMemoryFunc
*s3c_uart_writefn
[] = {
1498 static void s3c_uart_save(QEMUFile
*f
, void *opaque
)
1500 struct s3c_uart_state_s
*s
= (struct s3c_uart_state_s
*) opaque
;
1501 qemu_put_8s(f
, &s
->data
);
1502 qemu_put_buffer(f
, s
->rxfifo
, sizeof(s
->rxfifo
));
1503 qemu_put_be32(f
, s
->rxstart
);
1504 qemu_put_be32(f
, s
->rxlen
);
1505 qemu_put_8s(f
, &s
->lcontrol
);
1506 qemu_put_8s(f
, &s
->fcontrol
);
1507 qemu_put_8s(f
, &s
->mcontrol
);
1508 qemu_put_be16s(f
, &s
->control
);
1509 qemu_put_be16s(f
, &s
->brdiv
);
1510 qemu_put_8s(f
, &s
->errstat
);
1513 static int s3c_uart_load(QEMUFile
*f
, void *opaque
, int version_id
)
1515 struct s3c_uart_state_s
*s
= (struct s3c_uart_state_s
*) opaque
;
1516 qemu_get_8s(f
, &s
->data
);
1517 qemu_get_buffer(f
, s
->rxfifo
, sizeof(s
->rxfifo
));
1518 s
->rxstart
= qemu_get_be32(f
);
1519 s
->rxlen
= qemu_get_be32(f
);
1520 qemu_get_8s(f
, &s
->lcontrol
);
1521 qemu_get_8s(f
, &s
->fcontrol
);
1522 qemu_get_8s(f
, &s
->mcontrol
);
1523 qemu_get_be16s(f
, &s
->control
);
1524 qemu_get_be16s(f
, &s
->brdiv
);
1525 qemu_get_8s(f
, &s
->errstat
);
1530 struct s3c_uart_state_s
*s3c_uart_init(struct s3c_freq_s
* freq
, target_phys_addr_t base
,
1531 qemu_irq
*irqs
, qemu_irq
*dma
)
1534 struct s3c_uart_state_s
*s
= (struct s3c_uart_state_s
*)
1535 qemu_mallocz(sizeof(struct s3c_uart_state_s
));
1544 iomemtype
= cpu_register_io_memory(0, s3c_uart_readfn
,
1545 s3c_uart_writefn
, s
);
1546 cpu_register_physical_memory(s
->base
, 0xfff, iomemtype
);
1548 register_savevm("s3c24xx_uart", base
, 0, s3c_uart_save
, s3c_uart_load
, s
);
1553 void s3c_uart_attach(struct s3c_uart_state_s
*s
, CharDriverState
*chr
)
1555 if (s
->chr_num
>= UART_MAX_CHR
)
1556 cpu_abort(cpu_single_env
, "%s: Too many devices\n", __FUNCTION__
);
1557 s
->chr
[s
->chr_num
++] = chr
;
1559 qemu_chr_add_handlers(chr
, s3c_uart_is_empty
,
1560 s3c_uart_rx
, s3c_uart_event
, s
);
1563 /* ADC & Touchscreen interface */
1564 struct s3c_adc_state_s
{
1565 target_phys_addr_t base
;
1586 static void s3c_adc_reset(struct s3c_adc_state_s
*s
)
1589 s
->control
= 0x3fc4;
1595 static void s3c_adc_start(struct s3c_adc_state_s
*s
)
1597 if (!s
->enable
|| (s
->ts
& 7) == 0)
1599 s
->control
&= ~(1 << 15);
1600 s
->in_idx
= (s
->control
>> 3) & 7;
1601 qemu_mod_timer(s
->convt
, qemu_get_clock(vm_clock
) + (ticks_per_sec
>> 5));
1604 static void s3c_adc_done(void *opaque
)
1606 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*) opaque
;
1607 s
->xdata
= s
->input
[s
->in_idx
] & 0x3ff;
1608 s
->control
|= 1 << 15;
1609 qemu_irq_raise(s
->irq
);
1612 static void s3c_adc_tick(void *opaque
)
1614 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*) opaque
;
1618 if ((s
->ts
& 3) == 3 && s
->enable
)
1619 qemu_irq_raise(s
->tcirq
);
1620 else if (s
->enable
&& ((s
->ts
& (1 << 2)) || (s
->ts
& 3))) {
1621 sx
= s
->x
* s
->scale
[0] + s
->y
* s
->scale
[1] + s
->scale
[2];
1622 sy
= s
->x
* s
->scale
[3] + s
->y
* s
->scale
[4] + s
->scale
[5];
1623 s
->xdata
= ((sx
>> 13) & 0xfff) | (1 << 14) | ((s
->ts
& 3) << 12);
1624 s
->ydata
= ((sy
>> 13) & 0xfff) | (1 << 14) | ((s
->ts
& 3) << 12);
1625 s
->xdata
^= s
->noise
>> 1;
1626 s
->ydata
^= s
->noise
>> 2;
1627 qemu_irq_raise(s
->irq
);
1631 qemu_mod_timer(s
->tst
, qemu_get_clock(vm_clock
) +
1632 (ticks_per_sec
>> 5));
1636 static void s3c_adc_event(void *opaque
,
1637 int x
, int y
, int z
, int buttons_state
)
1639 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*) opaque
;
1640 s
->down
= !!buttons_state
;
1646 #define S3C_ADCCON 0x00 /* ADC Control register */
1647 #define S3C_ADCTSC 0x04 /* ADC Touchscreen Control register */
1648 #define S3C_ADCDLY 0x08 /* ADC Start or Interval Delay register */
1649 #define S3C_ADCDAT0 0x0c /* ADC Conversion Data register 0 */
1650 #define S3C_ADCDAT1 0x10 /* ADC Conversion Data register 1 */
1652 static uint32_t s3c_adc_read(void *opaque
, target_phys_addr_t addr
)
1654 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*) opaque
;
1666 return ((!s
->down
) << 15) | s
->xdata
;
1668 return ((!s
->down
) << 15) | s
->ydata
;
1670 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1676 static void s3c_adc_write(void *opaque
, target_phys_addr_t addr
,
1679 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*) opaque
;
1683 s
->control
= (s
->control
& 0x8000) | (value
& 0x7ffe);
1684 s
->enable
= !(value
& 4);
1685 if ((value
& 1) && !(value
& 2))
1688 qemu_del_timer(s
->convt
);
1693 s
->ts
= value
& 0xff;
1697 s
->delay
= value
& 0xffff;
1701 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1705 static CPUReadMemoryFunc
*s3c_adc_readfn
[] = {
1711 static CPUWriteMemoryFunc
*s3c_adc_writefn
[] = {
1717 static void s3c_adc_save(QEMUFile
*f
, void *opaque
)
1719 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*) opaque
;
1721 qemu_put_be32(f
, s
->enable
);
1722 for (i
= 0; i
< 8; i
++)
1723 qemu_put_be32(f
, s
->input
[i
]);
1724 qemu_put_be32(f
, s
->in_idx
);
1725 qemu_put_be32(f
, s
->noise
);
1727 qemu_put_be16s(f
, &s
->control
);
1728 qemu_put_be16s(f
, &s
->ts
);
1729 qemu_put_be16s(f
, &s
->delay
);
1730 qemu_put_sbe16s(f
, &s
->xdata
);
1731 qemu_put_sbe16s(f
, &s
->ydata
);
1734 static int s3c_adc_load(QEMUFile
*f
, void *opaque
, int version_id
)
1736 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*) opaque
;
1738 s
->enable
= qemu_get_be32(f
);
1739 for (i
= 0; i
< 8; i
++)
1740 s
->input
[i
] = qemu_get_be32(f
);
1741 s
->in_idx
= qemu_get_be32(f
);
1742 s
->noise
= qemu_get_be32(f
);
1744 qemu_get_be16s(f
, &s
->control
);
1745 qemu_get_be16s(f
, &s
->ts
);
1746 qemu_get_be16s(f
, &s
->delay
);
1747 qemu_get_sbe16s(f
, &s
->xdata
);
1748 qemu_get_sbe16s(f
, &s
->ydata
);
1750 if (s
->enable
&& (s
->ts
& 7) && !(s
->control
& (1 << 15)))
1756 struct s3c_adc_state_s
*s3c_adc_init(target_phys_addr_t base
, qemu_irq irq
,
1760 struct s3c_adc_state_s
*s
= (struct s3c_adc_state_s
*)
1761 qemu_mallocz(sizeof(struct s3c_adc_state_s
));
1766 s
->convt
= qemu_new_timer(vm_clock
, s3c_adc_done
, s
);
1767 s
->tst
= qemu_new_timer(vm_clock
, s3c_adc_tick
, s
);
1771 iomemtype
= cpu_register_io_memory(0, s3c_adc_readfn
,
1772 s3c_adc_writefn
, s
);
1773 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
1775 /* We want absolute coordinates */
1776 qemu_add_mouse_event_handler(s3c_adc_event
, s
, 1,
1777 "QEMU S3C2410-driven Touchscreen");
1779 register_savevm("s3c24xx_adc", 0, 0, s3c_adc_save
, s3c_adc_load
, s
);
1784 void s3c_adc_setscale(struct s3c_adc_state_s
*adc
, const int m
[])
1786 memcpy(adc
->scale
, m
, 6 * sizeof(int));
1789 /* IIC-bus serial interface */
1790 struct s3c_i2c_state_s
{
1793 target_phys_addr_t base
;
1805 static void s3c_i2c_irq(struct s3c_i2c_state_s
*s
)
1807 s
->control
|= 1 << 4;
1808 if (s
->control
& (1 << 5))
1809 qemu_irq_raise(s
->irq
);
1812 static void s3c_i2c_reset(struct s3c_i2c_state_s
*s
)
1821 static void s3c_i2c_event(i2c_slave
*i2c
, enum i2c_event event
)
1823 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) i2c
;
1824 if (!(s
->status
& (1 << 4)))
1828 case I2C_START_RECV
:
1829 case I2C_START_SEND
:
1830 s
->status
|= 1 << 2;
1837 s
->status
|= 1 << 0;
1844 static int s3c_i2c_tx(i2c_slave
*i2c
, uint8_t data
)
1846 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) i2c
;
1847 if (!(s
->status
& (1 << 4)))
1850 if ((s
->status
>> 6) == 0)
1851 s
->data
= data
; /* TODO */
1852 s
->status
&= ~(1 << 0);
1855 return !(s
->control
& (1 << 7));
1858 static int s3c_i2c_rx(i2c_slave
*i2c
)
1860 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) i2c
;
1861 if (!(s
->status
& (1 << 4)))
1864 if ((s
->status
>> 6) == 1) {
1865 s
->status
&= ~(1 << 0);
1873 static void s3c_master_work(void *opaque
)
1875 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) opaque
;
1876 int start
= 0, stop
= 0, ack
= 1;
1877 if (s
->control
& (1 << 4)) /* Interrupt pending */
1879 if ((s
->status
& 0x90) != 0x90) /* Master */
1881 stop
= ~s
->status
& (1 << 5);
1882 if (s
->newstart
&& s
->status
& (1 << 5)) { /* START */
1891 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, (~s
->status
>> 6) & 1);
1893 i2c_end_transfer(s
->bus
);
1894 else if (s
->status
& (1 << 6))
1895 ack
= !i2c_send(s
->bus
, s
->data
);
1897 s
->data
= i2c_recv(s
->bus
);
1899 if (!(s
->control
& (1 << 7))) /* ACK */
1903 if (!(s
->status
& (1 << 5))) {
1914 #define S3C_IICCON 0x00 /* IIC-Bus Control register */
1915 #define S3C_IICSTAT 0x04 /* IIC-Bus Control / Status register */
1916 #define S3C_IICADD 0x08 /* IIC-Bus Address register */
1917 #define S3C_IICDS 0x0c /* IIC-Bus Tx / Rx Data Shift register */
1919 #define S3C2440_IICLC 0x10 /* IIC-Bus multi-master line control register */
1921 static uint32_t s3c_i2c_read(void *opaque
, target_phys_addr_t addr
)
1923 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) opaque
;
1929 return s
->status
& ~(1 << 5); /* Busy signal */
1934 case S3C2440_IICLC
: /* s3c2440 only ! */
1937 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1943 static void s3c_i2c_write(void *opaque
, target_phys_addr_t addr
,
1946 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) opaque
;
1950 s
->control
= (s
->control
| 0xef) & value
;
1957 s
->status
|= value
& 0xf0;
1958 if (s
->status
& (1 << 5))
1964 s
->addy
= value
& 0x7f;
1965 i2c_set_slave_address(&s
->slave
, s
->addy
);
1969 s
->data
= value
& 0xff;
1972 case S3C2440_IICLC
: /* s3c2440 only ! */
1973 s
->mmaster
= value
& 0xff;
1977 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
1981 static CPUReadMemoryFunc
*s3c_i2c_readfn
[] = {
1987 static CPUWriteMemoryFunc
*s3c_i2c_writefn
[] = {
1993 static void s3c_i2c_save(QEMUFile
*f
, void *opaque
)
1995 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) opaque
;
1996 qemu_put_8s(f
, &s
->control
);
1997 qemu_put_8s(f
, &s
->status
);
1998 qemu_put_8s(f
, &s
->data
);
1999 qemu_put_8s(f
, &s
->addy
);
2000 qemu_put_8s(f
, &s
->mmaster
);
2002 qemu_put_be32(f
, s
->busy
);
2003 qemu_put_be32(f
, s
->newstart
);
2005 i2c_slave_save(f
, &s
->slave
);
2008 static int s3c_i2c_load(QEMUFile
*f
, void *opaque
, int version_id
)
2010 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*) opaque
;
2011 qemu_get_8s(f
, &s
->control
);
2012 qemu_get_8s(f
, &s
->status
);
2013 qemu_get_8s(f
, &s
->data
);
2014 qemu_get_8s(f
, &s
->addy
);
2015 qemu_get_8s(f
, &s
->mmaster
);
2017 s
->busy
= qemu_get_be32(f
);
2018 s
->newstart
= qemu_get_be32(f
);
2020 i2c_slave_load(f
, &s
->slave
);
2024 struct s3c_i2c_state_s
*s3c_i2c_init(target_phys_addr_t base
, qemu_irq irq
)
2027 struct s3c_i2c_state_s
*s
= (struct s3c_i2c_state_s
*)
2028 qemu_mallocz(sizeof(struct s3c_i2c_state_s
));
2032 s
->slave
.event
= s3c_i2c_event
;
2033 s
->slave
.send
= s3c_i2c_tx
;
2034 s
->slave
.recv
= s3c_i2c_rx
;
2035 s
->bus
= i2c_init_bus();
2039 iomemtype
= cpu_register_io_memory(0, s3c_i2c_readfn
,
2040 s3c_i2c_writefn
, s
);
2041 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
2043 register_savevm("s3c24xx_i2c", 0, 0, s3c_i2c_save
, s3c_i2c_load
, s
);
2048 i2c_bus
*s3c_i2c_bus(struct s3c_i2c_state_s
*s
)
2053 /* Serial Peripheral Interface */
2054 struct s3c_spi_state_s
{
2055 target_phys_addr_t base
;
2074 uint8_t (*txrx
[2])(void *opaque
, uint8_t value
);
2075 uint8_t (*btxrx
[2])(void *opaque
, uint8_t value
);
2079 static void s3c_spi_update(struct s3c_spi_state_s
*s
)
2082 for (i
= 0; i
< 2; i
++) {
2083 switch ((s
->chan
[i
].control
>> 5) & 3) { /* SMOD */
2085 qemu_irq_raise(s
->chan
[i
].irq
);
2088 qemu_irq_raise(s
->chan
[i
].drq
);
2094 static void s3c_spi_reset(struct s3c_spi_state_s
*s
)
2096 memset(s
->chan
, 0, sizeof(s
->chan
));
2097 s
->chan
[0].pin
= 0x02;
2098 s
->chan
[1].pin
= 0x02;
2102 #define S3C_SPCON0 0x00 /* SPI channel 0 control register */
2103 #define S3C_SPSTA0 0x04 /* SPI channel 0 status register */
2104 #define S3C_SPPIN0 0x08 /* SPI channel 0 pin control register */
2105 #define S3C_SPPRE0 0x0c /* SPI channel 0 baudrate prescaler register */
2106 #define S3C_SPTDAT0 0x10 /* SPI channel 0 Tx data register */
2107 #define S3C_SPRDAT0 0x14 /* SPI channel 0 Rx data register */
2108 #define S3C_SPCON1 0x20 /* SPI channel 1 control register */
2109 #define S3C_SPSTA1 0x24 /* SPI channel 1 status register */
2110 #define S3C_SPPIN1 0x28 /* SPI channel 1 pin control register */
2111 #define S3C_SPPRE1 0x2c /* SPI channel 1 baudrate prescaler register */
2112 #define S3C_SPTDAT1 0x30 /* SPI channel 1 Tx data register */
2113 #define S3C_SPRDAT1 0x34 /* SPI channel 1 Rx data register */
2115 static uint32_t s3c_spi_read(void *opaque
, target_phys_addr_t addr
)
2117 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*) opaque
;
2125 return s
->chan
[ch
].control
;
2133 return s
->chan
[ch
].pin
;
2137 return s
->chan
[ch
].pre
;
2141 return s
->chan
[ch
+ 2].txbuf
;
2145 if (s
->txrx
[ch
] && (s
->chan
[ch
].control
& 0x19) == 0x19)
2146 s
->chan
[ch
].rxbuf
= s
->txrx
[ch
](s
->opaque
[ch
], 'Q');
2148 return s
->chan
[ch
].rxbuf
;
2151 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
2157 static void s3c_spi_write(void *opaque
, target_phys_addr_t addr
,
2160 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*) opaque
;
2168 s
->chan
[ch
].control
= value
& 0x7f;
2174 s
->chan
[ch
].pin
= value
& 0x07;
2179 s
->chan
[ch
].pre
= value
& 0xff;
2184 s
->chan
[ch
].txbuf
= value
& 0xff;
2185 if (s
->txrx
[ch
] && (s
->chan
[ch
].control
& 0x19) == 0x18)
2186 s
->chan
[ch
].rxbuf
= s
->txrx
[ch
](s
->opaque
[ch
], value
& 0xff);
2191 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
2195 static CPUReadMemoryFunc
*s3c_spi_readfn
[] = {
2201 static CPUWriteMemoryFunc
*s3c_spi_writefn
[] = {
2207 static void s3c_spi_save(QEMUFile
*f
, void *opaque
)
2209 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*) opaque
;
2211 for (i
= 0; i
< 2; i
++) {
2212 qemu_put_8s(f
, &s
->chan
[i
].control
);
2213 qemu_put_8s(f
, &s
->chan
[i
].pin
);
2214 qemu_put_8s(f
, &s
->chan
[i
].pre
);
2216 qemu_put_8s(f
, &s
->chan
[i
].txbuf
);
2217 qemu_put_8s(f
, &s
->chan
[i
].rxbuf
);
2218 qemu_put_be32(f
, s
->chan
[i
].cs_pin
);
2219 qemu_put_be32(f
, s
->chan
[i
].clk_pin
);
2220 qemu_put_be32(f
, s
->chan
[i
].mosi_pin
);
2221 qemu_put_be32(f
, s
->chan
[i
].bit
);
2225 static int s3c_spi_load(QEMUFile
*f
, void *opaque
, int version_id
)
2227 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*) opaque
;
2229 for (i
= 0; i
< 2; i
++) {
2230 qemu_get_8s(f
, &s
->chan
[i
].control
);
2231 qemu_get_8s(f
, &s
->chan
[i
].pin
);
2232 qemu_get_8s(f
, &s
->chan
[i
].pre
);
2234 qemu_get_8s(f
, &s
->chan
[i
].txbuf
);
2235 qemu_get_8s(f
, &s
->chan
[i
].rxbuf
);
2236 s
->chan
[i
].cs_pin
= qemu_get_be32(f
);
2237 s
->chan
[i
].clk_pin
= qemu_get_be32(f
);
2238 s
->chan
[i
].mosi_pin
= qemu_get_be32(f
);
2239 s
->chan
[i
].bit
= qemu_get_be32(f
);
2245 static void s3c_spi_bitbang_cs(void *opaque
, int line
, int level
)
2247 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*) opaque
;
2249 if (s
->chan
[ch
].cs_pin
|| level
) {
2250 if (s
->chan
[ch
].bit
&& s
->txrx
[ch
] && !s
->btxrx
[ch
]) {
2251 s
->chan
[ch
].txbuf
<<= 8 - s
->chan
[ch
].bit
;
2252 s
->chan
[ch
].rxbuf
= s
->txrx
[ch
](s
->opaque
[ch
], s
->chan
[ch
].txbuf
);
2254 } else if (!s
->chan
[ch
].cs_pin
|| !level
)
2255 s
->chan
[ch
].bit
= 0;
2257 /* SSn is active low. */
2258 s
->chan
[ch
].cs_pin
= !level
;
2261 static void s3c_spi_bitbang_clk(void *opaque
, int line
, int level
)
2263 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*) opaque
;
2265 if (!s
->chan
[ch
].cs_pin
)
2268 /* Detect CLK rising edge */
2269 if (s
->chan
[ch
].clk_pin
|| !level
)
2273 qemu_set_irq(s
->chan
[ch
].miso
,
2274 s
->btxrx
[ch
](s
->opaque
[ch
], s
->chan
[ch
].mosi_pin
));
2278 s
->chan
[ch
].txbuf
<<= 1;
2279 s
->chan
[ch
].txbuf
|= s
->chan
[ch
].mosi_pin
;
2281 qemu_set_irq(s
->chan
[ch
].miso
, (s
->chan
[ch
].rxbuf
>> 7) & 1);
2282 s
->chan
[ch
].rxbuf
<<= 1;
2284 if (++ s
->chan
[ch
].bit
== 8) {
2286 s
->chan
[ch
].rxbuf
= s
->txrx
[ch
](s
->opaque
[ch
], s
->chan
[ch
].txbuf
);
2287 s
->chan
[ch
].bit
= 0;
2291 s
->chan
[ch
].clk_pin
= level
;
2294 static void s3c_spi_bitbang_mosi(void *opaque
, int line
, int level
)
2296 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*) opaque
;
2298 s
->chan
[ch
].mosi_pin
= level
;
2301 static const struct {
2302 int cs
, clk
, miso
, mosi
;
2303 } s3c_spi_pins
[2] = {
2304 { S3C_GPG(2), S3C_GPE(13), S3C_GPE(11), S3C_GPE(12) },
2305 { S3C_GPG(3), S3C_GPG(7), S3C_GPG(5), S3C_GPG(6) },
2308 static void s3c_spi_bitbang_init(struct s3c_spi_state_s
*s
,
2309 struct s3c_gpio_state_s
*gpio
)
2312 qemu_irq
*cs
= qemu_allocate_irqs(s3c_spi_bitbang_cs
, s
, 2);
2313 qemu_irq
*clk
= qemu_allocate_irqs(s3c_spi_bitbang_clk
, s
, 2);
2314 qemu_irq
*mosi
= qemu_allocate_irqs(s3c_spi_bitbang_mosi
, s
, 2);
2316 for (i
= 0; i
< 2; i
++) {
2317 s3c_gpio_out_set(gpio
, s3c_spi_pins
[i
].cs
, cs
[i
]);
2318 s3c_gpio_out_set(gpio
, s3c_spi_pins
[i
].clk
, clk
[i
]);
2319 s
->chan
[i
].miso
= s3c_gpio_in_get(gpio
)[s3c_spi_pins
[i
].miso
];
2320 s3c_gpio_out_set(gpio
, s3c_spi_pins
[i
].mosi
, mosi
[i
]);
2324 struct s3c_spi_state_s
*s3c_spi_init(target_phys_addr_t base
,
2325 qemu_irq irq0
, qemu_irq drq0
, qemu_irq irq1
, qemu_irq drq1
,
2326 struct s3c_gpio_state_s
*gpio
)
2329 struct s3c_spi_state_s
*s
= (struct s3c_spi_state_s
*)
2330 qemu_mallocz(sizeof(struct s3c_spi_state_s
));
2333 s
->chan
[0].irq
= irq0
;
2334 s
->chan
[0].drq
= drq0
;
2335 s
->chan
[1].irq
= irq1
;
2336 s
->chan
[1].drq
= drq1
;
2340 iomemtype
= cpu_register_io_memory(0, s3c_spi_readfn
,
2341 s3c_spi_writefn
, s
);
2342 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
2344 s3c_spi_bitbang_init(s
, gpio
);
2346 register_savevm("s3c24xx_spi", 0, 0, s3c_spi_save
, s3c_spi_load
, s
);
2351 void s3c_spi_attach(struct s3c_spi_state_s
*s
, int ch
,
2352 uint8_t (*txrx
)(void *opaque
, uint8_t value
),
2353 uint8_t (*btxrx
)(void *opaque
, uint8_t value
), void *opaque
)
2356 cpu_abort(cpu_single_env
, "%s: No channel %i\n", __FUNCTION__
, ch
);
2358 s
->btxrx
[ch
] = btxrx
;
2359 s
->opaque
[ch
] = opaque
;
2362 /* IIS-BUS interface */
2363 static inline void s3c_i2s_update(struct s3c_i2s_state_s
*s
)
2366 (s
->control
& (1 << 0)) && !(s
->control
& (1 << 3)) &&
2367 (s
->mode
& (1 << 7)) && (s
->fcontrol
& (1 << 13));
2369 (s
->control
& (1 << 0)) && !(s
->control
& (1 << 2)) &&
2370 (s
->mode
& (1 << 6)) && (s
->fcontrol
& (1 << 12));
2371 s
->control
&= ~0xc0;
2372 /* The specs are unclear about the FIFO-ready flags logic.
2373 * Implement semantics that make most sense. */
2374 if (s
->tx_en
&& s
->tx_len
)
2375 s
->control
|= (1 << 7);
2376 if (s
->rx_en
&& s
->rx_len
)
2377 s
->control
|= (1 << 6);
2379 qemu_set_irq(s
->dma
[S3C_RQ_I2SSDO
], (s
->control
>> 5) &
2380 (s
->control
>> 7) & (s
->fcontrol
>> 15) & 1);
2381 qemu_set_irq(s
->dma
[S3C_RQ_I2SSDI0
], (s
->control
>> 4) &
2382 (s
->control
>> 6) & (s
->fcontrol
>> 14) & 1);
2383 qemu_set_irq(s
->dma
[S3C_RQ_I2SSDI1
], (s
->control
>> 4) &
2384 (s
->control
>> 6) & (s
->fcontrol
>> 14) & 1);
2387 static void s3c_i2s_reset(struct s3c_i2s_state_s
*s
)
2391 s
->prescaler
= 0x000;
2392 s
->fcontrol
= 0x0000;
2398 #define S3C_IISCON 0x00 /* IIS Control register */
2399 #define S3C_IISMOD 0x04 /* IIS Mode register */
2400 #define S3C_IISPSR 0x08 /* IIS Prescaler register */
2401 #define S3C_IISFCON 0x0c /* IIS FIFO Interface register */
2402 #define S3C_IISFIFO 0x10 /* IIS FIFO register */
2404 static uint32_t s3c_i2s_read(void *opaque
, target_phys_addr_t addr
)
2406 struct s3c_i2s_state_s
*s
= (struct s3c_i2s_state_s
*) opaque
;
2415 return s
->prescaler
;
2417 return s
->fcontrol
|
2418 (MAX(32 - s
->tx_len
, 0) << 6) |
2421 if (s
->rx_len
> 0) {
2426 s
->buffer
= (uint16_t) (ret
= s
->codec_in(s
->opaque
));
2432 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
2438 static void s3c_i2s_write(void *opaque
, target_phys_addr_t addr
,
2441 struct s3c_i2s_state_s
*s
= (struct s3c_i2s_state_s
*) opaque
;
2445 s
->control
= (s
->control
& 0x100) | (value
& 0x03f);
2449 s
->mode
= value
& 0x1ff;
2453 s
->prescaler
= value
& 0x3ff;
2456 s
->fcontrol
= value
& 0xf000;
2460 if (s
->tx_len
&& s
->tx_en
) {
2464 s
->codec_out(s
->opaque
, value
| ((uint32_t) s
->buffer
<< 16));
2466 s
->buffer
= (uint16_t) value
;
2471 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
2475 static CPUReadMemoryFunc
*s3c_i2s_readfn
[] = {
2481 static CPUWriteMemoryFunc
*s3c_i2s_writefn
[] = {
2487 static void s3c_i2s_save(QEMUFile
*f
, void *opaque
)
2489 struct s3c_i2s_state_s
*s
= (struct s3c_i2s_state_s
*) opaque
;
2490 qemu_put_be16s(f
, &s
->control
);
2491 qemu_put_be16s(f
, &s
->mode
);
2492 qemu_put_be16s(f
, &s
->prescaler
);
2493 qemu_put_be16s(f
, &s
->fcontrol
);
2495 qemu_put_be32(f
, s
->tx_en
);
2496 qemu_put_be32(f
, s
->rx_en
);
2497 qemu_put_be32(f
, s
->tx_len
);
2498 qemu_put_be32(f
, s
->rx_len
);
2499 qemu_put_be16(f
, s
->buffer
);
2500 qemu_put_be32(f
, s
->cycle
);
2503 static int s3c_i2s_load(QEMUFile
*f
, void *opaque
, int version_id
)
2505 struct s3c_i2s_state_s
*s
= (struct s3c_i2s_state_s
*) opaque
;
2506 qemu_get_be16s(f
, &s
->control
);
2507 qemu_get_be16s(f
, &s
->mode
);
2508 qemu_get_be16s(f
, &s
->prescaler
);
2509 qemu_get_be16s(f
, &s
->fcontrol
);
2511 s
->tx_en
= qemu_get_be32(f
);
2512 s
->rx_en
= qemu_get_be32(f
);
2513 s
->tx_len
= qemu_get_be32(f
);
2514 s
->rx_len
= qemu_get_be32(f
);
2515 s
->buffer
= qemu_get_be16(f
);
2516 s
->cycle
= qemu_get_be32(f
);
2521 static void s3c_i2s_data_req(void *opaque
, int tx
, int rx
)
2523 struct s3c_i2s_state_s
*s
= (struct s3c_i2s_state_s
*) opaque
;
2529 struct s3c_i2s_state_s
*s3c_i2s_init(target_phys_addr_t base
, qemu_irq
*dma
)
2532 struct s3c_i2s_state_s
*s
= (struct s3c_i2s_state_s
*)
2533 qemu_mallocz(sizeof(struct s3c_i2s_state_s
));
2537 s
->data_req
= s3c_i2s_data_req
;
2541 iomemtype
= cpu_register_io_memory(0, s3c_i2s_readfn
,
2542 s3c_i2s_writefn
, s
);
2543 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
2545 register_savevm("s3c24xx_iis", 0, 0, s3c_i2s_save
, s3c_i2s_load
, s
);
2550 /* Watchdog Timer */
2551 struct s3c_wdt_state_s
{
2552 struct s3c_freq_s
* freq
;
2553 target_phys_addr_t base
;
2562 static void s3c_wdt_start(struct s3c_wdt_state_s
*s
)
2564 int enable
= s
->control
& (1 << 5);
2565 int prescaler
= (s
->control
>> 8) + 1;
2566 int divider
= prescaler
<< (((s
->control
>> 3) & 3) + 4);
2568 s
->timestamp
= qemu_get_clock(vm_clock
);
2569 qemu_mod_timer(s
->tm
, s
->timestamp
+ muldiv64(divider
* s
->count
,
2570 ticks_per_sec
, s
->freq
->pclk
));
2572 qemu_del_timer(s
->tm
);
2575 static void s3c_wdt_stop(struct s3c_wdt_state_s
*s
)
2577 int prescaler
= (s
->control
>> 8) + 1;
2578 int divider
= prescaler
<< (((s
->control
>> 3) & 3) + 4);
2581 diff
= muldiv64(qemu_get_clock(vm_clock
) - s
->timestamp
, s
->freq
->pclk
,
2582 ticks_per_sec
) / divider
;
2583 s
->count
-= MIN(s
->count
, diff
);
2584 s
->timestamp
= qemu_get_clock(vm_clock
);
2587 static void s3c_wdt_reset(struct s3c_wdt_state_s
*s
)
2589 s
->control
= 0x8021;
2595 static void s3c_wdt_timeout(void *opaque
)
2597 struct s3c_wdt_state_s
*s
= (struct s3c_wdt_state_s
*) opaque
;
2598 if (s
->control
& (1 << 0)) {
2599 qemu_system_reset_request();
2602 if (s
->control
& (1 << 2))
2603 qemu_irq_raise(s
->irq
);
2608 #define S3C_WTCON 0x00 /* Watchdog timer control register */
2609 #define S3C_WTDAT 0x04 /* Watchdog timer data register */
2610 #define S3C_WTCNT 0x08 /* Watchdog timer count register */
2612 static uint32_t s3c_wdt_read(void *opaque
, target_phys_addr_t addr
)
2614 struct s3c_wdt_state_s
*s
= (struct s3c_wdt_state_s
*) opaque
;
2625 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
2631 static void s3c_wdt_write(void *opaque
, target_phys_addr_t addr
,
2634 struct s3c_wdt_state_s
*s
= (struct s3c_wdt_state_s
*) opaque
;
2650 printf("%s: Bad register 0x%lx\n", __FUNCTION__
, (unsigned long)addr
);
2654 static CPUReadMemoryFunc
*s3c_wdt_readfn
[] = {
2660 static CPUWriteMemoryFunc
*s3c_wdt_writefn
[] = {
2666 static void s3c_wdt_save(QEMUFile
*f
, void *opaque
)
2668 struct s3c_wdt_state_s
*s
= (struct s3c_wdt_state_s
*) opaque
;
2671 qemu_put_be16s(f
, &s
->control
);
2672 qemu_put_be16s(f
, &s
->data
);
2673 qemu_put_be16s(f
, &s
->count
);
2674 qemu_put_sbe64s(f
, &s
->timestamp
);
2677 static int s3c_wdt_load(QEMUFile
*f
, void *opaque
, int version_id
)
2679 struct s3c_wdt_state_s
*s
= (struct s3c_wdt_state_s
*) opaque
;
2681 qemu_get_be16s(f
, &s
->control
);
2682 qemu_get_be16s(f
, &s
->data
);
2683 qemu_get_be16s(f
, &s
->count
);
2684 qemu_get_sbe64s(f
, &s
->timestamp
);
2690 struct s3c_wdt_state_s
*s3c_wdt_init(struct s3c_freq_s
* freq
, target_phys_addr_t base
, qemu_irq irq
)
2693 struct s3c_wdt_state_s
*s
= (struct s3c_wdt_state_s
*)
2694 qemu_mallocz(sizeof(struct s3c_wdt_state_s
));
2699 s
->tm
= qemu_new_timer(vm_clock
, s3c_wdt_timeout
, s
);
2703 iomemtype
= cpu_register_io_memory(0, s3c_wdt_readfn
,
2704 s3c_wdt_writefn
, s
);
2705 cpu_register_physical_memory(s
->base
, 0xffffff, iomemtype
);
2707 register_savevm("s3c24xx_wdt", 0, 0, s3c_wdt_save
, s3c_wdt_load
, s
);
2714 target_phys_addr_t base
;
2717 } s3c2410_uart
[] = {
2720 { S3C_PICS_RXD0
, S3C_PICS_TXD0
, S3C_PICS_ERR0
},
2725 { S3C_PICS_RXD1
, S3C_PICS_TXD1
, S3C_PICS_ERR1
},
2730 { S3C_PICS_RXD2
, S3C_PICS_TXD2
, S3C_PICS_ERR2
},
2733 { 0, { 0, 0, 0 }, { 0 } }
2736 /* General CPU reset */
2737 static void s3c2410_reset(void *opaque
)
2739 struct s3c_state_s
*s
= (struct s3c_state_s
*) opaque
;
2742 s3c_pic_reset(s
->pic
);
2743 s3c_dma_reset(s
->dma
);
2744 s3c_gpio_reset(s
->io
);
2745 s3c_lcd_reset(s
->lcd
);
2746 s3c_timers_reset(s
->timers
);
2747 s3c_mmci_reset(s
->mmci
);
2748 s3c_adc_reset(s
->adc
);
2749 s3c_i2c_reset(s
->i2c
);
2750 s3c_i2s_reset(s
->i2s
);
2751 s3c_rtc_reset(s
->rtc
);
2752 s3c_spi_reset(s
->spi
);
2753 s3c_udc_reset(s
->udc
);
2754 s3c_wdt_reset(s
->wdt
);
2755 s3c_clkpwr_reset(s
);
2756 s
->nand
->reset(s
->nand
);
2757 for (i
= 0; s3c2410_uart
[i
].base
; i
++)
2758 s3c_uart_reset(s
->uart
[i
]);
2762 struct s3c_state_s
* g_s3c
;
2764 /* Initialise an S3C24XX microprocessor. */
2765 struct s3c_state_s
*s3c24xx_init(
2768 unsigned int sdram_size
,
2769 uint32_t sram_address
,
2772 struct s3c_state_s
*s
;
2774 s
= (struct s3c_state_s
*) qemu_mallocz(sizeof(struct s3c_state_s
));
2779 s
->clock
.xtal
= xtal
;
2780 s
->clock
.pclk
= 66500000; // S3C_PCLK_FREQ; // TEMP
2782 s
->env
= cpu_init("arm920t");
2784 fprintf(stderr
, "Unable to initialize ARM920T\n");
2787 register_savevm("s3c24xx", 0, 0,
2788 cpu_save
, cpu_load
, s
->env
);
2790 cpu_register_physical_memory(S3C_RAM_BASE
, sdram_size
,
2791 qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2793 /* If OM pins are 00, SRAM is mapped at 0x0 instead. */
2794 cpu_register_physical_memory(sram_address
, S3C_SRAM_SIZE
,
2795 qemu_ram_alloc(S3C_SRAM_SIZE
) | IO_MEM_RAM
);
2797 s
->mc_base
= 0x48000000;
2799 iomemtype
= cpu_register_io_memory(0, s3c_mc_readfn
, s3c_mc_writefn
, s
);
2800 cpu_register_physical_memory(s
->mc_base
, 0xffffff, iomemtype
);
2801 register_savevm("s3c24xx_mc", 0, 0, s3c_mc_save
, s3c_mc_load
, s
);
2803 s
->pic
= s3c_pic_init(0x4a000000, arm_pic_init_cpu(s
->env
));
2804 s
->irq
= s3c_pic_get(s
->pic
);
2806 s
->dma
= s3c_dma_init(0x4b000000, &s
->irq
[S3C_PIC_DMA0
]);
2807 s
->drq
= s3c_dma_get(s
->dma
);
2809 s
->clkpwr_base
= 0x4c000000;
2810 s3c_clkpwr_reset(s
);
2812 iomemtype
= cpu_register_io_memory(0, s3c_clkpwr_readfn
,
2813 s3c_clkpwr_writefn
, s
);
2814 cpu_register_physical_memory(s
->clkpwr_base
, 0xffffff, iomemtype
);
2815 register_savevm("s3c24xx_clkpwr", 0, 0,
2816 s3c_clkpwr_save
, s3c_clkpwr_load
, s
);
2818 s
->lcd
= s3c_lcd_init(0x4d000000, s
->irq
[S3C_PIC_LCD
]);
2820 if (s
->cpu_id
== S3C_CPU_2440
)
2821 s
->nand
= s3c2440_nand_init();
2823 s
->nand
= s3c2410_nand_init();
2825 for (i
= 0; s3c2410_uart
[i
].base
; i
++) {
2826 s
->uart
[i
] = s3c_uart_init(&s
->clock
,
2827 s3c2410_uart
[i
].base
,
2828 &s
->irq
[s3c2410_uart
[i
].irq
[0]],
2829 &s
->drq
[s3c2410_uart
[i
].dma
[0]]);
2831 s3c_uart_attach(s
->uart
[i
], serial_hds
[i
]);
2834 s
->timers
= s3c_timers_init(&s
->clock
, 0x51000000, &s
->irq
[S3C_PIC_TIMER0
], s
->drq
);
2836 s
->udc
= s3c_udc_init(0x52000000, s
->irq
[S3C_PIC_USBD
], s
->drq
);
2838 s
->wdt
= s3c_wdt_init(&s
->clock
, 0x53000000, s
->irq
[S3C_PIC_WDT
]);
2840 s
->i2c
= s3c_i2c_init(0x54000000, s
->irq
[S3C_PIC_IIC
]);
2842 s
->i2s
= s3c_i2s_init(0x55000000, s
->drq
);
2844 s
->io
= s3c_gpio_init(0x56000000, s
->irq
, s
->cpu_id
);
2846 s
->rtc
= s3c_rtc_init(0x57000000, s
->irq
[S3C_PIC_RTC
]);
2848 s
->adc
= s3c_adc_init(0x58000000, s
->irq
[S3C_PICS_ADC
],
2849 s
->irq
[S3C_PICS_TC
]);
2851 s
->spi
= s3c_spi_init(0x59000000,
2852 s
->irq
[S3C_PIC_SPI0
], s
->drq
[S3C_RQ_SPI0
],
2853 s
->irq
[S3C_PIC_SPI1
], s
->drq
[S3C_RQ_SPI1
], s
->io
);
2855 s
->mmci
= s3c_mmci_init(0x5a000000, s
->cpu_id
, mmc
,
2856 s
->irq
[S3C_PIC_SDI
], s
->drq
);
2859 usb_ohci_init_pxa(0x49000000, 3, -1, s
->irq
[S3C_PIC_USBH
]);
2862 qemu_register_reset(s3c2410_reset
, s
);
2864 s
->nand
->setwp(s
->nand
, 1);
2866 /* Power on reset */
2867 s3c_gpio_setpwrstat(s
->io
, 1);