2022-09-14 | Peter Maydell | target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly... encoding cp15, 0, c0, c{0-7}, {0-7} are all... |
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2021-07-18 | Richard Henderson | target/arm: Fix offsets for TTBCR Use cp15.tcr_el[*].raw_tcr as the offsetofhigh32... |
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2020-01-03 | Peter Maydell | Merge remote-tracking branch 'remotes/pmaydell/tags... ... rebuild hflags after setting CP15 bits in arm_set_cpu_on() ... rebuild hflags after setting CP15 bits in arm_set_cpu_on() |
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2019-12-20 | Niek Linnenbank | arm/arm-powerctl: rebuild hflags after setting CP15... ... rebuild hflags after setting CP15 bits in arm_set_cpu_on() After setting CP15 bits in arm_set_cpu_on() the cached... |
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2019-12-16 | Peter Maydell | Merge remote-tracking branch 'remotes/pmaydell/tags... * Handle AArch32 CP15 trapping via HSTR_EL2 target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 |
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2019-12-16 | Marc Zyngier | target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 ...offers a way to trap ranges of CP15 system register |
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2019-09-27 | Luc Michel | target/arm: fix CBAR register for AArch64 CPUs ...AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0) - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0... |
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2019-04-29 | Peter Maydell | target/arm: Implement dummy versions of M-profile FP... cpu->cp15.nsacr and cpu->cp15.cpacr_el1... inside the cp15 substruct |
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2018-08-20 | Peter Maydell | target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1... tried to access them under cp15. |
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2017-07-31 | Peter Maydell | Merge remote-tracking branch 'remotes/pmaydell/tags... target/arm: Rename cp15.c6_rgnr to pmsav7.rnr |
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2017-07-31 | Peter Maydell | target/arm: Rename cp15.c6_rgnr to pmsav7.rnr target/arm: Rename cp15.c6_rgnr to pmsav7.rnr number register, which is in cp15.c6_rgnr. This exception not store state in the cp15 substruct. Rename cp15.c6_rgnr to pmsav7.rnr accordingly. |
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2017-06-05 | Peter Maydell | Merge remote-tracking branch 'remotes/mjt/tags/trivial... ...arm: add data cache invalidation cp15 instruction to cortex-r5 |
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2017-06-04 | Luc MICHEL | target/arm: add data cache invalidation cp15 instruction... ...arm: add data cache invalidation cp15 instruction to cortex-r5 The cp15, CRn=15, opc1=0, CRm=5, opc2=0... |
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2015-10-16 | Davorin Mista | target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs in ARMCPUState.cp15 struct (oslsr_el1). This variable... |
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2015-05-18 | Peter Crosthwaite | target-arm: cpu64: generalise name of A57 regs the CP15 registers (such as ACTLR) are... |
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2014-12-22 | Greg Bellows | target-arm: Merge EL3 CP15 register lists target-arm: Merge EL3 CP15 register lists |
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2014-12-11 | Fabian Aggeler | target-arm: make TTBCR banked ...element array of the new structs in cp15. This |
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2014-12-11 | Greg Bellows | target-arm: add SDER definition ...SDER and SDER32_EL3 as well as cp15.sder for |
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2014-08-19 | Peter Maydell | target-arm: Allow STATE_BOTH reginfo descriptions for... ...this where the AArch32 view is in cp15. It turns out that |
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2014-05-02 | Peter Maydell | Merge remote-tracking branch 'remotes/pmaydell/tags... * implement XScale cache lockdown cp15 ops |
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2014-05-01 | Rabin Vincent | armv7m_nvic: fix CPUID Base Register cp15.c0_cpuid is never initialized... |
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2014-04-17 | Peter Maydell | target-arm: Add AArch64 ELR_EL1 register. ...that this does not live in env->cp15: for KVM migration |
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2014-01-07 | Peter Maydell | target-arm: Widen thread-local register state fields... CPU is that when in AArch32 the cp15 register is a view of the |
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2014-01-07 | Peter Maydell | target-arm: Widen thread-local register state fields... CPU is that when in AArch32 the cp15 register is a view of the |
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2014-01-07 | Peter Maydell | target-arm: A64: Implement MRS/MSR/SYS/SYSL cp15 coprocessor registers is the set... in with other cp15 registers. Implement these instructions |
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2013-12-17 | Peter Crosthwaite | target-arm/cpu: Convert reset CBAR to a property The reset value of the CP15 CBAR is a vendor (machine) configurable |
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2013-12-17 | Peter Crosthwaite | target-arm: Define and use ARM_FEATURE_CBAR CP15 configuration base address (CBAR... |
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2013-12-17 | Peter Crosthwaite | target-arm/helper.c: Allow cp15.c15 dummy override target-arm/helper.c: Allow cp15.c15 dummy override The cp15.c15 space is implementation defined... |
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2013-10-31 | Nathan Rossi | target-arm: Add CP15 VBAR support target-arm: Add CP15 VBAR support |
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2013-09-10 | Peter Maydell | target-arm: Make '-cpu any' available in linux-user... values or implementation specific cp15 registers. (Unsurprisingly, some |
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2013-08-20 | Peter Maydell | target-arm: Implement the generic timer via cp15 registers. Newer kernels will... |
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2013-07-15 | Anthony Liguori | Merge remote-tracking branch 'pmaydell/tags/pull-target... target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup |
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2013-07-15 | Peter Crosthwaite | target-arm/helper.c: Implement MIDR aliases Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default |
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2013-07-15 | Peter Crosthwaite | target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup |
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2013-04-19 | Peter Maydell | target-arm: Add some missing CPU state fields to VMState our migration state: some OMAP specific cp15 registers, and |
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2012-09-10 | Stefan Weil | target-arm: Fix potential buffer overflow buffer overflow 'env->cp15.c6_region' 8 <= 8 buffer overflow 'env->cp15.c6_region' 8 <= 8 |
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2012-07-14 | Blue Swirl | Merge branch 'target-arm.for-upstream' of git://git... target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers target-arm: Fix CP15 based WFI |
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2012-07-12 | Peter Maydell | target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1... |
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2012-07-12 | Peter Maydell | target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers |
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2012-07-12 | Paul Brook | target-arm: Fix CP15 based WFI target-arm: Fix CP15 based WFI The coprocessor register rework broke cp15 based WFI instructions. |
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2012-06-24 | Blue Swirl | Merge branch 'target-arm.for-upstream' of git://git... target-arm: Remove remaining old cp15 infrastructure ...arm: Move block cache ops to new cp15 framework target-arm: Convert cp15 cache ID registers target-arm: Convert cp15 crn=0 crm={1,2} feature registers target-arm: Convert cp15 crn=1 registers target-arm: Convert cp15 crn=9 registers target-arm: Convert cp15 crn=6 registers target-arm: convert cp15 crn=7 registers target-arm: Convert cp15 VA-PA translation registers target-arm: Convert cp15 MMU TLB control target-arm: Convert cp15 crn=15 registers target-arm: Convert cp15 crn=10 registers target-arm: Convert cp15 crn=13 registers target-arm: Convert cp15 crn=2 registers ...arm: Convert MMU fault status cp15 registers target-arm: Convert cp15 c3 register |
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2012-06-20 | Peter Maydell | target-arm: Remove remaining old cp15 infrastructure target-arm: Remove remaining old cp15 infrastructure There are now no uses of the old cp15 infrastructure, |
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2012-06-20 | Peter Maydell | target-arm: Move block cache ops to new cp15 framework ...arm: Move block cache ops to new cp15 framework ...optional block cache ops to the new cp15 framework. |
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2012-06-20 | Peter Maydell | target-arm: Convert final ID registers ...final ID registers to the new cp15 scheme. |
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2012-06-20 | Peter Maydell | target-arm: Convert MPIDR Convert the MPIDR to the new cp15 register scheme. |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 cache ID registers target-arm: Convert cp15 cache ID registers Convert the cp15 cache ID registers to the new... |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=0 crm={1,2} feature registers target-arm: Convert cp15 crn=0 crm={1,2} feature registers Convert the cp15 crn=0 crm={1,2} features registers to |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=1 registers target-arm: Convert cp15 crn=1 registers Convert the cp15 crn=1 registers to the new scheme. |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=9 registers target-arm: Convert cp15 crn=9 registers Convert cp15 crn=9 registers (mostly cache... |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=6 registers target-arm: Convert cp15 crn=6 registers Convert the cp15 crn=6 registers to the new scheme. |
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2012-06-20 | Peter Maydell | target-arm: convert cp15 crn=7 registers target-arm: convert cp15 crn=7 registers Convert the cp15 crn=7 registers to the new scheme. cp15 crn=7 reads: |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 VA-PA translation registers target-arm: Convert cp15 VA-PA translation registers Convert the cp15 VA-PA translation registers (a... |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 MMU TLB control target-arm: Convert cp15 MMU TLB control Convert cp15 MMU TLB control (crn=8) to new... |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=15 registers target-arm: Convert cp15 crn=15 registers Convert the cp15 crn=15 (implementation specific... |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=10 registers target-arm: Convert cp15 crn=10 registers |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=13 registers target-arm: Convert cp15 crn=13 registers Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 crn=2 registers target-arm: Convert cp15 crn=2 registers Convert the cp15 crn=2 registers (MMU page table... |
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2012-06-20 | Peter Maydell | target-arm: Convert MMU fault status cp15 registers ...arm: Convert MMU fault status cp15 registers ...status and MPU access permission cp15 |
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2012-06-20 | Peter Maydell | target-arm: Convert cp15 c3 register target-arm: Convert cp15 c3 register Convert the cp15 c3 register (MMU domain access... |
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2012-06-20 | Peter Maydell | target-arm: Convert generic timer cp15 regs target-arm: Convert generic timer cp15 regs Convert the (dummy) generic timer cp15 implementation. |
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2012-06-20 | Peter Maydell | target-arm: Convert performance monitor registers Convert the v7 performance monitor cp15 registers to |
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2012-06-20 | Peter Maydell | target-arm: Convert TLS registers Convert TLS registers to the new cp15 framework |
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2012-04-27 | Peter Maydell | target-arm: Move A9 config_base_address reset value... Move the A9 config_base_address cp15 register reset value to |
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2012-04-23 | Anthony Liguori | Merge remote-tracking branch 'origin/master' into staging target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset |
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2012-04-21 | Peter Maydell | target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; |
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2012-03-29 | Andreas Färber | target-arm: Minimalistic CPU QOM'ification cp15 registers to not interfere with... |
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2012-03-17 | Blue Swirl | Merge branch 'target-arm.for-upstream' of git://git... target-arm: Fix typo in ARM946 cp15 c5 handling |
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2012-03-15 | Peter Maydell | target-arm: Fix typo in ARM946 cp15 c5 handling target-arm: Fix typo in ARM946 cp15 c5 handling ...typo in handling of the ARM946 cp15 c5 c0 0 1 handling |
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2012-01-28 | Blue Swirl | Merge branch 'target-arm.for-upstream' of git://git... ...implementation of generic timer cp15 registers |
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2012-01-25 | Peter Maydell | Add dummy implementation of generic timer cp15 registers ...implementation of generic timer cp15 registers Add a dummy implementation of the cp15 registers for the generic |
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2012-01-07 | Aurelien Jarno | Merge branch 'target-arm.for-upstream' of git://git... arm: add dummy A9-specific cp15 registers |
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2012-01-05 | Mark Langsdorf | arm: add dummy A9-specific cp15 registers arm: add dummy A9-specific cp15 registers Add dummy register support for the cp15, CRn=c15 registers. |
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2011-12-13 | Jean-Christophe... | arm: Fix CP15 FSR (C5) domain setting arm: Fix CP15 FSR (C5) domain setting ...value in the domain field in the cp15 DFSR |
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2011-07-26 | Peter Maydell | target-arm: Support v6 barriers in linux-user mode ...operations as special cases of cp15 accesses ...doesn't provide a functional get_cp15 helper) as well as cp15_user_ok()). |
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2011-06-22 | Peter Maydell | target-arm: Minimal implementation of performance counters cp15 registers. Provide a minimal implementa... |
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2011-04-09 | Dmitry Eremin-Solenikov | arm: basic support for ARMv4/ARMv4T emulation ...doesn _not_ include disabling of cp15 access and base-updated |
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2011-03-06 | Adam Lackorzynski | target-arm: Implement cp15 VA->PA translation target-arm: Implement cp15 VA->PA translation Implement VA->PA translations by cp15-c7 that went through unchanged |
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2011-03-06 | Peter Maydell | target-arm: Don't decode old cp15 WFI instructions... target-arm: Don't decode old cp15 WFI instructions on v7 cores via a cp15 coprocessor register. Add correct... decoding of the cp15 WFI instructions so that they... |
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2011-02-04 | Peter Maydell | target-arm: Clean up handling of MPIDR The ARM cp15 register 0,c0,c0,5 is standardised... |
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2010-12-27 | Juha Riihimäki | target-arm: correct cp15 c1_sys reset value for arm1136... target-arm: correct cp15 c1_sys reset value for arm1136... |
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2010-12-27 | Mattias Holm | target-arm: correct cp15 c1_sys reset value for cortex-a8 target-arm: correct cp15 c1_sys reset value for cortex-a8 |
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2010-02-23 | Paul Brook | ARM CP15 tls fix ARM CP15 tls fix Fix temporary handling in cp15 tls register load/store. |
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2010-02-06 | Riku Voipio | target-arm: refactor cp15.c13 register access target-arm: refactor cp15.c13 register access Access the cp15.c13 TLS registers directly with... a slow helper. If the the cp15 read/write was not TLS register... fall back to the cp15 helper. with -mtp=cp15 possible. legal cp15 register... already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available... |
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2010-02-05 | Riku Voipio | target-arm: refactor cp15.c13 register access target-arm: refactor cp15.c13 register access Access the cp15.c13 TLS registers directly with... a slow helper. If the the cp15 read/write was not TLS register... fall back to the cp15 helper. with -mtp=cp15 possible. legal cp15 register... already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available... |
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2009-03-07 | aurel32 | Fix correct reset value for ARM CP15 c1 auxiliary control... Fix correct reset value for ARM CP15 c1 auxiliary control register ...Reference Manual, the reset value for CP15 c1 auxiliary control |
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2008-12-19 | pbrook | Implement ARMv7 cp15 cache ID registers. Implement ARMv7 cp15 cache ID registers. |
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2008-10-22 | pbrook | Optimize redundant cp15 coprocessor access control... Optimize redundant cp15 coprocessor access control register... |
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2007-10-31 | balrog | Invalidate TLBs when domains are changed (Matthew Warton). Legalise cp15 pid register writes (Matthew Warton). |
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2007-06-24 | balrog | Reset ARM cp15.c1_sys to default values. Fix XScale... Reset ARM cp15.c1_sys to default values. Fix... |
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2006-07-21 | pbrook | Fix Arm cp15 c13 (Process ID) register writes. Fix Arm cp15 c13 (Process ID) register writes. |
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