repo.or.cz
/
qemu.git
/
search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
first
·
prev
·
next
Merge tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu into staging
2022-10-14
Alistair F
r
ancis
target/riscv: p
m
p
:
Fixup TLB si
z
e cal
c
ulation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-09-26
Alis
t
air Francis
hw
/
riscv: opentitan: Expos
e
th
e
r
e
se
t
vec as a SoC pro
p
er
t
y
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-09-26
Alist
a
ir Fran
c
is
hw/
r
iscv: opentitan: Fixup resetv
e
c
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-09-26
Ali
s
tair Francis
target/riscv:
Set the CPU re
s
et
v
ec dir
e
c
t
ly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-07-03
A
l
istair Francis
hw/ri
s
cv:
b
oot: Reduce FDT ad
d
ress alignm
e
nt
constraints
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-07-03
Alistai
r
F
r
a
n
c
is
target
/
riscv: Ibex: Sup
p
ort p
r
iv version 1
.
1
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-07-03
Alis
t
air Francis
target/riscv: Fixu
p
MSEC
C
FG minimum priv
check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
A
l
istair Franc
i
s
target/ri
s
cv: t
r
ans_r
v
v: Avoid asse
r
t fo
r
RV32 an
d
e64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
A
lis
t
air Francis
ta
r
get/risc
v
: Don't
e
xpose the
CPU propertie
s
o
n
names
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
Alistair Francis
h
w
/intc: sifive_plic: Avoid
o
verflow
i
ng the addr_c
o
nfi
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
A
l
ista
i
r
Francis
MAINTA
I
N
E
RS: Cover hw/core
/
uboot_ima
g
e
.
h within
Gene
r
i
c
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alist
a
ir Francis
hw/riscv:
Enable TPM backe
n
d
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Al
i
s
t
air Francis
hw/ri
s
cv:
v
irt: Add device plug
sup
p
ort
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alistai
r
Fr
a
ncis
hw/riscv:
v
irt: A
d
d support for
g
enera
t
ing plat
f
orm
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alistair Francis
hw
/
riscv: virt: Create a pl
a
tfor
m
bus
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
A
l
istair
F
ranc
i
s
hw/
c
ore:
M
o
v
e
t
h
e ARM sysbu
s
-f
d
t to c
o
re
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Al
i
s
tair Fra
n
cis
hw/r
i
s
c
v
:
v
irt: Add a machine done noti
f
ie
r
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-22
Alistair
F
rancis
target/riscv: Allow
s
o
ftware
access to MIP SE
I
P
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-22
Alis
t
air
F
ranc
i
s
target/riscv
:
cpu:
F
ixu
p
indenta
t
io
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
listair
Francis
targe
t
/risc
v
:
I
mplemen
t
th
e
s
tval
/
mtval illegal in
s
tru
c
tio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Al
i
s
t
air Francis
target/r
i
scv: Fixup set
t
i
n
g GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
l
istair Francis
target/riscv: Set th
e
op
c
ode in DisasC
o
ntext
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
lis
t
air Francis
hw/riscv: virt: Allow support for 32 cores
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Francis
hw/riscv:
U
se error_fatal
f
or SoC
r
ealisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Francis
tar
g
et/r
i
scv: En
a
ble the Hypervis
o
r extens
i
on by d
e
f
a
u
l
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
l
istai
r
Francis
target/risc
v
:
Mar
k
t
h
e Hypervisor extensio
n
as
n
on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair F
r
ancis
hw/intc: sifive_p
l
ic: Cleanup
r
emain
i
ng
f
unctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Fr
a
ncis
hw/i
n
t
c: sifive_plic: C
l
eanup the read
function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair
F
ranci
s
hw/i
n
tc: sifive_pl
i
c: Clean
u
p
the write fu
n
ction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Al
i
stai
r
F
rancis
hw/
i
ntc: sifive_p
l
i
c
:
A
dd a reset
fu
n
c
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alistair F
r
ancis
hw/riscv: opentita
n
:
F
ix
u
p the PL
I
C context addr
e
sses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alistair
F
ran
c
is
hw/riscv: vi
r
t:
U
s
e
the P
L
IC config
h
elper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
A
l
ista
i
r Francis
hw/riscv: microchi
p
_pfsoc:
U
se the PLIC confi
g
helper
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alis
t
air Francis
hw/riscv: sifive_u:
U
se the PLIC
c
onfig helper
func
t
i
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
A
l
i
stair Fr
a
nci
s
hw/riscv
:
boot: Add a PLIC config s
t
r
i
n
g functi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
A
listair
Fr
a
ncis
hw/ri
s
cv: vi
r
t: Do
n
't use
a m
a
cro
f
or the PLIC
conf
i
guration
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alist
a
i
r
Francis
hw/int
c
:
sifive_
p
l
i
c: Clean
u
p the irq_re
q
uest fun
c
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Al
i
stair Fr
a
ncis
hw/int
c
:
sif
i
ve_
p
lic: Cleanup the
realize functi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alista
i
r Fr
a
n
cis
h
w
/
i
ntc: sifive_plic: Move the propert
i
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alistair Franc
i
s
h
w
/intc: Remove
t
he Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alistair Francis
hw/riscv: ope
n
titan: Update to
the
l
atest build
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-21
Alistai
r
F
r
a
n
cis
ta
r
get/
r
i
s
c
v: Or
g
anise t
h
e CP
U
properties
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-21
Alistair Fran
c
is
target/risc
v
: Remove some unused m
a
cros
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-06
Alistair Francis
hw/riscv: shakti_c: Mark as not us
e
r crea
t
a
ble
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-21
Alistair Francis
hw/riscv: opentitan
:
Correct th
e
USB
D
ev address
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
A
listair Fran
c
is
sif
i
v
e
_
u: C
o
nnect the SiFiv
e
PWM devi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair F
r
ancis
hw/timer:
Add SiFive PWM support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Al
i
stair Francis
hw/intc
:
ibex_timer
:
Convert the ti
m
er to use RISC
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistai
r
Francis
hw/int
c
: si
f
ive_
p
lic: Con
v
ert the PLIC to use R
I
SC
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alist
a
i
r Fra
n
cis
hw/
i
ntc: ibex
_
plic: Convert the
PLIC
to u
s
e RISC-V
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair Francis
hw/int
c
: sifive_clint: Use RISC-V CPU GPIO
lin
e
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair Francis
t
a
rget/ri
s
cv:
E
xp
o
se inte
r
r
upt pending bi
t
s as GPIO
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
A
l
ista
i
r
Fr
a
ncis
target/riscv: Update the ePMP CSR a
d
dress
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Alistair Franc
i
s
hw/riscv/
b
oot:
C
h
e
ck t
h
e
e
rror o
f
fdt_pack()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
A
li
s
tair Francis
hw/riscv: open
t
i
tan: Add
the f
l
ash alia
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Alistair
Francis
h
w
/
r
iscv: opentitan: Add the unim
p
lement rv_core_ibex_peri
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Alistai
r
Fr
a
ncis
c
har: ibex_uart: Upda
t
e t
h
e
register l
a
yout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Alistair Fr
a
ncis
hw/
r
iscv: OpenTitan
:
Connect the m
t
ime an
d
mtimecmp
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Al
i
sta
i
r Franci
s
hw/ti
m
er: Init
i
al
c
ommit of Ibe
x
Timer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Ali
s
ta
i
r
Francis
hw/char/
i
bex_uart: Ma
k
e
t
he register
l
ayout pri
v
a
te
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Alista
i
r Franci
s
target/riscv:
Use target_ulong
fo
r
the DisasContext
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-07
A
l
istair
F
ra
n
ci
s
tar
g
e
t
/
r
is
c
v/pmp: Ad
d
assert for ePMP
o
pe
r
ations
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-07
Ali
s
tair Francis
docs/system:
Move the RISC-V -bios info
r
mation
t
o rem
o
ved
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistai
r
Francis
target
/
riscv: Fix the RV6
4
H decode com
m
e
n
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
stair
F
rancis
t
a
rget/riscv:
Co
n
s
oli
d
ate RV32/6
4
1
6
-b
i
t instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fra
n
cis
target/riscv: Consolidate RV32/64 32-bit instruction
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
Francis
t
a
rget/riscv: Re
m
ov
e
an unused CA
S
E_OP_32_64 macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alista
i
r Franci
s
target/riscv: R
e
m
o
v
e
the unuse
d
HSTATUS_WPRI macr
o
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
Francis
target/riscv: Remove
the h
a
r
d
c
o
d
e
d
S
ATP_MODE macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
istair Francis
target/riscv:
Remove the hardcoded
M
STATUS_S
D
macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
istair F
r
ancis
target
/
riscv: Remove th
e
hardc
o
d
ed HGAT
P
_
M
OD
E
macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
tair Francis
t
arg
e
t/riscv: R
e
mov
e
the
h
ar
d
cod
e
d SSTATUS_SD m
a
c
ro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
is
t
air Francis
target/ris
c
v: Re
m
ove the
h
ardcoded RVX
L
EN macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fran
c
is
target/riscv:
Add e
P
M
P
supp
o
r
t for
the
Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fran
c
is
targe
t
/riscv/pmp:
Remove outdated comment
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Fra
n
c
is
t
a
r
g
e
t/riscv: Add
t
h
e
ePMP feature
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
listai
r
Francis
targ
e
t/ri
s
cv: Fix the PMP i
s
locked check wh
e
n using TOR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fr
a
nc
i
s
hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alis
t
air F
r
ancis
hw/openti
t
an:
Update the
i
nterrupt layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistai
r
Fran
c
i
s
M
A
INTA
I
NERS: Up
d
ate t
h
e RISC-V CP
U
Main
t
ainers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
Franc
i
s
target/riscv: Us
e
R
ISCVExce
p
tion
e
num for CSR ac
c
ess
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
lista
i
r
Francis
targ
e
t/ris
c
v
: Use the R
I
SCVException enum
f
or CSR
o
p
eratio
n
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
listair Francis
ta
r
get/r
i
sc
v
:
F
i
x 32-bit
H
S
mode access perm
i
s
s
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
tar
g
et/riscv
:
U
se the R
I
SCVException
e
nu
m
for CSR pr
e
dicates
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Francis
target/r
i
scv: Convert
the RISC-V
exc
e
pt
i
ons to an en
u
m
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Ali
s
tair Francis
MAINTAINERS: Add a SiFive m
a
chine s
e
ction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistair Francis
linux-
u
ser/si
g
nal: Decode
w
aitid si_
c
ode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Alistair Francis
ris
c
v: Pass
RISC
V
HartArraySta
t
e by pointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair
F
rancis
riscv/opent
i
tan: Update the OpenTitan memory la
y
out
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Francis
hw/ris
c
v: Use
t
h
e CPU
to determine if 3
2
-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fran
c
is
target/riscv: cpu:
S
et XLEN independe
n
tly from
t
arg
e
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
s
ta
i
r Francis
target/riscv: csr: Remove
c
ompile time
XLEN c
h
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
list
a
i
r
Francis
target/riscv:
c
pu
_
h
e
l
p
er: R
e
move
c
ompile time XLEN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Franc
i
s
targ
e
t/riscv: cpu: Re
m
o
v
e compile time XLEN
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Fra
n
ci
s
targe
t
/r
i
sc
v
: Sp
e
cify t
h
e XLEN for CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
a
n
c
is
target/riscv
:
A
dd a r
i
s
c
v
_cpu
_
is_32bit() h
e
lper functi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Fr
a
ncis
target/riscv:
f
p
u_helper: Match function defs in
HELP
E
R
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tai
r
Franc
i
s
h
w
/
riscv:
s
i
f
i
ve_u: Rem
o
v
e
com
p
ile time XLEN c
h
ecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
ta
i
r Fr
a
ncis
hw/r
i
scv:
s
p
ike: R
e
move com
p
ile time XLEN chec
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/
r
is
c
v: virt
:
Remove co
m
pile t
i
me
XLEN
c
hecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
next