Make it obvious that pci_nic_init() can't fail
[qemu-kvm/fedora.git] / ppc-dis.c
blobca5765a60e13074e65375f201d1d39cd80eaadfb
1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not,
20 see <http://www.gnu.org/licenses/>. */
21 #include "dis-asm.h"
22 #define BFD_DEFAULT_TARGET_SIZE 64
24 /* ppc.h -- Header file for PowerPC opcode table
25 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
26 2007 Free Software Foundation, Inc.
27 Written by Ian Lance Taylor, Cygnus Support
29 This file is part of GDB, GAS, and the GNU binutils.
31 GDB, GAS, and the GNU binutils are free software; you can redistribute
32 them and/or modify them under the terms of the GNU General Public
33 License as published by the Free Software Foundation; either version
34 1, or (at your option) any later version.
36 GDB, GAS, and the GNU binutils are distributed in the hope that they
37 will be useful, but WITHOUT ANY WARRANTY; without even the implied
38 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
39 the GNU General Public License for more details.
41 You should have received a copy of the GNU General Public License
42 along with this file; see the file COPYING. If not,
43 see <http://www.gnu.org/licenses/>. */
45 /* The opcode table is an array of struct powerpc_opcode. */
47 struct powerpc_opcode
49 /* The opcode name. */
50 const char *name;
52 /* The opcode itself. Those bits which will be filled in with
53 operands are zeroes. */
54 unsigned long opcode;
56 /* The opcode mask. This is used by the disassembler. This is a
57 mask containing ones indicating those bits which must match the
58 opcode field, and zeroes indicating those bits which need not
59 match (and are presumably filled in by operands). */
60 unsigned long mask;
62 /* One bit flags for the opcode. These are used to indicate which
63 specific processors support the instructions. The defined values
64 are listed below. */
65 unsigned long flags;
67 /* An array of operand codes. Each code is an index into the
68 operand table. They appear in the order which the operands must
69 appear in assembly code, and are terminated by a zero. */
70 unsigned char operands[8];
73 /* The table itself is sorted by major opcode number, and is otherwise
74 in the order in which the disassembler should consider
75 instructions. */
76 extern const struct powerpc_opcode powerpc_opcodes[];
77 extern const int powerpc_num_opcodes;
79 /* Values defined for the flags field of a struct powerpc_opcode. */
81 /* Opcode is defined for the PowerPC architecture. */
82 #define PPC_OPCODE_PPC 1
84 /* Opcode is defined for the POWER (RS/6000) architecture. */
85 #define PPC_OPCODE_POWER 2
87 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
88 #define PPC_OPCODE_POWER2 4
90 /* Opcode is only defined on 32 bit architectures. */
91 #define PPC_OPCODE_32 8
93 /* Opcode is only defined on 64 bit architectures. */
94 #define PPC_OPCODE_64 0x10
96 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
97 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
98 but it also supports many additional POWER instructions. */
99 #define PPC_OPCODE_601 0x20
101 /* Opcode is supported in both the Power and PowerPC architectures
102 (ie, compiler's -mcpu=common or assembler's -mcom). */
103 #define PPC_OPCODE_COMMON 0x40
105 /* Opcode is supported for any Power or PowerPC platform (this is
106 for the assembler's -many option, and it eliminates duplicates). */
107 #define PPC_OPCODE_ANY 0x80
109 /* Opcode is supported as part of the 64-bit bridge. */
110 #define PPC_OPCODE_64_BRIDGE 0x100
112 /* Opcode is supported by Altivec Vector Unit */
113 #define PPC_OPCODE_ALTIVEC 0x200
115 /* Opcode is supported by PowerPC 403 processor. */
116 #define PPC_OPCODE_403 0x400
118 /* Opcode is supported by PowerPC BookE processor. */
119 #define PPC_OPCODE_BOOKE 0x800
121 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
122 #define PPC_OPCODE_BOOKE64 0x1000
124 /* Opcode is supported by PowerPC 440 processor. */
125 #define PPC_OPCODE_440 0x2000
127 /* Opcode is only supported by Power4 architecture. */
128 #define PPC_OPCODE_POWER4 0x4000
130 /* Opcode isn't supported by Power4 architecture. */
131 #define PPC_OPCODE_NOPOWER4 0x8000
133 /* Opcode is only supported by POWERPC Classic architecture. */
134 #define PPC_OPCODE_CLASSIC 0x10000
136 /* Opcode is only supported by e500x2 Core. */
137 #define PPC_OPCODE_SPE 0x20000
139 /* Opcode is supported by e500x2 Integer select APU. */
140 #define PPC_OPCODE_ISEL 0x40000
142 /* Opcode is an e500 SPE floating point instruction. */
143 #define PPC_OPCODE_EFS 0x80000
145 /* Opcode is supported by branch locking APU. */
146 #define PPC_OPCODE_BRLOCK 0x100000
148 /* Opcode is supported by performance monitor APU. */
149 #define PPC_OPCODE_PMR 0x200000
151 /* Opcode is supported by cache locking APU. */
152 #define PPC_OPCODE_CACHELCK 0x400000
154 /* Opcode is supported by machine check APU. */
155 #define PPC_OPCODE_RFMCI 0x800000
157 /* Opcode is only supported by Power5 architecture. */
158 #define PPC_OPCODE_POWER5 0x1000000
160 /* Opcode is supported by PowerPC e300 family. */
161 #define PPC_OPCODE_E300 0x2000000
163 /* Opcode is only supported by Power6 architecture. */
164 #define PPC_OPCODE_POWER6 0x4000000
166 /* Opcode is only supported by PowerPC Cell family. */
167 #define PPC_OPCODE_CELL 0x8000000
169 /* A macro to extract the major opcode from an instruction. */
170 #define PPC_OP(i) (((i) >> 26) & 0x3f)
172 /* The operands table is an array of struct powerpc_operand. */
174 struct powerpc_operand
176 /* A bitmask of bits in the operand. */
177 unsigned int bitm;
179 /* How far the operand is left shifted in the instruction.
180 -1 to indicate that BITM and SHIFT cannot be used to determine
181 where the operand goes in the insn. */
182 int shift;
184 /* Insertion function. This is used by the assembler. To insert an
185 operand value into an instruction, check this field.
187 If it is NULL, execute
188 i |= (op & o->bitm) << o->shift;
189 (i is the instruction which we are filling in, o is a pointer to
190 this structure, and op is the operand value).
192 If this field is not NULL, then simply call it with the
193 instruction and the operand value. It will return the new value
194 of the instruction. If the ERRMSG argument is not NULL, then if
195 the operand value is illegal, *ERRMSG will be set to a warning
196 string (the operand will be inserted in any case). If the
197 operand value is legal, *ERRMSG will be unchanged (most operands
198 can accept any value). */
199 unsigned long (*insert)
200 (unsigned long instruction, long op, int dialect, const char **errmsg);
202 /* Extraction function. This is used by the disassembler. To
203 extract this operand type from an instruction, check this field.
205 If it is NULL, compute
206 op = (i >> o->shift) & o->bitm;
207 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
208 sign_extend (op);
209 (i is the instruction, o is a pointer to this structure, and op
210 is the result).
212 If this field is not NULL, then simply call it with the
213 instruction value. It will return the value of the operand. If
214 the INVALID argument is not NULL, *INVALID will be set to
215 non-zero if this operand type can not actually be extracted from
216 this operand (i.e., the instruction does not match). If the
217 operand is valid, *INVALID will not be changed. */
218 long (*extract) (unsigned long instruction, int dialect, int *invalid);
220 /* One bit syntax flags. */
221 unsigned long flags;
224 /* Elements in the table are retrieved by indexing with values from
225 the operands field of the powerpc_opcodes table. */
227 extern const struct powerpc_operand powerpc_operands[];
228 extern const unsigned int num_powerpc_operands;
230 /* Values defined for the flags field of a struct powerpc_operand. */
232 /* This operand takes signed values. */
233 #define PPC_OPERAND_SIGNED (0x1)
235 /* This operand takes signed values, but also accepts a full positive
236 range of values when running in 32 bit mode. That is, if bits is
237 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
238 this flag is ignored. */
239 #define PPC_OPERAND_SIGNOPT (0x2)
241 /* This operand does not actually exist in the assembler input. This
242 is used to support extended mnemonics such as mr, for which two
243 operands fields are identical. The assembler should call the
244 insert function with any op value. The disassembler should call
245 the extract function, ignore the return value, and check the value
246 placed in the valid argument. */
247 #define PPC_OPERAND_FAKE (0x4)
249 /* The next operand should be wrapped in parentheses rather than
250 separated from this one by a comma. This is used for the load and
251 store instructions which want their operands to look like
252 reg,displacement(reg)
254 #define PPC_OPERAND_PARENS (0x8)
256 /* This operand may use the symbolic names for the CR fields, which
258 lt 0 gt 1 eq 2 so 3 un 3
259 cr0 0 cr1 1 cr2 2 cr3 3
260 cr4 4 cr5 5 cr6 6 cr7 7
261 These may be combined arithmetically, as in cr2*4+gt. These are
262 only supported on the PowerPC, not the POWER. */
263 #define PPC_OPERAND_CR (0x10)
265 /* This operand names a register. The disassembler uses this to print
266 register names with a leading 'r'. */
267 #define PPC_OPERAND_GPR (0x20)
269 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
270 #define PPC_OPERAND_GPR_0 (0x40)
272 /* This operand names a floating point register. The disassembler
273 prints these with a leading 'f'. */
274 #define PPC_OPERAND_FPR (0x80)
276 /* This operand is a relative branch displacement. The disassembler
277 prints these symbolically if possible. */
278 #define PPC_OPERAND_RELATIVE (0x100)
280 /* This operand is an absolute branch address. The disassembler
281 prints these symbolically if possible. */
282 #define PPC_OPERAND_ABSOLUTE (0x200)
284 /* This operand is optional, and is zero if omitted. This is used for
285 example, in the optional BF field in the comparison instructions. The
286 assembler must count the number of operands remaining on the line,
287 and the number of operands remaining for the opcode, and decide
288 whether this operand is present or not. The disassembler should
289 print this operand out only if it is not zero. */
290 #define PPC_OPERAND_OPTIONAL (0x400)
292 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
293 is omitted, then for the next operand use this operand value plus
294 1, ignoring the next operand field for the opcode. This wretched
295 hack is needed because the Power rotate instructions can take
296 either 4 or 5 operands. The disassembler should print this operand
297 out regardless of the PPC_OPERAND_OPTIONAL field. */
298 #define PPC_OPERAND_NEXT (0x800)
300 /* This operand should be regarded as a negative number for the
301 purposes of overflow checking (i.e., the normal most negative
302 number is disallowed and one more than the normal most positive
303 number is allowed). This flag will only be set for a signed
304 operand. */
305 #define PPC_OPERAND_NEGATIVE (0x1000)
307 /* This operand names a vector unit register. The disassembler
308 prints these with a leading 'v'. */
309 #define PPC_OPERAND_VR (0x2000)
311 /* This operand is for the DS field in a DS form instruction. */
312 #define PPC_OPERAND_DS (0x4000)
314 /* This operand is for the DQ field in a DQ form instruction. */
315 #define PPC_OPERAND_DQ (0x8000)
317 /* Valid range of operand is 0..n rather than 0..n-1. */
318 #define PPC_OPERAND_PLUS1 (0x10000)
320 /* The POWER and PowerPC assemblers use a few macros. We keep them
321 with the operands table for simplicity. The macro table is an
322 array of struct powerpc_macro. */
324 struct powerpc_macro
326 /* The macro name. */
327 const char *name;
329 /* The number of operands the macro takes. */
330 unsigned int operands;
332 /* One bit flags for the opcode. These are used to indicate which
333 specific processors support the instructions. The values are the
334 same as those for the struct powerpc_opcode flags field. */
335 unsigned long flags;
337 /* A format string to turn the macro into a normal instruction.
338 Each %N in the string is replaced with operand number N (zero
339 based). */
340 const char *format;
343 extern const struct powerpc_macro powerpc_macros[];
344 extern const int powerpc_num_macros;
346 /* ppc-opc.c -- PowerPC opcode list
347 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
348 2005, 2006, 2007 Free Software Foundation, Inc.
349 Written by Ian Lance Taylor, Cygnus Support
351 This file is part of GDB, GAS, and the GNU binutils.
353 GDB, GAS, and the GNU binutils are free software; you can redistribute
354 them and/or modify them under the terms of the GNU General Public
355 License as published by the Free Software Foundation; either version
356 2, or (at your option) any later version.
358 GDB, GAS, and the GNU binutils are distributed in the hope that they
359 will be useful, but WITHOUT ANY WARRANTY; without even the implied
360 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
361 the GNU General Public License for more details.
363 You should have received a copy of the GNU General Public License
364 along with this file; see the file COPYING.
365 If not, see <http://www.gnu.org/licenses/>. */
367 /* This file holds the PowerPC opcode table. The opcode table
368 includes almost all of the extended instruction mnemonics. This
369 permits the disassembler to use them, and simplifies the assembler
370 logic, at the cost of increasing the table size. The table is
371 strictly constant data, so the compiler should be able to put it in
372 the .text section.
374 This file also holds the operand table. All knowledge about
375 inserting operands into instructions and vice-versa is kept in this
376 file. */
378 /* Local insertion and extraction functions. */
380 static unsigned long insert_bat (unsigned long, long, int, const char **);
381 static long extract_bat (unsigned long, int, int *);
382 static unsigned long insert_bba (unsigned long, long, int, const char **);
383 static long extract_bba (unsigned long, int, int *);
384 static unsigned long insert_bdm (unsigned long, long, int, const char **);
385 static long extract_bdm (unsigned long, int, int *);
386 static unsigned long insert_bdp (unsigned long, long, int, const char **);
387 static long extract_bdp (unsigned long, int, int *);
388 static unsigned long insert_bo (unsigned long, long, int, const char **);
389 static long extract_bo (unsigned long, int, int *);
390 static unsigned long insert_boe (unsigned long, long, int, const char **);
391 static long extract_boe (unsigned long, int, int *);
392 static unsigned long insert_fxm (unsigned long, long, int, const char **);
393 static long extract_fxm (unsigned long, int, int *);
394 static unsigned long insert_mbe (unsigned long, long, int, const char **);
395 static long extract_mbe (unsigned long, int, int *);
396 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
397 static long extract_mb6 (unsigned long, int, int *);
398 static long extract_nb (unsigned long, int, int *);
399 static unsigned long insert_nsi (unsigned long, long, int, const char **);
400 static long extract_nsi (unsigned long, int, int *);
401 static unsigned long insert_ral (unsigned long, long, int, const char **);
402 static unsigned long insert_ram (unsigned long, long, int, const char **);
403 static unsigned long insert_raq (unsigned long, long, int, const char **);
404 static unsigned long insert_ras (unsigned long, long, int, const char **);
405 static unsigned long insert_rbs (unsigned long, long, int, const char **);
406 static long extract_rbs (unsigned long, int, int *);
407 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
408 static long extract_sh6 (unsigned long, int, int *);
409 static unsigned long insert_spr (unsigned long, long, int, const char **);
410 static long extract_spr (unsigned long, int, int *);
411 static unsigned long insert_sprg (unsigned long, long, int, const char **);
412 static long extract_sprg (unsigned long, int, int *);
413 static unsigned long insert_tbr (unsigned long, long, int, const char **);
414 static long extract_tbr (unsigned long, int, int *);
416 /* The operands table.
418 The fields are bitm, shift, insert, extract, flags.
420 We used to put parens around the various additions, like the one
421 for BA just below. However, that caused trouble with feeble
422 compilers with a limit on depth of a parenthesized expression, like
423 (reportedly) the compiler in Microsoft Developer Studio 5. So we
424 omit the parens, since the macros are never used in a context where
425 the addition will be ambiguous. */
427 const struct powerpc_operand powerpc_operands[] =
429 /* The zero index is used to indicate the end of the list of
430 operands. */
431 #define UNUSED 0
432 { 0, 0, NULL, NULL, 0 },
434 /* The BA field in an XL form instruction. */
435 #define BA UNUSED + 1
436 /* The BI field in a B form or XL form instruction. */
437 #define BI BA
438 #define BI_MASK (0x1f << 16)
439 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
441 /* The BA field in an XL form instruction when it must be the same
442 as the BT field in the same instruction. */
443 #define BAT BA + 1
444 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
446 /* The BB field in an XL form instruction. */
447 #define BB BAT + 1
448 #define BB_MASK (0x1f << 11)
449 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
451 /* The BB field in an XL form instruction when it must be the same
452 as the BA field in the same instruction. */
453 #define BBA BB + 1
454 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
456 /* The BD field in a B form instruction. The lower two bits are
457 forced to zero. */
458 #define BD BBA + 1
459 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
461 /* The BD field in a B form instruction when absolute addressing is
462 used. */
463 #define BDA BD + 1
464 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
466 /* The BD field in a B form instruction when the - modifier is used.
467 This sets the y bit of the BO field appropriately. */
468 #define BDM BDA + 1
469 { 0xfffc, 0, insert_bdm, extract_bdm,
470 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
472 /* The BD field in a B form instruction when the - modifier is used
473 and absolute address is used. */
474 #define BDMA BDM + 1
475 { 0xfffc, 0, insert_bdm, extract_bdm,
476 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
478 /* The BD field in a B form instruction when the + modifier is used.
479 This sets the y bit of the BO field appropriately. */
480 #define BDP BDMA + 1
481 { 0xfffc, 0, insert_bdp, extract_bdp,
482 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
484 /* The BD field in a B form instruction when the + modifier is used
485 and absolute addressing is used. */
486 #define BDPA BDP + 1
487 { 0xfffc, 0, insert_bdp, extract_bdp,
488 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
490 /* The BF field in an X or XL form instruction. */
491 #define BF BDPA + 1
492 /* The CRFD field in an X form instruction. */
493 #define CRFD BF
494 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
496 /* The BF field in an X or XL form instruction. */
497 #define BFF BF + 1
498 { 0x7, 23, NULL, NULL, 0 },
500 /* An optional BF field. This is used for comparison instructions,
501 in which an omitted BF field is taken as zero. */
502 #define OBF BFF + 1
503 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
505 /* The BFA field in an X or XL form instruction. */
506 #define BFA OBF + 1
507 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
509 /* The BO field in a B form instruction. Certain values are
510 illegal. */
511 #define BO BFA + 1
512 #define BO_MASK (0x1f << 21)
513 { 0x1f, 21, insert_bo, extract_bo, 0 },
515 /* The BO field in a B form instruction when the + or - modifier is
516 used. This is like the BO field, but it must be even. */
517 #define BOE BO + 1
518 { 0x1e, 21, insert_boe, extract_boe, 0 },
520 #define BH BOE + 1
521 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
523 /* The BT field in an X or XL form instruction. */
524 #define BT BH + 1
525 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
527 /* The condition register number portion of the BI field in a B form
528 or XL form instruction. This is used for the extended
529 conditional branch mnemonics, which set the lower two bits of the
530 BI field. This field is optional. */
531 #define CR BT + 1
532 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
534 /* The CRB field in an X form instruction. */
535 #define CRB CR + 1
536 /* The MB field in an M form instruction. */
537 #define MB CRB
538 #define MB_MASK (0x1f << 6)
539 { 0x1f, 6, NULL, NULL, 0 },
541 /* The CRFS field in an X form instruction. */
542 #define CRFS CRB + 1
543 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
545 /* The CT field in an X form instruction. */
546 #define CT CRFS + 1
547 /* The MO field in an mbar instruction. */
548 #define MO CT
549 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
551 /* The D field in a D form instruction. This is a displacement off
552 a register, and implies that the next operand is a register in
553 parentheses. */
554 #define D CT + 1
555 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
557 /* The DE field in a DE form instruction. This is like D, but is 12
558 bits only. */
559 #define DE D + 1
560 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
562 /* The DES field in a DES form instruction. This is like DS, but is 14
563 bits only (12 stored.) */
564 #define DES DE + 1
565 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
567 /* The DQ field in a DQ form instruction. This is like D, but the
568 lower four bits are forced to zero. */
569 #define DQ DES + 1
570 { 0xfff0, 0, NULL, NULL,
571 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
573 /* The DS field in a DS form instruction. This is like D, but the
574 lower two bits are forced to zero. */
575 #define DS DQ + 1
576 { 0xfffc, 0, NULL, NULL,
577 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
579 /* The E field in a wrteei instruction. */
580 #define E DS + 1
581 { 0x1, 15, NULL, NULL, 0 },
583 /* The FL1 field in a POWER SC form instruction. */
584 #define FL1 E + 1
585 /* The U field in an X form instruction. */
586 #define U FL1
587 { 0xf, 12, NULL, NULL, 0 },
589 /* The FL2 field in a POWER SC form instruction. */
590 #define FL2 FL1 + 1
591 { 0x7, 2, NULL, NULL, 0 },
593 /* The FLM field in an XFL form instruction. */
594 #define FLM FL2 + 1
595 { 0xff, 17, NULL, NULL, 0 },
597 /* The FRA field in an X or A form instruction. */
598 #define FRA FLM + 1
599 #define FRA_MASK (0x1f << 16)
600 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
602 /* The FRB field in an X or A form instruction. */
603 #define FRB FRA + 1
604 #define FRB_MASK (0x1f << 11)
605 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
607 /* The FRC field in an A form instruction. */
608 #define FRC FRB + 1
609 #define FRC_MASK (0x1f << 6)
610 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
612 /* The FRS field in an X form instruction or the FRT field in a D, X
613 or A form instruction. */
614 #define FRS FRC + 1
615 #define FRT FRS
616 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
618 /* The FXM field in an XFX instruction. */
619 #define FXM FRS + 1
620 { 0xff, 12, insert_fxm, extract_fxm, 0 },
622 /* Power4 version for mfcr. */
623 #define FXM4 FXM + 1
624 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
626 /* The L field in a D or X form instruction. */
627 #define L FXM4 + 1
628 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
630 /* The LEV field in a POWER SVC form instruction. */
631 #define SVC_LEV L + 1
632 { 0x7f, 5, NULL, NULL, 0 },
634 /* The LEV field in an SC form instruction. */
635 #define LEV SVC_LEV + 1
636 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
638 /* The LI field in an I form instruction. The lower two bits are
639 forced to zero. */
640 #define LI LEV + 1
641 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
643 /* The LI field in an I form instruction when used as an absolute
644 address. */
645 #define LIA LI + 1
646 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
648 /* The LS field in an X (sync) form instruction. */
649 #define LS LIA + 1
650 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
652 /* The ME field in an M form instruction. */
653 #define ME LS + 1
654 #define ME_MASK (0x1f << 1)
655 { 0x1f, 1, NULL, NULL, 0 },
657 /* The MB and ME fields in an M form instruction expressed a single
658 operand which is a bitmask indicating which bits to select. This
659 is a two operand form using PPC_OPERAND_NEXT. See the
660 description in opcode/ppc.h for what this means. */
661 #define MBE ME + 1
662 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
663 { -1, 0, insert_mbe, extract_mbe, 0 },
665 /* The MB or ME field in an MD or MDS form instruction. The high
666 bit is wrapped to the low end. */
667 #define MB6 MBE + 2
668 #define ME6 MB6
669 #define MB6_MASK (0x3f << 5)
670 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
672 /* The NB field in an X form instruction. The value 32 is stored as
673 0. */
674 #define NB MB6 + 1
675 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
677 /* The NSI field in a D form instruction. This is the same as the
678 SI field, only negated. */
679 #define NSI NB + 1
680 { 0xffff, 0, insert_nsi, extract_nsi,
681 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
683 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
684 #define RA NSI + 1
685 #define RA_MASK (0x1f << 16)
686 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
688 /* As above, but 0 in the RA field means zero, not r0. */
689 #define RA0 RA + 1
690 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
692 /* The RA field in the DQ form lq instruction, which has special
693 value restrictions. */
694 #define RAQ RA0 + 1
695 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
697 /* The RA field in a D or X form instruction which is an updating
698 load, which means that the RA field may not be zero and may not
699 equal the RT field. */
700 #define RAL RAQ + 1
701 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
703 /* The RA field in an lmw instruction, which has special value
704 restrictions. */
705 #define RAM RAL + 1
706 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
708 /* The RA field in a D or X form instruction which is an updating
709 store or an updating floating point load, which means that the RA
710 field may not be zero. */
711 #define RAS RAM + 1
712 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
714 /* The RA field of the tlbwe instruction, which is optional. */
715 #define RAOPT RAS + 1
716 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
718 /* The RB field in an X, XO, M, or MDS form instruction. */
719 #define RB RAOPT + 1
720 #define RB_MASK (0x1f << 11)
721 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
723 /* The RB field in an X form instruction when it must be the same as
724 the RS field in the instruction. This is used for extended
725 mnemonics like mr. */
726 #define RBS RB + 1
727 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
729 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
730 instruction or the RT field in a D, DS, X, XFX or XO form
731 instruction. */
732 #define RS RBS + 1
733 #define RT RS
734 #define RT_MASK (0x1f << 21)
735 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
737 /* The RS and RT fields of the DS form stq instruction, which have
738 special value restrictions. */
739 #define RSQ RS + 1
740 #define RTQ RSQ
741 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
743 /* The RS field of the tlbwe instruction, which is optional. */
744 #define RSO RSQ + 1
745 #define RTO RSO
746 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
748 /* The SH field in an X or M form instruction. */
749 #define SH RSO + 1
750 #define SH_MASK (0x1f << 11)
751 /* The other UIMM field in a EVX form instruction. */
752 #define EVUIMM SH
753 { 0x1f, 11, NULL, NULL, 0 },
755 /* The SH field in an MD form instruction. This is split. */
756 #define SH6 SH + 1
757 #define SH6_MASK ((0x1f << 11) | (1 << 1))
758 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
760 /* The SH field of the tlbwe instruction, which is optional. */
761 #define SHO SH6 + 1
762 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
764 /* The SI field in a D form instruction. */
765 #define SI SHO + 1
766 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
768 /* The SI field in a D form instruction when we accept a wide range
769 of positive values. */
770 #define SISIGNOPT SI + 1
771 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
773 /* The SPR field in an XFX form instruction. This is flipped--the
774 lower 5 bits are stored in the upper 5 and vice- versa. */
775 #define SPR SISIGNOPT + 1
776 #define PMR SPR
777 #define SPR_MASK (0x3ff << 11)
778 { 0x3ff, 11, insert_spr, extract_spr, 0 },
780 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
781 #define SPRBAT SPR + 1
782 #define SPRBAT_MASK (0x3 << 17)
783 { 0x3, 17, NULL, NULL, 0 },
785 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
786 #define SPRG SPRBAT + 1
787 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
789 /* The SR field in an X form instruction. */
790 #define SR SPRG + 1
791 { 0xf, 16, NULL, NULL, 0 },
793 /* The STRM field in an X AltiVec form instruction. */
794 #define STRM SR + 1
795 { 0x3, 21, NULL, NULL, 0 },
797 /* The SV field in a POWER SC form instruction. */
798 #define SV STRM + 1
799 { 0x3fff, 2, NULL, NULL, 0 },
801 /* The TBR field in an XFX form instruction. This is like the SPR
802 field, but it is optional. */
803 #define TBR SV + 1
804 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
806 /* The TO field in a D or X form instruction. */
807 #define TO TBR + 1
808 #define TO_MASK (0x1f << 21)
809 { 0x1f, 21, NULL, NULL, 0 },
811 /* The UI field in a D form instruction. */
812 #define UI TO + 1
813 { 0xffff, 0, NULL, NULL, 0 },
815 /* The VA field in a VA, VX or VXR form instruction. */
816 #define VA UI + 1
817 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
819 /* The VB field in a VA, VX or VXR form instruction. */
820 #define VB VA + 1
821 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
823 /* The VC field in a VA form instruction. */
824 #define VC VB + 1
825 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
827 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
828 #define VD VC + 1
829 #define VS VD
830 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
832 /* The SIMM field in a VX form instruction. */
833 #define SIMM VD + 1
834 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
836 /* The UIMM field in a VX form instruction, and TE in Z form. */
837 #define UIMM SIMM + 1
838 #define TE UIMM
839 { 0x1f, 16, NULL, NULL, 0 },
841 /* The SHB field in a VA form instruction. */
842 #define SHB UIMM + 1
843 { 0xf, 6, NULL, NULL, 0 },
845 /* The other UIMM field in a half word EVX form instruction. */
846 #define EVUIMM_2 SHB + 1
847 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
849 /* The other UIMM field in a word EVX form instruction. */
850 #define EVUIMM_4 EVUIMM_2 + 1
851 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
853 /* The other UIMM field in a double EVX form instruction. */
854 #define EVUIMM_8 EVUIMM_4 + 1
855 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
857 /* The WS field. */
858 #define WS EVUIMM_8 + 1
859 { 0x7, 11, NULL, NULL, 0 },
861 /* The L field in an mtmsrd or A form instruction or W in an X form. */
862 #define A_L WS + 1
863 #define W A_L
864 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
866 #define RMC A_L + 1
867 { 0x3, 9, NULL, NULL, 0 },
869 #define R RMC + 1
870 { 0x1, 16, NULL, NULL, 0 },
872 #define SP R + 1
873 { 0x3, 19, NULL, NULL, 0 },
875 #define S SP + 1
876 { 0x1, 20, NULL, NULL, 0 },
878 /* SH field starting at bit position 16. */
879 #define SH16 S + 1
880 /* The DCM and DGM fields in a Z form instruction. */
881 #define DCM SH16
882 #define DGM DCM
883 { 0x3f, 10, NULL, NULL, 0 },
885 /* The EH field in larx instruction. */
886 #define EH SH16 + 1
887 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
889 /* The L field in an mtfsf or XFL form instruction. */
890 #define XFL_L EH + 1
891 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
894 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
895 / sizeof (powerpc_operands[0]));
897 /* The functions used to insert and extract complicated operands. */
899 /* The BA field in an XL form instruction when it must be the same as
900 the BT field in the same instruction. This operand is marked FAKE.
901 The insertion function just copies the BT field into the BA field,
902 and the extraction function just checks that the fields are the
903 same. */
905 static unsigned long
906 insert_bat (unsigned long insn,
907 long value ATTRIBUTE_UNUSED,
908 int dialect ATTRIBUTE_UNUSED,
909 const char **errmsg ATTRIBUTE_UNUSED)
911 return insn | (((insn >> 21) & 0x1f) << 16);
914 static long
915 extract_bat (unsigned long insn,
916 int dialect ATTRIBUTE_UNUSED,
917 int *invalid)
919 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
920 *invalid = 1;
921 return 0;
924 /* The BB field in an XL form instruction when it must be the same as
925 the BA field in the same instruction. This operand is marked FAKE.
926 The insertion function just copies the BA field into the BB field,
927 and the extraction function just checks that the fields are the
928 same. */
930 static unsigned long
931 insert_bba (unsigned long insn,
932 long value ATTRIBUTE_UNUSED,
933 int dialect ATTRIBUTE_UNUSED,
934 const char **errmsg ATTRIBUTE_UNUSED)
936 return insn | (((insn >> 16) & 0x1f) << 11);
939 static long
940 extract_bba (unsigned long insn,
941 int dialect ATTRIBUTE_UNUSED,
942 int *invalid)
944 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
945 *invalid = 1;
946 return 0;
949 /* The BD field in a B form instruction when the - modifier is used.
950 This modifier means that the branch is not expected to be taken.
951 For chips built to versions of the architecture prior to version 2
952 (ie. not Power4 compatible), we set the y bit of the BO field to 1
953 if the offset is negative. When extracting, we require that the y
954 bit be 1 and that the offset be positive, since if the y bit is 0
955 we just want to print the normal form of the instruction.
956 Power4 compatible targets use two bits, "a", and "t", instead of
957 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
958 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
959 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
960 for branch on CTR. We only handle the taken/not-taken hint here.
961 Note that we don't relax the conditions tested here when
962 disassembling with -Many because insns using extract_bdm and
963 extract_bdp always occur in pairs. One or the other will always
964 be valid. */
966 static unsigned long
967 insert_bdm (unsigned long insn,
968 long value,
969 int dialect,
970 const char **errmsg ATTRIBUTE_UNUSED)
972 if ((dialect & PPC_OPCODE_POWER4) == 0)
974 if ((value & 0x8000) != 0)
975 insn |= 1 << 21;
977 else
979 if ((insn & (0x14 << 21)) == (0x04 << 21))
980 insn |= 0x02 << 21;
981 else if ((insn & (0x14 << 21)) == (0x10 << 21))
982 insn |= 0x08 << 21;
984 return insn | (value & 0xfffc);
987 static long
988 extract_bdm (unsigned long insn,
989 int dialect,
990 int *invalid)
992 if ((dialect & PPC_OPCODE_POWER4) == 0)
994 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
995 *invalid = 1;
997 else
999 if ((insn & (0x17 << 21)) != (0x06 << 21)
1000 && (insn & (0x1d << 21)) != (0x18 << 21))
1001 *invalid = 1;
1004 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1007 /* The BD field in a B form instruction when the + modifier is used.
1008 This is like BDM, above, except that the branch is expected to be
1009 taken. */
1011 static unsigned long
1012 insert_bdp (unsigned long insn,
1013 long value,
1014 int dialect,
1015 const char **errmsg ATTRIBUTE_UNUSED)
1017 if ((dialect & PPC_OPCODE_POWER4) == 0)
1019 if ((value & 0x8000) == 0)
1020 insn |= 1 << 21;
1022 else
1024 if ((insn & (0x14 << 21)) == (0x04 << 21))
1025 insn |= 0x03 << 21;
1026 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1027 insn |= 0x09 << 21;
1029 return insn | (value & 0xfffc);
1032 static long
1033 extract_bdp (unsigned long insn,
1034 int dialect,
1035 int *invalid)
1037 if ((dialect & PPC_OPCODE_POWER4) == 0)
1039 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1040 *invalid = 1;
1042 else
1044 if ((insn & (0x17 << 21)) != (0x07 << 21)
1045 && (insn & (0x1d << 21)) != (0x19 << 21))
1046 *invalid = 1;
1049 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1052 /* Check for legal values of a BO field. */
1054 static int
1055 valid_bo (long value, int dialect, int extract)
1057 if ((dialect & PPC_OPCODE_POWER4) == 0)
1059 int valid;
1060 /* Certain encodings have bits that are required to be zero.
1061 These are (z must be zero, y may be anything):
1062 001zy
1063 011zy
1064 1z00y
1065 1z01y
1066 1z1zz
1068 switch (value & 0x14)
1070 default:
1071 case 0:
1072 valid = 1;
1073 break;
1074 case 0x4:
1075 valid = (value & 0x2) == 0;
1076 break;
1077 case 0x10:
1078 valid = (value & 0x8) == 0;
1079 break;
1080 case 0x14:
1081 valid = value == 0x14;
1082 break;
1084 /* When disassembling with -Many, accept power4 encodings too. */
1085 if (valid
1086 || (dialect & PPC_OPCODE_ANY) == 0
1087 || !extract)
1088 return valid;
1091 /* Certain encodings have bits that are required to be zero.
1092 These are (z must be zero, a & t may be anything):
1093 0000z
1094 0001z
1095 0100z
1096 0101z
1097 001at
1098 011at
1099 1a00t
1100 1a01t
1101 1z1zz
1103 if ((value & 0x14) == 0)
1104 return (value & 0x1) == 0;
1105 else if ((value & 0x14) == 0x14)
1106 return value == 0x14;
1107 else
1108 return 1;
1111 /* The BO field in a B form instruction. Warn about attempts to set
1112 the field to an illegal value. */
1114 static unsigned long
1115 insert_bo (unsigned long insn,
1116 long value,
1117 int dialect,
1118 const char **errmsg)
1120 if (!valid_bo (value, dialect, 0))
1121 *errmsg = _("invalid conditional option");
1122 return insn | ((value & 0x1f) << 21);
1125 static long
1126 extract_bo (unsigned long insn,
1127 int dialect,
1128 int *invalid)
1130 long value;
1132 value = (insn >> 21) & 0x1f;
1133 if (!valid_bo (value, dialect, 1))
1134 *invalid = 1;
1135 return value;
1138 /* The BO field in a B form instruction when the + or - modifier is
1139 used. This is like the BO field, but it must be even. When
1140 extracting it, we force it to be even. */
1142 static unsigned long
1143 insert_boe (unsigned long insn,
1144 long value,
1145 int dialect,
1146 const char **errmsg)
1148 if (!valid_bo (value, dialect, 0))
1149 *errmsg = _("invalid conditional option");
1150 else if ((value & 1) != 0)
1151 *errmsg = _("attempt to set y bit when using + or - modifier");
1153 return insn | ((value & 0x1f) << 21);
1156 static long
1157 extract_boe (unsigned long insn,
1158 int dialect,
1159 int *invalid)
1161 long value;
1163 value = (insn >> 21) & 0x1f;
1164 if (!valid_bo (value, dialect, 1))
1165 *invalid = 1;
1166 return value & 0x1e;
1169 /* FXM mask in mfcr and mtcrf instructions. */
1171 static unsigned long
1172 insert_fxm (unsigned long insn,
1173 long value,
1174 int dialect,
1175 const char **errmsg)
1177 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1178 one bit of the mask field is set. */
1179 if ((insn & (1 << 20)) != 0)
1181 if (value == 0 || (value & -value) != value)
1183 *errmsg = _("invalid mask field");
1184 value = 0;
1188 /* If the optional field on mfcr is missing that means we want to use
1189 the old form of the instruction that moves the whole cr. In that
1190 case we'll have VALUE zero. There doesn't seem to be a way to
1191 distinguish this from the case where someone writes mfcr %r3,0. */
1192 else if (value == 0)
1195 /* If only one bit of the FXM field is set, we can use the new form
1196 of the instruction, which is faster. Unlike the Power4 branch hint
1197 encoding, this is not backward compatible. Do not generate the
1198 new form unless -mpower4 has been given, or -many and the two
1199 operand form of mfcr was used. */
1200 else if ((value & -value) == value
1201 && ((dialect & PPC_OPCODE_POWER4) != 0
1202 || ((dialect & PPC_OPCODE_ANY) != 0
1203 && (insn & (0x3ff << 1)) == 19 << 1)))
1204 insn |= 1 << 20;
1206 /* Any other value on mfcr is an error. */
1207 else if ((insn & (0x3ff << 1)) == 19 << 1)
1209 *errmsg = _("ignoring invalid mfcr mask");
1210 value = 0;
1213 return insn | ((value & 0xff) << 12);
1216 static long
1217 extract_fxm (unsigned long insn,
1218 int dialect ATTRIBUTE_UNUSED,
1219 int *invalid)
1221 long mask = (insn >> 12) & 0xff;
1223 /* Is this a Power4 insn? */
1224 if ((insn & (1 << 20)) != 0)
1226 /* Exactly one bit of MASK should be set. */
1227 if (mask == 0 || (mask & -mask) != mask)
1228 *invalid = 1;
1231 /* Check that non-power4 form of mfcr has a zero MASK. */
1232 else if ((insn & (0x3ff << 1)) == 19 << 1)
1234 if (mask != 0)
1235 *invalid = 1;
1238 return mask;
1241 /* The MB and ME fields in an M form instruction expressed as a single
1242 operand which is itself a bitmask. The extraction function always
1243 marks it as invalid, since we never want to recognize an
1244 instruction which uses a field of this type. */
1246 static unsigned long
1247 insert_mbe (unsigned long insn,
1248 long value,
1249 int dialect ATTRIBUTE_UNUSED,
1250 const char **errmsg)
1252 unsigned long uval, mask;
1253 int mb, me, mx, count, last;
1255 uval = value;
1257 if (uval == 0)
1259 *errmsg = _("illegal bitmask");
1260 return insn;
1263 mb = 0;
1264 me = 32;
1265 if ((uval & 1) != 0)
1266 last = 1;
1267 else
1268 last = 0;
1269 count = 0;
1271 /* mb: location of last 0->1 transition */
1272 /* me: location of last 1->0 transition */
1273 /* count: # transitions */
1275 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1277 if ((uval & mask) && !last)
1279 ++count;
1280 mb = mx;
1281 last = 1;
1283 else if (!(uval & mask) && last)
1285 ++count;
1286 me = mx;
1287 last = 0;
1290 if (me == 0)
1291 me = 32;
1293 if (count != 2 && (count != 0 || ! last))
1294 *errmsg = _("illegal bitmask");
1296 return insn | (mb << 6) | ((me - 1) << 1);
1299 static long
1300 extract_mbe (unsigned long insn,
1301 int dialect ATTRIBUTE_UNUSED,
1302 int *invalid)
1304 long ret;
1305 int mb, me;
1306 int i;
1308 *invalid = 1;
1310 mb = (insn >> 6) & 0x1f;
1311 me = (insn >> 1) & 0x1f;
1312 if (mb < me + 1)
1314 ret = 0;
1315 for (i = mb; i <= me; i++)
1316 ret |= 1L << (31 - i);
1318 else if (mb == me + 1)
1319 ret = ~0;
1320 else /* (mb > me + 1) */
1322 ret = ~0;
1323 for (i = me + 1; i < mb; i++)
1324 ret &= ~(1L << (31 - i));
1326 return ret;
1329 /* The MB or ME field in an MD or MDS form instruction. The high bit
1330 is wrapped to the low end. */
1332 static unsigned long
1333 insert_mb6 (unsigned long insn,
1334 long value,
1335 int dialect ATTRIBUTE_UNUSED,
1336 const char **errmsg ATTRIBUTE_UNUSED)
1338 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1341 static long
1342 extract_mb6 (unsigned long insn,
1343 int dialect ATTRIBUTE_UNUSED,
1344 int *invalid ATTRIBUTE_UNUSED)
1346 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1349 /* The NB field in an X form instruction. The value 32 is stored as
1350 0. */
1352 static long
1353 extract_nb (unsigned long insn,
1354 int dialect ATTRIBUTE_UNUSED,
1355 int *invalid ATTRIBUTE_UNUSED)
1357 long ret;
1359 ret = (insn >> 11) & 0x1f;
1360 if (ret == 0)
1361 ret = 32;
1362 return ret;
1365 /* The NSI field in a D form instruction. This is the same as the SI
1366 field, only negated. The extraction function always marks it as
1367 invalid, since we never want to recognize an instruction which uses
1368 a field of this type. */
1370 static unsigned long
1371 insert_nsi (unsigned long insn,
1372 long value,
1373 int dialect ATTRIBUTE_UNUSED,
1374 const char **errmsg ATTRIBUTE_UNUSED)
1376 return insn | (-value & 0xffff);
1379 static long
1380 extract_nsi (unsigned long insn,
1381 int dialect ATTRIBUTE_UNUSED,
1382 int *invalid)
1384 *invalid = 1;
1385 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1388 /* The RA field in a D or X form instruction which is an updating
1389 load, which means that the RA field may not be zero and may not
1390 equal the RT field. */
1392 static unsigned long
1393 insert_ral (unsigned long insn,
1394 long value,
1395 int dialect ATTRIBUTE_UNUSED,
1396 const char **errmsg)
1398 if (value == 0
1399 || (unsigned long) value == ((insn >> 21) & 0x1f))
1400 *errmsg = "invalid register operand when updating";
1401 return insn | ((value & 0x1f) << 16);
1404 /* The RA field in an lmw instruction, which has special value
1405 restrictions. */
1407 static unsigned long
1408 insert_ram (unsigned long insn,
1409 long value,
1410 int dialect ATTRIBUTE_UNUSED,
1411 const char **errmsg)
1413 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1414 *errmsg = _("index register in load range");
1415 return insn | ((value & 0x1f) << 16);
1418 /* The RA field in the DQ form lq instruction, which has special
1419 value restrictions. */
1421 static unsigned long
1422 insert_raq (unsigned long insn,
1423 long value,
1424 int dialect ATTRIBUTE_UNUSED,
1425 const char **errmsg)
1427 long rtvalue = (insn & RT_MASK) >> 21;
1429 if (value == rtvalue)
1430 *errmsg = _("source and target register operands must be different");
1431 return insn | ((value & 0x1f) << 16);
1434 /* The RA field in a D or X form instruction which is an updating
1435 store or an updating floating point load, which means that the RA
1436 field may not be zero. */
1438 static unsigned long
1439 insert_ras (unsigned long insn,
1440 long value,
1441 int dialect ATTRIBUTE_UNUSED,
1442 const char **errmsg)
1444 if (value == 0)
1445 *errmsg = _("invalid register operand when updating");
1446 return insn | ((value & 0x1f) << 16);
1449 /* The RB field in an X form instruction when it must be the same as
1450 the RS field in the instruction. This is used for extended
1451 mnemonics like mr. This operand is marked FAKE. The insertion
1452 function just copies the BT field into the BA field, and the
1453 extraction function just checks that the fields are the same. */
1455 static unsigned long
1456 insert_rbs (unsigned long insn,
1457 long value ATTRIBUTE_UNUSED,
1458 int dialect ATTRIBUTE_UNUSED,
1459 const char **errmsg ATTRIBUTE_UNUSED)
1461 return insn | (((insn >> 21) & 0x1f) << 11);
1464 static long
1465 extract_rbs (unsigned long insn,
1466 int dialect ATTRIBUTE_UNUSED,
1467 int *invalid)
1469 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1470 *invalid = 1;
1471 return 0;
1474 /* The SH field in an MD form instruction. This is split. */
1476 static unsigned long
1477 insert_sh6 (unsigned long insn,
1478 long value,
1479 int dialect ATTRIBUTE_UNUSED,
1480 const char **errmsg ATTRIBUTE_UNUSED)
1482 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1485 static long
1486 extract_sh6 (unsigned long insn,
1487 int dialect ATTRIBUTE_UNUSED,
1488 int *invalid ATTRIBUTE_UNUSED)
1490 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1493 /* The SPR field in an XFX form instruction. This is flipped--the
1494 lower 5 bits are stored in the upper 5 and vice- versa. */
1496 static unsigned long
1497 insert_spr (unsigned long insn,
1498 long value,
1499 int dialect ATTRIBUTE_UNUSED,
1500 const char **errmsg ATTRIBUTE_UNUSED)
1502 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1505 static long
1506 extract_spr (unsigned long insn,
1507 int dialect ATTRIBUTE_UNUSED,
1508 int *invalid ATTRIBUTE_UNUSED)
1510 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1513 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1515 static unsigned long
1516 insert_sprg (unsigned long insn,
1517 long value,
1518 int dialect,
1519 const char **errmsg)
1521 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1522 as a synonym. If ever a 405 specific dialect is added this
1523 check should use that instead. */
1524 if (value > 7
1525 || (value > 3
1526 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1527 *errmsg = _("invalid sprg number");
1529 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1530 user mode. Anything else must use spr 272..279. */
1531 if (value <= 3 || (insn & 0x100) != 0)
1532 value |= 0x10;
1534 return insn | ((value & 0x17) << 16);
1537 static long
1538 extract_sprg (unsigned long insn,
1539 int dialect,
1540 int *invalid)
1542 unsigned long val = (insn >> 16) & 0x1f;
1544 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1545 If not BOOKE or 405, then both use only 272..275. */
1546 if (val <= 3
1547 || (val < 0x10 && (insn & 0x100) != 0)
1548 || (val - 0x10 > 3
1549 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1550 *invalid = 1;
1551 return val & 7;
1554 /* The TBR field in an XFX instruction. This is just like SPR, but it
1555 is optional. When TBR is omitted, it must be inserted as 268 (the
1556 magic number of the TB register). These functions treat 0
1557 (indicating an omitted optional operand) as 268. This means that
1558 ``mftb 4,0'' is not handled correctly. This does not matter very
1559 much, since the architecture manual does not define mftb as
1560 accepting any values other than 268 or 269. */
1562 #define TB (268)
1564 static unsigned long
1565 insert_tbr (unsigned long insn,
1566 long value,
1567 int dialect ATTRIBUTE_UNUSED,
1568 const char **errmsg ATTRIBUTE_UNUSED)
1570 if (value == 0)
1571 value = TB;
1572 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1575 static long
1576 extract_tbr (unsigned long insn,
1577 int dialect ATTRIBUTE_UNUSED,
1578 int *invalid ATTRIBUTE_UNUSED)
1580 long ret;
1582 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1583 if (ret == TB)
1584 ret = 0;
1585 return ret;
1588 /* Macros used to form opcodes. */
1590 /* The main opcode. */
1591 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1592 #define OP_MASK OP (0x3f)
1594 /* The main opcode combined with a trap code in the TO field of a D
1595 form instruction. Used for extended mnemonics for the trap
1596 instructions. */
1597 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1598 #define OPTO_MASK (OP_MASK | TO_MASK)
1600 /* The main opcode combined with a comparison size bit in the L field
1601 of a D form or X form instruction. Used for extended mnemonics for
1602 the comparison instructions. */
1603 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1604 #define OPL_MASK OPL (0x3f,1)
1606 /* An A form instruction. */
1607 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1608 #define A_MASK A (0x3f, 0x1f, 1)
1610 /* An A_MASK with the FRB field fixed. */
1611 #define AFRB_MASK (A_MASK | FRB_MASK)
1613 /* An A_MASK with the FRC field fixed. */
1614 #define AFRC_MASK (A_MASK | FRC_MASK)
1616 /* An A_MASK with the FRA and FRC fields fixed. */
1617 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1619 /* An AFRAFRC_MASK, but with L bit clear. */
1620 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1622 /* A B form instruction. */
1623 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1624 #define B_MASK B (0x3f, 1, 1)
1626 /* A B form instruction setting the BO field. */
1627 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1628 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1630 /* A BBO_MASK with the y bit of the BO field removed. This permits
1631 matching a conditional branch regardless of the setting of the y
1632 bit. Similarly for the 'at' bits used for power4 branch hints. */
1633 #define Y_MASK (((unsigned long) 1) << 21)
1634 #define AT1_MASK (((unsigned long) 3) << 21)
1635 #define AT2_MASK (((unsigned long) 9) << 21)
1636 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1637 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1639 /* A B form instruction setting the BO field and the condition bits of
1640 the BI field. */
1641 #define BBOCB(op, bo, cb, aa, lk) \
1642 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1643 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1645 /* A BBOCB_MASK with the y bit of the BO field removed. */
1646 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1647 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1648 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1650 /* A BBOYCB_MASK in which the BI field is fixed. */
1651 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1652 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1654 /* An Context form instruction. */
1655 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1656 #define CTX_MASK CTX(0x3f, 0x7)
1658 /* An User Context form instruction. */
1659 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1660 #define UCTX_MASK UCTX(0x3f, 0x1f)
1662 /* The main opcode mask with the RA field clear. */
1663 #define DRA_MASK (OP_MASK | RA_MASK)
1665 /* A DS form instruction. */
1666 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1667 #define DS_MASK DSO (0x3f, 3)
1669 /* A DE form instruction. */
1670 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1671 #define DE_MASK DEO (0x3e, 0xf)
1673 /* An EVSEL form instruction. */
1674 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1675 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1677 /* An M form instruction. */
1678 #define M(op, rc) (OP (op) | ((rc) & 1))
1679 #define M_MASK M (0x3f, 1)
1681 /* An M form instruction with the ME field specified. */
1682 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1684 /* An M_MASK with the MB and ME fields fixed. */
1685 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1687 /* An M_MASK with the SH and ME fields fixed. */
1688 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1690 /* An MD form instruction. */
1691 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1692 #define MD_MASK MD (0x3f, 0x7, 1)
1694 /* An MD_MASK with the MB field fixed. */
1695 #define MDMB_MASK (MD_MASK | MB6_MASK)
1697 /* An MD_MASK with the SH field fixed. */
1698 #define MDSH_MASK (MD_MASK | SH6_MASK)
1700 /* An MDS form instruction. */
1701 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1702 #define MDS_MASK MDS (0x3f, 0xf, 1)
1704 /* An MDS_MASK with the MB field fixed. */
1705 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1707 /* An SC form instruction. */
1708 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1709 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1711 /* An VX form instruction. */
1712 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1714 /* The mask for an VX form instruction. */
1715 #define VX_MASK VX(0x3f, 0x7ff)
1717 /* An VA form instruction. */
1718 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1720 /* The mask for an VA form instruction. */
1721 #define VXA_MASK VXA(0x3f, 0x3f)
1723 /* An VXR form instruction. */
1724 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1726 /* The mask for a VXR form instruction. */
1727 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1729 /* An X form instruction. */
1730 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1732 /* A Z form instruction. */
1733 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1735 /* An X form instruction with the RC bit specified. */
1736 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1738 /* A Z form instruction with the RC bit specified. */
1739 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1741 /* The mask for an X form instruction. */
1742 #define X_MASK XRC (0x3f, 0x3ff, 1)
1744 /* The mask for a Z form instruction. */
1745 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1746 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1748 /* An X_MASK with the RA field fixed. */
1749 #define XRA_MASK (X_MASK | RA_MASK)
1751 /* An XRA_MASK with the W field clear. */
1752 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1754 /* An X_MASK with the RB field fixed. */
1755 #define XRB_MASK (X_MASK | RB_MASK)
1757 /* An X_MASK with the RT field fixed. */
1758 #define XRT_MASK (X_MASK | RT_MASK)
1760 /* An XRT_MASK mask with the L bits clear. */
1761 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1763 /* An X_MASK with the RA and RB fields fixed. */
1764 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1766 /* An XRARB_MASK, but with the L bit clear. */
1767 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1769 /* An X_MASK with the RT and RA fields fixed. */
1770 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1772 /* An XRTRA_MASK, but with L bit clear. */
1773 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1775 /* An X form instruction with the L bit specified. */
1776 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1778 /* The mask for an X form comparison instruction. */
1779 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1781 /* The mask for an X form comparison instruction with the L field
1782 fixed. */
1783 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1785 /* An X form trap instruction with the TO field specified. */
1786 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1787 #define XTO_MASK (X_MASK | TO_MASK)
1789 /* An X form tlb instruction with the SH field specified. */
1790 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1791 #define XTLB_MASK (X_MASK | SH_MASK)
1793 /* An X form sync instruction. */
1794 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1796 /* An X form sync instruction with everything filled in except the LS field. */
1797 #define XSYNC_MASK (0xff9fffff)
1799 /* An X_MASK, but with the EH bit clear. */
1800 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1802 /* An X form AltiVec dss instruction. */
1803 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1804 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1806 /* An XFL form instruction. */
1807 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1808 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1810 /* An X form isel instruction. */
1811 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1812 #define XISEL_MASK XISEL(0x3f, 0x1f)
1814 /* An XL form instruction with the LK field set to 0. */
1815 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1817 /* An XL form instruction which uses the LK field. */
1818 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1820 /* The mask for an XL form instruction. */
1821 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1823 /* An XL form instruction which explicitly sets the BO field. */
1824 #define XLO(op, bo, xop, lk) \
1825 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1826 #define XLO_MASK (XL_MASK | BO_MASK)
1828 /* An XL form instruction which explicitly sets the y bit of the BO
1829 field. */
1830 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1831 #define XLYLK_MASK (XL_MASK | Y_MASK)
1833 /* An XL form instruction which sets the BO field and the condition
1834 bits of the BI field. */
1835 #define XLOCB(op, bo, cb, xop, lk) \
1836 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1837 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1839 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1840 #define XLBB_MASK (XL_MASK | BB_MASK)
1841 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1842 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1844 /* A mask for branch instructions using the BH field. */
1845 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1847 /* An XL_MASK with the BO and BB fields fixed. */
1848 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1850 /* An XL_MASK with the BO, BI and BB fields fixed. */
1851 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1853 /* An XO form instruction. */
1854 #define XO(op, xop, oe, rc) \
1855 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1856 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1858 /* An XO_MASK with the RB field fixed. */
1859 #define XORB_MASK (XO_MASK | RB_MASK)
1861 /* An XS form instruction. */
1862 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1863 #define XS_MASK XS (0x3f, 0x1ff, 1)
1865 /* A mask for the FXM version of an XFX form instruction. */
1866 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1868 /* An XFX form instruction with the FXM field filled in. */
1869 #define XFXM(op, xop, fxm, p4) \
1870 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1871 | ((unsigned long)(p4) << 20))
1873 /* An XFX form instruction with the SPR field filled in. */
1874 #define XSPR(op, xop, spr) \
1875 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1876 #define XSPR_MASK (X_MASK | SPR_MASK)
1878 /* An XFX form instruction with the SPR field filled in except for the
1879 SPRBAT field. */
1880 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1882 /* An XFX form instruction with the SPR field filled in except for the
1883 SPRG field. */
1884 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1886 /* An X form instruction with everything filled in except the E field. */
1887 #define XE_MASK (0xffff7fff)
1889 /* An X form user context instruction. */
1890 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1891 #define XUC_MASK XUC(0x3f, 0x1f)
1893 /* The BO encodings used in extended conditional branch mnemonics. */
1894 #define BODNZF (0x0)
1895 #define BODNZFP (0x1)
1896 #define BODZF (0x2)
1897 #define BODZFP (0x3)
1898 #define BODNZT (0x8)
1899 #define BODNZTP (0x9)
1900 #define BODZT (0xa)
1901 #define BODZTP (0xb)
1903 #define BOF (0x4)
1904 #define BOFP (0x5)
1905 #define BOFM4 (0x6)
1906 #define BOFP4 (0x7)
1907 #define BOT (0xc)
1908 #define BOTP (0xd)
1909 #define BOTM4 (0xe)
1910 #define BOTP4 (0xf)
1912 #define BODNZ (0x10)
1913 #define BODNZP (0x11)
1914 #define BODZ (0x12)
1915 #define BODZP (0x13)
1916 #define BODNZM4 (0x18)
1917 #define BODNZP4 (0x19)
1918 #define BODZM4 (0x1a)
1919 #define BODZP4 (0x1b)
1921 #define BOU (0x14)
1923 /* The BI condition bit encodings used in extended conditional branch
1924 mnemonics. */
1925 #define CBLT (0)
1926 #define CBGT (1)
1927 #define CBEQ (2)
1928 #define CBSO (3)
1930 /* The TO encodings used in extended trap mnemonics. */
1931 #define TOLGT (0x1)
1932 #define TOLLT (0x2)
1933 #define TOEQ (0x4)
1934 #define TOLGE (0x5)
1935 #define TOLNL (0x5)
1936 #define TOLLE (0x6)
1937 #define TOLNG (0x6)
1938 #define TOGT (0x8)
1939 #define TOGE (0xc)
1940 #define TONL (0xc)
1941 #define TOLT (0x10)
1942 #define TOLE (0x14)
1943 #define TONG (0x14)
1944 #define TONE (0x18)
1945 #define TOU (0x1f)
1947 /* Smaller names for the flags so each entry in the opcodes table will
1948 fit on a single line. */
1949 #undef PPC
1950 #define PPC PPC_OPCODE_PPC
1951 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1952 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1953 #define POWER4 PPC_OPCODE_POWER4
1954 #define POWER5 PPC_OPCODE_POWER5
1955 #define POWER6 PPC_OPCODE_POWER6
1956 #define CELL PPC_OPCODE_CELL
1957 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1958 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1959 #define PPC403 PPC_OPCODE_403
1960 #define PPC405 PPC403
1961 #define PPC440 PPC_OPCODE_440
1962 #define PPC750 PPC
1963 #define PPC860 PPC
1964 #define PPCVEC PPC_OPCODE_ALTIVEC
1965 #define POWER PPC_OPCODE_POWER
1966 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1967 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1968 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1969 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1970 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1971 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1972 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1973 #define MFDEC1 PPC_OPCODE_POWER
1974 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1975 #define BOOKE PPC_OPCODE_BOOKE
1976 #define BOOKE64 PPC_OPCODE_BOOKE64
1977 #define CLASSIC PPC_OPCODE_CLASSIC
1978 #define PPCE300 PPC_OPCODE_E300
1979 #define PPCSPE PPC_OPCODE_SPE
1980 #define PPCISEL PPC_OPCODE_ISEL
1981 #define PPCEFS PPC_OPCODE_EFS
1982 #define PPCBRLK PPC_OPCODE_BRLOCK
1983 #define PPCPMR PPC_OPCODE_PMR
1984 #define PPCCHLK PPC_OPCODE_CACHELCK
1985 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1986 #define PPCRFMCI PPC_OPCODE_RFMCI
1988 /* The opcode table.
1990 The format of the opcode table is:
1992 NAME OPCODE MASK FLAGS { OPERANDS }
1994 NAME is the name of the instruction.
1995 OPCODE is the instruction opcode.
1996 MASK is the opcode mask; this is used to tell the disassembler
1997 which bits in the actual opcode must match OPCODE.
1998 FLAGS are flags indicated what processors support the instruction.
1999 OPERANDS is the list of operands.
2001 The disassembler reads the table in order and prints the first
2002 instruction which matches, so this table is sorted to put more
2003 specific instructions before more general instructions. It is also
2004 sorted by major opcode. */
2006 const struct powerpc_opcode powerpc_opcodes[] = {
2007 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
2008 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
2009 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
2010 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
2011 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
2012 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
2013 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2014 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
2015 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
2016 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
2017 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
2018 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
2019 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
2020 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
2021 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
2022 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
2024 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
2025 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
2026 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
2027 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
2028 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
2029 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
2030 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
2031 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
2032 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
2033 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
2034 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2035 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
2036 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
2037 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
2038 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
2039 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
2040 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
2041 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
2042 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
2044 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
2045 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
2046 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
2047 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
2048 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
2049 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
2050 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
2051 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
2052 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
2053 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2055 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2056 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2057 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2071 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2072 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2073 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2074 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2075 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2076 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2077 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2078 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2079 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2080 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2081 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2082 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2083 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2084 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2085 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2086 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2087 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2088 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2089 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2090 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2091 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2092 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2093 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2094 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2095 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2096 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2097 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2098 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2099 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2100 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2101 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2102 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2103 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2104 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2105 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2106 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2107 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2108 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2109 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2110 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2111 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2112 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2113 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2114 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2115 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2116 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2117 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2118 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2119 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2120 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2121 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2122 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2123 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2124 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2125 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2126 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2127 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2128 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2129 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2130 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2131 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2132 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2133 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2134 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2135 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2136 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2137 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2138 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2139 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2140 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2142 /* Double-precision opcodes. */
2143 /* Some of these conflict with AltiVec, so move them before, since
2144 PPCVEC includes the PPC_OPCODE_PPC set. */
2145 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2146 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2147 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2148 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2149 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2150 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2151 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2152 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2153 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2154 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2155 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2156 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2157 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2158 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2159 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2160 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2161 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2162 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2163 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2164 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2165 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2166 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2167 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2168 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2169 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2170 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2171 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2172 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2173 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2174 /* End of double-precision opcodes. */
2176 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2177 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2178 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2179 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2180 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2181 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2182 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2183 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2184 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2185 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2186 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2187 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2188 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2189 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2190 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2191 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2192 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2193 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2194 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2195 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2196 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2197 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2198 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2199 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2200 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2201 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2202 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2203 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2204 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2205 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2206 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2207 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2208 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2209 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2210 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2211 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2212 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2213 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2214 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2215 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2216 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2217 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2218 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2219 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2220 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2221 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2222 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2223 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2224 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2225 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2226 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2227 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2228 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2229 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2230 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2231 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2232 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2233 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2234 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2235 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2236 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2237 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2238 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2239 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2240 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2241 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2242 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2243 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2244 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2245 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2246 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2247 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2248 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2249 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2250 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2251 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2252 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2253 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2254 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2255 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2256 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2257 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2258 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2259 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2260 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2261 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2262 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2263 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2264 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2265 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2266 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2267 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2268 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2269 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2270 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2271 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2272 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2273 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2274 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2275 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2276 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2277 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2278 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2279 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2280 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2281 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2282 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2283 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2284 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2285 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2286 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2287 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2288 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2289 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2290 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2291 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2292 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2293 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2294 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2295 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2296 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2297 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2298 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2299 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2300 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2301 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2302 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2303 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2304 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2305 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2306 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2307 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2308 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2309 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2310 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2311 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2312 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2313 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2314 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2315 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2316 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2317 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2318 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2319 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2320 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2321 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2322 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2323 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2324 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2325 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2326 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2327 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2328 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2329 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2330 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2332 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2333 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2334 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2335 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2336 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2337 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2338 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2339 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2340 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2341 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2342 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2343 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2344 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2346 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2349 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2350 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2351 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2352 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2353 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2357 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2359 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2361 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2362 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2363 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2364 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2365 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2366 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2367 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2368 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2369 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2370 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2371 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2372 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2374 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2375 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2376 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2377 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2378 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2379 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2381 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2382 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2383 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2384 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2385 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2386 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2387 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2388 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2389 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2390 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2391 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2392 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2393 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2394 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2395 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2396 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2397 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2398 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2400 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2402 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2404 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2405 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2406 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2407 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2408 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2409 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2410 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2411 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2412 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2413 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2415 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2417 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2419 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2420 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2421 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2422 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2423 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2424 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2425 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2426 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2427 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2428 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2429 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2430 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2431 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2432 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2433 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2434 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2435 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2436 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2437 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2438 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2439 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2440 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2441 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2443 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2444 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2445 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2446 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2447 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2448 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2449 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2450 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2451 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2452 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2453 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2454 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2455 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2456 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2457 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2458 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2459 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2460 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2461 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2462 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2463 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2464 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2465 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2467 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2468 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2469 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2470 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2471 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2472 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2473 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2474 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2475 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2477 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2486 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2491 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2494 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2495 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2497 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2498 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2499 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2500 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2501 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2502 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2503 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2504 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2505 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2506 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2507 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2508 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2510 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2511 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2512 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2513 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2514 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2515 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2517 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2518 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2519 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2520 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2521 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2522 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2524 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2525 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2526 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2527 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2528 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2529 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2530 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2531 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2533 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2534 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2536 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2537 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2538 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2539 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2541 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2542 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2543 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2544 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2546 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2547 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2548 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2549 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2550 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2551 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2552 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2553 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2555 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2556 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2557 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2558 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2560 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2561 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2562 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2563 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2565 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2566 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2567 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2568 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2570 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2571 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2572 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2573 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2575 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2577 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2578 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2580 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2581 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2583 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2584 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2586 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2588 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2589 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2590 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2591 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2593 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2594 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2595 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2596 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2598 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2599 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2600 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2601 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2603 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2604 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2605 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2607 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2608 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2609 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2611 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2612 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2613 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2614 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2615 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2616 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2618 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2619 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2620 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2621 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2622 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2624 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2625 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2626 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2627 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2628 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2629 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2630 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2631 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2632 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2633 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2634 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2635 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2636 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2637 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2638 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2639 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2640 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2641 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2642 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2643 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2644 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2645 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2646 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2647 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2648 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2649 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2650 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2651 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2652 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2653 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2654 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2655 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2656 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2657 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2658 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2659 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2660 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2661 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2662 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2663 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2664 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2665 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2666 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2667 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2668 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2669 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2670 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2671 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2672 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2673 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2674 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2675 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2676 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2677 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2678 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2679 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2680 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2681 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2682 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2683 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2684 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2685 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2686 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2687 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2688 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2689 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2690 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2691 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2692 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2693 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2694 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2695 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2696 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2697 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2698 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2699 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2700 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2701 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2702 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2703 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2704 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2705 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2706 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2707 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2708 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2709 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2710 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2711 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2712 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2713 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2714 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2715 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2716 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2717 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2718 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2719 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2720 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2721 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2722 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2723 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2724 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2725 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2726 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2727 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2728 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2729 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2730 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2731 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2732 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2733 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2734 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2735 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2736 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2737 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2738 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2739 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2740 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2741 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2742 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2743 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2744 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2745 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2746 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2747 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2748 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2749 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2750 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2751 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2752 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2753 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2754 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2755 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2756 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2757 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2758 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2759 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2760 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2761 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2762 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2763 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2764 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2765 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2766 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2767 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2768 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2769 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2770 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2771 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2772 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2773 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2774 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2775 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2776 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2777 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2778 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2779 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2780 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2781 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2782 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2783 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2784 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2785 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2786 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2787 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2788 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2789 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2790 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2791 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2792 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2793 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2794 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2795 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2796 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2797 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2798 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2799 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2800 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2801 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2802 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2803 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2804 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2805 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2806 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2807 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2808 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2809 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2810 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2811 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2812 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2813 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2814 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2815 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2816 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2817 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2818 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2819 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2820 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2821 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2822 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2823 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2824 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2825 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2826 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2827 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2828 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2829 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2830 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2831 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2832 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2833 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2834 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2835 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2836 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2837 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2838 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2839 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2840 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2841 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2842 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2843 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2844 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2845 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2846 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2847 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2848 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2849 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2850 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2851 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2852 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2853 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2854 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2855 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2856 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2857 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2858 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2859 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2860 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2861 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2862 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2863 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2864 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2865 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2866 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2867 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2868 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2869 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2870 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2871 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2872 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2873 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2874 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2875 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2876 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2877 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2878 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2879 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2880 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2881 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2882 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2883 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2884 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2885 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2886 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2887 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2889 { "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2890 { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2891 { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2892 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2893 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2895 { "b", B(18,0,0), B_MASK, COM, { LI } },
2896 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2897 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2898 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2900 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2902 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2903 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2904 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2905 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2906 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2907 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2908 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2909 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2910 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2911 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2912 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2913 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2914 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2915 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2916 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2917 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2918 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2919 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2920 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2921 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2922 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2923 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2924 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2925 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2926 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2927 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2928 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2929 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2930 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2931 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2932 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2933 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2934 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2935 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2936 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2937 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2938 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2939 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2941 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2942 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2943 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2944 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2945 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2946 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2947 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2948 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2949 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2950 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2951 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2952 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2953 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2955 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2956 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2957 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2958 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2959 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2961 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2962 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2963 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2965 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2966 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2967 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2968 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2969 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2971 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2972 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2973 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2974 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2975 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2976 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2977 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2978 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2979 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2980 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2981 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2982 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2985 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2986 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2987 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2990 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2991 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2992 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2993 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2995 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2996 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2997 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3001 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3002 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3003 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3004 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3005 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3006 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3007 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3008 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3009 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3011 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3013 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3014 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3015 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3016 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3017 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3020 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3021 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3022 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3023 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3024 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3025 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3026 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3027 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3032 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3033 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3034 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3035 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3036 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3037 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3038 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3039 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3043 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3044 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3045 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3046 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3047 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3049 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3050 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3051 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3052 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3053 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3054 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3055 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3056 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3057 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3058 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3059 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3060 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3061 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3062 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3063 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3064 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3065 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3066 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3067 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3068 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3069 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3070 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3071 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3072 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3073 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3074 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3075 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3076 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3077 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3078 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3079 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3080 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3081 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3082 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3083 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3084 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3085 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3086 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3087 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3088 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3089 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3090 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3091 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3092 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3093 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3094 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3095 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3096 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3097 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3098 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3099 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3100 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3101 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3102 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3103 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3104 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3105 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3106 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3107 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3108 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3109 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3110 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3111 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3112 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3113 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3114 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3115 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3116 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3117 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3118 { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3119 { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3120 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
3121 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
3122 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
3123 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
3125 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
3127 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
3128 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
3129 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
3131 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
3132 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
3134 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3136 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
3138 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3139 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3141 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3142 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3144 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3146 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3148 { "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
3150 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3151 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3153 { "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
3155 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3157 { "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
3159 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3160 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3162 { "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
3163 { "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
3165 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3166 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3167 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3168 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3169 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3170 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3171 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3172 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3173 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3174 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3175 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3176 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3177 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3178 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3179 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3180 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3181 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3182 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3183 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3184 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3185 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3186 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3187 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3188 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3189 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3190 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3191 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3192 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3193 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3194 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3195 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3196 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3197 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3198 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3199 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3200 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3201 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3202 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3203 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3204 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3205 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3206 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3207 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3208 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3209 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3210 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3211 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3212 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3213 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3214 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3215 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3216 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3217 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3218 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3219 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3220 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3221 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3222 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3223 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3224 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3225 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3226 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3227 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3228 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3229 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3230 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3231 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3232 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3233 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3234 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3235 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3236 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3237 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3238 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3239 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3240 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3241 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3242 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3243 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3244 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3245 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3246 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3247 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3248 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3249 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3250 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3251 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3252 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3253 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3254 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3255 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3256 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3257 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3258 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3259 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3260 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3261 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3262 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3263 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3264 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3265 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3266 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3267 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3268 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3269 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3270 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3271 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3272 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3273 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3274 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3275 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3276 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3277 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3278 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3279 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3280 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3281 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3282 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3283 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3284 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3285 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3286 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3287 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3288 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3289 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3290 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3291 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3292 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3293 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3294 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3295 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3296 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3297 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3298 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3299 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3300 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3301 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3302 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3303 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3304 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3305 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3306 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3307 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3308 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3309 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3310 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3311 { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3312 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3313 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3314 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3315 { "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
3316 { "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
3318 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3319 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3321 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3322 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3324 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3325 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3326 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3327 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3328 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3329 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3330 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3331 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3333 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3334 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3336 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3337 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3338 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3339 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3341 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3342 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3343 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3344 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3345 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3346 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3348 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3349 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3350 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3352 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3353 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3355 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3356 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3358 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3359 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3361 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3362 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3364 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3365 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3367 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3368 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3369 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3370 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3371 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3372 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3374 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3375 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3377 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3378 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3380 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3381 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3383 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3384 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3385 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3386 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3388 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3389 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3391 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3392 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3393 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3394 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3396 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3397 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3398 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3399 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3400 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3401 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3402 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3403 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3404 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3405 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3406 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3407 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3408 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3409 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3410 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3411 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3412 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3413 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3414 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3415 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3416 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3417 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3418 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3420 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3421 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3422 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3423 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3424 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3425 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3426 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3428 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3429 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3430 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3431 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3432 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3433 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3434 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3435 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3436 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3437 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3438 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3439 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3441 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3442 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3444 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3445 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3446 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3447 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3448 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3449 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3450 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3451 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3453 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3454 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3456 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3457 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3458 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3459 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3461 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3462 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3463 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3465 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3467 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3469 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3470 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3472 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3473 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3475 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3476 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3477 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3478 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3480 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3481 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3482 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3483 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3485 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3486 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3488 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3489 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3491 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3492 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3494 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3496 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3498 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3499 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3500 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3501 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3503 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3504 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3505 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3506 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3507 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3508 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3509 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3510 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3512 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3514 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3516 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3517 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3519 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3521 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3523 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3524 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3526 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3527 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3529 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3530 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3531 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3532 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3533 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3534 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3535 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3536 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3537 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3538 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3539 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3540 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3541 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3542 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3543 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3545 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3546 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3548 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3549 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3551 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3552 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3554 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3556 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3558 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3560 { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3561 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
3563 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3565 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3567 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3569 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3570 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3571 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3572 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3574 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3575 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3576 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3577 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3579 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3581 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3583 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3585 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3587 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3588 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3589 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3590 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3592 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3594 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3596 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3598 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3600 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3601 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3602 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3603 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3604 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3605 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3606 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3607 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3609 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3610 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3611 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3612 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3613 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3614 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3615 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3616 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3618 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3620 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3621 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3622 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3624 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3626 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3628 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3630 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3631 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3633 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3635 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3637 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3638 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3640 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3641 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3643 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3645 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3647 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3648 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3650 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
3652 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3654 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3655 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3657 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3658 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3660 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3662 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3664 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3665 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3666 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3667 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3668 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3669 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3670 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3671 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3673 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3674 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3675 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3676 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3677 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3678 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3679 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3680 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3682 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3684 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3686 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3688 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3689 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3691 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3692 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3694 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3696 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3698 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3699 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3700 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3701 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3702 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3703 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3704 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3705 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3707 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3708 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3709 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3710 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3712 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3713 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3714 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3715 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3716 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3717 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3718 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3719 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3721 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3722 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3723 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3724 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3725 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3726 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3727 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3728 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3730 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3731 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3732 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3734 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3736 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3738 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3739 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3741 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3743 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3745 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3747 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3748 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3749 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3750 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3752 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3753 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3754 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3755 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3756 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3757 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3758 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3759 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3761 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3763 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3765 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3766 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3768 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3770 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3772 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3773 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3775 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3777 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3779 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3780 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3782 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3784 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3786 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3787 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3789 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3791 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3792 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3793 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3794 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3795 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3796 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3797 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3798 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3799 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3800 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3801 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3802 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3803 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3804 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3805 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3806 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3807 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3808 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3809 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3810 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3811 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3812 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3813 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3814 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3815 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3816 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3817 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3818 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3819 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3820 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3821 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3822 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3823 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3824 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3825 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3827 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3828 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3829 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3830 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3832 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3834 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3835 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3836 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3837 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3838 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3839 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3840 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3841 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3842 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3843 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3844 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3845 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3846 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3847 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3848 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3849 { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3850 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3851 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3852 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3853 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3854 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3855 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3856 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3857 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3858 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3859 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3860 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3861 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3862 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3863 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3864 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3865 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3866 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3867 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3868 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3869 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3870 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3871 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3872 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3873 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3874 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3875 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3876 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3877 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3878 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3879 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3880 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3881 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3882 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3883 { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3884 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3885 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3886 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3887 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3888 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3889 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3890 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3891 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3892 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3893 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3894 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3895 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3896 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3897 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3898 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3899 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3900 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3901 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3902 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3903 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3904 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3905 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3906 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3907 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3908 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3909 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3910 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3911 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3912 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3913 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3914 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3915 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3916 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3917 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3918 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3919 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3920 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3921 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3922 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3923 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3924 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3925 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3926 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3927 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3928 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3929 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3930 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3931 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3932 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3933 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3934 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3935 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3936 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3937 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3938 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3939 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3940 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3941 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3942 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3943 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3944 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3945 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3946 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3947 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3948 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3949 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3950 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3951 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3952 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3953 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3954 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3955 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3956 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3957 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3958 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3959 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3960 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3961 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3962 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3963 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3964 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3965 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3966 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3967 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3968 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3969 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3970 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3971 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3972 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3973 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3974 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3975 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3976 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3977 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3978 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3979 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3980 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3981 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3982 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3983 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3984 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3985 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3986 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3987 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3988 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3989 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3990 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3991 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3992 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3993 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3994 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3995 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3996 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3997 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3998 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3999 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
4000 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
4001 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
4002 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
4003 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
4004 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
4005 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
4006 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
4007 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
4008 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
4009 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
4010 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
4011 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
4012 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
4013 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
4014 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
4015 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
4016 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
4017 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
4018 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
4019 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
4020 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
4021 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
4023 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
4025 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4026 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4028 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
4030 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
4032 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4033 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4035 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
4037 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
4038 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
4039 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
4040 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
4042 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
4043 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
4044 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
4045 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
4047 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
4049 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
4051 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
4053 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
4055 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
4057 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
4059 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4060 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4062 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4063 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4065 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
4067 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
4069 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4071 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4073 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4075 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4077 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4079 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4081 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4083 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4085 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4086 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4088 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4089 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
4091 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4093 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4095 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4097 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4099 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4101 { "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
4102 { "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
4103 { "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
4104 { "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
4105 { "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
4106 { "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
4107 { "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
4108 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4109 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4110 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4111 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4113 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4114 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4115 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4116 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4117 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4118 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4119 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4120 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4121 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4122 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4123 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4124 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4125 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4126 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4127 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4128 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4129 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4130 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4131 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4132 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4133 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4134 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4135 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4136 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4137 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4138 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4139 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4140 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4141 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4142 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4143 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4144 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4145 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4146 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4147 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4149 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4150 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4152 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4153 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4154 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4155 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4157 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4158 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4160 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4161 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4162 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4163 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4165 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4166 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4167 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4168 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4169 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4170 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4171 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4172 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4173 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4174 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4175 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4176 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4177 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4178 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4179 { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
4180 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4181 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4182 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4183 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4184 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4185 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4186 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4187 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4188 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4189 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4190 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4191 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4192 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4193 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4194 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4195 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4196 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4197 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4198 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4199 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4200 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4201 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4202 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4203 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4204 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4205 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4206 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4207 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4208 { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4209 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4210 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4211 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4212 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4213 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4214 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4215 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4216 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4217 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4218 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4219 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4220 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4221 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4222 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4223 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4224 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4225 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4226 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4227 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4228 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4229 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4230 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4231 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4232 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4233 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4234 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4235 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4236 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4237 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4238 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4239 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4240 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4241 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4242 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4243 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4244 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4245 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4246 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4247 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4248 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4249 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4250 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4251 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4252 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4253 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4254 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4255 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4256 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4257 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4258 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4259 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4260 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4261 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4262 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4263 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4264 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4265 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4266 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4267 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4268 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4269 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4270 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4271 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4272 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4273 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4274 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4275 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4276 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4277 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4278 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4279 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4280 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4281 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4282 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4283 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4284 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4285 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4286 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4287 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4288 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4289 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4290 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4291 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4292 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4293 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4294 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4295 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4296 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4297 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4298 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4299 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4300 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4301 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4302 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4303 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4304 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4305 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4306 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4307 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4308 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4309 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4310 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4311 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4312 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4313 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4314 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4315 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4316 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4317 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4319 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4321 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4322 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4324 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4326 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4328 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4330 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4332 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4333 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4334 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4335 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4336 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4337 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4339 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4340 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4341 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4342 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4344 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4345 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4347 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4348 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4349 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4350 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4352 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4354 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4356 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4358 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4360 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4362 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4363 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4365 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4367 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4369 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4370 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4372 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4373 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4375 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4377 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4378 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4379 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4380 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4382 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4383 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4385 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4386 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4388 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4389 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4391 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4393 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4395 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4397 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4399 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4401 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4403 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4405 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4406 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4408 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4409 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4410 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4411 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4412 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4414 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4416 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4418 { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4420 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4422 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4424 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4426 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4428 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4430 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4432 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4433 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4435 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4436 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4438 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4440 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4441 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4443 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4444 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4446 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4448 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4450 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4452 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4453 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4455 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4457 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4458 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4460 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4462 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4463 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4465 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4466 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4468 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4470 { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4472 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4474 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4476 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4477 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4479 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4481 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4483 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4484 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4486 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4488 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4490 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4491 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4492 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4493 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4495 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4496 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4498 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4500 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4501 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4503 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4505 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4507 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4508 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4510 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4511 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4512 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4513 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4515 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4517 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4519 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4520 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4522 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4524 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4526 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4527 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4528 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
4529 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
4531 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4533 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4535 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4537 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4538 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4540 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4541 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4543 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4544 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4545 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4546 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4548 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4550 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4552 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4553 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4554 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4556 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4558 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4559 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4561 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4562 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4564 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4566 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4568 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4569 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4570 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4571 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4573 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4575 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4577 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4579 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4580 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4582 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4584 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4585 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4587 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4589 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4591 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4592 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4593 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4595 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4597 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4598 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4599 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4600 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4601 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4602 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4603 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4604 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4605 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4606 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4607 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4608 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4610 /* New load/store left/right index vector instructions that are in the Cell only. */
4611 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4612 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4613 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4614 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4615 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4616 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4617 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4618 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4620 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4621 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4623 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4624 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4626 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4628 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4630 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4631 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4633 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4634 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4636 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4638 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4640 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4642 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4644 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4646 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4648 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4650 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4652 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4653 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4655 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4656 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4658 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4660 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4662 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4664 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4666 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4668 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4670 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4672 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4674 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4676 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4678 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4680 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4682 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4683 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4684 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4685 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4686 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4687 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4688 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4689 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4690 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4691 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4692 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4693 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4694 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4695 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4697 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4699 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4701 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4703 { "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4704 { "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4706 { "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4707 { "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4709 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4710 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4712 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4713 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4715 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4716 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4718 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4719 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4721 { "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4722 { "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4724 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4725 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4727 { "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4728 { "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4730 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4731 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4733 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4734 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4736 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4737 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4739 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4740 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4742 { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4743 { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4745 { "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4746 { "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4748 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4749 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4751 { "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4752 { "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4754 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4755 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4757 { "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4758 { "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4760 { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4762 { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4763 { "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4764 { "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4766 { "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4767 { "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4769 { "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4770 { "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4772 { "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4773 { "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4775 { "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4776 { "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4778 { "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4779 { "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4781 { "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4782 { "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4784 { "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4785 { "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4787 { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4789 { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4791 { "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4792 { "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4794 { "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4795 { "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4797 { "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4798 { "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4800 { "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4801 { "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4803 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4805 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4807 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4809 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4810 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4811 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4812 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4813 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4814 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4815 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4816 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4817 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4818 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4819 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4820 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4822 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4824 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4826 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4828 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4830 { "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4831 { "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4833 { "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4834 { "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4836 { "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4837 { "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4839 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4840 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4842 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4843 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4844 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4845 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4847 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4848 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4849 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4850 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4852 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4853 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4854 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4855 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4857 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4858 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4859 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4860 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4862 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4863 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4864 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4865 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4867 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4868 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4870 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4871 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4873 { "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4874 { "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4876 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4877 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4878 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4879 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4881 { "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4882 { "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4884 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4885 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4886 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4887 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4889 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4890 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4891 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4892 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4894 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4895 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4896 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4897 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4899 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4900 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4901 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4902 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4904 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4906 { "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4907 { "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4909 { "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4910 { "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4912 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4913 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4915 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4916 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4918 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4920 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4921 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4923 { "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4924 { "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4926 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4927 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4929 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4930 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4932 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4933 { "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4935 { "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4936 { "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4938 { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4940 { "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4941 { "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4943 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4944 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4946 { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4947 { "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4948 { "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4950 { "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4951 { "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4953 { "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4954 { "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4956 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4957 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4959 { "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4960 { "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4962 { "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4963 { "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4965 { "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4966 { "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4968 { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4969 { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4970 { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4971 { "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4972 { "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4973 { "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4974 { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4975 { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4977 { "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4978 { "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4980 { "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4981 { "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4983 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4984 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4986 { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4988 { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4990 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
4991 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
4993 { "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4994 { "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4996 { "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4997 { "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4999 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
5000 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
5002 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
5003 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
5005 { "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
5006 { "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
5008 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
5009 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
5011 { "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
5012 { "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
5016 const int powerpc_num_opcodes =
5017 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5019 /* The macro table. This is only used by the assembler. */
5021 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5022 when x=0; 32-x when x is between 1 and 31; are negative if x is
5023 negative; and are 32 or more otherwise. This is what you want
5024 when, for instance, you are emulating a right shift by a
5025 rotate-left-and-mask, because the underlying instructions support
5026 shifts of size 0 but not shifts of size 32. By comparison, when
5027 extracting x bits from some word you want to use just 32-x, because
5028 the underlying instructions don't support extracting 0 bits but do
5029 support extracting the whole word (32 bits in this case). */
5031 const struct powerpc_macro powerpc_macros[] = {
5032 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
5033 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
5034 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
5035 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
5036 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
5037 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
5038 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
5039 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
5040 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
5041 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
5042 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
5043 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
5044 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
5045 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
5046 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
5047 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
5049 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
5050 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
5051 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5052 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5053 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
5054 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5055 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
5056 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5057 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5058 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5059 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
5060 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
5061 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
5062 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
5063 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5064 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5065 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5066 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5067 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
5068 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
5069 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
5070 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
5073 const int powerpc_num_macros =
5074 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
5077 /* This file provides several disassembler functions, all of which use
5078 the disassembler interface defined in dis-asm.h. Several functions
5079 are provided because this file handles disassembly for the PowerPC
5080 in both big and little endian mode and also for the POWER (RS/6000)
5081 chip. */
5083 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
5085 /* Determine which set of machines to disassemble for. PPC403/601 or
5086 BookE. For convenience, also disassemble instructions supported
5087 by the AltiVec vector unit. */
5089 static int
5090 powerpc_dialect (struct disassemble_info *info)
5092 int dialect = PPC_OPCODE_PPC;
5094 if (BFD_DEFAULT_TARGET_SIZE == 64)
5095 dialect |= PPC_OPCODE_64;
5097 if (info->disassembler_options
5098 && strstr (info->disassembler_options, "booke") != NULL)
5099 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
5100 else if ((info->mach == bfd_mach_ppc_e500)
5101 || (info->disassembler_options
5102 && strstr (info->disassembler_options, "e500") != NULL))
5103 dialect |= (PPC_OPCODE_BOOKE
5104 | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
5105 | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
5106 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
5107 | PPC_OPCODE_RFMCI);
5108 else if (info->disassembler_options
5109 && strstr (info->disassembler_options, "efs") != NULL)
5110 dialect |= PPC_OPCODE_EFS;
5111 else if (info->disassembler_options
5112 && strstr (info->disassembler_options, "e300") != NULL)
5113 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
5114 else if (info->disassembler_options
5115 && strstr (info->disassembler_options, "440") != NULL)
5116 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
5117 | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
5118 else
5119 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
5120 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
5122 if (info->disassembler_options
5123 && strstr (info->disassembler_options, "power4") != NULL)
5124 dialect |= PPC_OPCODE_POWER4;
5126 if (info->disassembler_options
5127 && strstr (info->disassembler_options, "power5") != NULL)
5128 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
5130 if (info->disassembler_options
5131 && strstr (info->disassembler_options, "cell") != NULL)
5132 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
5134 if (info->disassembler_options
5135 && strstr (info->disassembler_options, "power6") != NULL)
5136 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
5138 if (info->disassembler_options
5139 && strstr (info->disassembler_options, "any") != NULL)
5140 dialect |= PPC_OPCODE_ANY;
5142 if (info->disassembler_options)
5144 if (strstr (info->disassembler_options, "32") != NULL)
5145 dialect &= ~PPC_OPCODE_64;
5146 else if (strstr (info->disassembler_options, "64") != NULL)
5147 dialect |= PPC_OPCODE_64;
5150 info->private_data = (char *) 0 + dialect;
5151 return dialect;
5154 /* Qemu default */
5156 print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info)
5158 int dialect = (char *) info->private_data - (char *) 0;
5159 return print_insn_powerpc (memaddr, info, 1, dialect);
5162 /* Print a big endian PowerPC instruction. */
5165 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5167 int dialect = (char *) info->private_data - (char *) 0;
5168 return print_insn_powerpc (memaddr, info, 1, dialect);
5171 /* Print a little endian PowerPC instruction. */
5174 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5176 int dialect = (char *) info->private_data - (char *) 0;
5177 return print_insn_powerpc (memaddr, info, 0, dialect);
5180 /* Print a POWER (RS/6000) instruction. */
5183 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
5185 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
5188 /* Extract the operand value from the PowerPC or POWER instruction. */
5190 static long
5191 operand_value_powerpc (const struct powerpc_operand *operand,
5192 unsigned long insn, int dialect)
5194 long value;
5195 int invalid;
5196 /* Extract the value from the instruction. */
5197 if (operand->extract)
5198 value = (*operand->extract) (insn, dialect, &invalid);
5199 else
5201 value = (insn >> operand->shift) & operand->bitm;
5202 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
5204 /* BITM is always some number of zeros followed by some
5205 number of ones, followed by some numer of zeros. */
5206 unsigned long top = operand->bitm;
5207 /* top & -top gives the rightmost 1 bit, so this
5208 fills in any trailing zeros. */
5209 top |= (top & -top) - 1;
5210 top &= ~(top >> 1);
5211 value = (value ^ top) - top;
5215 return value;
5218 /* Determine whether the optional operand(s) should be printed. */
5220 static int
5221 skip_optional_operands (const unsigned char *opindex,
5222 unsigned long insn, int dialect)
5224 const struct powerpc_operand *operand;
5226 for (; *opindex != 0; opindex++)
5228 operand = &powerpc_operands[*opindex];
5229 if ((operand->flags & PPC_OPERAND_NEXT) != 0
5230 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
5231 && operand_value_powerpc (operand, insn, dialect) != 0))
5232 return 0;
5235 return 1;
5238 /* Print a PowerPC or POWER instruction. */
5240 static int
5241 print_insn_powerpc (bfd_vma memaddr,
5242 struct disassemble_info *info,
5243 int bigendian,
5244 int dialect)
5246 bfd_byte buffer[4];
5247 int status;
5248 unsigned long insn;
5249 const struct powerpc_opcode *opcode;
5250 const struct powerpc_opcode *opcode_end;
5251 unsigned long op;
5253 if (dialect == 0)
5254 dialect = powerpc_dialect (info);
5256 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
5257 if (status != 0)
5259 (*info->memory_error_func) (status, memaddr, info);
5260 return -1;
5263 if (bigendian)
5264 insn = bfd_getb32 (buffer);
5265 else
5266 insn = bfd_getl32 (buffer);
5268 /* Get the major opcode of the instruction. */
5269 op = PPC_OP (insn);
5271 /* Find the first match in the opcode table. We could speed this up
5272 a bit by doing a binary search on the major opcode. */
5273 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
5274 again:
5275 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
5277 unsigned long table_op;
5278 const unsigned char *opindex;
5279 const struct powerpc_operand *operand;
5280 int invalid;
5281 int need_comma;
5282 int need_paren;
5283 int skip_optional;
5285 table_op = PPC_OP (opcode->opcode);
5286 if (op < table_op)
5287 break;
5288 if (op > table_op)
5289 continue;
5291 if ((insn & opcode->mask) != opcode->opcode
5292 || (opcode->flags & dialect) == 0)
5293 continue;
5295 /* Make two passes over the operands. First see if any of them
5296 have extraction functions, and, if they do, make sure the
5297 instruction is valid. */
5298 invalid = 0;
5299 for (opindex = opcode->operands; *opindex != 0; opindex++)
5301 operand = powerpc_operands + *opindex;
5302 if (operand->extract)
5303 (*operand->extract) (insn, dialect, &invalid);
5305 if (invalid)
5306 continue;
5308 /* The instruction is valid. */
5309 if (opcode->operands[0] != 0)
5310 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
5311 else
5312 (*info->fprintf_func) (info->stream, "%s", opcode->name);
5314 /* Now extract and print the operands. */
5315 need_comma = 0;
5316 need_paren = 0;
5317 skip_optional = -1;
5318 for (opindex = opcode->operands; *opindex != 0; opindex++)
5320 long value;
5322 operand = powerpc_operands + *opindex;
5324 /* Operands that are marked FAKE are simply ignored. We
5325 already made sure that the extract function considered
5326 the instruction to be valid. */
5327 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
5328 continue;
5330 /* If all of the optional operands have the value zero,
5331 then don't print any of them. */
5332 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
5334 if (skip_optional < 0)
5335 skip_optional = skip_optional_operands (opindex, insn,
5336 dialect);
5337 if (skip_optional)
5338 continue;
5341 value = operand_value_powerpc (operand, insn, dialect);
5343 if (need_comma)
5345 (*info->fprintf_func) (info->stream, ",");
5346 need_comma = 0;
5349 /* Print the operand as directed by the flags. */
5350 if ((operand->flags & PPC_OPERAND_GPR) != 0
5351 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
5352 (*info->fprintf_func) (info->stream, "r%ld", value);
5353 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
5354 (*info->fprintf_func) (info->stream, "f%ld", value);
5355 else if ((operand->flags & PPC_OPERAND_VR) != 0)
5356 (*info->fprintf_func) (info->stream, "v%ld", value);
5357 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
5358 (*info->print_address_func) (memaddr + value, info);
5359 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
5360 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
5361 else if ((operand->flags & PPC_OPERAND_CR) == 0
5362 || (dialect & PPC_OPCODE_PPC) == 0)
5363 (*info->fprintf_func) (info->stream, "%ld", value);
5364 else
5366 if (operand->bitm == 7)
5367 (*info->fprintf_func) (info->stream, "cr%ld", value);
5368 else
5370 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
5371 int cr;
5372 int cc;
5374 cr = value >> 2;
5375 if (cr != 0)
5376 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
5377 cc = value & 3;
5378 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
5382 if (need_paren)
5384 (*info->fprintf_func) (info->stream, ")");
5385 need_paren = 0;
5388 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
5389 need_comma = 1;
5390 else
5392 (*info->fprintf_func) (info->stream, "(");
5393 need_paren = 1;
5397 /* We have found and printed an instruction; return. */
5398 return 4;
5401 if ((dialect & PPC_OPCODE_ANY) != 0)
5403 dialect = ~PPC_OPCODE_ANY;
5404 goto again;
5407 /* We could not find a match. */
5408 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
5410 return 4;