src/flash/nand/arm_io.c

   1 /*
   2  * Copyright (C) 2009 by Marvell Semiconductors, Inc.
   3  * Written by Nicolas Pitre <nico at marvell.com>
   4  *
   5  * Copyright (C) 2009 by David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the
  19  * Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  21  */
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "core.h"
  28 #include "arm_io.h"
  29 #include <helper/binarybuffer.h>
  30 #include <target/arm.h>
  31 #include <target/armv7m.h>
  32 #include <target/algorithm.h>
  33
  34 /**
  35  * Copies code to a working area.  This will allocate room for the code plus the
  36  * additional amount requested if the working area pointer is null.
  37  *
  38  * @param target Pointer to the target to copy code to
  39  * @param code Pointer to the code area to be copied
  40  * @param code_size Size of the code being copied
  41  * @param additional Size of the additional area to be allocated in addition to
  42  *                   code
  43  * @param area Pointer to a pointer to a working area to copy code to
  44  * @return Success or failure of the operation
  45  */
  46 static int arm_code_to_working_area(struct target *target,
  47         const uint32_t *code, unsigned code_size,
  48         unsigned additional, struct working_area **area)
  49 {
  50         uint8_t code_buf[code_size];
  51         int retval;
  52         unsigned size = code_size + additional;
  53
  54         /* REVISIT this assumes size doesn't ever change.
  55          * That's usually correct; but there are boards with
  56          * both large and small page chips, where it won't be...
  57          */
  58
  59         /* make sure we have a working area */
  60         if (NULL == *area) {
  61                 retval = target_alloc_working_area(target, size, area);
  62                 if (retval != ERROR_OK) {
  63                         LOG_DEBUG("%s: no %d byte buffer", __func__, (int) size);
  64                         return ERROR_NAND_NO_BUFFER;
  65                 }
  66         }
  67
  68         /* buffer code in target endianness */
  69         target_buffer_set_u32_array(target, code_buf, code_size / 4, code);
  70
  71         /* copy code to work area */
  72         retval = target_write_memory(target, (*area)->address,
  73                         4, code_size / 4, code_buf);
  74
  75         return retval;
  76 }
  77
  78 /**
  79  * ARM-specific bulk write from buffer to address of 8-bit wide NAND.
  80  * For now this supports ARMv4,ARMv5 and ARMv7-M cores.
  81  *
  82  * Enhancements to target_run_algorithm() could enable:
  83  *   - ARMv6 and ARMv7 cores in ARM mode
  84  *
  85  * Different code fragments could handle:
  86  *   - 16-bit wide data (needs different setup)
  87  *
  88  * @param nand Pointer to the arm_nand_data struct that defines the I/O
  89  * @param data Pointer to the data to be copied to flash
  90  * @param size Size of the data being copied
  91  * @return Success or failure of the operation
  92  */
  93 int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
  94 {
  95         struct target *target = nand->target;
  96         struct arm_algorithm armv4_5_algo;
  97         struct armv7m_algorithm armv7m_algo;
  98         void *arm_algo;
  99         struct arm *arm = target->arch_info;
 100         struct reg_param reg_params[3];
 101         uint32_t target_buf;
 102         uint32_t exit_var = 0;
 103         int retval;
 104
 105         /* Inputs:
 106          *  r0  NAND data address (byte wide)
 107          *  r1  buffer address
 108          *  r2  buffer length
 109          */
 110         static const uint32_t code_armv4_5[] = {
 111                 0xe4d13001,     /* s: ldrb  r3, [r1], #1 */
 112                 0xe5c03000,     /*    strb  r3, [r0]     */
 113                 0xe2522001,     /*    subs  r2, r2, #1   */
 114                 0x1afffffb,     /*    bne   s            */
 115
 116                 /* exit: ARMv4 needs hardware breakpoint */
 117                 0xe1200070,     /* e: bkpt  #0           */
 118         };
 119
 120         /* Inputs:
 121          *  r0  NAND data address (byte wide)
 122          *  r1  buffer address
 123          *  r2  buffer length
 124          *
 125          * see contrib/loaders/flash/armv7m_io.s for src
 126          */
 127         static const uint32_t code_armv7m[] = {
 128                 0x3b01f811,
 129                 0x3a017003,
 130                 0xaffaf47f,
 131                 0xbf00be00,
 132         };
 133
 134         int target_code_size = 0;
 135         const uint32_t *target_code_src = NULL;
 136
 137         /* set up algorithm */
 138         if (is_armv7m(target_to_armv7m(target))) {  /* armv7m target */
 139                 armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
 140                 armv7m_algo.core_mode = ARM_MODE_THREAD;
 141                 arm_algo = &armv7m_algo;
 142                 target_code_size = sizeof(code_armv7m);
 143                 target_code_src = code_armv7m;
 144         } else {
 145                 armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
 146                 armv4_5_algo.core_mode = ARM_MODE_SVC;
 147                 armv4_5_algo.core_state = ARM_STATE_ARM;
 148                 arm_algo = &armv4_5_algo;
 149                 target_code_size = sizeof(code_armv4_5);
 150                 target_code_src = code_armv4_5;
 151         }
 152
 153         if (nand->op != ARM_NAND_WRITE || !nand->copy_area) {
 154                 retval = arm_code_to_working_area(target, target_code_src, target_code_size,
 155                                 nand->chunk_size, &nand->copy_area);
 156                 if (retval != ERROR_OK)
 157                         return retval;
 158         }
 159
 160         nand->op = ARM_NAND_WRITE;
 161
 162         /* copy data to work area */
 163         target_buf = nand->copy_area->address + target_code_size;
 164         retval = target_write_buffer(target, target_buf, size, data);
 165         if (retval != ERROR_OK)
 166                 return retval;
 167
 168         /* set up parameters */
 169         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
 170         init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
 171         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
 172
 173         buf_set_u32(reg_params[0].value, 0, 32, nand->data);
 174         buf_set_u32(reg_params[1].value, 0, 32, target_buf);
 175         buf_set_u32(reg_params[2].value, 0, 32, size);
 176
 177         /* armv4 must exit using a hardware breakpoint */
 178         if (arm->is_armv4)
 179                 exit_var = nand->copy_area->address + target_code_size - 4;
 180
 181         /* use alg to write data from work area to NAND chip */
 182         retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 183                         nand->copy_area->address, exit_var, 1000, arm_algo);
 184         if (retval != ERROR_OK)
 185                 LOG_ERROR("error executing hosted NAND write");
 186
 187         destroy_reg_param(&reg_params[0]);
 188         destroy_reg_param(&reg_params[1]);
 189         destroy_reg_param(&reg_params[2]);
 190
 191         return retval;
 192 }
 193
 194 /**
 195  * Uses an on-chip algorithm for an ARM device to read from a NAND device and
 196  * store the data into the host machine's memory.
 197  *
 198  * @param nand Pointer to the arm_nand_data struct that defines the I/O
 199  * @param data Pointer to the data buffer to store the read data
 200  * @param size Amount of data to be stored to the buffer.
 201  * @return Success or failure of the operation
 202  */
 203 int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 204 {
 205         struct target *target = nand->target;
 206         struct arm_algorithm armv4_5_algo;
 207         struct armv7m_algorithm armv7m_algo;
 208         void *arm_algo;
 209         struct arm *arm = target->arch_info;
 210         struct reg_param reg_params[3];
 211         uint32_t target_buf;
 212         uint32_t exit_var = 0;
 213         int retval;
 214
 215         /* Inputs:
 216          *  r0  buffer address
 217          *  r1  NAND data address (byte wide)
 218          *  r2  buffer length
 219          */
 220         static const uint32_t code_armv4_5[] = {
 221                 0xe5d13000,     /* s: ldrb  r3, [r1]     */
 222                 0xe4c03001,     /*    strb  r3, [r0], #1 */
 223                 0xe2522001,     /*    subs  r2, r2, #1   */
 224                 0x1afffffb,     /*    bne   s            */
 225
 226                 /* exit: ARMv4 needs hardware breakpoint */
 227                 0xe1200070,     /* e: bkpt  #0           */
 228         };
 229
 230         /* Inputs:
 231          *  r0  buffer address
 232          *  r1  NAND data address (byte wide)
 233          *  r2  buffer length
 234          *
 235          * see contrib/loaders/flash/armv7m_io.s for src
 236          */
 237         static const uint32_t code_armv7m[] = {
 238                 0xf800780b,
 239                 0x3a013b01,
 240                 0xaffaf47f,
 241                 0xbf00be00,
 242         };
 243
 244         int target_code_size = 0;
 245         const uint32_t *target_code_src = NULL;
 246
 247         /* set up algorithm */
 248         if (is_armv7m(target_to_armv7m(target))) {  /* armv7m target */
 249                 armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
 250                 armv7m_algo.core_mode = ARM_MODE_THREAD;
 251                 arm_algo = &armv7m_algo;
 252                 target_code_size = sizeof(code_armv7m);
 253                 target_code_src = code_armv7m;
 254         } else {
 255                 armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
 256                 armv4_5_algo.core_mode = ARM_MODE_SVC;
 257                 armv4_5_algo.core_state = ARM_STATE_ARM;
 258                 arm_algo = &armv4_5_algo;
 259                 target_code_size = sizeof(code_armv4_5);
 260                 target_code_src = code_armv4_5;
 261         }
 262
 263         /* create the copy area if not yet available */
 264         if (nand->op != ARM_NAND_READ || !nand->copy_area) {
 265                 retval = arm_code_to_working_area(target, target_code_src, target_code_size,
 266                                 nand->chunk_size, &nand->copy_area);
 267                 if (retval != ERROR_OK)
 268                         return retval;
 269         }
 270
 271         nand->op = ARM_NAND_READ;
 272         target_buf = nand->copy_area->address + target_code_size;
 273
 274         /* set up parameters */
 275         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
 276         init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
 277         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
 278
 279         buf_set_u32(reg_params[0].value, 0, 32, target_buf);
 280         buf_set_u32(reg_params[1].value, 0, 32, nand->data);
 281         buf_set_u32(reg_params[2].value, 0, 32, size);
 282
 283         /* armv4 must exit using a hardware breakpoint */
 284         if (arm->is_armv4)
 285                 exit_var = nand->copy_area->address + target_code_size - 4;
 286
 287         /* use alg to write data from NAND chip to work area */
 288         retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 289                         nand->copy_area->address, exit_var, 1000, arm_algo);
 290         if (retval != ERROR_OK)
 291                 LOG_ERROR("error executing hosted NAND read");
 292
 293         destroy_reg_param(&reg_params[0]);
 294         destroy_reg_param(&reg_params[1]);
 295         destroy_reg_param(&reg_params[2]);
 296
 297         /* read from work area to the host's memory */
 298         retval = target_read_buffer(target, target_buf, size, data);
 299
 300         return retval;
 301 }