2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
30 #include <helper/command.h>
36 * Holds the interface to ARM cores.
38 * At this writing, only "classic ARM" cores built on the ARMv4 register
39 * and mode model are supported. The Thumb2-only microcontroller profile
40 * support has not yet been integrated, affecting Cortex-M parts.
44 * Represent state of an ARM core.
46 * Most numbers match the five low bits of the *PSR registers on
47 * "classic ARM" processors, which build on the ARMv4 processor
48 * modes and register set.
50 * ARM_MODE_ANY is a magic value, often used as a wildcard.
52 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
53 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
67 ARM_MODE_USER_THREAD
= 1,
73 const char *arm_mode_name(unsigned psr_mode
);
74 bool is_arm_mode(unsigned psr_mode
);
76 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
84 #define ARM_COMMON_MAGIC 0x0A450A45
87 * Represents a generic ARM core, with standard application registers.
89 * There are sixteen application registers (including PC, SP, LR) and a PSR.
90 * Cortex-M series cores do not support as many core states or shadowed
91 * registers as traditional ARM cores, and only support Thumb2 instructions.
95 struct reg_cache
*core_cache
;
97 /** Handle to the PC; valid in all core modes. */
100 /** Handle to the CPSR/xPSR; valid in all core modes. */
103 /** Handle to the SPSR; valid only in core modes with an SPSR. */
106 /** Support for arm_reg_current() */
110 * Indicates what registers are in the ARM state core register set.
111 * ARM_MODE_ANY indicates the standard set of 37 registers,
112 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
113 * more registers are shadowed, for "Secure Monitor" mode.
114 * ARM_MODE_THREAD indicates a microcontroller profile core,
115 * which only shadows SP.
117 enum arm_mode core_type
;
119 /** Record the current core mode: SVC, USR, or some other mode. */
120 enum arm_mode core_mode
;
122 /** Record the current core state: ARM, Thumb, or otherwise. */
123 enum arm_state core_state
;
125 /** Flag reporting unavailability of the BKPT instruction. */
128 /** Flag reporting armv6m based core. */
131 /** Flag reporting whether semihosting is active. */
134 /** Value to be returned by semihosting SYS_ERRNO request. */
135 int semihosting_errno
;
137 int (*setup_semihosting
)(struct target
*target
, int enable
);
139 /** Backpointer to the target. */
140 struct target
*target
;
142 /** Handle for the debug module, if one is present. */
145 /** Handle for the Embedded Trace Module, if one is present. */
146 struct etm_context
*etm
;
148 /* FIXME all these methods should take "struct arm *" not target */
150 /** Retrieve all core registers, for display. */
151 int (*full_context
)(struct target
*target
);
153 /** Retrieve a single core register. */
154 int (*read_core_reg
)(struct target
*target
, struct reg
*reg
,
155 int num
, enum arm_mode mode
);
156 int (*write_core_reg
)(struct target
*target
, struct reg
*reg
,
157 int num
, enum arm_mode mode
, uint32_t value
);
159 /** Read coprocessor register. */
160 int (*mrc
)(struct target
*target
, int cpnum
,
161 uint32_t op1
, uint32_t op2
,
162 uint32_t CRn
, uint32_t CRm
,
165 /** Write coprocessor register. */
166 int (*mcr
)(struct target
*target
, int cpnum
,
167 uint32_t op1
, uint32_t op2
,
168 uint32_t CRn
, uint32_t CRm
,
173 /** For targets conforming to ARM Debug Interface v5,
174 * this handle references the Debug Access Port (DAP)
175 * used to make requests to the target.
177 struct adiv5_dap
*dap
;
180 /** Convert target handle to generic ARM target state handle. */
181 static inline struct arm
*target_to_arm(struct target
*target
)
183 assert(target
!= NULL
);
184 return target
->arch_info
;
187 static inline bool is_arm(struct arm
*arm
)
190 return arm
->common_magic
== ARM_COMMON_MAGIC
;
193 struct arm_algorithm
{
196 enum arm_mode core_mode
;
197 enum arm_state core_state
;
203 struct target
*target
;
208 struct reg_cache
*arm_build_reg_cache(struct target
*target
, struct arm
*arm
);
210 extern const struct command_registration arm_command_handlers
[];
212 int arm_arch_state(struct target
*target
);
213 int arm_get_gdb_reg_list(struct target
*target
,
214 struct reg
**reg_list
[], int *reg_list_size
,
215 enum target_register_class reg_class
);
217 int arm_init_arch_info(struct target
*target
, struct arm
*arm
);
219 /* REVISIT rename this once it's usable by ARMv7-M */
220 int armv4_5_run_algorithm(struct target
*target
,
221 int num_mem_params
, struct mem_param
*mem_params
,
222 int num_reg_params
, struct reg_param
*reg_params
,
223 uint32_t entry_point
, uint32_t exit_point
,
224 int timeout_ms
, void *arch_info
);
225 int armv4_5_run_algorithm_inner(struct target
*target
,
226 int num_mem_params
, struct mem_param
*mem_params
,
227 int num_reg_params
, struct reg_param
*reg_params
,
228 uint32_t entry_point
, uint32_t exit_point
,
229 int timeout_ms
, void *arch_info
,
230 int (*run_it
)(struct target
*target
, uint32_t exit_point
,
231 int timeout_ms
, void *arch_info
));
233 int arm_checksum_memory(struct target
*target
,
234 uint32_t address
, uint32_t count
, uint32_t *checksum
);
235 int arm_blank_check_memory(struct target
*target
,
236 uint32_t address
, uint32_t count
, uint32_t *blank
);
238 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
239 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
);
241 extern struct reg arm_gdb_dummy_fp_reg
;
242 extern struct reg arm_gdb_dummy_fps_reg
;