1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 /* stm32x register locations */
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
62 /* option byte location */
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
73 /* FLASH_CR register bits */
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
84 /* FLASH_SR register bits */
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
91 /* STM32_FLASH_OBR bit definitions (reading) */
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
100 /* register unlock keys */
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
107 #define FLASH_WRITE_TIMEOUT 10
108 #define FLASH_ERASE_TIMEOUT 100
110 struct stm32x_options
{
112 uint16_t user_options
;
114 uint16_t protection
[4];
117 struct stm32x_flash_bank
{
118 struct stm32x_options option_bytes
;
123 /* used to access dual flash bank stm32xl */
124 uint32_t register_base
;
125 int user_data_offset
;
128 static int stm32x_mass_erase(struct flash_bank
*bank
);
129 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
130 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
131 uint32_t offset
, uint32_t count
);
133 /* flash bank stm32x <base> <size> 0 0 <target#>
135 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
137 struct stm32x_flash_bank
*stm32x_info
;
140 return ERROR_COMMAND_SYNTAX_ERROR
;
142 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
144 bank
->driver_priv
= stm32x_info
;
145 stm32x_info
->probed
= 0;
146 stm32x_info
->has_dual_banks
= false;
147 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
152 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
154 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
155 return reg
+ stm32x_info
->register_base
;
158 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
160 struct target
*target
= bank
->target
;
161 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
164 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
166 struct target
*target
= bank
->target
;
168 int retval
= ERROR_OK
;
170 /* wait for busy to clear */
172 retval
= stm32x_get_flash_status(bank
, &status
);
173 if (retval
!= ERROR_OK
)
175 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
176 if ((status
& FLASH_BSY
) == 0)
178 if (timeout
-- <= 0) {
179 LOG_ERROR("timed out waiting for flash");
185 if (status
& FLASH_WRPRTERR
) {
186 LOG_ERROR("stm32x device protected");
190 if (status
& FLASH_PGERR
) {
191 LOG_ERROR("stm32x device programming failed");
195 /* Clear but report errors */
196 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
197 /* If this operation fails, we ignore it and report the original
200 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
201 FLASH_WRPRTERR
| FLASH_PGERR
);
206 int stm32x_check_operation_supported(struct flash_bank
*bank
)
208 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
210 /* if we have a dual flash bank device then
211 * we need to perform option byte stuff on bank0 only */
212 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
213 LOG_ERROR("Option Byte Operation's must use bank0");
214 return ERROR_FLASH_OPERATION_FAILED
;
220 static int stm32x_read_options(struct flash_bank
*bank
)
223 struct stm32x_flash_bank
*stm32x_info
= NULL
;
224 struct target
*target
= bank
->target
;
226 stm32x_info
= bank
->driver_priv
;
228 /* read current option bytes */
229 int retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optiondata
);
230 if (retval
!= ERROR_OK
)
233 stm32x_info
->option_bytes
.user_options
= (uint16_t)0xFFF8 | ((optiondata
>> 2) & 0x07);
234 stm32x_info
->option_bytes
.user_data
= (optiondata
>> stm32x_info
->user_data_offset
) & 0xffff;
235 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
237 if (optiondata
& (1 << OPT_READOUT
))
238 LOG_INFO("Device Security Bit Set");
240 /* each bit refers to a 4bank protection */
241 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &optiondata
);
242 if (retval
!= ERROR_OK
)
245 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
246 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
247 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
248 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
253 static int stm32x_erase_options(struct flash_bank
*bank
)
255 struct stm32x_flash_bank
*stm32x_info
= NULL
;
256 struct target
*target
= bank
->target
;
258 stm32x_info
= bank
->driver_priv
;
260 /* read current options */
261 stm32x_read_options(bank
);
263 /* unlock flash registers */
264 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
265 if (retval
!= ERROR_OK
)
268 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
269 if (retval
!= ERROR_OK
)
272 /* unlock option flash registers */
273 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
274 if (retval
!= ERROR_OK
)
276 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
277 if (retval
!= ERROR_OK
)
280 /* erase option bytes */
281 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
282 if (retval
!= ERROR_OK
)
284 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
285 if (retval
!= ERROR_OK
)
288 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
289 if (retval
!= ERROR_OK
)
292 /* clear readout protection and complementary option bytes
293 * this will also force a device unlock if set */
294 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
299 static int stm32x_write_options(struct flash_bank
*bank
)
301 struct stm32x_flash_bank
*stm32x_info
= NULL
;
302 struct target
*target
= bank
->target
;
304 stm32x_info
= bank
->driver_priv
;
306 /* unlock flash registers */
307 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
308 if (retval
!= ERROR_OK
)
310 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
311 if (retval
!= ERROR_OK
)
314 /* unlock option flash registers */
315 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
316 if (retval
!= ERROR_OK
)
318 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
319 if (retval
!= ERROR_OK
)
322 /* program option bytes */
323 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
324 if (retval
!= ERROR_OK
)
327 uint8_t opt_bytes
[16];
329 target_buffer_set_u16(target
, opt_bytes
, stm32x_info
->option_bytes
.RDP
);
330 target_buffer_set_u16(target
, opt_bytes
+ 2, stm32x_info
->option_bytes
.user_options
);
331 target_buffer_set_u16(target
, opt_bytes
+ 4, stm32x_info
->option_bytes
.user_data
& 0xff);
332 target_buffer_set_u16(target
, opt_bytes
+ 6, (stm32x_info
->option_bytes
.user_data
>> 8) & 0xff);
333 target_buffer_set_u16(target
, opt_bytes
+ 8, stm32x_info
->option_bytes
.protection
[0]);
334 target_buffer_set_u16(target
, opt_bytes
+ 10, stm32x_info
->option_bytes
.protection
[1]);
335 target_buffer_set_u16(target
, opt_bytes
+ 12, stm32x_info
->option_bytes
.protection
[2]);
336 target_buffer_set_u16(target
, opt_bytes
+ 14, stm32x_info
->option_bytes
.protection
[3]);
338 uint32_t offset
= STM32_OB_RDP
- bank
->base
;
339 retval
= stm32x_write_block(bank
, opt_bytes
, offset
, sizeof(opt_bytes
) / 2);
340 if (retval
!= ERROR_OK
) {
341 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
342 LOG_ERROR("working area required to erase options bytes");
346 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
347 if (retval
!= ERROR_OK
)
353 static int stm32x_protect_check(struct flash_bank
*bank
)
355 struct target
*target
= bank
->target
;
356 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
363 if (target
->state
!= TARGET_HALTED
) {
364 LOG_ERROR("Target not halted");
365 return ERROR_TARGET_NOT_HALTED
;
368 int retval
= stm32x_check_operation_supported(bank
);
369 if (ERROR_OK
!= retval
)
372 /* medium density - each bit refers to a 4bank protection
373 * high density - each bit refers to a 2bank protection */
374 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
375 if (retval
!= ERROR_OK
)
378 /* medium density - each protection bit is for 4 * 1K pages
379 * high density - each protection bit is for 2 * 2K pages */
380 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
382 if (stm32x_info
->ppage_size
== 2) {
383 /* high density flash/connectivity line protection */
387 if (protection
& (1 << 31))
390 /* bit 31 controls sector 62 - 255 protection for high density
391 * bit 31 controls sector 62 - 127 protection for connectivity line */
392 for (s
= 62; s
< bank
->num_sectors
; s
++)
393 bank
->sectors
[s
].is_protected
= set
;
395 if (bank
->num_sectors
> 61)
398 for (i
= 0; i
< num_bits
; i
++) {
401 if (protection
& (1 << i
))
404 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
405 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
408 /* low/medium density flash protection */
409 for (i
= 0; i
< num_bits
; i
++) {
412 if (protection
& (1 << i
))
415 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
416 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
423 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
425 struct target
*target
= bank
->target
;
428 if (bank
->target
->state
!= TARGET_HALTED
) {
429 LOG_ERROR("Target not halted");
430 return ERROR_TARGET_NOT_HALTED
;
433 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
434 return stm32x_mass_erase(bank
);
436 /* unlock flash registers */
437 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
438 if (retval
!= ERROR_OK
)
440 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
441 if (retval
!= ERROR_OK
)
444 for (i
= first
; i
<= last
; i
++) {
445 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
446 if (retval
!= ERROR_OK
)
448 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
449 bank
->base
+ bank
->sectors
[i
].offset
);
450 if (retval
!= ERROR_OK
)
452 retval
= target_write_u32(target
,
453 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
454 if (retval
!= ERROR_OK
)
457 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
458 if (retval
!= ERROR_OK
)
461 bank
->sectors
[i
].is_erased
= 1;
464 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
465 if (retval
!= ERROR_OK
)
471 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
473 struct stm32x_flash_bank
*stm32x_info
= NULL
;
474 struct target
*target
= bank
->target
;
475 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
480 stm32x_info
= bank
->driver_priv
;
482 if (target
->state
!= TARGET_HALTED
) {
483 LOG_ERROR("Target not halted");
484 return ERROR_TARGET_NOT_HALTED
;
487 int retval
= stm32x_check_operation_supported(bank
);
488 if (ERROR_OK
!= retval
)
491 if ((first
% stm32x_info
->ppage_size
) != 0) {
492 LOG_WARNING("aligned start protect sector to a %d sector boundary",
493 stm32x_info
->ppage_size
);
494 first
= first
- (first
% stm32x_info
->ppage_size
);
496 if (((last
+ 1) % stm32x_info
->ppage_size
) != 0) {
497 LOG_WARNING("aligned end protect sector to a %d sector boundary",
498 stm32x_info
->ppage_size
);
500 last
= last
- (last
% stm32x_info
->ppage_size
);
504 /* medium density - each bit refers to a 4bank protection
505 * high density - each bit refers to a 2bank protection */
506 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
507 if (retval
!= ERROR_OK
)
510 prot_reg
[0] = (uint16_t)protection
;
511 prot_reg
[1] = (uint16_t)(protection
>> 8);
512 prot_reg
[2] = (uint16_t)(protection
>> 16);
513 prot_reg
[3] = (uint16_t)(protection
>> 24);
515 if (stm32x_info
->ppage_size
== 2) {
516 /* high density flash */
518 /* bit 7 controls sector 62 - 255 protection */
521 prot_reg
[3] &= ~(1 << 7);
523 prot_reg
[3] |= (1 << 7);
531 for (i
= first
; i
<= last
; i
++) {
532 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
533 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
536 prot_reg
[reg
] &= ~(1 << bit
);
538 prot_reg
[reg
] |= (1 << bit
);
541 /* medium density flash */
542 for (i
= first
; i
<= last
; i
++) {
543 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
544 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
547 prot_reg
[reg
] &= ~(1 << bit
);
549 prot_reg
[reg
] |= (1 << bit
);
553 status
= stm32x_erase_options(bank
);
554 if (status
!= ERROR_OK
)
557 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
558 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
559 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
560 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
562 return stm32x_write_options(bank
);
565 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
566 uint32_t offset
, uint32_t count
)
568 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
569 struct target
*target
= bank
->target
;
570 uint32_t buffer_size
= 16384;
571 struct working_area
*write_algorithm
;
572 struct working_area
*source
;
573 uint32_t address
= bank
->base
+ offset
;
574 struct reg_param reg_params
[5];
575 struct armv7m_algorithm armv7m_info
;
576 int retval
= ERROR_OK
;
578 /* see contrib/loaders/flash/stm32f1x.S for src */
580 static const uint8_t stm32x_flash_write_code
[] = {
581 /* #define STM32_FLASH_SR_OFFSET 0x0C */
583 0x16, 0x68, /* ldr r6, [r2, #0] */
584 0x00, 0x2e, /* cmp r6, #0 */
585 0x18, 0xd0, /* beq exit */
586 0x55, 0x68, /* ldr r5, [r2, #4] */
587 0xb5, 0x42, /* cmp r5, r6 */
588 0xf9, 0xd0, /* beq wait_fifo */
589 0x2e, 0x88, /* ldrh r6, [r5, #0] */
590 0x26, 0x80, /* strh r6, [r4, #0] */
591 0x02, 0x35, /* adds r5, #2 */
592 0x02, 0x34, /* adds r4, #2 */
594 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
595 0x01, 0x27, /* movs r7, #1 */
596 0x3e, 0x42, /* tst r6, r7 */
597 0xfb, 0xd1, /* bne busy */
598 0x14, 0x27, /* movs r7, #0x14 */
599 0x3e, 0x42, /* tst r6, r7 */
600 0x08, 0xd1, /* bne error */
601 0x9d, 0x42, /* cmp r5, r3 */
602 0x01, 0xd3, /* bcc no_wrap */
603 0x15, 0x46, /* mov r5, r2 */
604 0x08, 0x35, /* adds r5, #8 */
606 0x55, 0x60, /* str r5, [r2, #4] */
607 0x01, 0x39, /* subs r1, r1, #1 */
608 0x00, 0x29, /* cmp r1, #0 */
609 0x02, 0xd0, /* beq exit */
610 0xe5, 0xe7, /* b wait_fifo */
612 0x00, 0x20, /* movs r0, #0 */
613 0x50, 0x60, /* str r0, [r2, #4] */
615 0x30, 0x46, /* mov r0, r6 */
616 0x00, 0xbe, /* bkpt #0 */
619 /* flash write code */
620 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
621 &write_algorithm
) != ERROR_OK
) {
622 LOG_WARNING("no working area available, can't do block memory writes");
623 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
626 retval
= target_write_buffer(target
, write_algorithm
->address
,
627 sizeof(stm32x_flash_write_code
), (uint8_t *)stm32x_flash_write_code
);
628 if (retval
!= ERROR_OK
)
632 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
634 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
635 if (buffer_size
<= 256) {
636 /* we already allocated the writing code, but failed to get a
637 * buffer, free the algorithm */
638 target_free_working_area(target
, write_algorithm
);
640 LOG_WARNING("no large enough working area available, can't do block memory writes");
641 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
645 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
646 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
647 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
648 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
649 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
651 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
652 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
653 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
654 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
655 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
657 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
658 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
660 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
663 source
->address
, source
->size
,
664 write_algorithm
->address
, 0,
667 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
668 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
669 buf_get_u32(reg_params
[4].value
, 0, 32));
671 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
672 LOG_ERROR("flash memory not erased before writing");
673 /* Clear but report errors */
674 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
677 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
678 LOG_ERROR("flash memory write protected");
679 /* Clear but report errors */
680 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
684 target_free_working_area(target
, source
);
685 target_free_working_area(target
, write_algorithm
);
687 destroy_reg_param(®_params
[0]);
688 destroy_reg_param(®_params
[1]);
689 destroy_reg_param(®_params
[2]);
690 destroy_reg_param(®_params
[3]);
691 destroy_reg_param(®_params
[4]);
696 static int stm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
697 uint32_t offset
, uint32_t count
)
699 struct target
*target
= bank
->target
;
700 uint8_t *new_buffer
= NULL
;
702 if (bank
->target
->state
!= TARGET_HALTED
) {
703 LOG_ERROR("Target not halted");
704 return ERROR_TARGET_NOT_HALTED
;
708 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
709 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
712 /* If there's an odd number of bytes, the data has to be padded. Duplicate
713 * the buffer and use the normal code path with a single block write since
714 * it's probably cheaper than to special case the last odd write using
715 * discrete accesses. */
717 new_buffer
= malloc(count
+ 1);
718 if (new_buffer
== NULL
) {
719 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
722 LOG_INFO("odd number of bytes to write, padding with 0xff");
723 buffer
= memcpy(new_buffer
, buffer
, count
);
724 buffer
[count
++] = 0xff;
727 uint32_t words_remaining
= count
/ 2;
730 /* unlock flash registers */
731 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
732 if (retval
!= ERROR_OK
)
734 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
735 if (retval
!= ERROR_OK
)
738 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
739 if (retval
!= ERROR_OK
)
742 /* try using a block write */
743 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
745 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
746 /* if block write failed (no sufficient working area),
747 * we use normal (slow) single halfword accesses */
748 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
750 while (words_remaining
> 0) {
752 memcpy(&value
, buffer
, sizeof(uint16_t));
754 retval
= target_write_u16(target
, bank
->base
+ offset
, value
);
755 if (retval
!= ERROR_OK
)
756 goto reset_pg_and_lock
;
758 retval
= stm32x_wait_status_busy(bank
, 5);
759 if (retval
!= ERROR_OK
)
760 goto reset_pg_and_lock
;
769 retval2
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
770 if (retval
== ERROR_OK
)
780 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
782 /* This check the device CPUID core register to detect
783 * the M0 from the M3 devices. */
785 struct target
*target
= bank
->target
;
786 uint32_t cpuid
, device_id_register
= 0;
788 /* Get the CPUID from the ARM Core
789 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
790 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
791 if (retval
!= ERROR_OK
)
794 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
795 /* 0xC20 is M0 devices */
796 device_id_register
= 0x40015800;
797 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
798 /* 0xC23 is M3 devices */
799 device_id_register
= 0xE0042000;
800 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
801 /* 0xC24 is M4 devices */
802 device_id_register
= 0xE0042000;
804 LOG_ERROR("Cannot identify target as a stm32x");
808 /* read stm32 device id register */
809 retval
= target_read_u32(target
, device_id_register
, device_id
);
810 if (retval
!= ERROR_OK
)
816 static int stm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_size_in_kb
)
818 struct target
*target
= bank
->target
;
819 uint32_t cpuid
, flash_size_reg
;
821 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
822 if (retval
!= ERROR_OK
)
825 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
826 /* 0xC20 is M0 devices */
827 flash_size_reg
= 0x1FFFF7CC;
828 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
829 /* 0xC23 is M3 devices */
830 flash_size_reg
= 0x1FFFF7E0;
831 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
832 /* 0xC24 is M4 devices */
833 flash_size_reg
= 0x1FFFF7CC;
835 LOG_ERROR("Cannot identify target as a stm32x");
839 retval
= target_read_u16(target
, flash_size_reg
, flash_size_in_kb
);
840 if (retval
!= ERROR_OK
)
846 static int stm32x_probe(struct flash_bank
*bank
)
848 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
850 uint16_t flash_size_in_kb
;
851 uint16_t max_flash_size_in_kb
;
854 uint32_t base_address
= 0x08000000;
856 stm32x_info
->probed
= 0;
857 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
858 stm32x_info
->user_data_offset
= 10;
860 /* read stm32 device id register */
861 int retval
= stm32x_get_device_id(bank
, &device_id
);
862 if (retval
!= ERROR_OK
)
865 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
867 /* set page size, protection granularity and max flash size depending on family */
868 switch (device_id
& 0xfff) {
869 case 0x410: /* medium density */
871 stm32x_info
->ppage_size
= 4;
872 max_flash_size_in_kb
= 128;
874 case 0x412: /* low density */
876 stm32x_info
->ppage_size
= 4;
877 max_flash_size_in_kb
= 32;
879 case 0x414: /* high density */
881 stm32x_info
->ppage_size
= 2;
882 max_flash_size_in_kb
= 512;
884 case 0x418: /* connectivity line density */
886 stm32x_info
->ppage_size
= 2;
887 max_flash_size_in_kb
= 256;
889 case 0x420: /* value line density */
891 stm32x_info
->ppage_size
= 4;
892 max_flash_size_in_kb
= 128;
894 case 0x422: /* stm32f30x */
896 stm32x_info
->ppage_size
= 2;
897 max_flash_size_in_kb
= 256;
898 stm32x_info
->user_data_offset
= 16;
900 case 0x428: /* value line High density */
902 stm32x_info
->ppage_size
= 4;
903 max_flash_size_in_kb
= 128;
905 case 0x430: /* xl line density (dual flash banks) */
907 stm32x_info
->ppage_size
= 2;
908 max_flash_size_in_kb
= 1024;
909 stm32x_info
->has_dual_banks
= true;
911 case 0x432: /* stm32f37x */
913 stm32x_info
->ppage_size
= 2;
914 max_flash_size_in_kb
= 256;
915 stm32x_info
->user_data_offset
= 16;
917 case 0x440: /* stm32f0x */
919 stm32x_info
->ppage_size
= 4;
920 max_flash_size_in_kb
= 64;
921 stm32x_info
->user_data_offset
= 16;
924 LOG_WARNING("Cannot identify target as a STM32 family.");
928 /* get flash size from target. */
929 retval
= stm32x_get_flash_size(bank
, &flash_size_in_kb
);
931 /* failed reading flash size or flash size invalid (early silicon),
932 * default to max target family */
933 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
934 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
935 max_flash_size_in_kb
);
936 flash_size_in_kb
= max_flash_size_in_kb
;
939 if (stm32x_info
->has_dual_banks
) {
940 /* split reported size into matching bank */
941 if (bank
->base
!= 0x08080000) {
942 /* bank 0 will be fixed 512k */
943 flash_size_in_kb
= 512;
945 flash_size_in_kb
-= 512;
946 /* bank1 also uses a register offset */
947 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
948 base_address
= 0x08080000;
952 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
954 /* did we assign flash size? */
955 assert(flash_size_in_kb
!= 0xffff);
957 /* calculate numbers of pages */
958 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
960 /* check that calculation result makes sense */
961 assert(num_pages
> 0);
965 bank
->sectors
= NULL
;
968 bank
->base
= base_address
;
969 bank
->size
= (num_pages
* page_size
);
970 bank
->num_sectors
= num_pages
;
971 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
973 for (i
= 0; i
< num_pages
; i
++) {
974 bank
->sectors
[i
].offset
= i
* page_size
;
975 bank
->sectors
[i
].size
= page_size
;
976 bank
->sectors
[i
].is_erased
= -1;
977 bank
->sectors
[i
].is_protected
= 1;
980 stm32x_info
->probed
= 1;
985 static int stm32x_auto_probe(struct flash_bank
*bank
)
987 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
988 if (stm32x_info
->probed
)
990 return stm32x_probe(bank
);
994 COMMAND_HANDLER(stm32x_handle_part_id_command
)
1000 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1005 /* read stm32 device id register */
1006 int retval
= stm32x_get_device_id(bank
, &device_id
);
1007 if (retval
!= ERROR_OK
)
1010 if ((device_id
& 0xfff) == 0x410) {
1011 printed
= snprintf(buf
, buf_size
, "stm32x (Medium Density) - Rev: ");
1013 buf_size
-= printed
;
1015 switch (device_id
>> 16) {
1017 snprintf(buf
, buf_size
, "A");
1021 snprintf(buf
, buf_size
, "B");
1025 snprintf(buf
, buf_size
, "Z");
1029 snprintf(buf
, buf_size
, "Y");
1033 snprintf(buf
, buf_size
, "unknown");
1036 } else if ((device_id
& 0xfff) == 0x412) {
1037 printed
= snprintf(buf
, buf_size
, "stm32x (Low Density) - Rev: ");
1039 buf_size
-= printed
;
1041 switch (device_id
>> 16) {
1043 snprintf(buf
, buf_size
, "A");
1047 snprintf(buf
, buf_size
, "unknown");
1050 } else if ((device_id
& 0xfff) == 0x414) {
1051 printed
= snprintf(buf
, buf_size
, "stm32x (High Density) - Rev: ");
1053 buf_size
-= printed
;
1055 switch (device_id
>> 16) {
1057 snprintf(buf
, buf_size
, "A");
1061 snprintf(buf
, buf_size
, "Z");
1065 snprintf(buf
, buf_size
, "unknown");
1068 } else if ((device_id
& 0xfff) == 0x418) {
1069 printed
= snprintf(buf
, buf_size
, "stm32x (Connectivity) - Rev: ");
1071 buf_size
-= printed
;
1073 switch (device_id
>> 16) {
1075 snprintf(buf
, buf_size
, "A");
1079 snprintf(buf
, buf_size
, "Z");
1083 snprintf(buf
, buf_size
, "unknown");
1086 } else if ((device_id
& 0xfff) == 0x420) {
1087 printed
= snprintf(buf
, buf_size
, "stm32x (Value) - Rev: ");
1089 buf_size
-= printed
;
1091 switch (device_id
>> 16) {
1093 snprintf(buf
, buf_size
, "A");
1097 snprintf(buf
, buf_size
, "Z");
1101 snprintf(buf
, buf_size
, "unknown");
1104 } else if ((device_id
& 0xfff) == 0x422) {
1105 printed
= snprintf(buf
, buf_size
, "stm32f30x - Rev: ");
1107 buf_size
-= printed
;
1109 switch (device_id
>> 16) {
1111 snprintf(buf
, buf_size
, "A");
1115 snprintf(buf
, buf_size
, "Z");
1119 snprintf(buf
, buf_size
, "B");
1123 snprintf(buf
, buf_size
, "unknown");
1126 } else if ((device_id
& 0xfff) == 0x428) {
1127 printed
= snprintf(buf
, buf_size
, "stm32x (Value HD) - Rev: ");
1129 buf_size
-= printed
;
1131 switch (device_id
>> 16) {
1133 snprintf(buf
, buf_size
, "A");
1137 snprintf(buf
, buf_size
, "Z");
1141 snprintf(buf
, buf_size
, "unknown");
1144 } else if ((device_id
& 0xfff) == 0x430) {
1145 printed
= snprintf(buf
, buf_size
, "stm32x (XL) - Rev: ");
1147 buf_size
-= printed
;
1149 switch (device_id
>> 16) {
1151 snprintf(buf
, buf_size
, "A");
1155 snprintf(buf
, buf_size
, "unknown");
1158 } else if ((device_id
& 0xfff) == 0x432) {
1159 printed
= snprintf(buf
, buf_size
, "stm32f37x - Rev: ");
1161 buf_size
-= printed
;
1163 switch (device_id
>> 16) {
1165 snprintf(buf
, buf_size
, "A");
1169 snprintf(buf
, buf_size
, "B");
1173 snprintf(buf
, buf_size
, "unknown");
1176 } else if ((device_id
& 0xfff) == 0x440) {
1177 printed
= snprintf(buf
, buf_size
, "stm32f0x - Rev: ");
1179 buf_size
-= printed
;
1181 switch (device_id
>> 16) {
1183 snprintf(buf
, buf_size
, "1.0");
1187 snprintf(buf
, buf_size
, "2.0");
1191 snprintf(buf
, buf_size
, "unknown");
1195 snprintf(buf
, buf_size
, "Cannot identify target as a stm32x\n");
1202 COMMAND_HANDLER(stm32x_handle_lock_command
)
1204 struct target
*target
= NULL
;
1205 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1208 return ERROR_COMMAND_SYNTAX_ERROR
;
1210 struct flash_bank
*bank
;
1211 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1212 if (ERROR_OK
!= retval
)
1215 stm32x_info
= bank
->driver_priv
;
1217 target
= bank
->target
;
1219 if (target
->state
!= TARGET_HALTED
) {
1220 LOG_ERROR("Target not halted");
1221 return ERROR_TARGET_NOT_HALTED
;
1224 retval
= stm32x_check_operation_supported(bank
);
1225 if (ERROR_OK
!= retval
)
1228 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1229 command_print(CMD_CTX
, "stm32x failed to erase options");
1233 /* set readout protection */
1234 stm32x_info
->option_bytes
.RDP
= 0;
1236 if (stm32x_write_options(bank
) != ERROR_OK
) {
1237 command_print(CMD_CTX
, "stm32x failed to lock device");
1241 command_print(CMD_CTX
, "stm32x locked");
1246 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1248 struct target
*target
= NULL
;
1251 return ERROR_COMMAND_SYNTAX_ERROR
;
1253 struct flash_bank
*bank
;
1254 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1255 if (ERROR_OK
!= retval
)
1258 target
= bank
->target
;
1260 if (target
->state
!= TARGET_HALTED
) {
1261 LOG_ERROR("Target not halted");
1262 return ERROR_TARGET_NOT_HALTED
;
1265 retval
= stm32x_check_operation_supported(bank
);
1266 if (ERROR_OK
!= retval
)
1269 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1270 command_print(CMD_CTX
, "stm32x failed to unlock device");
1274 if (stm32x_write_options(bank
) != ERROR_OK
) {
1275 command_print(CMD_CTX
, "stm32x failed to lock device");
1279 command_print(CMD_CTX
, "stm32x unlocked.\n"
1280 "INFO: a reset or power cycle is required "
1281 "for the new settings to take effect.");
1286 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1288 uint32_t optionbyte
;
1289 struct target
*target
= NULL
;
1290 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1293 return ERROR_COMMAND_SYNTAX_ERROR
;
1295 struct flash_bank
*bank
;
1296 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1297 if (ERROR_OK
!= retval
)
1300 stm32x_info
= bank
->driver_priv
;
1302 target
= bank
->target
;
1304 if (target
->state
!= TARGET_HALTED
) {
1305 LOG_ERROR("Target not halted");
1306 return ERROR_TARGET_NOT_HALTED
;
1309 retval
= stm32x_check_operation_supported(bank
);
1310 if (ERROR_OK
!= retval
)
1313 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1314 if (retval
!= ERROR_OK
)
1316 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1318 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_ERROR
, 1))
1319 command_print(CMD_CTX
, "Option Byte Complement Error");
1321 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_READOUT
, 1))
1322 command_print(CMD_CTX
, "Readout Protection On");
1324 command_print(CMD_CTX
, "Readout Protection Off");
1326 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDWDGSW
, 1))
1327 command_print(CMD_CTX
, "Software Watchdog");
1329 command_print(CMD_CTX
, "Hardware Watchdog");
1331 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTOP
, 1))
1332 command_print(CMD_CTX
, "Stop: No reset generated");
1334 command_print(CMD_CTX
, "Stop: Reset generated");
1336 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTDBY
, 1))
1337 command_print(CMD_CTX
, "Standby: No reset generated");
1339 command_print(CMD_CTX
, "Standby: Reset generated");
1341 if (stm32x_info
->has_dual_banks
) {
1342 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_BFB2
, 1))
1343 command_print(CMD_CTX
, "Boot: Bank 0");
1345 command_print(CMD_CTX
, "Boot: Bank 1");
1348 command_print(CMD_CTX
, "User Option0: 0x%02" PRIx8
,
1349 (optionbyte
>> stm32x_info
->user_data_offset
) & 0xff);
1350 command_print(CMD_CTX
, "User Option1: 0x%02" PRIx8
,
1351 (optionbyte
>> (stm32x_info
->user_data_offset
+ 8)) & 0xff);
1356 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1358 struct target
*target
= NULL
;
1359 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1360 uint16_t optionbyte
= 0xF8;
1363 return ERROR_COMMAND_SYNTAX_ERROR
;
1365 struct flash_bank
*bank
;
1366 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1367 if (ERROR_OK
!= retval
)
1370 stm32x_info
= bank
->driver_priv
;
1372 target
= bank
->target
;
1374 if (target
->state
!= TARGET_HALTED
) {
1375 LOG_ERROR("Target not halted");
1376 return ERROR_TARGET_NOT_HALTED
;
1379 retval
= stm32x_check_operation_supported(bank
);
1380 if (ERROR_OK
!= retval
)
1383 /* REVISIT: ignores some options which we will display...
1384 * and doesn't insist on the specified syntax.
1388 if (strcmp(CMD_ARGV
[1], "SWWDG") == 0)
1389 optionbyte
|= (1 << 0);
1390 else /* REVISIT must be "HWWDG" then ... */
1391 optionbyte
&= ~(1 << 0);
1394 if (strcmp(CMD_ARGV
[2], "NORSTSTOP") == 0)
1395 optionbyte
|= (1 << 1);
1396 else /* REVISIT must be "RSTSTNDBY" then ... */
1397 optionbyte
&= ~(1 << 1);
1399 /* OPT_RDRSTSTDBY */
1400 if (strcmp(CMD_ARGV
[3], "NORSTSTNDBY") == 0)
1401 optionbyte
|= (1 << 2);
1402 else /* REVISIT must be "RSTSTOP" then ... */
1403 optionbyte
&= ~(1 << 2);
1405 if (CMD_ARGC
> 4 && stm32x_info
->has_dual_banks
) {
1407 if (strcmp(CMD_ARGV
[4], "BOOT0") == 0)
1408 optionbyte
|= (1 << 3);
1410 optionbyte
&= ~(1 << 3);
1413 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1414 command_print(CMD_CTX
, "stm32x failed to erase options");
1418 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1420 if (stm32x_write_options(bank
) != ERROR_OK
) {
1421 command_print(CMD_CTX
, "stm32x failed to write options");
1425 command_print(CMD_CTX
, "stm32x write options complete.\n"
1426 "INFO: a reset or power cycle is required "
1427 "for the new settings to take effect.");
1432 static int stm32x_mass_erase(struct flash_bank
*bank
)
1434 struct target
*target
= bank
->target
;
1436 if (target
->state
!= TARGET_HALTED
) {
1437 LOG_ERROR("Target not halted");
1438 return ERROR_TARGET_NOT_HALTED
;
1441 /* unlock option flash registers */
1442 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1443 if (retval
!= ERROR_OK
)
1445 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1446 if (retval
!= ERROR_OK
)
1449 /* mass erase flash memory */
1450 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1451 if (retval
!= ERROR_OK
)
1453 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1454 FLASH_MER
| FLASH_STRT
);
1455 if (retval
!= ERROR_OK
)
1458 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1459 if (retval
!= ERROR_OK
)
1462 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1463 if (retval
!= ERROR_OK
)
1469 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1474 return ERROR_COMMAND_SYNTAX_ERROR
;
1476 struct flash_bank
*bank
;
1477 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1478 if (ERROR_OK
!= retval
)
1481 retval
= stm32x_mass_erase(bank
);
1482 if (retval
== ERROR_OK
) {
1483 /* set all sectors as erased */
1484 for (i
= 0; i
< bank
->num_sectors
; i
++)
1485 bank
->sectors
[i
].is_erased
= 1;
1487 command_print(CMD_CTX
, "stm32x mass erase complete");
1489 command_print(CMD_CTX
, "stm32x mass erase failed");
1494 static const struct command_registration stm32x_exec_command_handlers
[] = {
1497 .handler
= stm32x_handle_lock_command
,
1498 .mode
= COMMAND_EXEC
,
1500 .help
= "Lock entire flash device.",
1504 .handler
= stm32x_handle_unlock_command
,
1505 .mode
= COMMAND_EXEC
,
1507 .help
= "Unlock entire protected flash device.",
1510 .name
= "mass_erase",
1511 .handler
= stm32x_handle_mass_erase_command
,
1512 .mode
= COMMAND_EXEC
,
1514 .help
= "Erase entire flash device.",
1517 .name
= "options_read",
1518 .handler
= stm32x_handle_options_read_command
,
1519 .mode
= COMMAND_EXEC
,
1521 .help
= "Read and display device option byte.",
1524 .name
= "options_write",
1525 .handler
= stm32x_handle_options_write_command
,
1526 .mode
= COMMAND_EXEC
,
1527 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1528 "('RSTSTNDBY'|'NORSTSTNDBY') "
1529 "('RSTSTOP'|'NORSTSTOP')",
1530 .help
= "Replace bits in device option byte.",
1532 COMMAND_REGISTRATION_DONE
1535 static const struct command_registration stm32x_command_handlers
[] = {
1538 .mode
= COMMAND_ANY
,
1539 .help
= "stm32f1x flash command group",
1541 .chain
= stm32x_exec_command_handlers
,
1543 COMMAND_REGISTRATION_DONE
1546 struct flash_driver stm32f1x_flash
= {
1548 .commands
= stm32x_command_handlers
,
1549 .flash_bank_command
= stm32x_flash_bank_command
,
1550 .erase
= stm32x_erase
,
1551 .protect
= stm32x_protect
,
1552 .write
= stm32x_write
,
1553 .read
= default_flash_read
,
1554 .probe
= stm32x_probe
,
1555 .auto_probe
= stm32x_auto_probe
,
1556 .erase_check
= default_flash_blank_check
,
1557 .protect_check
= stm32x_protect_check
,
1558 .info
= get_stm32x_info
,