src/jtag/drivers/ep93xx.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include <jtag/interface.h>
  26 #include "bitbang.h"
  27
  28 #define TDO_BIT         1
  29 #define TDI_BIT         2
  30 #define TCK_BIT         4
  31 #define TMS_BIT         8
  32 #define TRST_BIT        16
  33 #define SRST_BIT        32
  34 #define VCC_BIT         64
  35
  36 #include <sys/mman.h>
  37
  38 static uint8_t output_value;
  39 static int dev_mem_fd;
  40 static void *gpio_controller;
  41 static volatile uint8_t *gpio_data_register;
  42 static volatile uint8_t *gpio_data_direction_register;
  43
  44 /* low level command set
  45  */
  46 static int ep93xx_read(void);
  47 static void ep93xx_write(int tck, int tms, int tdi);
  48 static void ep93xx_reset(int trst, int srst);
  49
  50 static int ep93xx_speed(int speed);
  51 static int ep93xx_init(void);
  52 static int ep93xx_quit(void);
  53
  54 struct timespec ep93xx_zzzz;
  55
  56 struct jtag_interface ep93xx_interface = {
  57         .name = "ep93xx",
  58
  59         .supported = DEBUG_CAP_TMS_SEQ,
  60         .execute_queue = bitbang_execute_queue,
  61
  62         .speed = ep93xx_speed,
  63         .init = ep93xx_init,
  64         .quit = ep93xx_quit,
  65 };
  66
  67 static struct bitbang_interface ep93xx_bitbang = {
  68         .read = ep93xx_read,
  69         .write = ep93xx_write,
  70         .reset = ep93xx_reset,
  71         .blink = 0,
  72 };
  73
  74 static int ep93xx_read(void)
  75 {
  76         return !!(*gpio_data_register & TDO_BIT);
  77 }
  78
  79 static void ep93xx_write(int tck, int tms, int tdi)
  80 {
  81         if (tck)
  82                 output_value |= TCK_BIT;
  83         else
  84                 output_value &= ~TCK_BIT;
  85
  86         if (tms)
  87                 output_value |= TMS_BIT;
  88         else
  89                 output_value &= ~TMS_BIT;
  90
  91         if (tdi)
  92                 output_value |= TDI_BIT;
  93         else
  94                 output_value &= ~TDI_BIT;
  95
  96         *gpio_data_register = output_value;
  97         nanosleep(&ep93xx_zzzz, NULL);
  98 }
  99
 100 /* (1) assert or (0) deassert reset lines */
 101 static void ep93xx_reset(int trst, int srst)
 102 {
 103         if (trst == 0)
 104                 output_value |= TRST_BIT;
 105         else if (trst == 1)
 106                 output_value &= ~TRST_BIT;
 107
 108         if (srst == 0)
 109                 output_value |= SRST_BIT;
 110         else if (srst == 1)
 111                 output_value &= ~SRST_BIT;
 112
 113         *gpio_data_register = output_value;
 114         nanosleep(&ep93xx_zzzz, NULL);
 115 }
 116
 117 static int ep93xx_speed(int speed)
 118 {
 119
 120         return ERROR_OK;
 121 }
 122
 123 static int set_gonk_mode(void)
 124 {
 125         void *syscon;
 126         uint32_t devicecfg;
 127
 128         syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 129                         MAP_SHARED, dev_mem_fd, 0x80930000);
 130         if (syscon == MAP_FAILED) {
 131                 perror("mmap");
 132                 return ERROR_JTAG_INIT_FAILED;
 133         }
 134
 135         devicecfg = *((volatile int *)(syscon + 0x80));
 136         *((volatile int *)(syscon + 0xc0)) = 0xaa;
 137         *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
 138
 139         munmap(syscon, 4096);
 140
 141         return ERROR_OK;
 142 }
 143
 144 static int ep93xx_init(void)
 145 {
 146         int ret;
 147
 148         bitbang_interface = &ep93xx_bitbang;
 149
 150         ep93xx_zzzz.tv_sec = 0;
 151         ep93xx_zzzz.tv_nsec = 10000000;
 152
 153         dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
 154         if (dev_mem_fd < 0) {
 155                 perror("open");
 156                 return ERROR_JTAG_INIT_FAILED;
 157         }
 158
 159         gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
 160                                 MAP_SHARED, dev_mem_fd, 0x80840000);
 161         if (gpio_controller == MAP_FAILED) {
 162                 perror("mmap");
 163                 close(dev_mem_fd);
 164                 return ERROR_JTAG_INIT_FAILED;
 165         }
 166
 167         ret = set_gonk_mode();
 168         if (ret != ERROR_OK) {
 169                 munmap(gpio_controller, 4096);
 170                 close(dev_mem_fd);
 171                 return ret;
 172         }
 173
 174 #if 0
 175         /* Use GPIO port A.  */
 176         gpio_data_register = gpio_controller + 0x00;
 177         gpio_data_direction_register = gpio_controller + 0x10;
 178
 179
 180         /* Use GPIO port B.  */
 181         gpio_data_register = gpio_controller + 0x04;
 182         gpio_data_direction_register = gpio_controller + 0x14;
 183
 184         /* Use GPIO port C.  */
 185         gpio_data_register = gpio_controller + 0x08;
 186         gpio_data_direction_register = gpio_controller + 0x18;
 187
 188         /* Use GPIO port D.  */
 189         gpio_data_register = gpio_controller + 0x0c;
 190         gpio_data_direction_register = gpio_controller + 0x1c;
 191 #endif
 192
 193         /* Use GPIO port C.  */
 194         gpio_data_register = gpio_controller + 0x08;
 195         gpio_data_direction_register = gpio_controller + 0x18;
 196
 197         LOG_INFO("gpio_data_register      = %p", gpio_data_register);
 198         LOG_INFO("gpio_data_direction_reg = %p", gpio_data_direction_register);
 199         /*
 200          * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
 201          * TMS, TRST, SRST) as outputs.  Drive TDI and TCK low, and
 202          * TMS/TRST/SRST high.
 203          */
 204         output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 205         *gpio_data_register = output_value;
 206         nanosleep(&ep93xx_zzzz, NULL);
 207
 208         /*
 209          * Configure the direction register.  1 = output, 0 = input.
 210          */
 211         *gpio_data_direction_register =
 212                 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
 213
 214         nanosleep(&ep93xx_zzzz, NULL);
 215         return ERROR_OK;
 216 }
 217
 218 static int ep93xx_quit(void)
 219 {
 220
 221         return ERROR_OK;
 222 }