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74505a85e1b669168640eaae4cf0ec7fa1f8b9c3
[openocd.git] / src / target / cortex_m.c
blob74505a85e1b669168640eaae4cf0ec7fa1f8b9c3
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 * *
26 * *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
28 * *
29 ***************************************************************************/
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
36 #include "cortex_m.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
40 #include "register.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
44
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
50 *
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
53 * any longer.
54 */
55
56 /**
57 * Returns the type of a break point required by address location
58 */
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
60
61
62 /* forward declarations */
63 static int cortex_m3_store_core_reg_u32(struct target *target,
64 enum armv7m_regtype type, uint32_t num, uint32_t value);
65
66 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
67 uint32_t *value, int regnum)
68 {
69 int retval;
70 uint32_t dcrdr;
71
72 /* because the DCB_DCRDR is used for the emulated dcc channel
73 * we have to save/restore the DCB_DCRDR when used */
74
75 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
76 if (retval != ERROR_OK)
77 return retval;
78
79 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
80 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
81 if (retval != ERROR_OK)
82 return retval;
83 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
84 if (retval != ERROR_OK)
85 return retval;
86
87 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
88 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
89 if (retval != ERROR_OK)
90 return retval;
91 retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
92 if (retval != ERROR_OK)
93 return retval;
94
95 retval = dap_run(swjdp);
96 if (retval != ERROR_OK)
97 return retval;
98
99 /* restore DCB_DCRDR - this needs to be in a seperate
100 * transaction otherwise the emulated DCC channel breaks */
101 if (retval == ERROR_OK)
102 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
103
104 return retval;
105 }
106
107 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
108 uint32_t value, int regnum)
109 {
110 int retval;
111 uint32_t dcrdr;
112
113 /* because the DCB_DCRDR is used for the emulated dcc channel
114 * we have to save/restore the DCB_DCRDR when used */
115
116 retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
117 if (retval != ERROR_OK)
118 return retval;
119
120 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
121 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
122 if (retval != ERROR_OK)
123 return retval;
124 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
125 if (retval != ERROR_OK)
126 return retval;
127
128 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
129 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
130 if (retval != ERROR_OK)
131 return retval;
132 retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
133 if (retval != ERROR_OK)
134 return retval;
135
136 retval = dap_run(swjdp);
137 if (retval != ERROR_OK)
138 return retval;
139
140 /* restore DCB_DCRDR - this needs to be in a seperate
141 * transaction otherwise the emulated DCC channel breaks */
142 if (retval == ERROR_OK)
143 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
144
145 return retval;
146 }
147
148 static int cortex_m3_write_debug_halt_mask(struct target *target,
149 uint32_t mask_on, uint32_t mask_off)
150 {
151 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
152 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
153
154 /* mask off status bits */
155 cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
156 /* create new register mask */
157 cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
158
159 return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
160 }
161
162 static int cortex_m3_clear_halt(struct target *target)
163 {
164 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
165 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
166 int retval;
167
168 /* clear step if any */
169 cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
170
171 /* Read Debug Fault Status Register */
172 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
173 if (retval != ERROR_OK)
174 return retval;
175
176 /* Clear Debug Fault Status */
177 retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
181
182 return ERROR_OK;
183 }
184
185 static int cortex_m3_single_step_core(struct target *target)
186 {
187 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
188 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
189 uint32_t dhcsr_save;
190 int retval;
191
192 /* backup dhcsr reg */
193 dhcsr_save = cortex_m3->dcb_dhcsr;
194
195 /* Mask interrupts before clearing halt, if done already. This avoids
196 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
197 * HALT can put the core into an unknown state.
198 */
199 if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) {
200 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
201 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
202 if (retval != ERROR_OK)
203 return retval;
204 }
205 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
206 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
207 if (retval != ERROR_OK)
208 return retval;
209 LOG_DEBUG(" ");
210
211 /* restore dhcsr reg */
212 cortex_m3->dcb_dhcsr = dhcsr_save;
213 cortex_m3_clear_halt(target);
214
215 return ERROR_OK;
216 }
217
218 static int cortex_m3_endreset_event(struct target *target)
219 {
220 int i;
221 int retval;
222 uint32_t dcb_demcr;
223 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
224 struct armv7m_common *armv7m = &cortex_m3->armv7m;
225 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
226 struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
227 struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
228
229 /* REVISIT The four debug monitor bits are currently ignored... */
230 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
231 if (retval != ERROR_OK)
232 return retval;
233 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
234
235 /* this register is used for emulated dcc channel */
236 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
237 if (retval != ERROR_OK)
238 return retval;
239
240 /* Enable debug requests */
241 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
242 if (retval != ERROR_OK)
243 return retval;
244 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) {
245 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
246 if (retval != ERROR_OK)
247 return retval;
248 }
249
250 /* clear any interrupt masking */
251 cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
252
253 /* Enable features controlled by ITM and DWT blocks, and catch only
254 * the vectors we were told to pay attention to.
255 *
256 * Target firmware is responsible for all fault handling policy
257 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
258 * or manual updates to the NVIC SHCSR and CCR registers.
259 */
260 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
261 if (retval != ERROR_OK)
262 return retval;
263
264 /* Paranoia: evidently some (early?) chips don't preserve all the
265 * debug state (including FBP, DWT, etc) across reset...
266 */
267
268 /* Enable FPB */
269 retval = target_write_u32(target, FP_CTRL, 3);
270 if (retval != ERROR_OK)
271 return retval;
272
273 cortex_m3->fpb_enabled = 1;
274
275 /* Restore FPB registers */
276 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) {
277 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
278 if (retval != ERROR_OK)
279 return retval;
280 }
281
282 /* Restore DWT registers */
283 for (i = 0; i < cortex_m3->dwt_num_comp; i++) {
284 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
285 dwt_list[i].comp);
286 if (retval != ERROR_OK)
287 return retval;
288 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
289 dwt_list[i].mask);
290 if (retval != ERROR_OK)
291 return retval;
292 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
293 dwt_list[i].function);
294 if (retval != ERROR_OK)
295 return retval;
296 }
297 retval = dap_run(swjdp);
298 if (retval != ERROR_OK)
299 return retval;
300
301 register_cache_invalidate(cortex_m3->armv7m.core_cache);
302
303 /* make sure we have latest dhcsr flags */
304 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
305
306 return retval;
307 }
308
309 static int cortex_m3_examine_debug_reason(struct target *target)
310 {
311 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
312
313 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
314 * only check the debug reason if we don't know it already */
315
316 if ((target->debug_reason != DBG_REASON_DBGRQ)
317 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
318 if (cortex_m3->nvic_dfsr & DFSR_BKPT) {
319 target->debug_reason = DBG_REASON_BREAKPOINT;
320 if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
321 target->debug_reason = DBG_REASON_WPTANDBKPT;
322 } else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
323 target->debug_reason = DBG_REASON_WATCHPOINT;
324 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
325 target->debug_reason = DBG_REASON_BREAKPOINT;
326 else /* EXTERNAL, HALTED */
327 target->debug_reason = DBG_REASON_UNDEFINED;
328 }
329
330 return ERROR_OK;
331 }
332
333 static int cortex_m3_examine_exception_reason(struct target *target)
334 {
335 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
336 struct armv7m_common *armv7m = target_to_armv7m(target);
337 struct adiv5_dap *swjdp = armv7m->arm.dap;
338 int retval;
339
340 retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
341 if (retval != ERROR_OK)
342 return retval;
343 switch (armv7m->exception_number) {
344 case 2: /* NMI */
345 break;
346 case 3: /* Hard Fault */
347 retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
348 if (retval != ERROR_OK)
349 return retval;
350 if (except_sr & 0x40000000) {
351 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
352 if (retval != ERROR_OK)
353 return retval;
354 }
355 break;
356 case 4: /* Memory Management */
357 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
358 if (retval != ERROR_OK)
359 return retval;
360 retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
361 if (retval != ERROR_OK)
362 return retval;
363 break;
364 case 5: /* Bus Fault */
365 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
366 if (retval != ERROR_OK)
367 return retval;
368 retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
369 if (retval != ERROR_OK)
370 return retval;
371 break;
372 case 6: /* Usage Fault */
373 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
374 if (retval != ERROR_OK)
375 return retval;
376 break;
377 case 11: /* SVCall */
378 break;
379 case 12: /* Debug Monitor */
380 retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
381 if (retval != ERROR_OK)
382 return retval;
383 break;
384 case 14: /* PendSV */
385 break;
386 case 15: /* SysTick */
387 break;
388 default:
389 except_sr = 0;
390 break;
391 }
392 retval = dap_run(swjdp);
393 if (retval == ERROR_OK)
394 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
395 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
396 armv7m_exception_string(armv7m->exception_number),
397 shcsr, except_sr, cfsr, except_ar);
398 return retval;
399 }
400
401 static int cortex_m3_debug_entry(struct target *target)
402 {
403 int i;
404 uint32_t xPSR;
405 int retval;
406 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
407 struct armv7m_common *armv7m = &cortex_m3->armv7m;
408 struct arm *arm = &armv7m->arm;
409 struct adiv5_dap *swjdp = armv7m->arm.dap;
410 struct reg *r;
411
412 LOG_DEBUG(" ");
413
414 cortex_m3_clear_halt(target);
415 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
416 if (retval != ERROR_OK)
417 return retval;
418
419 retval = armv7m->examine_debug_reason(target);
420 if (retval != ERROR_OK)
421 return retval;
422
423 /* Examine target state and mode
424 * First load register acessible through core debug port*/
425 int num_regs = armv7m->core_cache->num_regs;
426
427 for (i = 0; i < num_regs; i++) {
428 if (!armv7m->core_cache->reg_list[i].valid)
429 armv7m->read_core_reg(target, i);
430 }
431
432 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
433 xPSR = buf_get_u32(r->value, 0, 32);
434
435 #ifdef ARMV7_GDB_HACKS
436 /* FIXME this breaks on scan chains with more than one Cortex-M3.
437 * Instead, each CM3 should have its own dummy value...
438 */
439 /* copy real xpsr reg for gdb, setting thumb bit */
440 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
441 buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
442 armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
443 armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
444 #endif
445
446 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
447 if (xPSR & 0xf00) {
448 r->dirty = r->valid;
449 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR & ~0xff);
450 }
451
452 /* Are we in an exception handler */
453 if (xPSR & 0x1FF) {
454 armv7m->core_mode = ARMV7M_MODE_HANDLER;
455 armv7m->exception_number = (xPSR & 0x1FF);
456
457 arm->core_mode = ARM_MODE_HANDLER;
458 arm->map = armv7m_msp_reg_map;
459 } else {
460 unsigned control = buf_get_u32(armv7m->core_cache
461 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
462
463 /* is this thread privileged? */
464 armv7m->core_mode = control & 1;
465 arm->core_mode = armv7m->core_mode
466 ? ARM_MODE_USER_THREAD
467 : ARM_MODE_THREAD;
468
469 /* which stack is it using? */
470 if (control & 2)
471 arm->map = armv7m_psp_reg_map;
472 else
473 arm->map = armv7m_msp_reg_map;
474
475 armv7m->exception_number = 0;
476 }
477
478 if (armv7m->exception_number)
479 cortex_m3_examine_exception_reason(target);
480
481 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
482 armv7m_mode_strings[armv7m->core_mode],
483 *(uint32_t *)(arm->pc->value),
484 target_state_name(target));
485
486 if (armv7m->post_debug_entry) {
487 retval = armv7m->post_debug_entry(target);
488 if (retval != ERROR_OK)
489 return retval;
490 }
491
492 return ERROR_OK;
493 }
494
495 static int cortex_m3_poll(struct target *target)
496 {
497 int detected_failure = ERROR_OK;
498 int retval = ERROR_OK;
499 enum target_state prev_target_state = target->state;
500 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
501 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
502
503 /* Read from Debug Halting Control and Status Register */
504 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
505 if (retval != ERROR_OK) {
506 target->state = TARGET_UNKNOWN;
507 return retval;
508 }
509
510 /* Recover from lockup. See ARMv7-M architecture spec,
511 * section B1.5.15 "Unrecoverable exception cases".
512 */
513 if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
514 LOG_ERROR("%s -- clearing lockup after double fault",
515 target_name(target));
516 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
517 target->debug_reason = DBG_REASON_DBGRQ;
518
519 /* We have to execute the rest (the "finally" equivalent, but
520 * still throw this exception again).
521 */
522 detected_failure = ERROR_FAIL;
523
524 /* refresh status bits */
525 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
526 if (retval != ERROR_OK)
527 return retval;
528 }
529
530 if (cortex_m3->dcb_dhcsr & S_RESET_ST) {
531 /* check if still in reset */
532 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
533 if (retval != ERROR_OK)
534 return retval;
535
536 if (cortex_m3->dcb_dhcsr & S_RESET_ST) {
537 target->state = TARGET_RESET;
538 return ERROR_OK;
539 }
540 }
541
542 if (target->state == TARGET_RESET) {
543 /* Cannot switch context while running so endreset is
544 * called with target->state == TARGET_RESET
545 */
546 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
547 cortex_m3->dcb_dhcsr);
548 cortex_m3_endreset_event(target);
549 target->state = TARGET_RUNNING;
550 prev_target_state = TARGET_RUNNING;
551 }
552
553 if (cortex_m3->dcb_dhcsr & S_HALT) {
554 target->state = TARGET_HALTED;
555
556 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
557 retval = cortex_m3_debug_entry(target);
558 if (retval != ERROR_OK)
559 return retval;
560
561 if (arm_semihosting(target, &retval) != 0)
562 return retval;
563
564 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
565 }
566 if (prev_target_state == TARGET_DEBUG_RUNNING) {
567 LOG_DEBUG(" ");
568 retval = cortex_m3_debug_entry(target);
569 if (retval != ERROR_OK)
570 return retval;
571
572 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
573 }
574 }
575
576 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
577 * How best to model low power modes?
578 */
579
580 if (target->state == TARGET_UNKNOWN) {
581 /* check if processor is retiring instructions */
582 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) {
583 target->state = TARGET_RUNNING;
584 retval = ERROR_OK;
585 }
586 }
587
588 /* Did we detect a failure condition that we cleared? */
589 if (detected_failure != ERROR_OK)
590 retval = detected_failure;
591 return retval;
592 }
593
594 static int cortex_m3_halt(struct target *target)
595 {
596 LOG_DEBUG("target->state: %s",
597 target_state_name(target));
598
599 if (target->state == TARGET_HALTED) {
600 LOG_DEBUG("target was already halted");
601 return ERROR_OK;
602 }
603
604 if (target->state == TARGET_UNKNOWN)
605 LOG_WARNING("target was in unknown state when halt was requested");
606
607 if (target->state == TARGET_RESET) {
608 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
609 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
610 return ERROR_TARGET_FAILURE;
611 } else {
612 /* we came here in a reset_halt or reset_init sequence
613 * debug entry was already prepared in cortex_m3_assert_reset()
614 */
615 target->debug_reason = DBG_REASON_DBGRQ;
616
617 return ERROR_OK;
618 }
619 }
620
621 /* Write to Debug Halting Control and Status Register */
622 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
623
624 target->debug_reason = DBG_REASON_DBGRQ;
625
626 return ERROR_OK;
627 }
628
629 static int cortex_m3_soft_reset_halt(struct target *target)
630 {
631 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
632 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
633 uint32_t dcb_dhcsr = 0;
634 int retval, timeout = 0;
635
636 /* Enter debug state on reset; restore DEMCR in endreset_event() */
637 retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
638 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
639 if (retval != ERROR_OK)
640 return retval;
641
642 /* Request a core-only reset */
643 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
644 AIRCR_VECTKEY | AIRCR_VECTRESET);
645 if (retval != ERROR_OK)
646 return retval;
647 target->state = TARGET_RESET;
648
649 /* registers are now invalid */
650 register_cache_invalidate(cortex_m3->armv7m.core_cache);
651
652 while (timeout < 100) {
653 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
654 if (retval == ERROR_OK) {
655 retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
656 &cortex_m3->nvic_dfsr);
657 if (retval != ERROR_OK)
658 return retval;
659 if ((dcb_dhcsr & S_HALT)
660 && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) {
661 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
662 "DFSR 0x%08x",
663 (unsigned) dcb_dhcsr,
664 (unsigned) cortex_m3->nvic_dfsr);
665 cortex_m3_poll(target);
666 /* FIXME restore user's vector catch config */
667 return ERROR_OK;
668 } else
669 LOG_DEBUG("waiting for system reset-halt, "
670 "DHCSR 0x%08x, %d ms",
671 (unsigned) dcb_dhcsr, timeout);
672 }
673 timeout++;
674 alive_sleep(1);
675 }
676
677 return ERROR_OK;
678 }
679
680 static void cortex_m3_enable_breakpoints(struct target *target)
681 {
682 struct breakpoint *breakpoint = target->breakpoints;
683
684 /* set any pending breakpoints */
685 while (breakpoint) {
686 if (!breakpoint->set)
687 cortex_m3_set_breakpoint(target, breakpoint);
688 breakpoint = breakpoint->next;
689 }
690 }
691
692 static int cortex_m3_resume(struct target *target, int current,
693 uint32_t address, int handle_breakpoints, int debug_execution)
694 {
695 struct armv7m_common *armv7m = target_to_armv7m(target);
696 struct breakpoint *breakpoint = NULL;
697 uint32_t resume_pc;
698 struct reg *r;
699
700 if (target->state != TARGET_HALTED) {
701 LOG_WARNING("target not halted");
702 return ERROR_TARGET_NOT_HALTED;
703 }
704
705 if (!debug_execution) {
706 target_free_all_working_areas(target);
707 cortex_m3_enable_breakpoints(target);
708 cortex_m3_enable_watchpoints(target);
709 }
710
711 if (debug_execution) {
712 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
713
714 /* Disable interrupts */
715 /* We disable interrupts in the PRIMASK register instead of
716 * masking with C_MASKINTS. This is probably the same issue
717 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
718 * in parallel with disabled interrupts can cause local faults
719 * to not be taken.
720 *
721 * REVISIT this clearly breaks non-debug execution, since the
722 * PRIMASK register state isn't saved/restored... workaround
723 * by never resuming app code after debug execution.
724 */
725 buf_set_u32(r->value, 0, 1, 1);
726 r->dirty = true;
727 r->valid = true;
728
729 /* Make sure we are in Thumb mode */
730 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
731 buf_set_u32(r->value, 24, 1, 1);
732 r->dirty = true;
733 r->valid = true;
734 }
735
736 /* current = 1: continue on current pc, otherwise continue at <address> */
737 r = armv7m->arm.pc;
738 if (!current) {
739 buf_set_u32(r->value, 0, 32, address);
740 r->dirty = true;
741 r->valid = true;
742 }
743
744 /* if we halted last time due to a bkpt instruction
745 * then we have to manually step over it, otherwise
746 * the core will break again */
747
748 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
749 && !debug_execution)
750 armv7m_maybe_skip_bkpt_inst(target, NULL);
751
752 resume_pc = buf_get_u32(r->value, 0, 32);
753
754 armv7m_restore_context(target);
755
756 /* the front-end may request us not to handle breakpoints */
757 if (handle_breakpoints) {
758 /* Single step past breakpoint at current address */
759 breakpoint = breakpoint_find(target, resume_pc);
760 if (breakpoint) {
761 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
762 breakpoint->address,
763 breakpoint->unique_id);
764 cortex_m3_unset_breakpoint(target, breakpoint);
765 cortex_m3_single_step_core(target);
766 cortex_m3_set_breakpoint(target, breakpoint);
767 }
768 }
769
770 /* Restart core */
771 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
772
773 target->debug_reason = DBG_REASON_NOTHALTED;
774
775 /* registers are now invalid */
776 register_cache_invalidate(armv7m->core_cache);
777
778 if (!debug_execution) {
779 target->state = TARGET_RUNNING;
780 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
781 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
782 } else {
783 target->state = TARGET_DEBUG_RUNNING;
784 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
785 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
786 }
787
788 return ERROR_OK;
789 }
790
791 /* int irqstepcount = 0; */
792 static int cortex_m3_step(struct target *target, int current,
793 uint32_t address, int handle_breakpoints)
794 {
795 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
796 struct armv7m_common *armv7m = &cortex_m3->armv7m;
797 struct adiv5_dap *swjdp = armv7m->arm.dap;
798 struct breakpoint *breakpoint = NULL;
799 struct reg *pc = armv7m->arm.pc;
800 bool bkpt_inst_found = false;
801 int retval;
802 bool isr_timed_out = false;
803
804 if (target->state != TARGET_HALTED) {
805 LOG_WARNING("target not halted");
806 return ERROR_TARGET_NOT_HALTED;
807 }
808
809 /* current = 1: continue on current pc, otherwise continue at <address> */
810 if (!current)
811 buf_set_u32(pc->value, 0, 32, address);
812
813 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
814
815 /* the front-end may request us not to handle breakpoints */
816 if (handle_breakpoints) {
817 breakpoint = breakpoint_find(target, pc_value);
818 if (breakpoint)
819 cortex_m3_unset_breakpoint(target, breakpoint);
820 }
821
822 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
823
824 target->debug_reason = DBG_REASON_SINGLESTEP;
825
826 armv7m_restore_context(target);
827
828 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
829
830 /* if no bkpt instruction is found at pc then we can perform
831 * a normal step, otherwise we have to manually step over the bkpt
832 * instruction - as such simulate a step */
833 if (bkpt_inst_found == false) {
834 /* Automatic ISR masking mode off: Just step over the next instruction */
835 if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO))
836 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
837 else {
838 /* Process interrupts during stepping in a way they don't interfere
839 * debugging.
840 *
841 * Principle:
842 *
843 * Set a temporary break point at the current pc and let the core run
844 * with interrupts enabled. Pending interrupts get served and we run
845 * into the breakpoint again afterwards. Then we step over the next
846 * instruction with interrupts disabled.
847 *
848 * If the pending interrupts don't complete within time, we leave the
849 * core running. This may happen if the interrupts trigger faster
850 * than the core can process them or the handler doesn't return.
851 *
852 * If no more breakpoints are available we simply do a step with
853 * interrupts enabled.
854 *
855 */
856
857 /* Set a temporary break point */
858 retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
859 bool tmp_bp_set = (retval == ERROR_OK);
860
861 /* No more breakpoints left, just do a step */
862 if (!tmp_bp_set)
863 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
864 else {
865 /* Start the core */
866 LOG_DEBUG("Starting core to serve pending interrupts");
867 int64_t t_start = timeval_ms();
868 cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
869
870 /* Wait for pending handlers to complete or timeout */
871 do {
872 retval = mem_ap_read_atomic_u32(swjdp,
873 DCB_DHCSR,
874 &cortex_m3->dcb_dhcsr);
875 if (retval != ERROR_OK) {
876 target->state = TARGET_UNKNOWN;
877 return retval;
878 }
879 isr_timed_out = ((timeval_ms() - t_start) > 500);
880 } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
881
882 /* Remove the temporary breakpoint */
883 breakpoint_remove(target, pc_value);
884
885 if (isr_timed_out) {
886 LOG_DEBUG("Interrupt handlers didn't complete within time, "
887 "leaving target running");
888 } else {
889 /* Step over next instruction with interrupts disabled */
890 cortex_m3_write_debug_halt_mask(target,
891 C_HALT | C_MASKINTS,
892 0);
893 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
894 /* Re-enable interrupts */
895 cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
896 }
897 }
898 }
899 }
900
901 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
902 if (retval != ERROR_OK)
903 return retval;
904
905 /* registers are now invalid */
906 register_cache_invalidate(cortex_m3->armv7m.core_cache);
907
908 if (breakpoint)
909 cortex_m3_set_breakpoint(target, breakpoint);
910
911 if (isr_timed_out) {
912 /* Leave the core running. The user has to stop execution manually. */
913 target->debug_reason = DBG_REASON_NOTHALTED;
914 target->state = TARGET_RUNNING;
915 return ERROR_OK;
916 }
917
918 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
919 " nvic_icsr = 0x%" PRIx32,
920 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
921
922 retval = cortex_m3_debug_entry(target);
923 if (retval != ERROR_OK)
924 return retval;
925 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
926
927 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
928 " nvic_icsr = 0x%" PRIx32,
929 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
930
931 return ERROR_OK;
932 }
933
934 static int cortex_m3_assert_reset(struct target *target)
935 {
936 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
937 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
938 enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
939
940 LOG_DEBUG("target->state: %s",
941 target_state_name(target));
942
943 enum reset_types jtag_reset_config = jtag_get_reset_config();
944
945 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
946 /* allow scripts to override the reset event */
947
948 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
949 register_cache_invalidate(cortex_m3->armv7m.core_cache);
950 target->state = TARGET_RESET;
951
952 return ERROR_OK;
953 }
954
955 /* some cores support connecting while srst is asserted
956 * use that mode is it has been configured */
957
958 bool srst_asserted = false;
959
960 if (jtag_reset_config & RESET_SRST_NO_GATING) {
961 adapter_assert_reset();
962 srst_asserted = true;
963 }
964
965 /* Enable debug requests */
966 int retval;
967 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
968 if (retval != ERROR_OK)
969 return retval;
970 if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) {
971 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
972 if (retval != ERROR_OK)
973 return retval;
974 }
975
976 retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
977 if (retval != ERROR_OK)
978 return retval;
979
980 if (!target->reset_halt) {
981 /* Set/Clear C_MASKINTS in a separate operation */
982 if (cortex_m3->dcb_dhcsr & C_MASKINTS) {
983 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
984 DBGKEY | C_DEBUGEN | C_HALT);
985 if (retval != ERROR_OK)
986 return retval;
987 }
988
989 /* clear any debug flags before resuming */
990 cortex_m3_clear_halt(target);
991
992 /* clear C_HALT in dhcsr reg */
993 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
994 } else {
995 /* Halt in debug on reset; endreset_event() restores DEMCR.
996 *
997 * REVISIT catching BUSERR presumably helps to defend against
998 * bad vector table entries. Should this include MMERR or
999 * other flags too?
1000 */
1001 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
1002 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1003 if (retval != ERROR_OK)
1004 return retval;
1005 }
1006
1007 if (jtag_reset_config & RESET_HAS_SRST) {
1008 /* default to asserting srst */
1009 if (!srst_asserted)
1010 adapter_assert_reset();
1011 } else {
1012 /* Use a standard Cortex-M3 software reset mechanism.
1013 * We default to using VECRESET as it is supported on all current cores.
1014 * This has the disadvantage of not resetting the peripherals, so a
1015 * reset-init event handler is needed to perform any peripheral resets.
1016 */
1017 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1018 AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1019 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1020 if (retval != ERROR_OK)
1021 return retval;
1022
1023 LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1024 ? "SYSRESETREQ" : "VECTRESET");
1025
1026 if (reset_config == CORTEX_M3_RESET_VECTRESET) {
1027 LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1028 "handler to reset any peripherals or configure hardware srst support.");
1029 }
1030
1031 {
1032 /* I do not know why this is necessary, but it
1033 * fixes strange effects (step/resume cause NMI
1034 * after reset) on LM3S6918 -- Michael Schwingen
1035 */
1036 uint32_t tmp;
1037 retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1038 if (retval != ERROR_OK)
1039 return retval;
1040 }
1041 }
1042
1043 target->state = TARGET_RESET;
1044 jtag_add_sleep(50000);
1045
1046 register_cache_invalidate(cortex_m3->armv7m.core_cache);
1047
1048 if (target->reset_halt) {
1049 retval = target_halt(target);
1050 if (retval != ERROR_OK)
1051 return retval;
1052 }
1053
1054 return ERROR_OK;
1055 }
1056
1057 static int cortex_m3_deassert_reset(struct target *target)
1058 {
1059 LOG_DEBUG("target->state: %s",
1060 target_state_name(target));
1061
1062 /* deassert reset lines */
1063 adapter_deassert_reset();
1064
1065 return ERROR_OK;
1066 }
1067
1068 int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1069 {
1070 int retval;
1071 int fp_num = 0;
1072 uint32_t hilo;
1073 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1074 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1075
1076 if (breakpoint->set) {
1077 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1078 return ERROR_OK;
1079 }
1080
1081 if (cortex_m3->auto_bp_type)
1082 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1083
1084 if (breakpoint->type == BKPT_HARD) {
1085 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1086 fp_num++;
1087 if (fp_num >= cortex_m3->fp_num_code) {
1088 LOG_ERROR("Can not find free FPB Comparator!");
1089 return ERROR_FAIL;
1090 }
1091 breakpoint->set = fp_num + 1;
1092 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1093 comparator_list[fp_num].used = 1;
1094 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1095 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1096 comparator_list[fp_num].fpcr_value);
1097 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1098 fp_num,
1099 comparator_list[fp_num].fpcr_value);
1100 if (!cortex_m3->fpb_enabled) {
1101 LOG_DEBUG("FPB wasn't enabled, do it now");
1102 target_write_u32(target, FP_CTRL, 3);
1103 }
1104 } else if (breakpoint->type == BKPT_SOFT) {
1105 uint8_t code[4];
1106
1107 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1108 * semihosting; don't use that. Otherwise the BKPT
1109 * parameter is arbitrary.
1110 */
1111 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1112 retval = target_read_memory(target,
1113 breakpoint->address & 0xFFFFFFFE,
1114 breakpoint->length, 1,
1115 breakpoint->orig_instr);
1116 if (retval != ERROR_OK)
1117 return retval;
1118 retval = target_write_memory(target,
1119 breakpoint->address & 0xFFFFFFFE,
1120 breakpoint->length, 1,
1121 code);
1122 if (retval != ERROR_OK)
1123 return retval;
1124 breakpoint->set = true;
1125 }
1126
1127 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1128 breakpoint->unique_id,
1129 (int)(breakpoint->type),
1130 breakpoint->address,
1131 breakpoint->length,
1132 breakpoint->set);
1133
1134 return ERROR_OK;
1135 }
1136
1137 int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1138 {
1139 int retval;
1140 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1141 struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1142
1143 if (!breakpoint->set) {
1144 LOG_WARNING("breakpoint not set");
1145 return ERROR_OK;
1146 }
1147
1148 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1149 breakpoint->unique_id,
1150 (int)(breakpoint->type),
1151 breakpoint->address,
1152 breakpoint->length,
1153 breakpoint->set);
1154
1155 if (breakpoint->type == BKPT_HARD) {
1156 int fp_num = breakpoint->set - 1;
1157 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code)) {
1158 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1159 return ERROR_OK;
1160 }
1161 comparator_list[fp_num].used = 0;
1162 comparator_list[fp_num].fpcr_value = 0;
1163 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1164 comparator_list[fp_num].fpcr_value);
1165 } else {
1166 /* restore original instruction (kept in target endianness) */
1167 if (breakpoint->length == 4) {
1168 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1169 breakpoint->orig_instr);
1170 if (retval != ERROR_OK)
1171 return retval;
1172 } else {
1173 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1174 breakpoint->orig_instr);
1175 if (retval != ERROR_OK)
1176 return retval;
1177 }
1178 }
1179 breakpoint->set = false;
1180
1181 return ERROR_OK;
1182 }
1183
1184 int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1185 {
1186 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1187
1188 if (cortex_m3->auto_bp_type) {
1189 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1190 #ifdef ARMV7_GDB_HACKS
1191 if (breakpoint->length != 2) {
1192 /* XXX Hack: Replace all breakpoints with length != 2 with
1193 * a hardware breakpoint. */
1194 breakpoint->type = BKPT_HARD;
1195 breakpoint->length = 2;
1196 }
1197 #endif
1198 }
1199
1200 if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1201 if (breakpoint->type == BKPT_HARD) {
1202 LOG_INFO("flash patch comparator requested outside code memory region");
1203 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1204 }
1205
1206 if (breakpoint->type == BKPT_SOFT) {
1207 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1208 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1209 }
1210 }
1211
1212 if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1)) {
1213 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1214 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1215 }
1216
1217 if ((breakpoint->length != 2)) {
1218 LOG_INFO("only breakpoints of two bytes length supported");
1219 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1220 }
1221
1222 if (breakpoint->type == BKPT_HARD)
1223 cortex_m3->fp_code_available--;
1224
1225 return cortex_m3_set_breakpoint(target, breakpoint);
1226 }
1227
1228 int cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1229 {
1230 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1231
1232 /* REVISIT why check? FBP can be updated with core running ... */
1233 if (target->state != TARGET_HALTED) {
1234 LOG_WARNING("target not halted");
1235 return ERROR_TARGET_NOT_HALTED;
1236 }
1237
1238 if (cortex_m3->auto_bp_type)
1239 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1240
1241 if (breakpoint->set)
1242 cortex_m3_unset_breakpoint(target, breakpoint);
1243
1244 if (breakpoint->type == BKPT_HARD)
1245 cortex_m3->fp_code_available++;
1246
1247 return ERROR_OK;
1248 }
1249
1250 int cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1251 {
1252 int dwt_num = 0;
1253 uint32_t mask, temp;
1254 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1255
1256 /* watchpoint params were validated earlier */
1257 mask = 0;
1258 temp = watchpoint->length;
1259 while (temp) {
1260 temp >>= 1;
1261 mask++;
1262 }
1263 mask--;
1264
1265 /* REVISIT Don't fully trust these "not used" records ... users
1266 * may set up breakpoints by hand, e.g. dual-address data value
1267 * watchpoint using comparator #1; comparator #0 matching cycle
1268 * count; send data trace info through ITM and TPIU; etc
1269 */
1270 struct cortex_m3_dwt_comparator *comparator;
1271
1272 for (comparator = cortex_m3->dwt_comparator_list;
1273 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1274 comparator++, dwt_num++)
1275 continue;
1276 if (dwt_num >= cortex_m3->dwt_num_comp) {
1277 LOG_ERROR("Can not find free DWT Comparator");
1278 return ERROR_FAIL;
1279 }
1280 comparator->used = 1;
1281 watchpoint->set = dwt_num + 1;
1282
1283 comparator->comp = watchpoint->address;
1284 target_write_u32(target, comparator->dwt_comparator_address + 0,
1285 comparator->comp);
1286
1287 comparator->mask = mask;
1288 target_write_u32(target, comparator->dwt_comparator_address + 4,
1289 comparator->mask);
1290
1291 switch (watchpoint->rw) {
1292 case WPT_READ:
1293 comparator->function = 5;
1294 break;
1295 case WPT_WRITE:
1296 comparator->function = 6;
1297 break;
1298 case WPT_ACCESS:
1299 comparator->function = 7;
1300 break;
1301 }
1302 target_write_u32(target, comparator->dwt_comparator_address + 8,
1303 comparator->function);
1304
1305 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1306 watchpoint->unique_id, dwt_num,
1307 (unsigned) comparator->comp,
1308 (unsigned) comparator->mask,
1309 (unsigned) comparator->function);
1310 return ERROR_OK;
1311 }
1312
1313 int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1314 {
1315 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1316 struct cortex_m3_dwt_comparator *comparator;
1317 int dwt_num;
1318
1319 if (!watchpoint->set) {
1320 LOG_WARNING("watchpoint (wpid: %d) not set",
1321 watchpoint->unique_id);
1322 return ERROR_OK;
1323 }
1324
1325 dwt_num = watchpoint->set - 1;
1326
1327 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1328 watchpoint->unique_id, dwt_num,
1329 (unsigned) watchpoint->address);
1330
1331 if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) {
1332 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1333 return ERROR_OK;
1334 }
1335
1336 comparator = cortex_m3->dwt_comparator_list + dwt_num;
1337 comparator->used = 0;
1338 comparator->function = 0;
1339 target_write_u32(target, comparator->dwt_comparator_address + 8,
1340 comparator->function);
1341
1342 watchpoint->set = false;
1343
1344 return ERROR_OK;
1345 }
1346
1347 int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1348 {
1349 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1350
1351 if (cortex_m3->dwt_comp_available < 1) {
1352 LOG_DEBUG("no comparators?");
1353 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1354 }
1355
1356 /* hardware doesn't support data value masking */
1357 if (watchpoint->mask != ~(uint32_t)0) {
1358 LOG_DEBUG("watchpoint value masks not supported");
1359 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1360 }
1361
1362 /* hardware allows address masks of up to 32K */
1363 unsigned mask;
1364
1365 for (mask = 0; mask < 16; mask++) {
1366 if ((1u << mask) == watchpoint->length)
1367 break;
1368 }
1369 if (mask == 16) {
1370 LOG_DEBUG("unsupported watchpoint length");
1371 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1372 }
1373 if (watchpoint->address & ((1 << mask) - 1)) {
1374 LOG_DEBUG("watchpoint address is unaligned");
1375 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1376 }
1377
1378 /* Caller doesn't seem to be able to describe watching for data
1379 * values of zero; that flags "no value".
1380 *
1381 * REVISIT This DWT may well be able to watch for specific data
1382 * values. Requires comparator #1 to set DATAVMATCH and match
1383 * the data, and another comparator (DATAVADDR0) matching addr.
1384 */
1385 if (watchpoint->value) {
1386 LOG_DEBUG("data value watchpoint not YET supported");
1387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1388 }
1389
1390 cortex_m3->dwt_comp_available--;
1391 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1392
1393 return ERROR_OK;
1394 }
1395
1396 int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1397 {
1398 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1399
1400 /* REVISIT why check? DWT can be updated with core running ... */
1401 if (target->state != TARGET_HALTED) {
1402 LOG_WARNING("target not halted");
1403 return ERROR_TARGET_NOT_HALTED;
1404 }
1405
1406 if (watchpoint->set)
1407 cortex_m3_unset_watchpoint(target, watchpoint);
1408
1409 cortex_m3->dwt_comp_available++;
1410 LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1411
1412 return ERROR_OK;
1413 }
1414
1415 void cortex_m3_enable_watchpoints(struct target *target)
1416 {
1417 struct watchpoint *watchpoint = target->watchpoints;
1418
1419 /* set any pending watchpoints */
1420 while (watchpoint) {
1421 if (!watchpoint->set)
1422 cortex_m3_set_watchpoint(target, watchpoint);
1423 watchpoint = watchpoint->next;
1424 }
1425 }
1426
1427 static int cortex_m3_load_core_reg_u32(struct target *target,
1428 enum armv7m_regtype type, uint32_t num, uint32_t *value)
1429 {
1430 int retval;
1431 struct armv7m_common *armv7m = target_to_armv7m(target);
1432 struct adiv5_dap *swjdp = armv7m->arm.dap;
1433
1434 /* NOTE: we "know" here that the register identifiers used
1435 * in the v7m header match the Cortex-M3 Debug Core Register
1436 * Selector values for R0..R15, xPSR, MSP, and PSP.
1437 */
1438 switch (num) {
1439 case 0 ... 18:
1440 /* read a normal core register */
1441 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1442
1443 if (retval != ERROR_OK) {
1444 LOG_ERROR("JTAG failure %i", retval);
1445 return ERROR_JTAG_DEVICE_ERROR;
1446 }
1447 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1448 break;
1449
1450 case ARMV7M_PRIMASK:
1451 case ARMV7M_BASEPRI:
1452 case ARMV7M_FAULTMASK:
1453 case ARMV7M_CONTROL:
1454 /* Cortex-M3 packages these four registers as bitfields
1455 * in one Debug Core register. So say r0 and r2 docs;
1456 * it was removed from r1 docs, but still works.
1457 */
1458 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1459
1460 switch (num) {
1461 case ARMV7M_PRIMASK:
1462 *value = buf_get_u32((uint8_t *)value, 0, 1);
1463 break;
1464
1465 case ARMV7M_BASEPRI:
1466 *value = buf_get_u32((uint8_t *)value, 8, 8);
1467 break;
1468
1469 case ARMV7M_FAULTMASK:
1470 *value = buf_get_u32((uint8_t *)value, 16, 1);
1471 break;
1472
1473 case ARMV7M_CONTROL:
1474 *value = buf_get_u32((uint8_t *)value, 24, 2);
1475 break;
1476 }
1477
1478 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1479 break;
1480
1481 default:
1482 return ERROR_COMMAND_SYNTAX_ERROR;
1483 }
1484
1485 return ERROR_OK;
1486 }
1487
1488 static int cortex_m3_store_core_reg_u32(struct target *target,
1489 enum armv7m_regtype type, uint32_t num, uint32_t value)
1490 {
1491 int retval;
1492 uint32_t reg;
1493 struct armv7m_common *armv7m = target_to_armv7m(target);
1494 struct adiv5_dap *swjdp = armv7m->arm.dap;
1495
1496 #ifdef ARMV7_GDB_HACKS
1497 /* If the LR register is being modified, make sure it will put us
1498 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1499 * hack to deal with the fact that gdb will sometimes "forge"
1500 * return addresses, and doesn't set the LSB correctly (i.e., when
1501 * printing expressions containing function calls, it sets LR = 0.)
1502 * Valid exception return codes have bit 0 set too.
1503 */
1504 if (num == ARMV7M_R14)
1505 value |= 0x01;
1506 #endif
1507
1508 /* NOTE: we "know" here that the register identifiers used
1509 * in the v7m header match the Cortex-M3 Debug Core Register
1510 * Selector values for R0..R15, xPSR, MSP, and PSP.
1511 */
1512 switch (num) {
1513 case 0 ... 18:
1514 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1515 if (retval != ERROR_OK) {
1516 struct reg *r;
1517
1518 LOG_ERROR("JTAG failure");
1519 r = armv7m->core_cache->reg_list + num;
1520 r->dirty = r->valid;
1521 return ERROR_JTAG_DEVICE_ERROR;
1522 }
1523 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1524 break;
1525
1526 case ARMV7M_PRIMASK:
1527 case ARMV7M_BASEPRI:
1528 case ARMV7M_FAULTMASK:
1529 case ARMV7M_CONTROL:
1530 /* Cortex-M3 packages these four registers as bitfields
1531 * in one Debug Core register. So say r0 and r2 docs;
1532 * it was removed from r1 docs, but still works.
1533 */
1534 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1535
1536 switch (num) {
1537 case ARMV7M_PRIMASK:
1538 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1539 break;
1540
1541 case ARMV7M_BASEPRI:
1542 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1543 break;
1544
1545 case ARMV7M_FAULTMASK:
1546 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1547 break;
1548
1549 case ARMV7M_CONTROL:
1550 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1551 break;
1552 }
1553
1554 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1555
1556 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1557 break;
1558
1559 default:
1560 return ERROR_COMMAND_SYNTAX_ERROR;
1561 }
1562
1563 return ERROR_OK;
1564 }
1565
1566 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1567 uint32_t size, uint32_t count, uint8_t *buffer)
1568 {
1569 struct armv7m_common *armv7m = target_to_armv7m(target);
1570 struct adiv5_dap *swjdp = armv7m->arm.dap;
1571 int retval = ERROR_COMMAND_SYNTAX_ERROR;
1572
1573 if (armv7m->arm.is_armv6m) {
1574 /* armv6m does not handle unaligned memory access */
1575 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1576 return ERROR_TARGET_UNALIGNED_ACCESS;
1577 }
1578
1579 /* cortex_m3 handles unaligned memory access */
1580 if (count && buffer) {
1581 switch (size) {
1582 case 4:
1583 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1584 break;
1585 case 2:
1586 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1587 break;
1588 case 1:
1589 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1590 break;
1591 }
1592 }
1593
1594 return retval;
1595 }
1596
1597 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1598 uint32_t size, uint32_t count, const uint8_t *buffer)
1599 {
1600 struct armv7m_common *armv7m = target_to_armv7m(target);
1601 struct adiv5_dap *swjdp = armv7m->arm.dap;
1602 int retval = ERROR_COMMAND_SYNTAX_ERROR;
1603
1604 if (armv7m->arm.is_armv6m) {
1605 /* armv6m does not handle unaligned memory access */
1606 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1607 return ERROR_TARGET_UNALIGNED_ACCESS;
1608 }
1609
1610 if (count && buffer) {
1611 switch (size) {
1612 case 4:
1613 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1614 break;
1615 case 2:
1616 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1617 break;
1618 case 1:
1619 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1620 break;
1621 }
1622 }
1623
1624 return retval;
1625 }
1626
1627 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1628 uint32_t count, const uint8_t *buffer)
1629 {
1630 return cortex_m3_write_memory(target, address, 4, count, buffer);
1631 }
1632
1633 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1634 struct target *target)
1635 {
1636 armv7m_build_reg_cache(target);
1637 return ERROR_OK;
1638 }
1639
1640 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1641 * on r/w if the core is not running, and clear on resume or reset ... or
1642 * at least, in a post_restore_context() method.
1643 */
1644
1645 struct dwt_reg_state {
1646 struct target *target;
1647 uint32_t addr;
1648 uint32_t value; /* scratch/cache */
1649 };
1650
1651 static int cortex_m3_dwt_get_reg(struct reg *reg)
1652 {
1653 struct dwt_reg_state *state = reg->arch_info;
1654
1655 return target_read_u32(state->target, state->addr, &state->value);
1656 }
1657
1658 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1659 {
1660 struct dwt_reg_state *state = reg->arch_info;
1661
1662 return target_write_u32(state->target, state->addr,
1663 buf_get_u32(buf, 0, reg->size));
1664 }
1665
1666 struct dwt_reg {
1667 uint32_t addr;
1668 char *name;
1669 unsigned size;
1670 };
1671
1672 static struct dwt_reg dwt_base_regs[] = {
1673 { DWT_CTRL, "dwt_ctrl", 32, },
1674 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1675 * increments while the core is asleep.
1676 */
1677 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1678 /* plus some 8 bit counters, useful for profiling with TPIU */
1679 };
1680
1681 static struct dwt_reg dwt_comp[] = {
1682 #define DWT_COMPARATOR(i) \
1683 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1684 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1685 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1686 DWT_COMPARATOR(0),
1687 DWT_COMPARATOR(1),
1688 DWT_COMPARATOR(2),
1689 DWT_COMPARATOR(3),
1690 #undef DWT_COMPARATOR
1691 };
1692
1693 static const struct reg_arch_type dwt_reg_type = {
1694 .get = cortex_m3_dwt_get_reg,
1695 .set = cortex_m3_dwt_set_reg,
1696 };
1697
1698 static void cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1699 {
1700 struct dwt_reg_state *state;
1701
1702 state = calloc(1, sizeof *state);
1703 if (!state)
1704 return;
1705 state->addr = d->addr;
1706 state->target = t;
1707
1708 r->name = d->name;
1709 r->size = d->size;
1710 r->value = &state->value;
1711 r->arch_info = state;
1712 r->type = &dwt_reg_type;
1713 }
1714
1715 void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1716 {
1717 uint32_t dwtcr;
1718 struct reg_cache *cache;
1719 struct cortex_m3_dwt_comparator *comparator;
1720 int reg, i;
1721
1722 target_read_u32(target, DWT_CTRL, &dwtcr);
1723 if (!dwtcr) {
1724 LOG_DEBUG("no DWT");
1725 return;
1726 }
1727
1728 cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1729 cm3->dwt_comp_available = cm3->dwt_num_comp;
1730 cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1731 sizeof(struct cortex_m3_dwt_comparator));
1732 if (!cm3->dwt_comparator_list) {
1733 fail0:
1734 cm3->dwt_num_comp = 0;
1735 LOG_ERROR("out of mem");
1736 return;
1737 }
1738
1739 cache = calloc(1, sizeof *cache);
1740 if (!cache) {
1741 fail1:
1742 free(cm3->dwt_comparator_list);
1743 goto fail0;
1744 }
1745 cache->name = "cortex-m3 dwt registers";
1746 cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1747 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1748 if (!cache->reg_list) {
1749 free(cache);
1750 goto fail1;
1751 }
1752
1753 for (reg = 0; reg < 2; reg++)
1754 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1755 dwt_base_regs + reg);
1756
1757 comparator = cm3->dwt_comparator_list;
1758 for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1759 int j;
1760
1761 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1762 for (j = 0; j < 3; j++, reg++)
1763 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1764 dwt_comp + 3 * i + j);
1765 }
1766
1767 *register_get_last_cache_p(&target->reg_cache) = cache;
1768 cm3->dwt_cache = cache;
1769
1770 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1771 dwtcr, cm3->dwt_num_comp,
1772 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1773
1774 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1775 * implement single-address data value watchpoints ... so we
1776 * won't need to check it later, when asked to set one up.
1777 */
1778 }
1779
1780 #define MVFR0 0xe000ef40
1781 #define MVFR1 0xe000ef44
1782
1783 #define MVFR0_DEFAULT_M4 0x10110021
1784 #define MVFR1_DEFAULT_M4 0x11000011
1785
1786 int cortex_m3_examine(struct target *target)
1787 {
1788 int retval;
1789 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1790 int i;
1791 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1792 struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
1793 struct armv7m_common *armv7m = target_to_armv7m(target);
1794
1795 /* stlink shares the examine handler but does not support
1796 * all its calls */
1797 if (!armv7m->stlink) {
1798 retval = ahbap_debugport_init(swjdp);
1799 if (retval != ERROR_OK)
1800 return retval;
1801 }
1802
1803 if (!target_was_examined(target)) {
1804 target_set_examined(target);
1805
1806 /* Read from Device Identification Registers */
1807 retval = target_read_u32(target, CPUID, &cpuid);
1808 if (retval != ERROR_OK)
1809 return retval;
1810
1811 /* Get CPU Type */
1812 i = (cpuid >> 4) & 0xf;
1813
1814 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1815 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1816 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1817
1818 /* test for floating point feature on cortex-m4 */
1819 if (i == 4) {
1820 target_read_u32(target, MVFR0, &mvfr0);
1821 target_read_u32(target, MVFR1, &mvfr1);
1822
1823 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
1824 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
1825 armv7m->fp_feature = FPv4_SP;
1826 }
1827 } else if (i == 0) {
1828 /* Cortex-M0 does not support unaligned memory access */
1829 armv7m->arm.is_armv6m = true;
1830 }
1831
1832 if (i == 4 || i == 3) {
1833 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1834 armv7m->dap.tar_autoincr_block = (1 << 12);
1835 }
1836
1837 /* NOTE: FPB and DWT are both optional. */
1838
1839 /* Setup FPB */
1840 target_read_u32(target, FP_CTRL, &fpcr);
1841 cortex_m3->auto_bp_type = 1;
1842 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits
1843 *[14:12]
1844 *and [7:4]
1845 **/
1846 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1847 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1848 cortex_m3->fp_comparator_list = calloc(
1849 cortex_m3->fp_num_code + cortex_m3->fp_num_lit,
1850 sizeof(struct cortex_m3_fp_comparator));
1851 cortex_m3->fpb_enabled = fpcr & 1;
1852 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) {
1853 cortex_m3->fp_comparator_list[i].type =
1854 (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1855 cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1856 }
1857 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
1858 fpcr,
1859 cortex_m3->fp_num_code,
1860 cortex_m3->fp_num_lit);
1861
1862 /* Setup DWT */
1863 cortex_m3_dwt_setup(cortex_m3, target);
1864
1865 /* These hardware breakpoints only work for code in flash! */
1866 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1867 target_name(target),
1868 cortex_m3->fp_num_code,
1869 cortex_m3->dwt_num_comp);
1870 }
1871
1872 return ERROR_OK;
1873 }
1874
1875 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1876 {
1877 uint16_t dcrdr;
1878 int retval;
1879
1880 mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
1881 *ctrl = (uint8_t)dcrdr;
1882 *value = (uint8_t)(dcrdr >> 8);
1883
1884 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1885
1886 /* write ack back to software dcc register
1887 * signify we have read data */
1888 if (dcrdr & (1 << 0)) {
1889 dcrdr = 0;
1890 retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
1891 if (retval != ERROR_OK)
1892 return retval;
1893 }
1894
1895 return ERROR_OK;
1896 }
1897
1898 static int cortex_m3_target_request_data(struct target *target,
1899 uint32_t size, uint8_t *buffer)
1900 {
1901 struct armv7m_common *armv7m = target_to_armv7m(target);
1902 struct adiv5_dap *swjdp = armv7m->arm.dap;
1903 uint8_t data;
1904 uint8_t ctrl;
1905 uint32_t i;
1906
1907 for (i = 0; i < (size * 4); i++) {
1908 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1909 buffer[i] = data;
1910 }
1911
1912 return ERROR_OK;
1913 }
1914
1915 static int cortex_m3_handle_target_request(void *priv)
1916 {
1917 struct target *target = priv;
1918 if (!target_was_examined(target))
1919 return ERROR_OK;
1920 struct armv7m_common *armv7m = target_to_armv7m(target);
1921 struct adiv5_dap *swjdp = armv7m->arm.dap;
1922
1923 if (!target->dbg_msg_enabled)
1924 return ERROR_OK;
1925
1926 if (target->state == TARGET_RUNNING) {
1927 uint8_t data;
1928 uint8_t ctrl;
1929
1930 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1931
1932 /* check if we have data */
1933 if (ctrl & (1 << 0)) {
1934 uint32_t request;
1935
1936 /* we assume target is quick enough */
1937 request = data;
1938 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1939 request |= (data << 8);
1940 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1941 request |= (data << 16);
1942 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1943 request |= (data << 24);
1944 target_request(target, request);
1945 }
1946 }
1947
1948 return ERROR_OK;
1949 }
1950
1951 static int cortex_m3_init_arch_info(struct target *target,
1952 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1953 {
1954 int retval;
1955 struct armv7m_common *armv7m = &cortex_m3->armv7m;
1956
1957 armv7m_init_arch_info(target, armv7m);
1958
1959 /* prepare JTAG information for the new target */
1960 cortex_m3->jtag_info.tap = tap;
1961 cortex_m3->jtag_info.scann_size = 4;
1962
1963 /* default reset mode is to use srst if fitted
1964 * if not it will use CORTEX_M3_RESET_VECTRESET */
1965 cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
1966
1967 armv7m->arm.dap = &armv7m->dap;
1968
1969 /* Leave (only) generic DAP stuff for debugport_init(); */
1970 armv7m->dap.jtag_info = &cortex_m3->jtag_info;
1971 armv7m->dap.memaccess_tck = 8;
1972
1973 /* Cortex-M3/M4 has 4096 bytes autoincrement range
1974 * but set a safe default to 1024 to support Cortex-M0
1975 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
1976 armv7m->dap.tar_autoincr_block = (1 << 10);
1977
1978 /* register arch-specific functions */
1979 armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1980
1981 armv7m->post_debug_entry = NULL;
1982
1983 armv7m->pre_restore_context = NULL;
1984
1985 armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1986 armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1987
1988 target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1989
1990 retval = arm_jtag_setup_connection(&cortex_m3->jtag_info);
1991 if (retval != ERROR_OK)
1992 return retval;
1993
1994 return ERROR_OK;
1995 }
1996
1997 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1998 {
1999 struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common));
2000
2001 cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
2002 cortex_m3_init_arch_info(target, cortex_m3, target->tap);
2003
2004 return ERROR_OK;
2005 }
2006
2007 /*--------------------------------------------------------------------------*/
2008
2009 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
2010 struct cortex_m3_common *cm3)
2011 {
2012 if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
2013 command_print(cmd_ctx, "target is not a Cortex-M3");
2014 return ERROR_TARGET_INVALID;
2015 }
2016 return ERROR_OK;
2017 }
2018
2019 /*
2020 * Only stuff below this line should need to verify that its target
2021 * is a Cortex-M3. Everything else should have indirected through the
2022 * cortexm3_target structure, which is only used with CM3 targets.
2023 */
2024
2025 static const struct {
2026 char name[10];
2027 unsigned mask;
2028 } vec_ids[] = {
2029 { "hard_err", VC_HARDERR, },
2030 { "int_err", VC_INTERR, },
2031 { "bus_err", VC_BUSERR, },
2032 { "state_err", VC_STATERR, },
2033 { "chk_err", VC_CHKERR, },
2034 { "nocp_err", VC_NOCPERR, },
2035 { "mm_err", VC_MMERR, },
2036 { "reset", VC_CORERESET, },
2037 };
2038
2039 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
2040 {
2041 struct target *target = get_current_target(CMD_CTX);
2042 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2043 struct armv7m_common *armv7m = &cortex_m3->armv7m;
2044 struct adiv5_dap *swjdp = armv7m->arm.dap;
2045 uint32_t demcr = 0;
2046 int retval;
2047
2048 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2049 if (retval != ERROR_OK)
2050 return retval;
2051
2052 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2053 if (retval != ERROR_OK)
2054 return retval;
2055
2056 if (CMD_ARGC > 0) {
2057 unsigned catch = 0;
2058
2059 if (CMD_ARGC == 1) {
2060 if (strcmp(CMD_ARGV[0], "all") == 0) {
2061 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2062 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2063 | VC_MMERR | VC_CORERESET;
2064 goto write;
2065 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2066 goto write;
2067 }
2068 while (CMD_ARGC-- > 0) {
2069 unsigned i;
2070 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2071 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2072 continue;
2073 catch |= vec_ids[i].mask;
2074 break;
2075 }
2076 if (i == ARRAY_SIZE(vec_ids)) {
2077 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2078 return ERROR_COMMAND_SYNTAX_ERROR;
2079 }
2080 }
2081 write:
2082 /* For now, armv7m->demcr only stores vector catch flags. */
2083 armv7m->demcr = catch;
2084
2085 demcr &= ~0xffff;
2086 demcr |= catch;
2087
2088 /* write, but don't assume it stuck (why not??) */
2089 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2090 if (retval != ERROR_OK)
2091 return retval;
2092 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2093 if (retval != ERROR_OK)
2094 return retval;
2095
2096 /* FIXME be sure to clear DEMCR on clean server shutdown.
2097 * Otherwise the vector catch hardware could fire when there's
2098 * no debugger hooked up, causing much confusion...
2099 */
2100 }
2101
2102 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2103 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2104 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2105 }
2106
2107 return ERROR_OK;
2108 }
2109
2110 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2111 {
2112 struct target *target = get_current_target(CMD_CTX);
2113 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2114 int retval;
2115
2116 static const Jim_Nvp nvp_maskisr_modes[] = {
2117 { .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO },
2118 { .name = "off", .value = CORTEX_M3_ISRMASK_OFF },
2119 { .name = "on", .value = CORTEX_M3_ISRMASK_ON },
2120 { .name = NULL, .value = -1 },
2121 };
2122 const Jim_Nvp *n;
2123
2124
2125 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2126 if (retval != ERROR_OK)
2127 return retval;
2128
2129 if (target->state != TARGET_HALTED) {
2130 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2131 return ERROR_OK;
2132 }
2133
2134 if (CMD_ARGC > 0) {
2135 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2136 if (n->name == NULL)
2137 return ERROR_COMMAND_SYNTAX_ERROR;
2138 cortex_m3->isrmasking_mode = n->value;
2139
2140
2141 if (cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
2142 cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2143 else
2144 cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2145 }
2146
2147 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
2148 command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
2149
2150 return ERROR_OK;
2151 }
2152
2153 COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
2154 {
2155 struct target *target = get_current_target(CMD_CTX);
2156 struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2157 int retval;
2158 char *reset_config;
2159
2160 retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2161 if (retval != ERROR_OK)
2162 return retval;
2163
2164 if (CMD_ARGC > 0) {
2165 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2166 cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
2167 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2168 cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2169 }
2170
2171 switch (cortex_m3->soft_reset_config) {
2172 case CORTEX_M3_RESET_SYSRESETREQ:
2173 reset_config = "sysresetreq";
2174 break;
2175
2176 case CORTEX_M3_RESET_VECTRESET:
2177 reset_config = "vectreset";
2178 break;
2179
2180 default:
2181 reset_config = "unknown";
2182 break;
2183 }
2184
2185 command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
2186
2187 return ERROR_OK;
2188 }
2189
2190 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2191 {
2192 .name = "maskisr",
2193 .handler = handle_cortex_m3_mask_interrupts_command,
2194 .mode = COMMAND_EXEC,
2195 .help = "mask cortex_m3 interrupts",
2196 .usage = "['auto'|'on'|'off']",
2197 },
2198 {
2199 .name = "vector_catch",
2200 .handler = handle_cortex_m3_vector_catch_command,
2201 .mode = COMMAND_EXEC,
2202 .help = "configure hardware vectors to trigger debug entry",
2203 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2204 },
2205 {
2206 .name = "reset_config",
2207 .handler = handle_cortex_m3_reset_config_command,
2208 .mode = COMMAND_ANY,
2209 .help = "configure software reset handling",
2210 .usage = "['srst'|'sysresetreq'|'vectreset']",
2211 },
2212 COMMAND_REGISTRATION_DONE
2213 };
2214 static const struct command_registration cortex_m3_command_handlers[] = {
2215 {
2216 .chain = armv7m_command_handlers,
2217 },
2218 {
2219 .name = "cortex_m3",
2220 .mode = COMMAND_EXEC,
2221 .help = "Cortex-M3 command group",
2222 .usage = "",
2223 .chain = cortex_m3_exec_command_handlers,
2224 },
2225 COMMAND_REGISTRATION_DONE
2226 };
2227
2228 struct target_type cortexm3_target = {
2229 .name = "cortex_m3",
2230
2231 .poll = cortex_m3_poll,
2232 .arch_state = armv7m_arch_state,
2233
2234 .target_request_data = cortex_m3_target_request_data,
2235
2236 .halt = cortex_m3_halt,
2237 .resume = cortex_m3_resume,
2238 .step = cortex_m3_step,
2239
2240 .assert_reset = cortex_m3_assert_reset,
2241 .deassert_reset = cortex_m3_deassert_reset,
2242 .soft_reset_halt = cortex_m3_soft_reset_halt,
2243
2244 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2245
2246 .read_memory = cortex_m3_read_memory,
2247 .write_memory = cortex_m3_write_memory,
2248 .bulk_write_memory = cortex_m3_bulk_write_memory,
2249 .checksum_memory = armv7m_checksum_memory,
2250 .blank_check_memory = armv7m_blank_check_memory,
2251
2252 .run_algorithm = armv7m_run_algorithm,
2253 .start_algorithm = armv7m_start_algorithm,
2254 .wait_algorithm = armv7m_wait_algorithm,
2255
2256 .add_breakpoint = cortex_m3_add_breakpoint,
2257 .remove_breakpoint = cortex_m3_remove_breakpoint,
2258 .add_watchpoint = cortex_m3_add_watchpoint,
2259 .remove_watchpoint = cortex_m3_remove_watchpoint,
2260
2261 .commands = cortex_m3_command_handlers,
2262 .target_create = cortex_m3_target_create,
2263 .init_target = cortex_m3_init_target,
2264 .examine = cortex_m3_examine,
2265 };
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