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70c785c6a55cc9453e527d0445dc5590317349d2
[openocd.git] / src / target / lakemont.c
blob70c785c6a55cc9453e527d0445dc5590317349d2
1 /*
2 * Copyright(c) 2013 Intel Corporation.
3 *
4 * Adrian Burns (adrian.burns@intel.com)
5 * Thomas Faust (thomas.faust@intel.com)
6 * Ivan De Cesaris (ivan.de.cesaris@intel.com)
7 * Julien Carreno (julien.carreno@intel.com)
8 * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * Contact Information:
24 * Intel Corporation
25 */
26
27 /*
28 * @file
29 * This implements the probemode operations for Lakemont 1 (LMT1).
30 */
31
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include <helper/log.h>
37
38 #include "target.h"
39 #include "target_type.h"
40 #include "lakemont.h"
41 #include "register.h"
42 #include "breakpoints.h"
43 #include "x86_32_common.h"
44
45 static int irscan(struct target *t, uint8_t *out,
46 uint8_t *in, uint8_t ir_len);
47 static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len);
48 static int save_context(struct target *target);
49 static int restore_context(struct target *target);
50 static uint32_t get_tapstatus(struct target *t);
51 static int enter_probemode(struct target *t);
52 static int exit_probemode(struct target *t);
53 static int halt_prep(struct target *t);
54 static int do_halt(struct target *t);
55 static int do_resume(struct target *t);
56 static int read_all_core_hw_regs(struct target *t);
57 static int write_all_core_hw_regs(struct target *t);
58 static int read_hw_reg(struct target *t,
59 int reg, uint32_t *regval, uint8_t cache);
60 static int write_hw_reg(struct target *t,
61 int reg, uint32_t regval, uint8_t cache);
62 static struct reg_cache *lakemont_build_reg_cache
63 (struct target *target);
64 static int submit_reg_pir(struct target *t, int num);
65 static int submit_instruction_pir(struct target *t, int num);
66 static int submit_pir(struct target *t, uint64_t op);
67 static int lakemont_get_core_reg(struct reg *reg);
68 static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf);
69
70 static struct scan_blk scan;
71
72 /* registers and opcodes for register access, pm_idx is used to identify the
73 * registers that are modified for lakemont probemode specific operations
74 */
75 static const struct {
76 uint8_t id;
77 const char *name;
78 uint64_t op;
79 uint8_t pm_idx;
80 unsigned bits;
81 enum reg_type type;
82 const char *group;
83 const char *feature;
84 } regs[] = {
85 /* general purpose registers */
86 { EAX, "eax", 0x000000D01D660000, 0, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
87 { ECX, "ecx", 0x000000501D660000, 1, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
88 { EDX, "edx", 0x000000901D660000, 2, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
89 { EBX, "ebx", 0x000000101D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
90 { ESP, "esp", 0x000000E01D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" },
91 { EBP, "ebp", 0x000000601D660000, NOT_PMREG, 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.i386.core" },
92 { ESI, "esi", 0x000000A01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
93 { EDI, "edi", 0x000000201D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
94
95 /* instruction pointer & flags */
96 { EIP, "eip", 0x000000C01D660000, 3, 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.i386.core" },
97 { EFLAGS, "eflags", 0x000000401D660000, 4, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
98
99 /* segment registers */
100 { CS, "cs", 0x000000281D660000, 5, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
101 { SS, "ss", 0x000000C81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
102 { DS, "ds", 0x000000481D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
103 { ES, "es", 0x000000A81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
104 { FS, "fs", 0x000000881D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
105 { GS, "gs", 0x000000081D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
106
107 /* floating point unit registers - not accessible via JTAG - here to satisfy GDB */
108 { ST0, "st0", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
109 { ST1, "st1", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
110 { ST2, "st2", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
111 { ST3, "st3", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
112 { ST4, "st4", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
113 { ST5, "st5", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
114 { ST6, "st6", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
115 { ST7, "st7", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
116 { FCTRL, "fctrl", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
117 { FSTAT, "fstat", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
118 { FTAG, "ftag", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
119 { FISEG, "fiseg", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
120 { FIOFF, "fioff", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
121 { FOSEG, "foseg", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
122 { FOOFF, "fooff", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
123 { FOP, "fop", 0x0, NOT_AVAIL_REG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.core" },
124
125 /* control registers */
126 { CR0, "cr0", 0x000000001D660000, 6, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
127 { CR2, "cr2", 0x000000BC1D660000, 7, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
128 { CR3, "cr3", 0x000000801D660000, 8, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
129 { CR4, "cr4", 0x0000002C1D660000, 9, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
130
131 /* debug registers */
132 { DR0, "dr0", 0x0000007C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
133 { DR1, "dr1", 0x000000FC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
134 { DR2, "dr2", 0x000000021D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
135 { DR3, "dr3", 0x000000821D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
136 { DR6, "dr6", 0x000000301D660000, 10, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
137 { DR7, "dr7", 0x000000B01D660000, 11, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
138
139 /* descriptor tables */
140 { IDTB, "idtbase", 0x000000581D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
141 { IDTL, "idtlimit", 0x000000D81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
142 { IDTAR, "idtar", 0x000000981D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
143 { GDTB, "gdtbase", 0x000000B81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
144 { GDTL, "gdtlimit", 0x000000781D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
145 { GDTAR, "gdtar", 0x000000381D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
146 { TR, "tr", 0x000000701D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
147 { LDTR, "ldtr", 0x000000F01D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
148 { LDTB, "ldbase", 0x000000041D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
149 { LDTL, "ldlimit", 0x000000841D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
150 { LDTAR, "ldtar", 0x000000F81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
151
152 /* segment registers */
153 { CSB, "csbase", 0x000000F41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
154 { CSL, "cslimit", 0x0000000C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
155 { CSAR, "csar", 0x000000741D660000, 12, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
156 { DSB, "dsbase", 0x000000941D660000, 13, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
157 { DSL, "dslimit", 0x000000541D660000, 14, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
158 { DSAR, "dsar", 0x000000141D660000, 15, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
159 { ESB, "esbase", 0x0000004C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
160 { ESL, "eslimit", 0x000000CC1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
161 { ESAR, "esar", 0x0000008C1D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
162 { FSB, "fsbase", 0x000000641D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
163 { FSL, "fslimit", 0x000000E41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
164 { FSAR, "fsar", 0x000000A41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
165 { GSB, "gsbase", 0x000000C41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
166 { GSL, "gslimit", 0x000000241D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
167 { GSAR, "gsar", 0x000000441D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
168 { SSB, "ssbase", 0x000000341D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
169 { SSL, "sslimit", 0x000000B41D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
170 { SSAR, "ssar", 0x000000D41D660000, 16, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
171 { TSSB, "tssbase", 0x000000E81D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
172 { TSSL, "tsslimit", 0x000000181D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
173 { TSSAR, "tssar", 0x000000681D660000, NOT_PMREG, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
174 /* probemode control register */
175 { PMCR, "pmcr", 0x000000421D660000, 17, 32, REG_TYPE_INT32, "general", "org.gnu.gdb.i386.sys" },
176 };
177
178 static const struct {
179 uint8_t id;
180 const char *name;
181 uint64_t op;
182 } instructions[] = {
183 /* memory read/write */
184 { MEMRDB32, "MEMRDB32", 0x0909090909090851 },
185 { MEMRDB16, "MEMRDB16", 0x09090909090851E6 },
186 { MEMRDH32, "MEMRDH32", 0x090909090908D166 },
187 { MEMRDH16, "MEMRDH16", 0x090909090908D1E6 },
188 { MEMRDW32, "MEMRDW32", 0x09090909090908D1 },
189 { MEMRDW16, "MEMRDW16", 0x0909090908D1E666 },
190 { MEMWRB32, "MEMWRB32", 0x0909090909090811 },
191 { MEMWRB16, "MEMWRB16", 0x09090909090811E6 },
192 { MEMWRH32, "MEMWRH32", 0x0909090909089166 },
193 { MEMWRH16, "MEMWRH16", 0x09090909090891E6 },
194 { MEMWRW32, "MEMWRW32", 0x0909090909090891 },
195 { MEMWRW16, "MEMWRW16", 0x090909090891E666 },
196 /* IO read/write */
197 { IORDB32, "IORDB32", 0x0909090909090937 },
198 { IORDB16, "IORDB16", 0x09090909090937E6 },
199 { IORDH32, "IORDH32", 0x090909090909B766 },
200 { IORDH16, "IORDH16", 0x090909090909B7E6 },
201 { IORDW32, "IORDW32", 0x09090909090909B7 },
202 { IORDW16, "IORDW16", 0x0909090909B7E666 },
203 { IOWRB32, "IOWRB32", 0x0909090909090977 },
204 { IOWRB16, "IOWRB16", 0x09090909090977E6 },
205 { IOWRH32, "IOWRH32", 0x090909090909F766 },
206 { IOWRH16, "IOWRH16", 0x090909090909F7E6 },
207 { IOWRW32, "IOWRW32", 0x09090909090909F7 },
208 { IOWRW16, "IOWRW16", 0x0909090909F7E666 },
209 /* lakemont1 core shadow ram access opcodes */
210 { SRAMACCESS, "SRAMACCESS", 0x0000000E9D660000 },
211 { SRAM2PDR, "SRAM2PDR", 0x4CF0000000000000 },
212 { PDR2SRAM, "PDR2SRAM", 0x0CF0000000000000 },
213 { WBINVD, "WBINVD", 0x09090909090990F0 },
214 };
215
216 bool check_not_halted(const struct target *t)
217 {
218 bool halted = t->state == TARGET_HALTED;
219 if (!halted)
220 LOG_ERROR("target running, halt it first");
221 return !halted;
222 }
223
224 static int irscan(struct target *t, uint8_t *out,
225 uint8_t *in, uint8_t ir_len)
226 {
227 int retval = ERROR_OK;
228 struct x86_32_common *x86_32 = target_to_x86_32(t);
229 if (NULL == t->tap) {
230 retval = ERROR_FAIL;
231 LOG_ERROR("%s invalid target tap", __func__);
232 return retval;
233 }
234 if (ir_len != t->tap->ir_length) {
235 retval = ERROR_FAIL;
236 if (t->tap->enabled)
237 LOG_ERROR("%s tap enabled but tap irlen=%d",
238 __func__, t->tap->ir_length);
239 else
240 LOG_ERROR("%s tap not enabled and irlen=%d",
241 __func__, t->tap->ir_length);
242 return retval;
243 }
244 struct scan_field *fields = &scan.field;
245 fields->num_bits = ir_len;
246 fields->out_value = out;
247 fields->in_value = in;
248 jtag_add_ir_scan(x86_32->curr_tap, fields, TAP_IDLE);
249 if (x86_32->flush) {
250 retval = jtag_execute_queue();
251 if (retval != ERROR_OK)
252 LOG_ERROR("%s failed to execute queue", __func__);
253 }
254 return retval;
255 }
256
257 static int drscan(struct target *t, uint8_t *out, uint8_t *in, uint8_t len)
258 {
259 int retval = ERROR_OK;
260 uint64_t data = 0;
261 struct x86_32_common *x86_32 = target_to_x86_32(t);
262 if (NULL == t->tap) {
263 retval = ERROR_FAIL;
264 LOG_ERROR("%s invalid target tap", __func__);
265 return retval;
266 }
267 if (len > MAX_SCAN_SIZE || 0 == len) {
268 retval = ERROR_FAIL;
269 LOG_ERROR("%s data len is %d bits, max is %d bits",
270 __func__, len, MAX_SCAN_SIZE);
271 return retval;
272 }
273 struct scan_field *fields = &scan.field;
274 fields->out_value = out;
275 fields->in_value = in;
276 fields->num_bits = len;
277 jtag_add_dr_scan(x86_32->curr_tap, 1, fields, TAP_IDLE);
278 if (x86_32->flush) {
279 retval = jtag_execute_queue();
280 if (retval != ERROR_OK) {
281 LOG_ERROR("%s drscan failed to execute queue", __func__);
282 return retval;
283 }
284 }
285 if (in != NULL) {
286 if (len >= 8) {
287 for (int n = (len / 8) - 1 ; n >= 0; n--)
288 data = (data << 8) + *(in+n);
289 } else
290 LOG_DEBUG("dr in 0x%02" PRIx8, *in);
291 } else {
292 LOG_ERROR("%s no drscan data", __func__);
293 retval = ERROR_FAIL;
294 }
295 return retval;
296 }
297
298 static int save_context(struct target *t)
299 {
300 int err;
301 /* read core registers from lakemont sram */
302 err = read_all_core_hw_regs(t);
303 if (err != ERROR_OK) {
304 LOG_ERROR("%s error reading regs", __func__);
305 return err;
306 }
307 return ERROR_OK;
308 }
309
310 static int restore_context(struct target *t)
311 {
312 int err = ERROR_OK;
313 uint32_t i;
314 struct x86_32_common *x86_32 = target_to_x86_32(t);
315
316 /* write core regs into the core PM SRAM from the reg_cache */
317 err = write_all_core_hw_regs(t);
318 if (err != ERROR_OK) {
319 LOG_ERROR("%s error writing regs", __func__);
320 return err;
321 }
322
323 for (i = 0; i < (x86_32->cache->num_regs); i++) {
324 x86_32->cache->reg_list[i].dirty = 0;
325 x86_32->cache->reg_list[i].valid = 0;
326 }
327 return err;
328 }
329
330 /*
331 * we keep reg_cache in sync with hardware at halt/resume time, we avoid
332 * writing to real hardware here bacause pm_regs reflects the hardware
333 * while we are halted then reg_cache syncs with hw on resume
334 * TODO - in order for "reg eip force" to work it assume get/set reads
335 * and writes from hardware, may be other reasons also because generally
336 * other openocd targets read/write from hardware in get/set - watch this!
337 */
338 static int lakemont_get_core_reg(struct reg *reg)
339 {
340 int retval = ERROR_OK;
341 struct lakemont_core_reg *lakemont_reg = reg->arch_info;
342 struct target *t = lakemont_reg->target;
343 if (check_not_halted(t))
344 return ERROR_TARGET_NOT_HALTED;
345 LOG_DEBUG("reg=%s, value=%08" PRIx32, reg->name,
346 buf_get_u32(reg->value, 0, 32));
347 return retval;
348 }
349
350 static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
351 {
352 struct lakemont_core_reg *lakemont_reg = reg->arch_info;
353 struct target *t = lakemont_reg->target;
354 uint32_t value = buf_get_u32(buf, 0, 32);
355 LOG_DEBUG("reg=%s, newval=%08" PRIx32, reg->name, value);
356 if (check_not_halted(t))
357 return ERROR_TARGET_NOT_HALTED;
358 buf_set_u32(reg->value, 0, 32, value);
359 reg->dirty = 1;
360 reg->valid = 1;
361 return ERROR_OK;
362 }
363
364 static const struct reg_arch_type lakemont_reg_type = {
365 /* these get called if reg_cache doesnt have a "valid" value
366 * of an individual reg eg "reg eip" but not for "reg" block
367 */
368 .get = lakemont_get_core_reg,
369 .set = lakemont_set_core_reg,
370 };
371
372 struct reg_cache *lakemont_build_reg_cache(struct target *t)
373 {
374 struct x86_32_common *x86_32 = target_to_x86_32(t);
375 int num_regs = ARRAY_SIZE(regs);
376 struct reg_cache **cache_p = register_get_last_cache_p(&t->reg_cache);
377 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
378 struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
379 struct lakemont_core_reg *arch_info = malloc(sizeof(struct lakemont_core_reg) * num_regs);
380 struct reg_feature *feature;
381 int i;
382
383 if (cache == NULL || reg_list == NULL || arch_info == NULL) {
384 free(cache);
385 free(reg_list);
386 free(arch_info);
387 LOG_ERROR("%s out of memory", __func__);
388 return NULL;
389 }
390
391 /* Build the process context cache */
392 cache->name = "lakemont registers";
393 cache->next = NULL;
394 cache->reg_list = reg_list;
395 cache->num_regs = num_regs;
396 (*cache_p) = cache;
397 x86_32->cache = cache;
398
399 for (i = 0; i < num_regs; i++) {
400 arch_info[i].target = t;
401 arch_info[i].x86_32_common = x86_32;
402 arch_info[i].op = regs[i].op;
403 arch_info[i].pm_idx = regs[i].pm_idx;
404 reg_list[i].name = regs[i].name;
405 reg_list[i].size = 32;
406 reg_list[i].value = calloc(1, 4);
407 reg_list[i].dirty = 0;
408 reg_list[i].valid = 0;
409 reg_list[i].type = &lakemont_reg_type;
410 reg_list[i].arch_info = &arch_info[i];
411
412 reg_list[i].group = regs[i].group;
413 reg_list[i].number = i;
414 reg_list[i].exist = true;
415 reg_list[i].caller_save = true; /* gdb defaults to true */
416
417 feature = calloc(1, sizeof(struct reg_feature));
418 if (feature) {
419 feature->name = regs[i].feature;
420 reg_list[i].feature = feature;
421 } else
422 LOG_ERROR("%s unable to allocate feature list", __func__);
423
424 reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
425 if (reg_list[i].reg_data_type)
426 reg_list[i].reg_data_type->type = regs[i].type;
427 else
428 LOG_ERROR("%s unable to allocate reg type list", __func__);
429 }
430 return cache;
431 }
432
433 static uint32_t get_tapstatus(struct target *t)
434 {
435 scan.out[0] = TAPSTATUS;
436 if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
437 return 0;
438 if (drscan(t, NULL, scan.out, TS_SIZE) != ERROR_OK)
439 return 0;
440 return buf_get_u32(scan.out, 0, 32);
441 }
442
443 static int enter_probemode(struct target *t)
444 {
445 uint32_t tapstatus = 0;
446 tapstatus = get_tapstatus(t);
447 LOG_DEBUG("TS before PM enter = %08" PRIx32, tapstatus);
448 if (tapstatus & TS_PM_BIT) {
449 LOG_DEBUG("core already in probemode");
450 return ERROR_OK;
451 }
452 scan.out[0] = PROBEMODE;
453 if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
454 return ERROR_FAIL;
455 scan.out[0] = 1;
456 if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
457 return ERROR_FAIL;
458 tapstatus = get_tapstatus(t);
459 LOG_DEBUG("TS after PM enter = %08" PRIx32, tapstatus);
460 if ((tapstatus & TS_PM_BIT) && (!(tapstatus & TS_EN_PM_BIT)))
461 return ERROR_OK;
462 else {
463 LOG_ERROR("%s PM enter error, tapstatus = %08" PRIx32
464 , __func__, tapstatus);
465 return ERROR_FAIL;
466 }
467 }
468
469 static int exit_probemode(struct target *t)
470 {
471 uint32_t tapstatus = get_tapstatus(t);
472 LOG_DEBUG("TS before PM exit = %08" PRIx32, tapstatus);
473
474 if (!(tapstatus & TS_PM_BIT)) {
475 LOG_USER("core not in PM");
476 return ERROR_OK;
477 }
478 scan.out[0] = PROBEMODE;
479 if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
480 return ERROR_FAIL;
481 scan.out[0] = 0;
482 if (drscan(t, scan.out, scan.in, 1) != ERROR_OK)
483 return ERROR_FAIL;
484 return ERROR_OK;
485 }
486
487 /* do whats needed to properly enter probemode for debug on lakemont */
488 static int halt_prep(struct target *t)
489 {
490 struct x86_32_common *x86_32 = target_to_x86_32(t);
491 if (write_hw_reg(t, DSB, PM_DSB, 0) != ERROR_OK)
492 return ERROR_FAIL;
493 LOG_DEBUG("write %s %08" PRIx32, regs[DSB].name, PM_DSB);
494 if (write_hw_reg(t, DSL, PM_DSL, 0) != ERROR_OK)
495 return ERROR_FAIL;
496 LOG_DEBUG("write %s %08" PRIx32, regs[DSL].name, PM_DSL);
497 if (write_hw_reg(t, DSAR, PM_DSAR, 0) != ERROR_OK)
498 return ERROR_FAIL;
499 LOG_DEBUG("write DSAR %08" PRIx32, PM_DSAR);
500 if (write_hw_reg(t, DR7, PM_DR7, 0) != ERROR_OK)
501 return ERROR_FAIL;
502 LOG_DEBUG("write DR7 %08" PRIx32, PM_DR7);
503
504 uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
505 uint32_t csar = buf_get_u32(x86_32->cache->reg_list[CSAR].value, 0, 32);
506 uint32_t ssar = buf_get_u32(x86_32->cache->reg_list[SSAR].value, 0, 32);
507 uint32_t cr0 = buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32);
508
509 /* clear VM86 and IF bits if they are set */
510 LOG_DEBUG("EFLAGS = %08" PRIx32 ", VM86 = %d, IF = %d", eflags,
511 eflags & EFLAGS_VM86 ? 1 : 0,
512 eflags & EFLAGS_IF ? 1 : 0);
513 if (eflags & EFLAGS_VM86
514 || eflags & EFLAGS_IF) {
515 x86_32->pm_regs[I(EFLAGS)] = eflags & ~(EFLAGS_VM86 | EFLAGS_IF);
516 if (write_hw_reg(t, EFLAGS, x86_32->pm_regs[I(EFLAGS)], 0) != ERROR_OK)
517 return ERROR_FAIL;
518 LOG_DEBUG("EFLAGS now = %08" PRIx32 ", VM86 = %d, IF = %d",
519 x86_32->pm_regs[I(EFLAGS)],
520 x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0,
521 x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0);
522 }
523
524 /* set CPL to 0 for memory access */
525 if (csar & CSAR_DPL) {
526 x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL;
527 if (write_hw_reg(t, CSAR, x86_32->pm_regs[I(CSAR)], 0) != ERROR_OK)
528 return ERROR_FAIL;
529 LOG_DEBUG("write CSAR_CPL to 0 %08" PRIx32, x86_32->pm_regs[I(CSAR)]);
530 }
531 if (ssar & SSAR_DPL) {
532 x86_32->pm_regs[I(SSAR)] = ssar & ~CSAR_DPL;
533 if (write_hw_reg(t, SSAR, x86_32->pm_regs[I(SSAR)], 0) != ERROR_OK)
534 return ERROR_FAIL;
535 LOG_DEBUG("write SSAR_CPL to 0 %08" PRIx32, x86_32->pm_regs[I(SSAR)]);
536 }
537
538 /* if cache's are enabled, disable and flush */
539 if (!(cr0 & CR0_CD)) {
540 LOG_DEBUG("caching enabled CR0 = %08" PRIx32, cr0);
541 if (cr0 & CR0_PG) {
542 x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG;
543 if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
544 return ERROR_FAIL;
545 LOG_DEBUG("cleared paging CR0_PG = %08" PRIx32, x86_32->pm_regs[I(CR0)]);
546 /* submit wbinvd to flush cache */
547 if (submit_reg_pir(t, WBINVD) != ERROR_OK)
548 return ERROR_FAIL;
549 x86_32->pm_regs[I(CR0)] =
550 x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG);
551 if (write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0) != ERROR_OK)
552 return ERROR_FAIL;
553 LOG_DEBUG("set CD, NW and PG, CR0 = %08" PRIx32, x86_32->pm_regs[I(CR0)]);
554 }
555 }
556 return ERROR_OK;
557 }
558
559 static int do_halt(struct target *t)
560 {
561 /* needs proper handling later if doing a halt errors out */
562 t->state = TARGET_DEBUG_RUNNING;
563 if (enter_probemode(t) != ERROR_OK)
564 return ERROR_FAIL;
565 if (save_context(t) != ERROR_OK)
566 return ERROR_FAIL;
567 if (halt_prep(t) != ERROR_OK)
568 return ERROR_FAIL;
569 t->state = TARGET_HALTED;
570
571 return target_call_event_callbacks(t, TARGET_EVENT_HALTED);
572 }
573
574 static int do_resume(struct target *t)
575 {
576 /* needs proper handling later */
577 t->state = TARGET_DEBUG_RUNNING;
578 if (restore_context(t) != ERROR_OK)
579 return ERROR_FAIL;
580 if (exit_probemode(t) != ERROR_OK)
581 return ERROR_FAIL;
582 t->state = TARGET_RUNNING;
583
584 t->debug_reason = DBG_REASON_NOTHALTED;
585 LOG_USER("target running");
586
587 return target_call_event_callbacks(t, TARGET_EVENT_RESUMED);
588 }
589
590 static int read_all_core_hw_regs(struct target *t)
591 {
592 int err;
593 uint32_t regval, i;
594 struct x86_32_common *x86_32 = target_to_x86_32(t);
595 for (i = 0; i < (x86_32->cache->num_regs); i++) {
596 if (NOT_AVAIL_REG == regs[i].pm_idx)
597 continue;
598 err = read_hw_reg(t, regs[i].id, &regval, 1);
599 if (err != ERROR_OK) {
600 LOG_ERROR("%s error saving reg %s",
601 __func__, x86_32->cache->reg_list[i].name);
602 return err;
603 }
604 }
605 LOG_DEBUG("read_all_core_hw_regs read %d registers ok", i);
606 return ERROR_OK;
607 }
608
609 static int write_all_core_hw_regs(struct target *t)
610 {
611 int err;
612 uint32_t i;
613 struct x86_32_common *x86_32 = target_to_x86_32(t);
614 for (i = 0; i < (x86_32->cache->num_regs); i++) {
615 if (NOT_AVAIL_REG == regs[i].pm_idx)
616 continue;
617 err = write_hw_reg(t, i, 0, 1);
618 if (err != ERROR_OK) {
619 LOG_ERROR("%s error restoring reg %s",
620 __func__, x86_32->cache->reg_list[i].name);
621 return err;
622 }
623 }
624 LOG_DEBUG("write_all_core_hw_regs wrote %d registers ok", i);
625 return ERROR_OK;
626 }
627
628 /* read reg from lakemont core shadow ram, update reg cache if needed */
629 static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cache)
630 {
631 struct x86_32_common *x86_32 = target_to_x86_32(t);
632 struct lakemont_core_reg *arch_info;
633 arch_info = x86_32->cache->reg_list[reg].arch_info;
634 x86_32->flush = 0; /* dont flush scans till we have a batch */
635 if (submit_reg_pir(t, reg) != ERROR_OK)
636 return ERROR_FAIL;
637 if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
638 return ERROR_FAIL;
639 if (submit_instruction_pir(t, SRAM2PDR) != ERROR_OK)
640 return ERROR_FAIL;
641 x86_32->flush = 1;
642 scan.out[0] = RDWRPDR;
643 if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
644 return ERROR_FAIL;
645 if (drscan(t, NULL, scan.out, PDR_SIZE) != ERROR_OK)
646 return ERROR_FAIL;
647
648 jtag_add_sleep(DELAY_SUBMITPIR);
649 *regval = buf_get_u32(scan.out, 0, 32);
650 if (cache) {
651 buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
652 x86_32->cache->reg_list[reg].valid = 1;
653 x86_32->cache->reg_list[reg].dirty = 0;
654 }
655 LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=%08" PRIx32,
656 x86_32->cache->reg_list[reg].name,
657 arch_info->op,
658 *regval);
659 return ERROR_OK;
660 }
661
662 /* write lakemont core shadow ram reg, update reg cache if needed */
663 static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cache)
664 {
665 struct x86_32_common *x86_32 = target_to_x86_32(t);
666 struct lakemont_core_reg *arch_info;
667 arch_info = x86_32->cache->reg_list[reg].arch_info;
668
669 uint8_t reg_buf[4];
670 if (cache)
671 regval = buf_get_u32(x86_32->cache->reg_list[reg].value, 0, 32);
672 buf_set_u32(reg_buf, 0, 32, regval);
673 LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=%08" PRIx32,
674 x86_32->cache->reg_list[reg].name,
675 arch_info->op,
676 regval);
677
678 scan.out[0] = RDWRPDR;
679 x86_32->flush = 0; /* dont flush scans till we have a batch */
680 if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
681 return ERROR_FAIL;
682 if (drscan(t, reg_buf, scan.out, PDR_SIZE) != ERROR_OK)
683 return ERROR_FAIL;
684 if (submit_reg_pir(t, reg) != ERROR_OK)
685 return ERROR_FAIL;
686 if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
687 return ERROR_FAIL;
688 x86_32->flush = 1;
689 if (submit_instruction_pir(t, PDR2SRAM) != ERROR_OK)
690 return ERROR_FAIL;
691
692 /* we are writing from the cache so ensure we reset flags */
693 if (cache) {
694 x86_32->cache->reg_list[reg].dirty = 0;
695 x86_32->cache->reg_list[reg].valid = 0;
696 }
697 return ERROR_OK;
698 }
699
700 static bool is_paging_enabled(struct target *t)
701 {
702 struct x86_32_common *x86_32 = target_to_x86_32(t);
703 if (x86_32->pm_regs[I(CR0)] & CR0_PG)
704 return true;
705 else
706 return false;
707 }
708
709 static uint8_t get_num_user_regs(struct target *t)
710 {
711 struct x86_32_common *x86_32 = target_to_x86_32(t);
712 return x86_32->cache->num_regs;
713 }
714 /* value of the CR0.PG (paging enabled) bit influences memory reads/writes */
715 static int disable_paging(struct target *t)
716 {
717 struct x86_32_common *x86_32 = target_to_x86_32(t);
718 x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG;
719 int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
720 if (err != ERROR_OK) {
721 LOG_ERROR("%s error disabling paging", __func__);
722 return err;
723 }
724 return err;
725 }
726
727 static int enable_paging(struct target *t)
728 {
729 struct x86_32_common *x86_32 = target_to_x86_32(t);
730 x86_32->pm_regs[I(CR0)] = (x86_32->pm_regs[I(CR0)] | CR0_PG);
731 int err = x86_32->write_hw_reg(t, CR0, x86_32->pm_regs[I(CR0)], 0);
732 if (err != ERROR_OK) {
733 LOG_ERROR("%s error enabling paging", __func__);
734 return err;
735 }
736 return err;
737 }
738
739 static bool sw_bpts_supported(struct target *t)
740 {
741 uint32_t tapstatus = get_tapstatus(t);
742 if (tapstatus & TS_SBP_BIT)
743 return true;
744 else
745 return false;
746 }
747
748 static int transaction_status(struct target *t)
749 {
750 uint32_t tapstatus = get_tapstatus(t);
751 if ((TS_EN_PM_BIT | TS_PRDY_BIT) & tapstatus) {
752 LOG_ERROR("%s transaction error tapstatus = %08" PRIx32
753 , __func__, tapstatus);
754 return ERROR_FAIL;
755 } else {
756 return ERROR_OK;
757 }
758 }
759
760 static int submit_instruction(struct target *t, int num)
761 {
762 int err = submit_instruction_pir(t, num);
763 if (err != ERROR_OK) {
764 LOG_ERROR("%s error submitting pir", __func__);
765 return err;
766 }
767 return err;
768 }
769
770 static int submit_reg_pir(struct target *t, int num)
771 {
772 LOG_DEBUG("reg %s op=0x%016" PRIx64, regs[num].name, regs[num].op);
773 int err = submit_pir(t, regs[num].op);
774 if (err != ERROR_OK) {
775 LOG_ERROR("%s error submitting pir", __func__);
776 return err;
777 }
778 return err;
779 }
780
781 static int submit_instruction_pir(struct target *t, int num)
782 {
783 LOG_DEBUG("%s op=0x%016" PRIx64, instructions[num].name,
784 instructions[num].op);
785 int err = submit_pir(t, instructions[num].op);
786 if (err != ERROR_OK) {
787 LOG_ERROR("%s error submitting pir", __func__);
788 return err;
789 }
790 return err;
791 }
792
793 /*
794 * PIR (Probe Mode Instruction Register), SUBMITPIR is an "IR only" TAP
795 * command; there is no corresponding data register
796 */
797 static int submit_pir(struct target *t, uint64_t op)
798 {
799 struct x86_32_common *x86_32 = target_to_x86_32(t);
800
801 uint8_t op_buf[8];
802 buf_set_u64(op_buf, 0, 64, op);
803 int flush = x86_32->flush;
804 x86_32->flush = 0;
805 scan.out[0] = WRPIR;
806 if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
807 return ERROR_FAIL;
808 if (drscan(t, op_buf, scan.out, PIR_SIZE) != ERROR_OK)
809 return ERROR_FAIL;
810 scan.out[0] = SUBMITPIR;
811 x86_32->flush = flush;
812 if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK)
813 return ERROR_FAIL;
814 jtag_add_sleep(DELAY_SUBMITPIR);
815 return ERROR_OK;
816 }
817
818 int lakemont_init_target(struct command_context *cmd_ctx, struct target *t)
819 {
820 lakemont_build_reg_cache(t);
821 t->state = TARGET_RUNNING;
822 t->debug_reason = DBG_REASON_NOTHALTED;
823 return ERROR_OK;
824 }
825
826 int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32)
827 {
828 x86_32->submit_instruction = submit_instruction;
829 x86_32->transaction_status = transaction_status;
830 x86_32->read_hw_reg = read_hw_reg;
831 x86_32->write_hw_reg = write_hw_reg;
832 x86_32->sw_bpts_supported = sw_bpts_supported;
833 x86_32->get_num_user_regs = get_num_user_regs;
834 x86_32->is_paging_enabled = is_paging_enabled;
835 x86_32->disable_paging = disable_paging;
836 x86_32->enable_paging = enable_paging;
837 return ERROR_OK;
838 }
839
840 int lakemont_poll(struct target *t)
841 {
842 /* LMT1 PMCR register currently allows code breakpoints, data breakpoints,
843 * single stepping and shutdowns to be redirected to PM but does not allow
844 * redirecting into PM as a result of SMM enter and SMM exit
845 */
846 uint32_t ts = get_tapstatus(t);
847
848 if (ts == 0xFFFFFFFF && t->state != TARGET_DEBUG_RUNNING) {
849 /* something is wrong here */
850 LOG_ERROR("tapstatus invalid - scan_chain serialization or locked JTAG access issues");
851 /* TODO: Give a hint that unlocking is wrong or maybe a
852 * 'jtag arp_init' helps
853 */
854 t->state = TARGET_DEBUG_RUNNING;
855 return ERROR_OK;
856 }
857
858 if (t->state == TARGET_HALTED && (!(ts & TS_PM_BIT))) {
859 LOG_INFO("target running for unknown reason");
860 t->state = TARGET_RUNNING;
861 }
862
863 if (t->state == TARGET_RUNNING &&
864 t->state != TARGET_DEBUG_RUNNING) {
865
866 if ((ts & TS_PM_BIT) && (ts & TS_PMCR_BIT)) {
867
868 LOG_DEBUG("redirect to PM, tapstatus=%08" PRIx32, get_tapstatus(t));
869
870 t->state = TARGET_DEBUG_RUNNING;
871 if (save_context(t) != ERROR_OK)
872 return ERROR_FAIL;
873 if (halt_prep(t) != ERROR_OK)
874 return ERROR_FAIL;
875 t->state = TARGET_HALTED;
876 t->debug_reason = DBG_REASON_UNDEFINED;
877
878 struct x86_32_common *x86_32 = target_to_x86_32(t);
879 uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
880 uint32_t dr6 = buf_get_u32(x86_32->cache->reg_list[DR6].value, 0, 32);
881 uint32_t hwbreakpoint = (uint32_t)-1;
882
883 if (dr6 & DR6_BRKDETECT_0)
884 hwbreakpoint = 0;
885 if (dr6 & DR6_BRKDETECT_1)
886 hwbreakpoint = 1;
887 if (dr6 & DR6_BRKDETECT_2)
888 hwbreakpoint = 2;
889 if (dr6 & DR6_BRKDETECT_3)
890 hwbreakpoint = 3;
891
892 if (hwbreakpoint != (uint32_t)-1) {
893 uint32_t dr7 = buf_get_u32(x86_32->cache->reg_list[DR7].value, 0, 32);
894 uint32_t type = dr7 & (0x03 << (DR7_RW_SHIFT + hwbreakpoint*DR7_RW_LEN_SIZE));
895 if (type == DR7_BP_EXECUTE) {
896 LOG_USER("hit hardware breakpoint (hwreg=%d) at 0x%08" PRIx32, hwbreakpoint, eip);
897 } else {
898 uint32_t address = 0;
899 switch (hwbreakpoint) {
900 default:
901 case 0:
902 address = buf_get_u32(x86_32->cache->reg_list[DR0].value, 0, 32);
903 break;
904 case 1:
905 address = buf_get_u32(x86_32->cache->reg_list[DR1].value, 0, 32);
906 break;
907 case 2:
908 address = buf_get_u32(x86_32->cache->reg_list[DR2].value, 0, 32);
909 break;
910 case 3:
911 address = buf_get_u32(x86_32->cache->reg_list[DR3].value, 0, 32);
912 break;
913 }
914 LOG_USER("hit '%s' watchpoint for 0x%08" PRIx32 " (hwreg=%d) at 0x%08" PRIx32,
915 type == DR7_BP_WRITE ? "write" : "access", address,
916 hwbreakpoint, eip);
917 }
918 t->debug_reason = DBG_REASON_BREAKPOINT;
919 } else {
920 /* Check if the target hit a software breakpoint.
921 * ! Watch out: EIP is currently pointing after the breakpoint opcode
922 */
923 struct breakpoint *bp = NULL;
924 bp = breakpoint_find(t, eip-1);
925 if (bp != NULL) {
926 t->debug_reason = DBG_REASON_BREAKPOINT;
927 if (bp->type == BKPT_SOFT) {
928 /* The EIP is now pointing the the next byte after the
929 * breakpoint instruction. This needs to be corrected.
930 */
931 buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
932 x86_32->cache->reg_list[EIP].dirty = 1;
933 x86_32->cache->reg_list[EIP].valid = 1;
934 LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
935 } else {
936 /* it's not a hardware breakpoint (checked already in DR6 state)
937 * and it's also not a software breakpoint ...
938 */
939 LOG_USER("hit unknown breakpoint at 0x%08" PRIx32, eip);
940 }
941 } else {
942
943 /* There is also the case that we hit an breakpoint instruction,
944 * which was not set by us. This needs to be handled be the
945 * application that introduced the breakpoint.
946 */
947
948 LOG_USER("unknown break reason at 0x%08" PRIx32, eip);
949 }
950 }
951
952 return target_call_event_callbacks(t, TARGET_EVENT_HALTED);
953 }
954 }
955 return ERROR_OK;
956 }
957
958 int lakemont_arch_state(struct target *t)
959 {
960 struct x86_32_common *x86_32 = target_to_x86_32(t);
961
962 LOG_USER("target halted due to %s at 0x%08" PRIx32 " in %s mode",
963 debug_reason_name(t),
964 buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32),
965 (buf_get_u32(x86_32->cache->reg_list[CR0].value, 0, 32) & CR0_PE) ? "protected" : "real");
966
967 return ERROR_OK;
968 }
969
970 int lakemont_halt(struct target *t)
971 {
972 if (t->state == TARGET_RUNNING) {
973 t->debug_reason = DBG_REASON_DBGRQ;
974 if (do_halt(t) != ERROR_OK)
975 return ERROR_FAIL;
976 return ERROR_OK;
977 } else {
978 LOG_ERROR("%s target not running", __func__);
979 return ERROR_FAIL;
980 }
981 }
982
983 int lakemont_resume(struct target *t, int current, uint32_t address,
984 int handle_breakpoints, int debug_execution)
985 {
986 struct breakpoint *bp = NULL;
987 struct x86_32_common *x86_32 = target_to_x86_32(t);
988
989 if (check_not_halted(t))
990 return ERROR_TARGET_NOT_HALTED;
991 /* TODO lakemont_enable_breakpoints(t); */
992 if (t->state == TARGET_HALTED) {
993
994 /* running away for a software breakpoint needs some special handling */
995 uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
996 bp = breakpoint_find(t, eip);
997 if (bp != NULL /*&& bp->type == BKPT_SOFT*/) {
998 /* the step will step over the breakpoint */
999 if (lakemont_step(t, 0, 0, 1) != ERROR_OK) {
1000 LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " "
1001 "failed to resume the target", __func__, eip);
1002 return ERROR_FAIL;
1003 }
1004 }
1005
1006 /* if breakpoints are enabled, we need to redirect these into probe mode */
1007 struct breakpoint *activeswbp = t->breakpoints;
1008 while (activeswbp != NULL && activeswbp->set == 0)
1009 activeswbp = activeswbp->next;
1010 struct watchpoint *activehwbp = t->watchpoints;
1011 while (activehwbp != NULL && activehwbp->set == 0)
1012 activehwbp = activehwbp->next;
1013 if (activeswbp != NULL || activehwbp != NULL)
1014 buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
1015 if (do_resume(t) != ERROR_OK)
1016 return ERROR_FAIL;
1017 } else {
1018 LOG_USER("target not halted");
1019 return ERROR_FAIL;
1020 }
1021 return ERROR_OK;
1022 }
1023
1024 int lakemont_step(struct target *t, int current,
1025 uint32_t address, int handle_breakpoints)
1026 {
1027 struct x86_32_common *x86_32 = target_to_x86_32(t);
1028 uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
1029 uint32_t eip = buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32);
1030 uint32_t pmcr = buf_get_u32(x86_32->cache->reg_list[PMCR].value, 0, 32);
1031 struct breakpoint *bp = NULL;
1032 int retval = ERROR_OK;
1033 uint32_t tapstatus = 0;
1034
1035 if (check_not_halted(t))
1036 return ERROR_TARGET_NOT_HALTED;
1037 bp = breakpoint_find(t, eip);
1038 if (retval == ERROR_OK && bp != NULL/*&& bp->type == BKPT_SOFT*/) {
1039 /* TODO: This should only be done for software breakpoints.
1040 * Stepping from hardware breakpoints should be possible with the resume flag
1041 * Needs testing.
1042 */
1043 retval = x86_32_common_remove_breakpoint(t, bp);
1044 }
1045
1046 /* Set EFLAGS[TF] and PMCR[IR], exit pm and wait for PRDY# */
1047 LOG_DEBUG("modifying PMCR = %d and EFLAGS = %08" PRIx32, pmcr, eflags);
1048 eflags = eflags | (EFLAGS_TF | EFLAGS_RF);
1049 buf_set_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32, eflags);
1050 buf_set_u32(x86_32->cache->reg_list[PMCR].value, 0, 32, 1);
1051 LOG_DEBUG("EFLAGS [TF] [RF] bits set=%08" PRIx32 ", PMCR=%d, EIP=%08" PRIx32,
1052 eflags, pmcr, eip);
1053
1054 tapstatus = get_tapstatus(t);
1055
1056 t->debug_reason = DBG_REASON_SINGLESTEP;
1057 t->state = TARGET_DEBUG_RUNNING;
1058 if (restore_context(t) != ERROR_OK)
1059 return ERROR_FAIL;
1060 if (exit_probemode(t) != ERROR_OK)
1061 return ERROR_FAIL;
1062
1063 target_call_event_callbacks(t, TARGET_EVENT_RESUMED);
1064
1065 tapstatus = get_tapstatus(t);
1066 if (tapstatus & (TS_PM_BIT | TS_EN_PM_BIT | TS_PRDY_BIT | TS_PMCR_BIT)) {
1067 /* target has stopped */
1068 if (save_context(t) != ERROR_OK)
1069 return ERROR_FAIL;
1070 if (halt_prep(t) != ERROR_OK)
1071 return ERROR_FAIL;
1072 t->state = TARGET_HALTED;
1073
1074 LOG_USER("step done from EIP 0x%08" PRIx32 " to 0x%08" PRIx32, eip,
1075 buf_get_u32(x86_32->cache->reg_list[EIP].value, 0, 32));
1076 target_call_event_callbacks(t, TARGET_EVENT_HALTED);
1077 } else {
1078 /* target didn't stop
1079 * I hope the poll() will catch it, but the deleted breakpoint is gone
1080 */
1081 LOG_ERROR("%s target didn't stop after executing a single step", __func__);
1082 t->state = TARGET_RUNNING;
1083 return ERROR_FAIL;
1084 }
1085
1086 /* try to re-apply the breakpoint, even of step failed
1087 * TODO: When a bp was set, we should try to stop the target - fix the return above
1088 */
1089 if (bp != NULL/*&& bp->type == BKPT_SOFT*/) {
1090 /* TODO: This should only be done for software breakpoints.
1091 * Stepping from hardware breakpoints should be possible with the resume flag
1092 * Needs testing.
1093 */
1094 retval = x86_32_common_add_breakpoint(t, bp);
1095 }
1096
1097 return retval;
1098 }
1099
1100 /* TODO - implement resetbreak fully through CLTAP registers */
1101 int lakemont_reset_assert(struct target *t)
1102 {
1103 LOG_DEBUG("-");
1104 return ERROR_OK;
1105 }
1106
1107 int lakemont_reset_deassert(struct target *t)
1108 {
1109 LOG_DEBUG("-");
1110 return ERROR_OK;
1111 }
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