?  search:
summary | log | graphiclog1 | graphiclog2 | refs | edit | fork

264a45ca6e8bf905b70e9d8842f04ccdf27b276e
[openocd.git] / src / flash / nor / stm32lx.c
blob264a45ca6e8bf905b70e9d8842f04ccdf27b276e
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32lx flash register locations */
37
38 #define FLASH_BASE 0x40023C00
39 #define FLASH_ACR 0x40023C00
40 #define FLASH_PECR 0x40023C04
41 #define FLASH_PDKEYR 0x40023C08
42 #define FLASH_PEKEYR 0x40023C0C
43 #define FLASH_PRGKEYR 0x40023C10
44 #define FLASH_OPTKEYR 0x40023C14
45 #define FLASH_SR 0x40023C18
46 #define FLASH_OBR 0x40023C1C
47 #define FLASH_WRPR 0x40023C20
48
49 /* FLASH_ACR bites */
50 #define FLASH_ACR__LATENCY (1<<0)
51 #define FLASH_ACR__PRFTEN (1<<1)
52 #define FLASH_ACR__ACC64 (1<<2)
53 #define FLASH_ACR__SLEEP_PD (1<<3)
54 #define FLASH_ACR__RUN_PD (1<<4)
55
56 /* FLASH_PECR bits */
57 #define FLASH_PECR__PELOCK (1<<0)
58 #define FLASH_PECR__PRGLOCK (1<<1)
59 #define FLASH_PECR__OPTLOCK (1<<2)
60 #define FLASH_PECR__PROG (1<<3)
61 #define FLASH_PECR__DATA (1<<4)
62 #define FLASH_PECR__FTDW (1<<8)
63 #define FLASH_PECR__ERASE (1<<9)
64 #define FLASH_PECR__FPRG (1<<10)
65 #define FLASH_PECR__EOPIE (1<<16)
66 #define FLASH_PECR__ERRIE (1<<17)
67 #define FLASH_PECR__OBL_LAUNCH (1<<18)
68
69 /* FLASH_SR bits */
70 #define FLASH_SR__BSY (1<<0)
71 #define FLASH_SR__EOP (1<<1)
72 #define FLASH_SR__ENDHV (1<<2)
73 #define FLASH_SR__READY (1<<3)
74 #define FLASH_SR__WRPERR (1<<8)
75 #define FLASH_SR__PGAERR (1<<9)
76 #define FLASH_SR__SIZERR (1<<10)
77 #define FLASH_SR__OPTVERR (1<<11)
78
79 /* Unlock keys */
80 #define PEKEY1 0x89ABCDEF
81 #define PEKEY2 0x02030405
82 #define PRGKEY1 0x8C9DAEBF
83 #define PRGKEY2 0x13141516
84 #define OPTKEY1 0xFBEAD9C8
85 #define OPTKEY2 0x24252627
86
87 /* other registers */
88 #define DBGMCU_IDCODE 0xE0042000
89 #define F_SIZE 0x1FF8004C
90
91 /* Constants */
92 #define FLASH_PAGE_SIZE 256
93 #define FLASH_SECTOR_SIZE 4096
94 #define FLASH_PAGES_PER_SECTOR 16
95 #define FLASH_BANK0_ADDRESS 0x08000000
96
97 /* stm32lx option byte register location */
98 #define OB_RDP 0x1FF80000
99 #define OB_USER 0x1FF80004
100 #define OB_WRP0_1 0x1FF80008
101 #define OB_WRP2_3 0x1FF8000C
102
103 /* OB_RDP values */
104 #define OB_RDP__LEVEL0 0xFF5500AA
105 #define OB_RDP__LEVEL1 0xFFFF0000
106
107 /* stm32lx RCC register locations */
108 #define RCC_CR 0x40023800
109 #define RCC_ICSCR 0x40023804
110 #define RCC_CFGR 0x40023808
111
112 /* RCC_ICSCR bits */
113 #define RCC_ICSCR__MSIRANGE_MASK (7<<13)
114
115 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
116 static int stm32lx_lock_program_memory(struct flash_bank *bank);
117 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
118 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
119 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
120
121 struct stm32lx_flash_bank {
122 int probed;
123 };
124
125 /* flash bank stm32lx <base> <size> 0 0 <target#>
126 */
127 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
128 {
129 struct stm32lx_flash_bank *stm32lx_info;
130 if (CMD_ARGC < 6)
131 return ERROR_COMMAND_SYNTAX_ERROR;
132
133 /* Create the bank structure */
134 stm32lx_info = malloc(sizeof(struct stm32lx_flash_bank));
135
136 /* Check allocation */
137 if (stm32lx_info == NULL) {
138 LOG_ERROR("failed to allocate bank structure");
139 return ERROR_FAIL;
140 }
141
142 bank->driver_priv = stm32lx_info;
143
144 stm32lx_info->probed = 0;
145
146 return ERROR_OK;
147 }
148
149 static int stm32lx_protect_check(struct flash_bank *bank)
150 {
151 int retval;
152 struct target *target = bank->target;
153
154 uint32_t wrpr;
155
156 if (target->state != TARGET_HALTED) {
157 LOG_ERROR("Target not halted");
158 return ERROR_TARGET_NOT_HALTED;
159 }
160
161 /*
162 * Read the WRPR word, and check each bit (corresponding to each
163 * flash sector
164 */
165 retval = target_read_u32(target, FLASH_WRPR, &wrpr);
166 if (retval != ERROR_OK)
167 return retval;
168
169 for (int i = 0; i < 32; i++) {
170 if (wrpr & (1 << i))
171 bank->sectors[i].is_protected = 1;
172 else
173 bank->sectors[i].is_protected = 0;
174 }
175 return ERROR_OK;
176 }
177
178 static int stm32lx_erase(struct flash_bank *bank, int first, int last)
179 {
180 int retval;
181
182 /*
183 * It could be possible to do a mass erase if all sectors must be
184 * erased, but it is not implemented yet.
185 */
186
187 if (bank->target->state != TARGET_HALTED) {
188 LOG_ERROR("Target not halted");
189 return ERROR_TARGET_NOT_HALTED;
190 }
191
192 /*
193 * Loop over the selected sectors and erase them
194 */
195 for (int i = first; i <= last; i++) {
196 retval = stm32lx_erase_sector(bank, i);
197 if (retval != ERROR_OK)
198 return retval;
199 bank->sectors[i].is_erased = 1;
200 }
201 return ERROR_OK;
202 }
203
204 static int stm32lx_protect(struct flash_bank *bank, int set, int first,
205 int last)
206 {
207 LOG_WARNING("protection of the STM32L flash is not implemented");
208 return ERROR_OK;
209 }
210
211 static int stm32lx_write_half_pages(struct flash_bank *bank, uint8_t *buffer,
212 uint32_t offset, uint32_t count)
213 {
214 struct target *target = bank->target;
215 uint32_t buffer_size = 16384;
216 struct working_area *write_algorithm;
217 struct working_area *source;
218 uint32_t address = bank->base + offset;
219
220 struct reg_param reg_params[3];
221 struct armv7m_algorithm armv7m_info;
222
223 int retval = ERROR_OK;
224
225 /* see contib/loaders/flash/stm32lx.S for src */
226
227 static const uint8_t stm32lx_flash_write_code[] = {
228 /* write_word: */
229 0x00, 0x23, /* movs r3, #0 */
230 0x04, 0xe0, /* b test_done */
231
232 /* write_word: */
233 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
234 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
235 0x01, 0x33, /* adds r3, #1 */
236
237 /* test_done: */
238 0x93, 0x42, /* cmp r3, r2 */
239 0xf8, 0xd3, /* bcc write_word */
240 0x00, 0xbe, /* bkpt 0 */
241 };
242
243 /* Check if there is an even number of half pages (128bytes) */
244 if (count % 128) {
245 LOG_ERROR("there should be an even number "
246 "of half pages = 128 bytes (count = %" PRIi32 " bytes)", count);
247 return ERROR_FAIL;
248 }
249
250 /* flash write code */
251 if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
252 &write_algorithm) != ERROR_OK) {
253 LOG_DEBUG("no working area for block memory writes");
254 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
255 };
256
257 /* Write the flashing code */
258 retval = target_write_buffer(target,
259 write_algorithm->address,
260 sizeof(stm32lx_flash_write_code),
261 (uint8_t *)stm32lx_flash_write_code);
262 if (retval != ERROR_OK) {
263 target_free_working_area(target, write_algorithm);
264 return retval;
265 }
266
267 /* Allocate half pages memory */
268 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
269 if (buffer_size > 1024)
270 buffer_size -= 1024;
271 else
272 buffer_size /= 2;
273
274 if (buffer_size <= 256) {
275 /* we already allocated the writing code, but failed to get a
276 * buffer, free the algorithm */
277 target_free_working_area(target, write_algorithm);
278
279 LOG_WARNING("no large enough working area available, can't do block memory writes");
280 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
281 }
282 }
283
284 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
285 armv7m_info.core_mode = ARMV7M_MODE_ANY;
286 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
287 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
288 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
289
290 /* Enable half-page write */
291 retval = stm32lx_enable_write_half_page(bank);
292 if (retval != ERROR_OK) {
293 target_free_working_area(target, source);
294 target_free_working_area(target, write_algorithm);
295
296 destroy_reg_param(&reg_params[0]);
297 destroy_reg_param(&reg_params[1]);
298 destroy_reg_param(&reg_params[2]);
299 return retval;
300 }
301
302 /* Loop while there are bytes to write */
303 while (count > 0) {
304 uint32_t this_count;
305 this_count = (count > buffer_size) ? buffer_size : count;
306
307 /* Write the next half pages */
308 retval = target_write_buffer(target, source->address, this_count, buffer);
309 if (retval != ERROR_OK)
310 break;
311
312 /* 4: Store useful information in the registers */
313 /* the destination address of the copy (R0) */
314 buf_set_u32(reg_params[0].value, 0, 32, address);
315 /* The source address of the copy (R1) */
316 buf_set_u32(reg_params[1].value, 0, 32, source->address);
317 /* The length of the copy (R2) */
318 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
319
320 /* 5: Execute the bunch of code */
321 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
322 / sizeof(*reg_params), reg_params,
323 write_algorithm->address, 0, 10000, &armv7m_info);
324 if (retval != ERROR_OK)
325 break;
326
327 /* 6: Wait while busy */
328 retval = stm32lx_wait_until_bsy_clear(bank);
329 if (retval != ERROR_OK)
330 break;
331
332 buffer += this_count;
333 address += this_count;
334 count -= this_count;
335 }
336
337 if (retval == ERROR_OK)
338 retval = stm32lx_lock_program_memory(bank);
339
340 target_free_working_area(target, source);
341 target_free_working_area(target, write_algorithm);
342
343 destroy_reg_param(&reg_params[0]);
344 destroy_reg_param(&reg_params[1]);
345 destroy_reg_param(&reg_params[2]);
346
347 return retval;
348 }
349
350 static int stm32lx_write(struct flash_bank *bank, uint8_t *buffer,
351 uint32_t offset, uint32_t count)
352 {
353 struct target *target = bank->target;
354
355 uint32_t halfpages_number;
356 uint32_t bytes_remaining = 0;
357 uint32_t address = bank->base + offset;
358 uint32_t bytes_written = 0;
359 int retval, retval2;
360
361 if (bank->target->state != TARGET_HALTED) {
362 LOG_ERROR("Target not halted");
363 return ERROR_TARGET_NOT_HALTED;
364 }
365
366 if (offset & 0x3) {
367 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
368 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
369 }
370
371 retval = stm32lx_unlock_program_memory(bank);
372 if (retval != ERROR_OK)
373 return retval;
374
375 /* first we need to write any unaligned head bytes upto
376 * the next 128 byte page */
377
378 if (offset % 128)
379 bytes_remaining = MIN(count, 128 - (offset % 128));
380
381 while (bytes_remaining > 0) {
382 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
383
384 /* copy remaining bytes into the write buffer */
385 uint32_t bytes_to_write = MIN(4, bytes_remaining);
386 memcpy(value, buffer + bytes_written, bytes_to_write);
387
388 retval = target_write_buffer(target, address, 4, value);
389 if (retval != ERROR_OK)
390 goto reset_pg_and_lock;
391
392 bytes_written += bytes_to_write;
393 bytes_remaining -= bytes_to_write;
394 address += 4;
395
396 retval = stm32lx_wait_until_bsy_clear(bank);
397 if (retval != ERROR_OK)
398 goto reset_pg_and_lock;
399 }
400
401 offset += bytes_written;
402 count -= bytes_written;
403
404 /* this should always pass this check here */
405 assert((offset % 128) == 0);
406
407 /* calculate half pages */
408 halfpages_number = count / 128;
409
410 if (halfpages_number) {
411 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, 128 * halfpages_number);
412 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
413 /* attempt slow memory writes */
414 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
415 halfpages_number = 0;
416 } else {
417 if (retval != ERROR_OK)
418 return ERROR_FAIL;
419 }
420 }
421
422 /* write any remaining bytes */
423 uint32_t page_bytes_written = 128 * halfpages_number;
424 bytes_written += page_bytes_written;
425 address += page_bytes_written;
426 bytes_remaining = count - page_bytes_written;
427
428 retval = stm32lx_unlock_program_memory(bank);
429 if (retval != ERROR_OK)
430 return retval;
431
432 while (bytes_remaining > 0) {
433 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
434
435 /* copy remaining bytes into the write buffer */
436 uint32_t bytes_to_write = MIN(4, bytes_remaining);
437 memcpy(value, buffer + bytes_written, bytes_to_write);
438
439 retval = target_write_buffer(target, address, 4, value);
440 if (retval != ERROR_OK)
441 goto reset_pg_and_lock;
442
443 bytes_written += bytes_to_write;
444 bytes_remaining -= bytes_to_write;
445 address += 4;
446
447 retval = stm32lx_wait_until_bsy_clear(bank);
448 if (retval != ERROR_OK)
449 goto reset_pg_and_lock;
450 }
451
452 reset_pg_and_lock:
453 retval2 = stm32lx_lock_program_memory(bank);
454 if (retval == ERROR_OK)
455 retval = retval2;
456
457 return retval;
458 }
459
460 static int stm32lx_probe(struct flash_bank *bank)
461 {
462 struct target *target = bank->target;
463 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
464 int i;
465 uint16_t flash_size_in_kb;
466 uint16_t max_flash_size_in_kb;
467 uint32_t device_id;
468
469 stm32lx_info->probed = 0;
470
471 /* read stm32 device id register */
472 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
473 if (retval != ERROR_OK)
474 return retval;
475
476 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
477
478 /* set max flash size depending on family */
479 switch (device_id & 0xfff) {
480 case 0x416:
481 max_flash_size_in_kb = 128;
482 break;
483 case 0x436:
484 max_flash_size_in_kb = 384;
485 break;
486 default:
487 LOG_WARNING("Cannot identify target as a STM32L family.");
488 return ERROR_FAIL;
489 }
490
491 /* get flash size from target. */
492 retval = target_read_u16(target, F_SIZE, &flash_size_in_kb);
493
494 /* failed reading flash size or flash size invalid (early silicon),
495 * default to max target family */
496 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
497 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
498 max_flash_size_in_kb);
499 flash_size_in_kb = max_flash_size_in_kb;
500 }
501
502 /* STM32L - we have 32 sectors, 16 pages per sector -> 512 pages
503 * 16 pages for a protection area */
504
505 /* calculate numbers of sectors (4kB per sector) */
506 int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
507 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
508
509 if (bank->sectors) {
510 free(bank->sectors);
511 bank->sectors = NULL;
512 }
513
514 bank->base = FLASH_BANK0_ADDRESS;
515 bank->size = flash_size_in_kb * 1024;
516 bank->num_sectors = num_sectors;
517 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
518 if (bank->sectors == NULL) {
519 LOG_ERROR("failed to allocate bank sectors");
520 return ERROR_FAIL;
521 }
522
523 for (i = 0; i < num_sectors; i++) {
524 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
525 bank->sectors[i].size = FLASH_SECTOR_SIZE;
526 bank->sectors[i].is_erased = -1;
527 bank->sectors[i].is_protected = 1;
528 }
529
530 stm32lx_info->probed = 1;
531
532 return ERROR_OK;
533 }
534
535 static int stm32lx_auto_probe(struct flash_bank *bank)
536 {
537 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
538
539 if (stm32lx_info->probed)
540 return ERROR_OK;
541
542 return stm32lx_probe(bank);
543 }
544
545 static int stm32lx_erase_check(struct flash_bank *bank)
546 {
547 struct target *target = bank->target;
548 const int buffer_size = 4096;
549 int i;
550 uint32_t nBytes;
551 int retval = ERROR_OK;
552
553 if (bank->target->state != TARGET_HALTED) {
554 LOG_ERROR("Target not halted");
555 return ERROR_TARGET_NOT_HALTED;
556 }
557
558 uint8_t *buffer = malloc(buffer_size);
559 if (buffer == NULL) {
560 LOG_ERROR("failed to allocate read buffer");
561 return ERROR_FAIL;
562 }
563
564 for (i = 0; i < bank->num_sectors; i++) {
565 uint32_t j;
566 bank->sectors[i].is_erased = 1;
567
568 /* Loop chunk by chunk over the sector */
569 for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
570 uint32_t chunk;
571 chunk = buffer_size;
572 if (chunk > (j - bank->sectors[i].size))
573 chunk = (j - bank->sectors[i].size);
574
575 retval = target_read_memory(target, bank->base
576 + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
577 if (retval != ERROR_OK)
578 break;
579
580 for (nBytes = 0; nBytes < chunk; nBytes++) {
581 if (buffer[nBytes] != 0x00) {
582 bank->sectors[i].is_erased = 0;
583 break;
584 }
585 }
586 }
587 if (retval != ERROR_OK)
588 break;
589 }
590 free(buffer);
591
592 return retval;
593 }
594
595 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
596 {
597 /* This method must return a string displaying information about the bank */
598
599 struct target *target = bank->target;
600 uint32_t device_id;
601 int printed;
602
603 /* read stm32 device id register */
604 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
605 if (retval != ERROR_OK)
606 return retval;
607
608 if ((device_id & 0xfff) == 0x416) {
609 printed = snprintf(buf, buf_size, "stm32lx - Rev: ");
610 buf += printed;
611 buf_size -= printed;
612
613 switch (device_id >> 16) {
614 case 0x1000:
615 snprintf(buf, buf_size, "A");
616 break;
617
618 case 0x1008:
619 snprintf(buf, buf_size, "Y");
620 break;
621
622 case 0x1018:
623 snprintf(buf, buf_size, "X");
624 break;
625
626 case 0x1038:
627 snprintf(buf, buf_size, "W");
628 break;
629
630 case 0x1078:
631 snprintf(buf, buf_size, "V");
632 break;
633
634 default:
635 snprintf(buf, buf_size, "unknown");
636 break;
637 }
638 } else if ((device_id & 0xfff) == 0x436) {
639 printed = snprintf(buf, buf_size, "stm32lx (HD) - Rev: ");
640 buf += printed;
641 buf_size -= printed;
642
643 switch (device_id >> 16) {
644 case 0x1000:
645 snprintf(buf, buf_size, "A");
646 break;
647
648 case 0x1008:
649 snprintf(buf, buf_size, "Z");
650 break;
651
652 case 0x1018:
653 snprintf(buf, buf_size, "Y");
654 break;
655
656 default:
657 snprintf(buf, buf_size, "unknown");
658 break;
659 }
660 } else {
661 snprintf(buf, buf_size, "Cannot identify target as a stm32lx");
662 return ERROR_FAIL;
663 }
664
665 return ERROR_OK;
666 }
667
668 static const struct command_registration stm32lx_exec_command_handlers[] = {
669 COMMAND_REGISTRATION_DONE
670 };
671
672 static const struct command_registration stm32lx_command_handlers[] = {
673 {
674 .name = "stm32lx",
675 .mode = COMMAND_ANY,
676 .help = "stm32lx flash command group",
677 .usage = "",
678 .chain = stm32lx_exec_command_handlers,
679 },
680 COMMAND_REGISTRATION_DONE
681 };
682
683 struct flash_driver stm32lx_flash = {
684 .name = "stm32lx",
685 .commands = stm32lx_command_handlers,
686 .flash_bank_command = stm32lx_flash_bank_command,
687 .erase = stm32lx_erase,
688 .protect = stm32lx_protect,
689 .write = stm32lx_write,
690 .read = default_flash_read,
691 .probe = stm32lx_probe,
692 .auto_probe = stm32lx_auto_probe,
693 .erase_check = stm32lx_erase_check,
694 .protect_check = stm32lx_protect_check,
695 .info = stm32lx_get_info,
696 };
697
698 /* Static methods implementation */
699 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
700 {
701 struct target *target = bank->target;
702 int retval;
703 uint32_t reg32;
704
705 /*
706 * Unlocking the program memory is done by unlocking the PECR,
707 * then by writing the 2 PRGKEY to the PRGKEYR register
708 */
709
710 /* check flash is not already unlocked */
711 retval = target_read_u32(target, FLASH_PECR, &reg32);
712 if (retval != ERROR_OK)
713 return retval;
714
715 if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
716 return ERROR_OK;
717
718 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
719 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY1);
720 if (retval != ERROR_OK)
721 return retval;
722
723 retval = target_write_u32(target, FLASH_PEKEYR, PEKEY2);
724 if (retval != ERROR_OK)
725 return retval;
726
727 /* Make sure it worked */
728 retval = target_read_u32(target, FLASH_PECR, &reg32);
729 if (retval != ERROR_OK)
730 return retval;
731
732 if (reg32 & FLASH_PECR__PELOCK) {
733 LOG_ERROR("PELOCK is not cleared :(");
734 return ERROR_FLASH_OPERATION_FAILED;
735 }
736
737 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY1);
738 if (retval != ERROR_OK)
739 return retval;
740 retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY2);
741 if (retval != ERROR_OK)
742 return retval;
743
744 /* Make sure it worked */
745 retval = target_read_u32(target, FLASH_PECR, &reg32);
746 if (retval != ERROR_OK)
747 return retval;
748
749 if (reg32 & FLASH_PECR__PRGLOCK) {
750 LOG_ERROR("PRGLOCK is not cleared :(");
751 return ERROR_FLASH_OPERATION_FAILED;
752 }
753
754 return ERROR_OK;
755 }
756
757 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
758 {
759 struct target *target = bank->target;
760 int retval;
761 uint32_t reg32;
762
763 /**
764 * Unlock the program memory, then set the FPRG bit in the PECR register.
765 */
766 retval = stm32lx_unlock_program_memory(bank);
767 if (retval != ERROR_OK)
768 return retval;
769
770 retval = target_read_u32(target, FLASH_PECR, &reg32);
771 if (retval != ERROR_OK)
772 return retval;
773
774 reg32 |= FLASH_PECR__FPRG;
775 retval = target_write_u32(target, FLASH_PECR, reg32);
776 if (retval != ERROR_OK)
777 return retval;
778
779 retval = target_read_u32(target, FLASH_PECR, &reg32);
780 if (retval != ERROR_OK)
781 return retval;
782
783 reg32 |= FLASH_PECR__PROG;
784 retval = target_write_u32(target, FLASH_PECR, reg32);
785
786 return retval;
787 }
788
789 static int stm32lx_lock_program_memory(struct flash_bank *bank)
790 {
791 struct target *target = bank->target;
792 int retval;
793 uint32_t reg32;
794
795 /* To lock the program memory, simply set the lock bit and lock PECR */
796
797 retval = target_read_u32(target, FLASH_PECR, &reg32);
798 if (retval != ERROR_OK)
799 return retval;
800
801 reg32 |= FLASH_PECR__PRGLOCK;
802 retval = target_write_u32(target, FLASH_PECR, reg32);
803 if (retval != ERROR_OK)
804 return retval;
805
806 retval = target_read_u32(target, FLASH_PECR, &reg32);
807 if (retval != ERROR_OK)
808 return retval;
809
810 reg32 |= FLASH_PECR__PELOCK;
811 retval = target_write_u32(target, FLASH_PECR, reg32);
812 if (retval != ERROR_OK)
813 return retval;
814
815 return ERROR_OK;
816 }
817
818 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
819 {
820 struct target *target = bank->target;
821 int retval;
822 uint32_t reg32;
823
824 /*
825 * To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
826 * first unlock the memory, loop over the pages of this sector
827 * and write 0x0 to its first word.
828 */
829
830 retval = stm32lx_unlock_program_memory(bank);
831 if (retval != ERROR_OK)
832 return retval;
833
834 for (int page = 0; page < FLASH_PAGES_PER_SECTOR; page++) {
835 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
836 retval = target_write_u32(target, FLASH_PECR, reg32);
837 if (retval != ERROR_OK)
838 return retval;
839
840 retval = stm32lx_wait_until_bsy_clear(bank);
841 if (retval != ERROR_OK)
842 return retval;
843
844 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
845 * FLASH_PAGE_SIZE);
846 retval = target_write_u32(target, addr, 0x0);
847 if (retval != ERROR_OK)
848 return retval;
849
850 retval = stm32lx_wait_until_bsy_clear(bank);
851 if (retval != ERROR_OK)
852 return retval;
853 }
854
855 retval = stm32lx_lock_program_memory(bank);
856 if (retval != ERROR_OK)
857 return retval;
858
859 return ERROR_OK;
860 }
861
862 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
863 {
864 struct target *target = bank->target;
865 uint32_t status;
866 int retval = ERROR_OK;
867 int timeout = 100;
868
869 /* wait for busy to clear */
870 for (;;) {
871 retval = target_read_u32(target, FLASH_SR, &status);
872 if (retval != ERROR_OK)
873 return retval;
874
875 if ((status & FLASH_SR__BSY) == 0)
876 break;
877 if (timeout-- <= 0) {
878 LOG_ERROR("timed out waiting for flash");
879 return ERROR_FAIL;
880 }
881 alive_sleep(1);
882 }
883
884 if (status & FLASH_SR__WRPERR) {
885 LOG_ERROR("access denied / write protected");
886 retval = ERROR_FAIL;
887 }
888
889 if (status & FLASH_SR__PGAERR) {
890 LOG_ERROR("invalid program address");
891 retval = ERROR_FAIL;
892 }
893
894 return retval;
895 }
Official OpenOCD Mirror