| blob | 958cbcb29f6c89aa4df0348e472f6a071df0fc11 |
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 if (TARGET_ARM) \
35 else \
37 \
38 if (TARGET_BIG_END) \
39 { \
41 if (TARGET_THUMB) \
43 if (TARGET_LITTLE_WORDS) \
45 } \
46 else \
47 { \
49 if (TARGET_THUMB) \
51 } \
52 \
53 if (TARGET_APCS_32) \
55 else \
57 \
58 if (TARGET_SOFT_FLOAT) \
60 \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
65 \
66 /* Add a define for interworking. \
68 if (TARGET_INTERWORK) \
70 \
73 } while (0)
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 #define TARGET_CPU_ep9312 0x0200
100 #define TARGET_CPU_iwmmxt 0x0400
101 /* Configure didn't specify. */
102 #define TARGET_CPU_generic 0x8000
105 {
108 }
109 arm_cc;
113 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
118 /* Run-time compilation parameters selecting different hardware subsets. */
120 /* The floating point instruction architecture, can be 2 or 3 */
122 /* Define the information needed to generate branch insns. This is
123 stored from the compare operation. */
126 /* The label of the current constant pool. */
128 /* Set to 1 when a return insn is output, this means that the epilogue
129 is not needed. */
131 /* Used to produce AOF syntax assembler. */
133 \f
134 /* Just in case configure has failed to define anything. */
135 #ifndef TARGET_CPU_DEFAULT
136 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
137 #endif
139 /* If the configuration file doesn't specify the cpu, the subtarget may
140 override it. If it doesn't, then default to an ARM6. */
141 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
142 #undef TARGET_CPU_DEFAULT
144 #ifdef SUBTARGET_CPU_DEFAULT
145 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
146 #else
147 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
148 #endif
149 #endif
151 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
153 #else
154 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
156 #else
157 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
159 #else
160 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
162 #else
163 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
165 #else
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
168 #else
169 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
171 /* Set TARGET_DEFAULT to the default, but without soft-float. */
172 #ifdef TARGET_DEFAULT
173 #undef TARGET_DEFAULT
174 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
175 #endif
176 #else
177 #if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
179 #else
180 #error Unrecognized value in TARGET_CPU_DEFAULT.
181 #endif
182 #endif
183 #endif
184 #endif
185 #endif
186 #endif
187 #endif
188 #endif
190 #undef CPP_SPEC
192 %{mapcs-32:%{mapcs-26: \
193 %e-mapcs-26 and -mapcs-32 may not be used together}} \
194 %{msoft-float:%{mhard-float: \
195 %e-msoft-float and -mhard_float may not be used together}} \
196 %{mbig-endian:%{mlittle-endian: \
197 %e-mbig-endian and -mlittle-endian may not be used together}}"
199 /* Set the architecture define -- if -march= is set, then it overrides
200 the -mcpu= setting. */
202 %{march=arm2:-D__ARM_ARCH_2__} \
203 %{march=arm250:-D__ARM_ARCH_2__} \
204 %{march=arm3:-D__ARM_ARCH_2__} \
205 %{march=arm6:-D__ARM_ARCH_3__} \
206 %{march=arm600:-D__ARM_ARCH_3__} \
207 %{march=arm610:-D__ARM_ARCH_3__} \
208 %{march=arm7:-D__ARM_ARCH_3__} \
209 %{march=arm700:-D__ARM_ARCH_3__} \
210 %{march=arm710:-D__ARM_ARCH_3__} \
211 %{march=arm720:-D__ARM_ARCH_3__} \
212 %{march=arm7100:-D__ARM_ARCH_3__} \
213 %{march=arm7500:-D__ARM_ARCH_3__} \
214 %{march=arm7500fe:-D__ARM_ARCH_3__} \
215 %{march=arm7m:-D__ARM_ARCH_3M__} \
216 %{march=arm7dm:-D__ARM_ARCH_3M__} \
217 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
218 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
219 %{march=arm8:-D__ARM_ARCH_4__} \
220 %{march=arm810:-D__ARM_ARCH_4__} \
221 %{march=arm9:-D__ARM_ARCH_4T__} \
222 %{march=arm920:-D__ARM_ARCH_4__} \
223 %{march=arm920t:-D__ARM_ARCH_4T__} \
224 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
225 %{march=strongarm:-D__ARM_ARCH_4__} \
226 %{march=strongarm110:-D__ARM_ARCH_4__} \
227 %{march=strongarm1100:-D__ARM_ARCH_4__} \
228 %{march=xscale:-D__ARM_ARCH_5TE__} \
229 %{march=xscale:-D__XSCALE__} \
230 %{march=ep9312:-D__ARM_ARCH_4T__} \
231 %{march=ep9312:-D__MAVERICK__} \
232 %{march=armv2:-D__ARM_ARCH_2__} \
233 %{march=armv2a:-D__ARM_ARCH_2__} \
234 %{march=armv3:-D__ARM_ARCH_3__} \
235 %{march=armv3m:-D__ARM_ARCH_3M__} \
236 %{march=armv4:-D__ARM_ARCH_4__} \
237 %{march=armv4t:-D__ARM_ARCH_4T__} \
238 %{march=armv5:-D__ARM_ARCH_5__} \
239 %{march=armv5t:-D__ARM_ARCH_5T__} \
240 %{march=armv5e:-D__ARM_ARCH_5E__} \
241 %{march=armv5te:-D__ARM_ARCH_5TE__} \
242 %{!march=*: \
243 %{mcpu=arm2:-D__ARM_ARCH_2__} \
244 %{mcpu=arm250:-D__ARM_ARCH_2__} \
245 %{mcpu=arm3:-D__ARM_ARCH_2__} \
246 %{mcpu=arm6:-D__ARM_ARCH_3__} \
247 %{mcpu=arm600:-D__ARM_ARCH_3__} \
248 %{mcpu=arm610:-D__ARM_ARCH_3__} \
249 %{mcpu=arm7:-D__ARM_ARCH_3__} \
250 %{mcpu=arm700:-D__ARM_ARCH_3__} \
251 %{mcpu=arm710:-D__ARM_ARCH_3__} \
252 %{mcpu=arm720:-D__ARM_ARCH_3__} \
253 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
254 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
255 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
256 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
257 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
258 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
259 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
260 %{mcpu=arm8:-D__ARM_ARCH_4__} \
261 %{mcpu=arm810:-D__ARM_ARCH_4__} \
262 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
263 %{mcpu=arm920:-D__ARM_ARCH_4__} \
264 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
265 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
266 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
267 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
268 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
269 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
270 %{mcpu=xscale:-D__XSCALE__} \
271 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
272 %{mcpu=ep9312:-D__MAVERICK__} \
273 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
274 %{mcpu=iwmmxt:-D__XSCALE__} \
275 %{mcpu=iwmmxt:-D__IWMMXT__} \
276 %{!mcpu*:%(cpp_cpu_arch_default)}} \
277 "
279 #ifndef CC1_SPEC
281 #endif
283 /* This macro defines names of additional specifications to put in the specs
284 that can be used in various specifications like CC1_SPEC. Its definition
285 is an initializer with a subgrouping for each command option.
287 Each subgrouping contains a string constant, that defines the
288 specification name, and a string constant that used by the GCC driver
289 program.
291 Do not define this macro if it does not need to do anything. */
292 #define EXTRA_SPECS \
296 SUBTARGET_EXTRA_SPECS
298 #ifndef SUBTARGET_EXTRA_SPECS
299 #define SUBTARGET_EXTRA_SPECS
300 #endif
302 #ifndef SUBTARGET_CPP_SPEC
304 #endif
305 \f
306 /* Run-time Target Specification. */
307 #ifndef TARGET_VERSION
309 #endif
311 /* Nonzero if the function prologue (and epilogue) should obey
312 the ARM Procedure Call Standard. */
313 #define ARM_FLAG_APCS_FRAME (1 << 0)
315 /* Nonzero if the function prologue should output the function name to enable
316 the post mortem debugger to print a backtrace (very useful on RISCOS,
317 unused on RISCiX). Specifying this flag also enables
318 -fno-omit-frame-pointer.
319 XXX Must still be implemented in the prologue. */
320 #define ARM_FLAG_POKE (1 << 1)
322 /* Nonzero if floating point instructions are emulated by the FPE, in which
323 case instruction scheduling becomes very uninteresting. */
324 #define ARM_FLAG_FPE (1 << 2)
326 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
327 that assume restoration of the condition flags when returning from a
328 branch and link (ie a function). */
329 #define ARM_FLAG_APCS_32 (1 << 3)
331 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
333 /* Nonzero if stack checking should be performed on entry to each function
334 which allocates temporary variables on the stack. */
335 #define ARM_FLAG_APCS_STACK (1 << 4)
337 /* Nonzero if floating point parameters should be passed to functions in
338 floating point registers. */
339 #define ARM_FLAG_APCS_FLOAT (1 << 5)
341 /* Nonzero if re-entrant, position independent code should be generated.
342 This is equivalent to -fpic. */
343 #define ARM_FLAG_APCS_REENT (1 << 6)
345 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
346 be loaded using either LDRH or LDRB instructions. */
347 #define ARM_FLAG_MMU_TRAPS (1 << 7)
349 /* Nonzero if all floating point instructions are missing (and there is no
350 emulator either). Generate function calls for all ops in this case. */
351 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
353 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
354 #define ARM_FLAG_BIG_END (1 << 9)
356 /* Nonzero if we should compile for Thumb interworking. */
357 #define ARM_FLAG_INTERWORK (1 << 10)
359 /* Nonzero if we should have little-endian words even when compiling for
360 big-endian (for backwards compatibility with older versions of GCC). */
361 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
363 /* Nonzero if we need to protect the prolog from scheduling */
364 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
366 /* Nonzero if a call to abort should be generated if a noreturn
367 function tries to return. */
368 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
370 /* Nonzero if function prologues should not load the PIC register. */
371 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
373 /* Nonzero if all call instructions should be indirect. */
374 #define ARM_FLAG_LONG_CALLS (1 << 15)
376 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
377 #define ARM_FLAG_THUMB (1 << 16)
379 /* Set if a TPCS style stack frame should be generated, for non-leaf
380 functions, even if they do not need one. */
381 #define THUMB_FLAG_BACKTRACE (1 << 17)
383 /* Set if a TPCS style stack frame should be generated, for leaf
384 functions, even if they do not need one. */
385 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
387 /* Set if externally visible functions should assume that they
388 might be called in ARM mode, from a non-thumb aware code. */
389 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
391 /* Set if calls via function pointers should assume that their
392 destination is non-Thumb aware. */
393 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
395 /* Nonzero means target uses VFP FP. */
396 #define ARM_FLAG_VFP (1 << 21)
398 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
399 #define ARM_FLAG_ATPCS (1 << 22)
401 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
402 #define CIRRUS_FIX_INVALID_INSNS (1 << 23)
404 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
405 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
406 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
407 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
408 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
409 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
410 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
411 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
412 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
413 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
414 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
415 #define TARGET_CIRRUS (arm_is_cirrus)
416 #define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS)
417 #define TARGET_IWMMXT (arm_arch_iwmmxt)
418 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
419 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
420 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
421 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
422 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
423 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
424 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
425 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
426 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
427 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
428 #define TARGET_ARM (! TARGET_THUMB)
430 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
431 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
432 #define TARGET_BACKTRACE (leaf_function_p () \
433 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
434 : (target_flags & THUMB_FLAG_BACKTRACE))
435 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
437 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
438 #ifndef SUBTARGET_SWITCHES
439 #define SUBTARGET_SWITCHES
440 #endif
442 #define TARGET_SWITCHES \
443 { \
518 SUBTARGET_SWITCHES \
520 }
522 #define TARGET_OPTIONS \
523 { \
536 }
538 /* Support for a compile-time default CPU, et cetera. The rules are:
539 --with-arch is ignored if -march or -mcpu are specified.
540 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
541 by --with-arch.
542 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
543 by -march).
544 --with-float is ignored if -mhard-float or -msoft-float are
545 specified. */
546 #define OPTION_DEFAULT_SPECS \
552 struct arm_cpu_select
553 {
557 };
559 /* This is a magic array. If the user specifies a command line switch
560 which matches one of the entries in TARGET_OPTIONS then the corresponding
561 string pointer will be set to the value specified by the user. */
564 enum prog_mode_type
565 {
566 prog_mode26,
567 prog_mode32
568 };
570 /* Recast the program mode class to be the prog_mode attribute */
571 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
575 /* What sort of floating point unit do we have? Hardware or software.
576 If software, is it issue 2 or issue 3? */
577 enum fputype
578 {
579 /* Software floating point, FPA style double fmt. */
580 FPUTYPE_SOFT_FPA,
581 /* Full FPA support. */
582 FPUTYPE_FPA,
583 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
584 FPUTYPE_FPA_EMU2,
585 /* Emulated FPA hardware, Issue 3 emulator. */
586 FPUTYPE_FPA_EMU3,
587 /* Cirrus Maverick floating point co-processor. */
588 FPUTYPE_MAVERICK
589 };
591 /* Recast the floating point class to be the floating point attribute. */
592 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
594 /* What type of floating point to tune for */
597 /* What type of floating point instructions are available */
600 /* Default floating point architecture. Override in sub-target if
601 necessary. */
602 #ifndef FPUTYPE_DEFAULT
603 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
604 #endif
606 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
607 #undef FPUTYPE_DEFAULT
608 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
609 #endif
611 /* Nonzero if the processor has a fast multiply insn, and one that does
612 a 64-bit multiply of two 32-bit values. */
615 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
618 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
621 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
624 /* Nonzero if this chip can benefit from load scheduling. */
627 /* Nonzero if generating thumb code. */
630 /* Nonzero if this chip is a StrongARM. */
633 /* Nonzero if this chip is a Cirrus variant. */
636 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
639 /* Nonzero if this chip is an XScale. */
642 /* Nonzero if tuning for XScale */
645 /* Nonzero if this chip is an ARM6 or an ARM7. */
648 #ifndef TARGET_DEFAULT
649 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
650 #endif
652 /* The frame pointer register used in gcc has nothing to do with debugging;
653 that is controlled by the APCS-FRAME option. */
654 #define CAN_DEBUG_WITHOUT_FP
656 #undef TARGET_MEM_FUNCTIONS
657 #define TARGET_MEM_FUNCTIONS 1
659 #define OVERRIDE_OPTIONS arm_override_options ()
661 /* Nonzero if PIC code requires explicit qualifiers to generate
662 PLT and GOT relocs rather than the assembler doing so implicitly.
663 Subtargets can override these if required. */
664 #ifndef NEED_GOT_RELOC
665 #define NEED_GOT_RELOC 0
666 #endif
667 #ifndef NEED_PLT_RELOC
668 #define NEED_PLT_RELOC 0
669 #endif
671 /* Nonzero if we need to refer to the GOT with a PC-relative
672 offset. In other words, generate
674 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
676 rather than
678 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
680 The default is true, which matches NetBSD. Subtargets can
681 override this if required. */
682 #ifndef GOT_PCREL
683 #define GOT_PCREL 1
684 #endif
685 \f
686 /* Target machine storage Layout. */
689 /* Define this macro if it is advisable to hold scalars in registers
690 in a wider mode than that declared by the program. In such cases,
691 the value is constrained to be within the bounds of the declared
692 type, but kept valid in the wider mode. The signedness of the
693 extension may differ from that of the type. */
695 /* It is far faster to zero extend chars than to sign extend them */
697 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
698 if (GET_MODE_CLASS (MODE) == MODE_INT \
699 && GET_MODE_SIZE (MODE) < 4) \
700 { \
701 if (MODE == QImode) \
702 UNSIGNEDP = 1; \
703 else if (MODE == HImode) \
704 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
705 (MODE) = SImode; \
706 }
708 /* Define this macro if the promotion described by `PROMOTE_MODE'
709 should also be done for outgoing function arguments. */
710 /* This is required to ensure that push insns always push a word. */
711 #define PROMOTE_FUNCTION_ARGS
713 /* Define this if most significant bit is lowest numbered
714 in instructions that operate on numbered bit-fields. */
715 #define BITS_BIG_ENDIAN 0
717 /* Define this if most significant byte of a word is the lowest numbered.
718 Most ARM processors are run in little endian mode, so that is the default.
719 If you want to have it run-time selectable, change the definition in a
720 cover file to be TARGET_BIG_ENDIAN. */
721 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
723 /* Define this if most significant word of a multiword number is the lowest
724 numbered.
725 This is always false, even when in big-endian mode. */
726 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
728 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
729 on processor pre-defineds when compiling libgcc2.c. */
730 #if defined(__ARMEB__) && !defined(__ARMWEL__)
731 #define LIBGCC2_WORDS_BIG_ENDIAN 1
732 #else
733 #define LIBGCC2_WORDS_BIG_ENDIAN 0
734 #endif
736 /* Define this if most significant word of doubles is the lowest numbered.
737 The rules are different based on whether or not we use FPA-format,
738 VFP-format or some other floating point co-processor's format doubles. */
739 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
741 #define UNITS_PER_WORD 4
743 #define PARM_BOUNDARY 32
745 #define IWMMXT_ALIGNMENT 64
747 #define STACK_BOUNDARY 32
749 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
751 #define FUNCTION_BOUNDARY 32
753 /* The lowest bit is used to indicate Thumb-mode functions, so the
754 vbit must go into the delta field of pointers to member
755 functions. */
756 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
758 #define EMPTY_FIELD_BOUNDARY 32
760 #define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32)
762 #define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \
763 (TARGET_REALLY_IWMMXT \
764 && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode)))
766 /* XXX Blah -- this macro is used directly by libobjc. Since it
767 supports no vector modes, cut out the complexity and fall back
768 on BIGGEST_FIELD_ALIGNMENT. */
769 #ifdef IN_TARGET_LIBS
770 #define BIGGEST_FIELD_ALIGNMENT 64
771 #else
772 /* An expression for the alignment of a structure field FIELD if the
773 alignment computed in the usual way is COMPUTED. GCC uses this
774 value instead of the value in `BIGGEST_ALIGNMENT' or
775 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
776 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
777 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \
778 ? IWMMXT_ALIGNMENT \
779 : (COMPUTED))
780 #endif
782 /* If defined, a C expression to compute the alignment for a static variable.
783 TYPE is the data type, and ALIGN is the alignment that the object
784 would ordinarily have. The value of this macro is used instead of that
785 alignment to align the object.
787 If this macro is not defined, then ALIGN is used. */
788 #define DATA_ALIGNMENT(TYPE, ALIGN) \
789 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
791 /* If defined, a C expression to compute the alignment for a
792 variables in the local store. TYPE is the data type, and
793 BASIC-ALIGN is the alignment that the object would ordinarily
794 have. The value of this macro is used instead of that alignment
795 to align the object.
797 If this macro is not defined, then BASIC-ALIGN is used. */
798 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
799 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
801 /* Make strings word-aligned so strcpy from constants will be faster. */
802 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_arch_xscale ? 1 : 2)
804 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
805 ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \
806 (TREE_CODE (EXP) == STRING_CST \
807 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
808 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
810 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
811 value set in previous versions of this toolchain was 8, which produces more
812 compact structures. The command line option -mstructure_size_boundary=<n>
813 can be used to change this value. For compatibility with the ARM SDK
814 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
815 0020D) page 2-20 says "Structures are aligned on word boundaries". */
816 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
819 /* This is the value used to initialize arm_structure_size_boundary. If a
820 particular arm target wants to change the default value it should change
821 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
822 for an example of this. */
823 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
824 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
825 #endif
827 /* Used when parsing command line option -mstructure_size_boundary. */
830 /* Nonzero if move instructions will actually fail to work
831 when given unaligned data. */
832 #define STRICT_ALIGNMENT 1
833 \f
834 /* Standard register usage. */
836 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
837 (S - saved over call).
839 r0 * argument word/integer result
840 r1-r3 argument word
842 r4-r8 S register variable
843 r9 S (rfp) register variable (real frame pointer)
845 r10 F S (sl) stack limit (used by -mapcs-stack-check)
846 r11 F S (fp) argument pointer
847 r12 (ip) temp workspace
848 r13 F S (sp) lower end of current stack frame
849 r14 (lr) link address/workspace
850 r15 F (pc) program counter
852 f0 floating point result
853 f1-f3 floating point scratch
855 f4-f7 S floating point variable
857 cc This is NOT a real register, but is used internally
858 to represent things that use or set the condition
859 codes.
860 sfp This isn't either. It is used during rtl generation
861 since the offset between the frame pointer and the
862 auto's isn't known until after register allocation.
863 afp Nor this, we only need this because of non-local
864 goto. Without it fp appears to be used and the
865 elimination code won't get rid of sfp. It tracks
866 fp exactly at all times.
868 *: See CONDITIONAL_REGISTER_USAGE */
870 /*
871 mvf0 Cirrus floating point result
872 mvf1-mvf3 Cirrus floating point scratch
873 mvf4-mvf15 S Cirrus floating point variable. */
875 /* The stack backtrace structure is as follows:
876 fp points to here: | save code pointer | [fp]
877 | return link value | [fp, #-4]
878 | return sp value | [fp, #-8]
879 | return fp value | [fp, #-12]
880 [| saved r10 value |]
881 [| saved r9 value |]
882 [| saved r8 value |]
883 [| saved r7 value |]
884 [| saved r6 value |]
885 [| saved r5 value |]
886 [| saved r4 value |]
887 [| saved r3 value |]
888 [| saved r2 value |]
889 [| saved r1 value |]
890 [| saved r0 value |]
891 [| saved f7 value |] three words
892 [| saved f6 value |] three words
893 [| saved f5 value |] three words
894 [| saved f4 value |] three words
895 r0-r3 are not normally saved in a C function. */
897 /* 1 for registers that have pervasive standard uses
898 and are not available for the register allocator. */
899 #define FIXED_REGISTERS \
900 { \
901 0,0,0,0,0,0,0,0, \
902 0,0,0,0,0,1,0,1, \
903 0,0,0,0,0,0,0,0, \
904 1,1,1, \
905 1,1,1,1,1,1,1,1, \
906 1,1,1,1,1,1,1,1, \
907 1,1,1,1,1,1,1,1, \
908 1,1,1,1,1,1,1,1, \
909 1,1,1,1 \
910 }
912 /* 1 for registers not available across function calls.
913 These must include the FIXED_REGISTERS and also any
914 registers that can be used without being saved.
915 The latter must include the registers where values are returned
916 and the register where structure-value addresses are passed.
917 Aside from that, you can include as many other registers as you like.
918 The CC is not preserved over function calls on the ARM 6, so it is
919 easier to assume this for all. SFP is preserved, since FP is. */
920 #define CALL_USED_REGISTERS \
921 { \
922 1,1,1,1,0,0,0,0, \
923 0,0,0,0,1,1,1,1, \
924 1,1,1,1,0,0,0,0, \
925 1,1,1, \
926 1,1,1,1,1,1,1,1, \
927 1,1,1,1,1,1,1,1, \
928 1,1,1,1,1,1,1,1, \
929 1,1,1,1,1,1,1,1, \
930 1,1,1,1 \
931 }
933 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
934 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
935 #endif
937 #define CONDITIONAL_REGISTER_USAGE \
938 { \
939 int regno; \
940 \
941 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
942 { \
943 for (regno = FIRST_ARM_FP_REGNUM; \
944 regno <= LAST_ARM_FP_REGNUM; ++regno) \
945 fixed_regs[regno] = call_used_regs[regno] = 1; \
946 } \
947 \
948 if (TARGET_CIRRUS) \
949 { \
950 for (regno = FIRST_ARM_FP_REGNUM; \
951 regno <= LAST_ARM_FP_REGNUM; ++ regno) \
952 fixed_regs[regno] = call_used_regs[regno] = 1; \
953 for (regno = FIRST_CIRRUS_FP_REGNUM; \
954 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
955 { \
956 fixed_regs[regno] = 0; \
957 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
958 } \
959 } \
960 \
961 if (TARGET_REALLY_IWMMXT) \
962 { \
963 regno = FIRST_IWMMXT_GR_REGNUM; \
964 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
965 and wCG1 as call-preserved registers. The 2002/11/21 \
966 revision changed this so that all wCG registers are \
968 for (regno = FIRST_IWMMXT_GR_REGNUM; \
969 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
970 fixed_regs[regno] = call_used_regs[regno] = 0; \
971 /* The XScale ABI has wR0 - wR9 as scratch registers, \
973 for (regno = FIRST_IWMMXT_REGNUM; \
974 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
975 { \
976 fixed_regs[regno] = 0; \
977 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
978 } \
979 } \
980 \
981 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
982 { \
983 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
984 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
985 } \
986 else if (TARGET_APCS_STACK) \
987 { \
988 fixed_regs[10] = 1; \
989 call_used_regs[10] = 1; \
990 } \
991 if (TARGET_APCS_FRAME) \
992 { \
993 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
994 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
995 } \
996 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
997 }
999 /* These are a couple of extensions to the formats accepted
1000 by asm_fprintf:
1001 %@ prints out ASM_COMMENT_START
1002 %r prints out REGISTER_PREFIX reg_names[arg] */
1003 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
1005 fputs (ASM_COMMENT_START, FILE); \
1006 break; \
1007 \
1009 fputs (REGISTER_PREFIX, FILE); \
1010 fputs (reg_names [va_arg (ARGS, int)], FILE); \
1011 break;
1013 /* Round X up to the nearest word. */
1014 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
1016 /* Convert fron bytes to ints. */
1017 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1019 /* The number of (integer) registers required to hold a quantity of type MODE. */
1020 #define ARM_NUM_REGS(MODE) \
1021 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
1023 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
1024 #define ARM_NUM_REGS2(MODE, TYPE) \
1025 ARM_NUM_INTS ((MODE) == BLKmode ? \
1026 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1028 /* The number of (integer) argument register available. */
1029 #define NUM_ARG_REGS 4
1031 /* Return the register number of the N'th (integer) argument. */
1032 #define ARG_REGISTER(N) (N - 1)
1035 returns, and will reserve its own hidden first argument. So
1036 if this macro is enabled a *second* hidden argument will be
1037 reserved, which will break binary compatibility with old
1038 toolchains and also thunk handling. One day this should be
1039 fixed. */
1040 /* RTX for structure returns. NULL means use a hidden first argument. */
1041 #define STRUCT_VALUE 0
1042 #else
1043 /* Register in which address to store a structure value
1044 is passed to a function. */
1045 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
1046 #endif
1048 /* Specify the registers used for certain standard purposes.
1049 The values of these macros are register numbers. */
1051 /* The number of the last argument register. */
1052 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
1054 /* The number of the last "lo" register (thumb). */
1055 #define LAST_LO_REGNUM 7
1057 /* The register that holds the return address in exception handlers. */
1058 #define EXCEPTION_LR_REGNUM 2
1060 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1061 as an invisible last argument (possible since varargs don't exist in
1062 Pascal), so the following is not true. */
1063 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1065 /* Define this to be where the real frame pointer is if it is not possible to
1066 work out the offset between the frame pointer and the automatic variables
1067 until after register allocation has taken place. FRAME_POINTER_REGNUM
1068 should point to a special register that we will make sure is eliminated.
1070 For the Thumb we have another problem. The TPCS defines the frame pointer
1071 as r11, and GCC believes that it is always possible to use the frame pointer
1072 as base register for addressing purposes. (See comments in
1073 find_reloads_address()). But - the Thumb does not allow high registers,
1074 including r11, to be used as base address registers. Hence our problem.
1076 The solution used here, and in the old thumb port is to use r7 instead of
1077 r11 as the hard frame pointer and to have special code to generate
1078 backtrace structures on the stack (if required to do so via a command line
1079 option) using r11. This is the only 'user visible' use of r11 as a frame
1080 pointer. */
1081 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1082 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1084 #define HARD_FRAME_POINTER_REGNUM \
1085 (TARGET_ARM \
1086 ? ARM_HARD_FRAME_POINTER_REGNUM \
1087 : THUMB_HARD_FRAME_POINTER_REGNUM)
1089 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1091 /* Register to use for pushing function arguments. */
1092 #define STACK_POINTER_REGNUM SP_REGNUM
1094 /* ARM floating pointer registers. */
1095 #define FIRST_ARM_FP_REGNUM 16
1096 #define LAST_ARM_FP_REGNUM 23
1098 #define FIRST_IWMMXT_GR_REGNUM 43
1099 #define LAST_IWMMXT_GR_REGNUM 46
1100 #define FIRST_IWMMXT_REGNUM 47
1101 #define LAST_IWMMXT_REGNUM 62
1102 #define IS_IWMMXT_REGNUM(REGNUM) \
1103 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1104 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1105 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1107 /* Base register for access to local variables of the function. */
1108 #define FRAME_POINTER_REGNUM 25
1110 /* Base register for access to arguments of the function. */
1111 #define ARG_POINTER_REGNUM 26
1113 #define FIRST_CIRRUS_FP_REGNUM 27
1114 #define LAST_CIRRUS_FP_REGNUM 42
1115 #define IS_CIRRUS_REGNUM(REGNUM) \
1116 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1118 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1119 /* + 16 Cirrus registers take us up to 43. */
1120 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1121 #define FIRST_PSEUDO_REGISTER 63
1123 /* Value should be nonzero if functions must have frame pointers.
1124 Zero means the frame pointer need not be set up (and parms may be accessed
1125 via the stack pointer) in functions that seem suitable.
1126 If we have to have a frame pointer we might as well make use of it.
1127 APCS says that the frame pointer does not need to be pushed in leaf
1128 functions, or simple tail call functions. */
1129 #define FRAME_POINTER_REQUIRED \
1130 (current_function_has_nonlocal_label \
1131 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1133 /* Return number of consecutive hard regs needed starting at reg REGNO
1134 to hold something of mode MODE.
1135 This is ordinarily the length in words of a value of mode MODE
1136 but can be less for certain modes in special long registers.
1138 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1139 mode. */
1140 #define HARD_REGNO_NREGS(REGNO, MODE) \
1141 ((TARGET_ARM \
1142 && REGNO >= FIRST_ARM_FP_REGNUM \
1143 && REGNO != FRAME_POINTER_REGNUM \
1144 && REGNO != ARG_POINTER_REGNUM) \
1145 ? 1 : ARM_NUM_REGS (MODE))
1147 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1148 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1149 arm_hard_regno_mode_ok ((REGNO), (MODE))
1151 /* Value is 1 if it is a good idea to tie two pseudo registers
1152 when one has mode MODE1 and one has mode MODE2.
1153 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1154 for any hard reg, then this must be 0 for correct output. */
1155 #define MODES_TIEABLE_P(MODE1, MODE2) \
1156 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1158 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1159 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1161 #define VALID_IWMMXT_REG_MODE(MODE) \
1162 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1164 /* The order in which register should be allocated. It is good to use ip
1165 since no saving is required (though calls clobber it) and it never contains
1166 function parameters. It is quite good to use lr since other calls may
1167 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1168 least likely to contain a function parameter; in addition results are
1169 returned in r0. */
1170 #define REG_ALLOC_ORDER \
1171 { \
1172 3, 2, 1, 0, 12, 14, 4, 5, \
1173 6, 7, 8, 10, 9, 11, 13, 15, \
1174 16, 17, 18, 19, 20, 21, 22, 23, \
1175 27, 28, 29, 30, 31, 32, 33, 34, \
1176 35, 36, 37, 38, 39, 40, 41, 42, \
1177 43, 44, 45, 46, 47, 48, 49, 50, \
1178 51, 52, 53, 54, 55, 56, 57, 58, \
1179 59, 60, 61, 62, \
1180 24, 25, 26 \
1181 }
1183 /* Interrupt functions can only use registers that have already been
1184 saved by the prologue, even if they would normally be
1185 call-clobbered. */
1186 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1187 (! IS_INTERRUPT (cfun->machine->func_type) || \
1188 regs_ever_live[DST])
1189 \f
1190 /* Register and constant classes. */
1192 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1193 Now that the Thumb is involved it has become more complicated. */
1194 enum reg_class
1195 {
1196 NO_REGS,
1197 FPA_REGS,
1198 CIRRUS_REGS,
1199 IWMMXT_GR_REGS,
1200 IWMMXT_REGS,
1201 LO_REGS,
1202 STACK_REG,
1203 BASE_REGS,
1204 HI_REGS,
1205 CC_REG,
1206 GENERAL_REGS,
1207 ALL_REGS,
1208 LIM_REG_CLASSES
1209 };
1211 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1213 /* Give names of register classes as strings for dump file. */
1214 #define REG_CLASS_NAMES \
1215 { \
1228 }
1230 /* Define which registers fit in which classes.
1231 This is an initializer for a vector of HARD_REG_SET
1232 of length N_REG_CLASSES. */
1233 #define REG_CLASS_CONTENTS \
1234 { \
1247 }
1249 /* The same information, inverted:
1250 Return the class number of the smallest class containing
1251 reg number REGNO. This could be a conditional expression
1252 or could index an array. */
1253 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1255 /* FPA registers can't do dubreg as all values are reformatted to internal
1256 precision. */
1257 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1258 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1259 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0)
1261 /* The class value for index registers, and the one for base regs. */
1262 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1263 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1265 /* For the Thumb the high registers cannot be used as base registers
1266 when addressing quantities in QI or HI mode; if we don't know the
1267 mode, then we must be conservative. After reload we must also be
1268 conservative, since we can't support SP+reg addressing, and we
1269 can't fix up any bad substitutions. */
1270 #define MODE_BASE_REG_CLASS(MODE) \
1271 (TARGET_ARM ? GENERAL_REGS : \
1272 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1274 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1275 registers explicitly used in the rtl to be used as spill registers
1276 but prevents the compiler from extending the lifetime of these
1277 registers. */
1278 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1280 /* Get reg_class from a letter such as appears in the machine description.
1281 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1282 ARM, but several more letters for the Thumb. */
1283 #define REG_CLASS_FROM_LETTER(C) \
1289 : TARGET_ARM ? NO_REGS \
1294 : NO_REGS)
1296 /* The letters I, J, K, L and M in a register constraint string
1297 can be used to stand for particular ranges of immediate operands.
1298 This macro defines what the ranges are.
1299 C is the letter, and VALUE is a constant value.
1300 Return 1 if VALUE is in the range specified by C.
1301 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1302 J: valid indexing constants.
1303 K: ~value ok in rhs argument of data operand.
1304 L: -value ok in rhs argument of data operand.
1305 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1306 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1312 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1313 : 0)
1315 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1321 && ((VAL) & 3) == 0) : \
1324 : 0)
1326 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1327 (TARGET_ARM ? \
1328 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1330 /* Constant letter 'G' for the FPA immediate constants.
1331 'H' means the same constant negated. */
1332 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1336 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1337 (TARGET_ARM ? \
1338 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1340 /* For the ARM, `Q' means that this is a memory operand that is just
1341 an offset from a register.
1342 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1343 address. This means that the symbol is in the text segment and can be
1344 accessed without using a load. */
1346 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1349 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1350 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1353 0)
1355 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1357 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1359 #define EXTRA_CONSTRAINT(X, C) \
1360 (TARGET_ARM ? \
1361 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1363 /* Given an rtx X being reloaded into a reg required to be
1364 in class CLASS, return the class of reg to actually use.
1365 In general this is just CLASS, but for the Thumb we prefer
1366 a LO_REGS class or a subset. */
1367 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1368 (TARGET_ARM ? (CLASS) : \
1369 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1371 /* Must leave BASE_REGS reloads alone */
1372 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1373 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1374 ? ((true_regnum (X) == -1 ? LO_REGS \
1375 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1376 : NO_REGS)) \
1377 : NO_REGS)
1379 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1380 ((CLASS) != LO_REGS \
1381 ? ((true_regnum (X) == -1 ? LO_REGS \
1382 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1383 : NO_REGS)) \
1384 : NO_REGS)
1386 /* Return the register class of a scratch register needed to copy IN into
1387 or out of a register in CLASS in MODE. If it can be done directly,
1388 NO_REGS is returned. */
1389 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1390 (TARGET_ARM ? \
1391 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1392 ? GENERAL_REGS : NO_REGS) \
1393 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1395 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1396 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1398 ((TARGET_CIRRUS \
1399 && (CLASS) == CIRRUS_REGS \
1400 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1401 ? GENERAL_REGS : \
1402 (TARGET_ARM ? \
1403 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1404 && CONSTANT_P (X)) \
1405 ? GENERAL_REGS : \
1406 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1407 && (GET_CODE (X) == MEM \
1408 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1409 && true_regnum (X) == -1))) \
1410 ? GENERAL_REGS : NO_REGS) \
1411 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1413 /* Try a machine-dependent way of reloading an illegitimate address
1414 operand. If we find one, push the reload and jump to WIN. This
1415 macro is used in only one place: `find_reloads_address' in reload.c.
1417 For the ARM, we wish to handle large displacements off a base
1418 register by splitting the addend across a MOV and the mem insn.
1419 This can cut the number of reloads needed. */
1420 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1421 do \
1422 { \
1423 if (GET_CODE (X) == PLUS \
1424 && GET_CODE (XEXP (X, 0)) == REG \
1425 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1426 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1427 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1428 { \
1429 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1430 HOST_WIDE_INT low, high; \
1431 \
1432 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1433 low = ((val & 0xf) ^ 0x8) - 0x8; \
1434 else if (TARGET_CIRRUS) \
1436 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1437 else if (MODE == SImode \
1438 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1439 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1441 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1442 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1444 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1445 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1446 && TARGET_HARD_FLOAT) \
1448 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1449 else \
1450 break; \
1451 \
1452 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1453 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1454 - (unsigned HOST_WIDE_INT) 0x80000000); \
1456 if (low == 0 || high == 0 || (high + low != val)) \
1457 break; \
1458 \
1459 /* Reload the high part into a base reg; leave the low part \
1461 X = gen_rtx_PLUS (GET_MODE (X), \
1462 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1463 GEN_INT (high)), \
1464 GEN_INT (low)); \
1465 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1466 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1467 VOIDmode, 0, 0, OPNUM, TYPE); \
1468 goto WIN; \
1469 } \
1470 } \
1471 while (0)
1473 /* XXX If an HImode FP+large_offset address is converted to an HImode
1474 SP+large_offset address, then reload won't know how to fix it. It sees
1475 only that SP isn't valid for HImode, and so reloads the SP into an index
1476 register, but the resulting address is still invalid because the offset
1477 is too big. We fix it here instead by reloading the entire address. */
1478 /* We could probably achieve better results by defining PROMOTE_MODE to help
1479 cope with the variances between the Thumb's signed and unsigned byte and
1480 halfword load instructions. */
1481 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1482 { \
1483 if (GET_CODE (X) == PLUS \
1484 && GET_MODE_SIZE (MODE) < 4 \
1485 && GET_CODE (XEXP (X, 0)) == REG \
1486 && XEXP (X, 0) == stack_pointer_rtx \
1487 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1488 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1489 { \
1490 rtx orig_X = X; \
1491 X = copy_rtx (X); \
1492 push_reload (orig_X, NULL_RTX, &X, NULL, \
1493 MODE_BASE_REG_CLASS (MODE), \
1494 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1495 goto WIN; \
1496 } \
1497 }
1499 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1500 if (TARGET_ARM) \
1501 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1502 else \
1503 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1505 /* Return the maximum number of consecutive registers
1506 needed to represent mode MODE in a register of class CLASS.
1507 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1508 #define CLASS_MAX_NREGS(CLASS, MODE) \
1509 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1511 /* If defined, gives a class of registers that cannot be used as the
1512 operand of a SUBREG that changes the mode of the object illegally. */
1514 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1515 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1516 (TARGET_ARM ? \
1517 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1518 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1519 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1520 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1521 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1522 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1523 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1524 2) \
1525 : \
1526 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1527 \f
1528 /* Stack layout; function entry, exit and calling. */
1530 /* Define this if pushing a word on the stack
1531 makes the stack pointer a smaller address. */
1532 #define STACK_GROWS_DOWNWARD 1
1534 /* Define this if the nominal address of the stack frame
1535 is at the high-address end of the local variables;
1536 that is, each additional local variable allocated
1537 goes at a more negative offset in the frame. */
1538 #define FRAME_GROWS_DOWNWARD 1
1540 /* Offset within stack frame to start allocating local variables at.
1541 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1542 first local allocated. Otherwise, it is the offset to the BEGINNING
1543 of the first local allocated. */
1544 #define STARTING_FRAME_OFFSET 0
1546 /* If we generate an insn to push BYTES bytes,
1547 this says how many the stack pointer really advances by. */
1548 /* The push insns do not do this rounding implicitly.
1549 So don't define this. */
1550 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1552 /* Define this if the maximum size of all the outgoing args is to be
1553 accumulated and pushed during the prologue. The amount can be
1554 found in the variable current_function_outgoing_args_size. */
1555 #define ACCUMULATE_OUTGOING_ARGS 1
1557 /* Offset of first parameter from the argument pointer register value. */
1558 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1560 /* Value is the number of byte of arguments automatically
1561 popped when returning from a subroutine call.
1562 FUNDECL is the declaration node of the function (as a tree),
1563 FUNTYPE is the data type of the function (as a tree),
1564 or for a library call it is an identifier node for the subroutine name.
1565 SIZE is the number of bytes of arguments passed on the stack.
1567 On the ARM, the caller does not pop any of its arguments that were passed
1568 on the stack. */
1569 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1571 /* Define how to find the value returned by a library function
1572 assuming the value has mode MODE. */
1573 #define LIBCALL_VALUE(MODE) \
1574 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1575 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1576 : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1577 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1578 : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \
1579 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1580 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1582 /* Define how to find the value returned by a function.
1583 VALTYPE is the data type of the value (as a tree).
1584 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1585 otherwise, FUNC is 0. */
1586 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1587 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1589 /* 1 if N is a possible register number for a function value.
1590 On the ARM, only r0 and f0 can return results. */
1591 /* On a Cirrus chip, mvf0 can return results. */
1592 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1593 ((REGNO) == ARG_REGISTER (1) \
1594 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \
1595 || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \
1596 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1598 /* How large values are returned */
1599 /* A C expression which can inhibit the returning of certain function values
1600 in registers, based on the type of value. */
1601 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1603 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1604 values must be in memory. On the ARM, they need only do so if larger
1605 than a word, or if they contain elements offset from zero in the struct. */
1606 #define DEFAULT_PCC_STRUCT_RETURN 0
1608 /* Flags for the call/call_value rtl operations set up by function_arg. */
1613 /* These bits describe the different types of function supported
1614 by the ARM backend. They are exclusive. ie a function cannot be both a
1615 normal function and an interworked function, for example. Knowing the
1616 type of a function is important for determining its prologue and
1617 epilogue sequences.
1618 Note value 7 is currently unassigned. Also note that the interrupt
1619 function types all have bit 2 set, so that they can be tested for easily.
1620 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1621 machine_function structure is initialized (to zero) func_type will
1622 default to unknown. This will force the first use of arm_current_func_type
1623 to call arm_compute_func_type. */
1632 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1634 /* In addition functions can have several type modifiers,
1635 outlined by these bit masks: */
1641 /* Some macros to test these flags. */
1642 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1643 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1644 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1645 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1646 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1648 /* A C structure for machine-specific, per-function data.
1649 This is added to the cfun structure. */
1651 {
1652 /* Additional stack adjustment in __builtin_eh_throw. */
1653 rtx eh_epilogue_sp_ofs;
1654 /* Records if LR has to be saved for far jumps. */
1656 /* Records if ARG_POINTER was ever live. */
1658 /* Records if the save of LR has been eliminated. */
1660 /* The size of the stack frame. Only valid after reload. */
1662 /* Records the type of the current function. */
1664 /* Record if the function has a variable argument list. */
1666 /* Records if sibcalls are blocked because an argument
1667 register is needed to preserve stack alignment. */
1669 }
1670 machine_function;
1672 /* A C type for declaring a variable that is used as the first argument of
1673 `FUNCTION_ARG' and other related values. For some target machines, the
1674 type `int' suffices and can hold the number of bytes of argument so far. */
1676 {
1677 /* This is the number of registers of arguments scanned so far. */
1679 /* This is the number of iWMMXt register arguments scanned so far. */
1683 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1687 /* Define where to put the arguments to a function.
1688 Value is zero to push the argument on the stack,
1689 or a hard register in which to store the argument.
1691 MODE is the argument's machine mode.
1692 TYPE is the data type of the argument (as a tree).
1693 This is null for libcalls where that information may
1694 not be available.
1695 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1696 the preceding args and about the function being called.
1697 NAMED is nonzero if this argument is a named parameter
1698 (otherwise it is an extra parameter matching an ellipsis).
1700 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1701 other arguments are passed on the stack. If (NAMED == 0) (which happens
1702 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1703 passed in the stack (function_prologue will indeed make it pass in the
1704 stack if necessary). */
1705 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1706 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1708 /* For an arg passed partly in registers and partly in memory,
1709 this is the number of registers used.
1710 For args passed entirely in registers or entirely in memory, zero. */
1711 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1712 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1713 NUM_ARG_REGS > (CUM).nregs \
1714 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1715 ? NUM_ARG_REGS - (CUM).nregs : 0)
1717 /* A C expression that indicates when an argument must be passed by
1718 reference. If nonzero for an argument, a copy of that argument is
1719 made in memory and a pointer to the argument is passed instead of
1720 the argument itself. The pointer is passed in whatever way is
1721 appropriate for passing a pointer to that type. */
1722 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1723 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1725 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1726 for a call to a function whose data type is FNTYPE.
1727 For a library call, FNTYPE is 0.
1728 On the ARM, the offset starts at 0. */
1729 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1730 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1732 /* Update the data in CUM to advance over an argument
1733 of mode MODE and data type TYPE.
1734 (TYPE is null for libcalls where that information may not be available.) */
1735 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1736 (CUM).nargs += 1; \
1737 if (VECTOR_MODE_SUPPORTED_P (MODE)) \
1738 if ((CUM).named_count <= (CUM).nargs) \
1739 (CUM).nregs += 2; \
1740 else \
1741 (CUM).iwmmxt_nregs += 1; \
1742 else \
1743 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1745 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1746 argument with the specified mode and type. If it is not defined,
1747 `PARM_BOUNDARY' is used for all arguments. */
1748 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1749 (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \
1750 ? IWMMXT_ALIGNMENT : PARM_BOUNDARY)
1752 /* 1 if N is a possible register number for function argument passing.
1753 On the ARM, r0-r3 are used to pass args. */
1754 #define FUNCTION_ARG_REGNO_P(REGNO) \
1755 (IN_RANGE ((REGNO), 0, 3) \
1756 || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1758 /* Implement `va_arg'. */
1759 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1760 arm_va_arg (valist, type)
1762 \f
1763 /* Perform any actions needed for a function that is receiving a variable
1764 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1765 of the current parameter. PRETEND_SIZE is a variable that should be set to
1766 the amount of stack that must be pushed by the prolog to pretend that our
1767 caller pushed it.
1769 Normally, this macro will push all remaining incoming registers on the
1770 stack and set PRETEND_SIZE to the length of the registers pushed.
1772 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1773 named arg and all anonymous args onto the stack.
1774 XXX I know the prologue shouldn't be pushing registers, but it is faster
1775 that way. */
1776 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1777 { \
1778 cfun->machine->uses_anonymous_args = 1; \
1779 if ((CUM).nregs < NUM_ARG_REGS) \
1780 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1781 }
1783 /* If your target environment doesn't prefix user functions with an
1784 underscore, you may wish to re-define this to prevent any conflicts.
1785 e.g. AOF may prefix mcount with an underscore. */
1786 #ifndef ARM_MCOUNT_NAME
1788 #endif
1790 /* Call the function profiler with a given profile label. The Acorn
1791 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1792 On the ARM the full profile code will look like:
1793 .data
1794 LP1
1795 .word 0
1796 .text
1797 mov ip, lr
1798 bl mcount
1799 .word LP1
1801 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1802 will output the .text section.
1804 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1805 ``prof'' doesn't seem to mind about this!
1807 Note - this version of the code is designed to work in both ARM and
1808 Thumb modes. */
1809 #ifndef ARM_FUNCTION_PROFILER
1810 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1811 { \
1812 char temp[20]; \
1813 rtx sym; \
1814 \
1816 IP_REGNUM, LR_REGNUM); \
1817 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1820 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1821 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1822 }
1823 #endif
1825 #ifdef THUMB_FUNCTION_PROFILER
1826 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1827 if (TARGET_ARM) \
1828 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1829 else \
1830 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1831 #else
1832 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1833 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1834 #endif
1836 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1837 the stack pointer does not matter. The value is tested only in
1838 functions that have frame pointers.
1839 No definition is equivalent to always zero.
1841 On the ARM, the function epilogue recovers the stack pointer from the
1842 frame. */
1843 #define EXIT_IGNORE_STACK 1
1845 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1847 /* Determine if the epilogue should be output as RTL.
1848 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1849 #define USE_RETURN_INSN(ISCOND) \
1850 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1852 /* Definitions for register eliminations.
1854 This is an array of structures. Each structure initializes one pair
1855 of eliminable registers. The "from" register number is given first,
1856 followed by "to". Eliminations of the same "from" register are listed
1857 in order of preference.
1859 We have two registers that can be eliminated on the ARM. First, the
1860 arg pointer register can often be eliminated in favor of the stack
1861 pointer register. Secondly, the pseudo frame pointer register can always
1862 be eliminated; it is replaced with either the stack or the real frame
1863 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1864 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1866 #define ELIMINABLE_REGS \
1867 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1868 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1869 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1870 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1871 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1872 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1873 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1875 /* Given FROM and TO register numbers, say whether this elimination is
1876 allowed. Frame pointer elimination is automatically handled.
1878 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1879 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1880 pointer, we must eliminate FRAME_POINTER_REGNUM into
1881 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1882 ARG_POINTER_REGNUM. */
1883 #define CAN_ELIMINATE(FROM, TO) \
1884 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1885 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1886 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1887 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1888 1)
1890 #define THUMB_REG_PUSHED_P(reg) \
1891 (regs_ever_live [reg] \
1892 && (! call_used_regs [reg] \
1893 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1894 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1896 /* Define the offset between two registers, one to be eliminated, and the
1897 other its replacement, at the start of a routine. */
1898 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1899 do \
1900 { \
1901 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1902 } \
1903 while (0)
1905 /* Note: This macro must match the code in thumb_function_prologue(). */
1906 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1907 { \
1908 (OFFSET) = 0; \
1909 if ((FROM) == ARG_POINTER_REGNUM) \
1910 { \
1911 int count_regs = 0; \
1912 int regno; \
1913 for (regno = 8; regno < 13; regno ++) \
1914 if (THUMB_REG_PUSHED_P (regno)) \
1915 count_regs ++; \
1916 if (count_regs) \
1917 (OFFSET) += 4 * count_regs; \
1918 count_regs = 0; \
1919 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1920 if (THUMB_REG_PUSHED_P (regno)) \
1921 count_regs ++; \
1922 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1923 (OFFSET) += 4 * (count_regs + 1); \
1924 if (TARGET_BACKTRACE) \
1925 { \
1926 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1927 (OFFSET) += 20; \
1928 else \
1929 (OFFSET) += 16; \
1930 } \
1931 } \
1932 if ((TO) == STACK_POINTER_REGNUM) \
1933 { \
1934 (OFFSET) += current_function_outgoing_args_size; \
1935 (OFFSET) += thumb_get_frame_size (); \
1936 } \
1937 }
1939 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1940 if (TARGET_ARM) \
1941 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1942 else \
1943 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1945 /* Special case handling of the location of arguments passed on the stack. */
1946 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1948 /* Initialize data used by insn expanders. This is called from insn_emit,
1949 once for every function before code is generated. */
1950 #define INIT_EXPANDERS arm_init_expanders ()
1952 /* Output assembler code for a block containing the constant parts
1953 of a trampoline, leaving space for the variable parts.
1955 On the ARM, (if r8 is the static chain regnum, and remembering that
1956 referencing pc adds an offset of 8) the trampoline looks like:
1957 ldr r8, [pc, #0]
1958 ldr pc, [pc]
1959 .word static chain value
1960 .word function's address
1961 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1962 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1963 { \
1965 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1967 PC_REGNUM, PC_REGNUM); \
1968 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1969 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1970 }
1972 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1973 Why - because it is easier. This code will always be branched to via
1974 a BX instruction and since the compiler magically generates the address
1975 of the function the linker has no opportunity to ensure that the
1976 bottom bit is set. Thus the processor will be in ARM mode when it
1977 reaches this code. So we duplicate the ARM trampoline code and add
1978 a switch into Thumb mode as well. */
1979 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1980 { \
1984 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1986 IP_REGNUM, PC_REGNUM); \
1988 IP_REGNUM, IP_REGNUM); \
1993 }
1995 #define TRAMPOLINE_TEMPLATE(FILE) \
1996 if (TARGET_ARM) \
1997 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1998 else \
1999 THUMB_TRAMPOLINE_TEMPLATE (FILE)
2001 /* Length in units of the trampoline for entering a nested function. */
2002 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
2004 /* Alignment required for a trampoline in bits. */
2005 #define TRAMPOLINE_ALIGNMENT 32
2007 /* Emit RTL insns to initialize the variable parts of a trampoline.
2008 FNADDR is an RTX for the address of the function's pure code.
2009 CXT is an RTX for the static chain value for the function. */
2010 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2011 { \
2012 emit_move_insn \
2013 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
2014 emit_move_insn \
2015 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
2016 }
2018 \f
2019 /* Addressing modes, and classification of registers for them. */
2020 #define HAVE_POST_INCREMENT 1
2021 #define HAVE_PRE_INCREMENT TARGET_ARM
2022 #define HAVE_POST_DECREMENT TARGET_ARM
2023 #define HAVE_PRE_DECREMENT TARGET_ARM
2024 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2025 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2026 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2027 #define HAVE_POST_MODIFY_REG TARGET_ARM
2029 /* Macros to check register numbers against specific register classes. */
2031 /* These assume that REGNO is a hard or pseudo reg number.
2032 They give nonzero only if REGNO is a hard reg of the suitable class
2033 or a pseudo reg currently allocated to a suitable hard reg.
2034 Since they use reg_renumber, they are safe only once reg_renumber
2035 has been allocated, which happens in local-alloc.c. */
2036 #define TEST_REGNO(R, TEST, VALUE) \
2037 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2039 /* On the ARM, don't allow the pc to be used. */
2040 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2041 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2042 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2043 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2045 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2046 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2047 || (GET_MODE_SIZE (MODE) >= 4 \
2048 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2050 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2051 (TARGET_THUMB \
2052 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2053 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2055 /* For ARM code, we don't care about the mode, but for Thumb, the index
2056 must be suitable for use in a QImode load. */
2057 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2058 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2060 /* Maximum number of registers that can appear in a valid memory address.
2061 Shifts in addresses can't be by a register. */
2062 #define MAX_REGS_PER_ADDRESS 2
2064 /* Recognize any constant value that is a valid address. */
2065 /* XXX We can address any constant, eventually... */
2067 #ifdef AOF_ASSEMBLER
2069 #define CONSTANT_ADDRESS_P(X) \
2070 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2072 #else
2074 #define CONSTANT_ADDRESS_P(X) \
2075 (GET_CODE (X) == SYMBOL_REF \
2076 && (CONSTANT_POOL_ADDRESS_P (X) \
2077 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2081 /* Nonzero if the constant value X is a legitimate general operand.
2082 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2084 On the ARM, allow any integer (invalid ones are removed later by insn
2085 patterns), nice doubles and symbol_refs which refer to the function's
2086 constant pool XXX.
2088 When generating pic allow anything. */
2089 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2091 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2092 ( GET_CODE (X) == CONST_INT \
2093 || GET_CODE (X) == CONST_DOUBLE \
2094 || CONSTANT_ADDRESS_P (X) \
2095 || flag_pic)
2097 #define LEGITIMATE_CONSTANT_P(X) \
2098 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2100 /* Special characters prefixed to function names
2101 in order to encode attribute like information.
2102 Note, '@' and '*' have already been taken. */
2106 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2107 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2109 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2110 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2112 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2113 #define SUBTARGET_NAME_ENCODING_LENGTHS
2114 #endif
2116 /* This is a C fragment for the inside of a switch statement.
2117 Each case label should return the number of characters to
2118 be stripped from the start of a function's name, if that
2119 name starts with the indicated character. */
2120 #define ARM_NAME_ENCODING_LENGTHS \
2121 case SHORT_CALL_FLAG_CHAR: return 1; \
2122 case LONG_CALL_FLAG_CHAR: return 1; \
2124 SUBTARGET_NAME_ENCODING_LENGTHS
2126 /* This is how to output a reference to a user-level label named NAME.
2127 `assemble_name' uses this. */
2128 #undef ASM_OUTPUT_LABELREF
2129 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2130 arm_asm_output_labelref (FILE, NAME)
2132 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2133 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2135 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2136 and check its validity for a certain class.
2137 We have two alternate definitions for each of them.
2138 The usual definition accepts all pseudo regs; the other rejects
2139 them unless they have been allocated suitable hard regs.
2140 The symbol REG_OK_STRICT causes the latter definition to be used. */
2141 #ifndef REG_OK_STRICT
2143 #define ARM_REG_OK_FOR_BASE_P(X) \
2144 (REGNO (X) <= LAST_ARM_REGNUM \
2145 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2146 || REGNO (X) == FRAME_POINTER_REGNUM \
2147 || REGNO (X) == ARG_POINTER_REGNUM)
2149 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2150 (REGNO (X) <= LAST_LO_REGNUM \
2151 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2152 || (GET_MODE_SIZE (MODE) >= 4 \
2153 && (REGNO (X) == STACK_POINTER_REGNUM \
2154 || (X) == hard_frame_pointer_rtx \
2155 || (X) == arg_pointer_rtx)))
2157 #define REG_STRICT_P 0
2161 #define ARM_REG_OK_FOR_BASE_P(X) \
2162 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2164 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2165 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2167 #define REG_STRICT_P 1
2171 /* Now define some helpers in terms of the above. */
2173 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2174 (TARGET_THUMB \
2175 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2176 : ARM_REG_OK_FOR_BASE_P (X))
2178 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2180 /* For Thumb, a valid index register is anything that can be used in
2181 a byte load instruction. */
2182 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2184 /* Nonzero if X is a hard reg that can be used as an index
2185 or if it is a pseudo reg. On the Thumb, the stack pointer
2186 is not suitable. */
2187 #define REG_OK_FOR_INDEX_P(X) \
2188 (TARGET_THUMB \
2189 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2190 : ARM_REG_OK_FOR_INDEX_P (X))
2192 \f
2193 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2194 that is a valid memory address for an instruction.
2195 The MODE argument is the machine mode for the MEM expression
2196 that wants to use this address. */
2198 #define ARM_BASE_REGISTER_RTX_P(X) \
2199 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2201 #define ARM_INDEX_REGISTER_RTX_P(X) \
2202 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2204 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2205 { \
2206 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2207 goto WIN; \
2208 }
2210 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2211 { \
2212 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2213 goto WIN; \
2214 }
2216 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2217 if (TARGET_ARM) \
2218 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2220 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2222 \f
2223 /* Try machine-dependent ways of modifying an illegitimate address
2224 to be legitimate. If we find one, return the new, valid address. */
2225 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2226 do { \
2227 X = arm_legitimize_address (X, OLDX, MODE); \
2228 \
2229 if (memory_address_p (MODE, X)) \
2230 goto WIN; \
2231 } while (0)
2233 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2234 do { \
2235 if (flag_pic) \
2236 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2237 } while (0)
2239 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2240 do { \
2241 if (TARGET_ARM) \
2242 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2243 else \
2244 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2245 } while (0)
2247 /* Go to LABEL if ADDR (a legitimate address expression)
2248 has an effect that depends on the machine mode it is used for. */
2249 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2250 { \
2251 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2252 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2253 goto LABEL; \
2254 }
2256 /* Nothing helpful to do for the Thumb */
2257 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2258 if (TARGET_ARM) \
2259 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2260 \f
2262 /* Specify the machine mode that this machine uses
2263 for the index in the tablejump instruction. */
2264 #define CASE_VECTOR_MODE Pmode
2266 /* Define as C expression which evaluates to nonzero if the tablejump
2267 instruction expects the table to contain offsets from the address of the
2268 table.
2269 Do not define this if the table should contain absolute addresses. */
2270 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2272 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2273 unsigned is probably best, but may break some code. */
2274 #ifndef DEFAULT_SIGNED_CHAR
2275 #define DEFAULT_SIGNED_CHAR 0
2276 #endif
2278 /* Don't cse the address of the function being compiled. */
2279 #define NO_RECURSIVE_FUNCTION_CSE 1
2281 /* Max number of bytes we can move from memory to memory
2282 in one reasonably fast instruction. */
2283 #define MOVE_MAX 4
2285 #undef MOVE_RATIO
2286 #define MOVE_RATIO (arm_arch_xscale ? 4 : 2)
2288 /* Define if operations between registers always perform the operation
2289 on the full register even if a narrower mode is specified. */
2290 #define WORD_REGISTER_OPERATIONS
2292 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2293 will either zero-extend or sign-extend. The value of this macro should
2294 be the code that says which one of the two operations is implicitly
2295 done, NIL if none. */
2296 #define LOAD_EXTEND_OP(MODE) \
2297 (TARGET_THUMB ? ZERO_EXTEND : \
2298 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2299 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2301 /* Nonzero if access to memory by bytes is slow and undesirable. */
2302 #define SLOW_BYTE_ACCESS 0
2304 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2306 /* Immediate shift counts are truncated by the output routines (or was it
2307 the assembler?). Shift counts in a register are truncated by ARM. Note
2308 that the native compiler puts too large (> 32) immediate shift counts
2309 into a register and shifts by the register, letting the ARM decide what
2310 to do instead of doing that itself. */
2311 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2312 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2313 On the arm, Y in a register is used modulo 256 for the shift. Only for
2314 rotates is modulo 32 used. */
2315 /* #define SHIFT_COUNT_TRUNCATED 1 */
2317 /* All integers have the same format so truncation is easy. */
2318 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2320 /* Calling from registers is a massive pain. */
2321 #define NO_FUNCTION_CSE 1
2323 /* Chars and shorts should be passed as ints. */
2324 #define PROMOTE_PROTOTYPES 1
2326 /* The machine modes of pointers and functions */
2327 #define Pmode SImode
2328 #define FUNCTION_MODE Pmode
2330 #define ARM_FRAME_RTX(X) \
2331 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2332 || (X) == arg_pointer_rtx)
2334 /* Moves to and from memory are quite expensive */
2335 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2336 (TARGET_ARM ? 10 : \
2337 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2338 * (CLASS == LO_REGS ? 1 : 2)))
2340 /* Try to generate sequences that don't involve branches, we can then use
2341 conditional instructions */
2342 #define BRANCH_COST \
2343 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2344 \f
2345 /* Position Independent Code. */
2346 /* We decide which register to use based on the compilation options and
2347 the assembler in use; this is more general than the APCS restriction of
2348 using sb (r9) all the time. */
2351 /* Used when parsing command line option -mpic-register=. */
2354 /* The register number of the register used to address a table of static
2355 data addresses in memory. */
2356 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2358 #define FINALIZE_PIC arm_finalize_pic (1)
2360 /* We can't directly access anything that contains a symbol,
2361 nor can we indirect via the constant pool. */
2362 #define LEGITIMATE_PIC_OPERAND_P(X) \
2363 (!(symbol_mentioned_p (X) \
2364 || label_mentioned_p (X) \
2365 || (GET_CODE (X) == SYMBOL_REF \
2366 && CONSTANT_POOL_ADDRESS_P (X) \
2367 && (symbol_mentioned_p (get_pool_constant (X)) \
2368 || label_mentioned_p (get_pool_constant (X))))))
2370 /* We need to know when we are making a constant pool; this determines
2371 whether data needs to be in the GOT or can be referenced via a GOT
2372 offset. */
2374 \f
2375 /* Handle pragmas for compatibility with Intel's compilers. */
2376 #define REGISTER_TARGET_PRAGMAS() do { \
2380 } while (0)
2382 /* Condition code information. */
2383 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2384 return the mode to be used for the comparison. */
2386 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2388 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2390 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2391 do \
2392 { \
2393 if (GET_CODE (OP1) == CONST_INT \
2394 && ! (const_ok_for_arm (INTVAL (OP1)) \
2395 || (const_ok_for_arm (- INTVAL (OP1))))) \
2396 { \
2397 rtx const_op = OP1; \
2398 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2399 OP1 = const_op; \
2400 } \
2401 } \
2402 while (0)
2404 /* The arm5 clz instruction returns 32. */
2405 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2406 \f
2407 #undef ASM_APP_OFF
2410 /* Output a push or a pop instruction (only used when profiling). */
2411 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2412 if (TARGET_ARM) \
2414 STACK_POINTER_REGNUM, REGNO); \
2415 else \
2419 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2420 if (TARGET_ARM) \
2422 STACK_POINTER_REGNUM, REGNO); \
2423 else \
2426 /* This is how to output a label which precedes a jumptable. Since
2427 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2428 #undef ASM_OUTPUT_CASE_LABEL
2429 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2430 do \
2431 { \
2432 if (TARGET_THUMB) \
2433 ASM_OUTPUT_ALIGN (FILE, 2); \
2434 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2435 } \
2436 while (0)
2438 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2439 do \
2440 { \
2441 if (TARGET_THUMB) \
2442 { \
2443 if (is_called_in_ARM_mode (DECL)) \
2445 else \
2447 } \
2448 if (TARGET_POKE_FUNCTION_NAME) \
2449 arm_poke_function_name (STREAM, (char *) NAME); \
2450 } \
2451 while (0)
2453 /* For aliases of functions we use .thumb_set instead. */
2454 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2455 do \
2456 { \
2457 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2458 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2459 \
2460 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2461 { \
2463 assemble_name (FILE, LABEL1); \
2465 assemble_name (FILE, LABEL2); \
2467 } \
2468 else \
2469 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2470 } \
2471 while (0)
2473 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2474 /* To support -falign-* switches we need to use .p2align so
2475 that alignment directives in code sections will be padded
2476 with no-op instructions, rather than zeroes. */
2477 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2478 if ((LOG) != 0) \
2479 { \
2480 if ((MAX_SKIP) == 0) \
2482 else \
2484 (int) (LOG), (int) (MAX_SKIP)); \
2485 }
2486 #endif
2487 \f
2488 /* Only perform branch elimination (by making instructions conditional) if
2489 we're optimizing. Otherwise it's of no use anyway. */
2490 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2491 if (TARGET_ARM && optimize) \
2492 arm_final_prescan_insn (INSN); \
2493 else if (TARGET_THUMB) \
2494 thumb_final_prescan_insn (INSN)
2496 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2501 /* Output an operand of an instruction. */
2502 #define PRINT_OPERAND(STREAM, X, CODE) \
2503 arm_print_operand (STREAM, X, CODE)
2505 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2506 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2507 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2508 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2509 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2510 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2511 : 0))))
2513 /* Output the address of an operand. */
2514 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2515 { \
2516 int is_minus = GET_CODE (X) == MINUS; \
2517 \
2518 if (GET_CODE (X) == REG) \
2520 else if (GET_CODE (X) == PLUS || is_minus) \
2521 { \
2522 rtx base = XEXP (X, 0); \
2523 rtx index = XEXP (X, 1); \
2524 HOST_WIDE_INT offset = 0; \
2525 if (GET_CODE (base) != REG) \
2526 { \
2529 rtx temp = base; \
2530 base = index; \
2531 index = temp; \
2532 } \
2533 switch (GET_CODE (index)) \
2534 { \
2535 case CONST_INT: \
2536 offset = INTVAL (index); \
2537 if (is_minus) \
2538 offset = -offset; \
2540 REGNO (base), offset); \
2541 break; \
2542 \
2543 case REG: \
2546 REGNO (index)); \
2547 break; \
2548 \
2549 case MULT: \
2550 case ASHIFTRT: \
2551 case LSHIFTRT: \
2552 case ASHIFT: \
2553 case ROTATERT: \
2554 { \
2557 REGNO (XEXP (index, 0))); \
2560 break; \
2561 } \
2562 \
2563 default: \
2564 abort(); \
2565 } \
2566 } \
2567 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2568 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2569 { \
2570 extern enum machine_mode output_memory_reference_mode; \
2571 \
2572 if (GET_CODE (XEXP (X, 0)) != REG) \
2573 abort (); \
2574 \
2575 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2577 REGNO (XEXP (X, 0)), \
2579 GET_MODE_SIZE (output_memory_reference_mode)); \
2580 else \
2582 REGNO (XEXP (X, 0)), \
2584 GET_MODE_SIZE (output_memory_reference_mode)); \
2585 } \
2586 else if (GET_CODE (X) == PRE_MODIFY) \
2587 { \
2589 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2591 INTVAL (XEXP (XEXP (X, 1), 1))); \
2592 else \
2594 REGNO (XEXP (XEXP (X, 1), 1))); \
2595 } \
2596 else if (GET_CODE (X) == POST_MODIFY) \
2597 { \
2599 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2601 INTVAL (XEXP (XEXP (X, 1), 1))); \
2602 else \
2604 REGNO (XEXP (XEXP (X, 1), 1))); \
2605 } \
2606 else output_addr_const (STREAM, X); \
2607 }
2609 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2610 { \
2611 if (GET_CODE (X) == REG) \
2613 else if (GET_CODE (X) == POST_INC) \
2615 else if (GET_CODE (X) == PLUS) \
2616 { \
2617 if (GET_CODE (XEXP (X, 0)) != REG) \
2618 abort (); \
2619 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2621 REGNO (XEXP (X, 0)), \
2622 INTVAL (XEXP (X, 1))); \
2623 else \
2625 REGNO (XEXP (X, 0)), \
2626 REGNO (XEXP (X, 1))); \
2627 } \
2628 else \
2629 output_addr_const (STREAM, X); \
2630 }
2632 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2633 if (TARGET_ARM) \
2634 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2635 else \
2636 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2638 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2639 if (GET_CODE (X) != CONST_VECTOR \
2640 || ! arm_emit_vector_const (FILE, X)) \
2641 goto FAIL;
2643 /* A C expression whose value is RTL representing the value of the return
2644 address for the frame COUNT steps up from the current frame. */
2646 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2647 arm_return_addr (COUNT, FRAME)
2649 /* Mask of the bits in the PC that contain the real return address
2650 when running in 26-bit mode. */
2651 #define RETURN_ADDR_MASK26 (0x03fffffc)
2653 /* Pick up the return address upon entry to a procedure. Used for
2654 dwarf2 unwind information. This also enables the table driven
2655 mechanism. */
2656 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2657 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2659 /* Used to mask out junk bits from the return address, such as
2660 processor state, interrupt status, condition codes and the like. */
2661 #define MASK_RETURN_ADDR \
2662 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2663 in 26 bit mode, the condition codes must be masked out of the \
2664 return address. This does not apply to ARM6 and later processors \
2666 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2667 : (arm_arch4 || TARGET_THUMB) ? \
2668 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2669 : arm_gen_return_addr_mask ())
2671 \f
2672 /* Define the codes that are matched by predicates in arm.c */
2673 #define PREDICATE_CODES \
2699 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2700 UNGE, UNGT}}, \
2711 /* Define this if you have special predicates that know special things
2712 about modes. Genrecog will warn about certain forms of
2713 match_operand without a mode; if the operand predicate is listed in
2714 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2715 #define SPECIAL_MODE_PREDICATES \
2718 enum arm_builtins
2719 {
2720 ARM_BUILTIN_GETWCX,
2721 ARM_BUILTIN_SETWCX,
2723 ARM_BUILTIN_WZERO,
2725 ARM_BUILTIN_WAVG2BR,
2726 ARM_BUILTIN_WAVG2HR,
2727 ARM_BUILTIN_WAVG2B,
2728 ARM_BUILTIN_WAVG2H,
2730 ARM_BUILTIN_WACCB,
2731 ARM_BUILTIN_WACCH,
2732 ARM_BUILTIN_WACCW,
2734 ARM_BUILTIN_WMACS,
2735 ARM_BUILTIN_WMACSZ,
2736 ARM_BUILTIN_WMACU,
2737 ARM_BUILTIN_WMACUZ,
2739 ARM_BUILTIN_WSADB,
2740 ARM_BUILTIN_WSADBZ,
2741 ARM_BUILTIN_WSADH,
2742 ARM_BUILTIN_WSADHZ,
2744 ARM_BUILTIN_WALIGN,
2746 ARM_BUILTIN_TMIA,
2747 ARM_BUILTIN_TMIAPH,
2748 ARM_BUILTIN_TMIABB,
2749 ARM_BUILTIN_TMIABT,
2750 ARM_BUILTIN_TMIATB,
2751 ARM_BUILTIN_TMIATT,
2753 ARM_BUILTIN_TMOVMSKB,
2754 ARM_BUILTIN_TMOVMSKH,
2755 ARM_BUILTIN_TMOVMSKW,
2757 ARM_BUILTIN_TBCSTB,
2758 ARM_BUILTIN_TBCSTH,
2759 ARM_BUILTIN_TBCSTW,
2761 ARM_BUILTIN_WMADDS,
2762 ARM_BUILTIN_WMADDU,
2764 ARM_BUILTIN_WPACKHSS,
2765 ARM_BUILTIN_WPACKWSS,
2766 ARM_BUILTIN_WPACKDSS,
2767 ARM_BUILTIN_WPACKHUS,
2768 ARM_BUILTIN_WPACKWUS,
2769 ARM_BUILTIN_WPACKDUS,
2771 ARM_BUILTIN_WADDB,
2772 ARM_BUILTIN_WADDH,
2773 ARM_BUILTIN_WADDW,
2774 ARM_BUILTIN_WADDSSB,
2775 ARM_BUILTIN_WADDSSH,
2776 ARM_BUILTIN_WADDSSW,
2777 ARM_BUILTIN_WADDUSB,
2778 ARM_BUILTIN_WADDUSH,
2779 ARM_BUILTIN_WADDUSW,
2780 ARM_BUILTIN_WSUBB,
2781 ARM_BUILTIN_WSUBH,
2782 ARM_BUILTIN_WSUBW,
2783 ARM_BUILTIN_WSUBSSB,
2784 ARM_BUILTIN_WSUBSSH,
2785 ARM_BUILTIN_WSUBSSW,
2786 ARM_BUILTIN_WSUBUSB,
2787 ARM_BUILTIN_WSUBUSH,
2788 ARM_BUILTIN_WSUBUSW,
2790 ARM_BUILTIN_WAND,
2791 ARM_BUILTIN_WANDN,
2792 ARM_BUILTIN_WOR,
2793 ARM_BUILTIN_WXOR,
2795 ARM_BUILTIN_WCMPEQB,
2796 ARM_BUILTIN_WCMPEQH,
2797 ARM_BUILTIN_WCMPEQW,
2798 ARM_BUILTIN_WCMPGTUB,
2799 ARM_BUILTIN_WCMPGTUH,
2800 ARM_BUILTIN_WCMPGTUW,
2801 ARM_BUILTIN_WCMPGTSB,
2802 ARM_BUILTIN_WCMPGTSH,
2803 ARM_BUILTIN_WCMPGTSW,
2805 ARM_BUILTIN_TEXTRMSB,
2806 ARM_BUILTIN_TEXTRMSH,
2807 ARM_BUILTIN_TEXTRMSW,
2808 ARM_BUILTIN_TEXTRMUB,
2809 ARM_BUILTIN_TEXTRMUH,
2810 ARM_BUILTIN_TEXTRMUW,
2811 ARM_BUILTIN_TINSRB,
2812 ARM_BUILTIN_TINSRH,
2813 ARM_BUILTIN_TINSRW,
2815 ARM_BUILTIN_WMAXSW,
2816 ARM_BUILTIN_WMAXSH,
2817 ARM_BUILTIN_WMAXSB,
2818 ARM_BUILTIN_WMAXUW,
2819 ARM_BUILTIN_WMAXUH,
2820 ARM_BUILTIN_WMAXUB,
2821 ARM_BUILTIN_WMINSW,
2822 ARM_BUILTIN_WMINSH,
2823 ARM_BUILTIN_WMINSB,
2824 ARM_BUILTIN_WMINUW,
2825 ARM_BUILTIN_WMINUH,
2826 ARM_BUILTIN_WMINUB,
2828 ARM_BUILTIN_WMULUH,
2829 ARM_BUILTIN_WMULSH,
2830 ARM_BUILTIN_WMULUL,
2832 ARM_BUILTIN_PSADBH,
2833 ARM_BUILTIN_WSHUFH,
2835 ARM_BUILTIN_WSLLH,
2836 ARM_BUILTIN_WSLLW,
2837 ARM_BUILTIN_WSLLD,
2838 ARM_BUILTIN_WSRAH,
2839 ARM_BUILTIN_WSRAW,
2840 ARM_BUILTIN_WSRAD,
2841 ARM_BUILTIN_WSRLH,
2842 ARM_BUILTIN_WSRLW,
2843 ARM_BUILTIN_WSRLD,
2844 ARM_BUILTIN_WRORH,
2845 ARM_BUILTIN_WRORW,
2846 ARM_BUILTIN_WRORD,
2847 ARM_BUILTIN_WSLLHI,
2848 ARM_BUILTIN_WSLLWI,
2849 ARM_BUILTIN_WSLLDI,
2850 ARM_BUILTIN_WSRAHI,
2851 ARM_BUILTIN_WSRAWI,
2852 ARM_BUILTIN_WSRADI,
2853 ARM_BUILTIN_WSRLHI,
2854 ARM_BUILTIN_WSRLWI,
2855 ARM_BUILTIN_WSRLDI,
2856 ARM_BUILTIN_WRORHI,
2857 ARM_BUILTIN_WRORWI,
2858 ARM_BUILTIN_WRORDI,
2860 ARM_BUILTIN_WUNPCKIHB,
2861 ARM_BUILTIN_WUNPCKIHH,
2862 ARM_BUILTIN_WUNPCKIHW,
2863 ARM_BUILTIN_WUNPCKILB,
2864 ARM_BUILTIN_WUNPCKILH,
2865 ARM_BUILTIN_WUNPCKILW,
2867 ARM_BUILTIN_WUNPCKEHSB,
2868 ARM_BUILTIN_WUNPCKEHSH,
2869 ARM_BUILTIN_WUNPCKEHSW,
2870 ARM_BUILTIN_WUNPCKEHUB,
2871 ARM_BUILTIN_WUNPCKEHUH,
2872 ARM_BUILTIN_WUNPCKEHUW,
2873 ARM_BUILTIN_WUNPCKELSB,
2874 ARM_BUILTIN_WUNPCKELSH,
2875 ARM_BUILTIN_WUNPCKELSW,
2876 ARM_BUILTIN_WUNPCKELUB,
2877 ARM_BUILTIN_WUNPCKELUH,
2878 ARM_BUILTIN_WUNPCKELUW,
2880 ARM_BUILTIN_MAX
2881 };