2007-03-01 Paul Brook <paul@codesourcery.com>
[official-gcc.git] / gcc / config / arm / arm.c
1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "rtl.h"
30 #include "tree.h"
31 #include "obstack.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "output.h"
38 #include "insn-attr.h"
39 #include "flags.h"
40 #include "reload.h"
41 #include "function.h"
42 #include "expr.h"
43 #include "optabs.h"
44 #include "toplev.h"
45 #include "recog.h"
46 #include "ggc.h"
47 #include "except.h"
48 #include "c-pragma.h"
49 #include "integrate.h"
50 #include "tm_p.h"
51 #include "target.h"
52 #include "target-def.h"
53 #include "debug.h"
54 #include "langhooks.h"
55
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
59
60 const struct attribute_spec arm_attribute_table[];
61
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
71 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
72 inline static int thumb1_index_register_rtx_p (rtx, int);
73 static int thumb_far_jump_used_p (void);
74 static bool thumb_force_lr_save (void);
75 static unsigned long thumb1_compute_save_reg_mask (void);
76 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
77 static rtx emit_sfm (int, int);
78 static int arm_size_return_regs (void);
79 #ifndef AOF_ASSEMBLER
80 static bool arm_assemble_integer (rtx, unsigned int, int);
81 #endif
82 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
83 static arm_cc get_arm_condition_code (rtx);
84 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
85 static rtx is_jump_table (rtx);
86 static const char *output_multi_immediate (rtx *, const char *, const char *,
87 int, HOST_WIDE_INT);
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static void thumb_exit (FILE *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
104 rtx);
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
115 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
116 #endif
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
120 static int arm_comp_type_attributes (tree, tree);
121 static void arm_set_default_type_attributes (tree);
122 static int arm_adjust_cost (rtx, rtx, rtx, int);
123 static int count_insns_for_constant (HOST_WIDE_INT, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree, tree);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
128 tree);
129 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
130 static bool arm_size_rtx_costs (rtx, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx, int, int, int *);
135 static int arm_address_cost (rtx);
136 static bool arm_memory_load_p (rtx);
137 static bool arm_cirrus_insn_p (rtx);
138 static void cirrus_reorg (rtx);
139 static void arm_init_builtins (void);
140 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx safe_vector_operand (rtx, enum machine_mode);
143 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
144 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
145 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
146 static void emit_constant_insn (rtx cond, rtx pattern);
147 static rtx emit_set_insn (rtx, rtx);
148 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
149 tree, bool);
150
151 #ifdef OBJECT_FORMAT_ELF
152 static void arm_elf_asm_constructor (rtx, int);
153 #endif
154 #ifndef ARM_PE
155 static void arm_encode_section_info (tree, rtx, int);
156 #endif
157
158 static void arm_file_end (void);
159 static void arm_file_start (void);
160
161 #ifdef AOF_ASSEMBLER
162 static void aof_globalize_label (FILE *, const char *);
163 static void aof_dump_imports (FILE *);
164 static void aof_dump_pic_table (FILE *);
165 static void aof_file_start (void);
166 static void aof_file_end (void);
167 static void aof_asm_init_sections (void);
168 #endif
169 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
170 tree, int *, int);
171 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
172 enum machine_mode, tree, bool);
173 static bool arm_promote_prototypes (tree);
174 static bool arm_default_short_enums (void);
175 static bool arm_align_anon_bitfield (void);
176 static bool arm_return_in_msb (tree);
177 static bool arm_must_pass_in_stack (enum machine_mode, tree);
178 #ifdef TARGET_UNWIND_INFO
179 static void arm_unwind_emit (FILE *, rtx);
180 static bool arm_output_ttype (rtx);
181 #endif
182 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
183
184 static tree arm_cxx_guard_type (void);
185 static bool arm_cxx_guard_mask_bit (void);
186 static tree arm_get_cookie_size (tree);
187 static bool arm_cookie_has_size (void);
188 static bool arm_cxx_cdtor_returns_this (void);
189 static bool arm_cxx_key_method_may_be_inline (void);
190 static void arm_cxx_determine_class_data_visibility (tree);
191 static bool arm_cxx_class_data_always_comdat (void);
192 static bool arm_cxx_use_aeabi_atexit (void);
193 static void arm_init_libfuncs (void);
194 static bool arm_handle_option (size_t, const char *, int);
195 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
196 static bool arm_cannot_copy_insn_p (rtx);
197 static bool arm_tls_symbol_p (rtx x);
198
199 \f
200 /* Initialize the GCC target structure. */
201 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
202 #undef TARGET_MERGE_DECL_ATTRIBUTES
203 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
204 #endif
205
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
208
209 #undef TARGET_ASM_FILE_START
210 #define TARGET_ASM_FILE_START arm_file_start
211 #undef TARGET_ASM_FILE_END
212 #define TARGET_ASM_FILE_END arm_file_end
213
214 #ifdef AOF_ASSEMBLER
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tDCB\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
221 #undef TARGET_ASM_GLOBALIZE_LABEL
222 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
223 #undef TARGET_ASM_FILE_START
224 #define TARGET_ASM_FILE_START aof_file_start
225 #undef TARGET_ASM_FILE_END
226 #define TARGET_ASM_FILE_END aof_file_end
227 #else
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP NULL
230 #undef TARGET_ASM_INTEGER
231 #define TARGET_ASM_INTEGER arm_assemble_integer
232 #endif
233
234 #undef TARGET_ASM_FUNCTION_PROLOGUE
235 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
236
237 #undef TARGET_ASM_FUNCTION_EPILOGUE
238 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
239
240 #undef TARGET_DEFAULT_TARGET_FLAGS
241 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
242 #undef TARGET_HANDLE_OPTION
243 #define TARGET_HANDLE_OPTION arm_handle_option
244
245 #undef TARGET_COMP_TYPE_ATTRIBUTES
246 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
247
248 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
249 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
250
251 #undef TARGET_SCHED_ADJUST_COST
252 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
253
254 #undef TARGET_ENCODE_SECTION_INFO
255 #ifdef ARM_PE
256 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
257 #else
258 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
259 #endif
260
261 #undef TARGET_STRIP_NAME_ENCODING
262 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
263
264 #undef TARGET_ASM_INTERNAL_LABEL
265 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
266
267 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
268 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
269
270 #undef TARGET_ASM_OUTPUT_MI_THUNK
271 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
272 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
273 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
274
275 /* This will be overridden in arm_override_options. */
276 #undef TARGET_RTX_COSTS
277 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
278 #undef TARGET_ADDRESS_COST
279 #define TARGET_ADDRESS_COST arm_address_cost
280
281 #undef TARGET_SHIFT_TRUNCATION_MASK
282 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
283 #undef TARGET_VECTOR_MODE_SUPPORTED_P
284 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
285
286 #undef TARGET_MACHINE_DEPENDENT_REORG
287 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
288
289 #undef TARGET_INIT_BUILTINS
290 #define TARGET_INIT_BUILTINS arm_init_builtins
291 #undef TARGET_EXPAND_BUILTIN
292 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
293
294 #undef TARGET_INIT_LIBFUNCS
295 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
296
297 #undef TARGET_PROMOTE_FUNCTION_ARGS
298 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
299 #undef TARGET_PROMOTE_FUNCTION_RETURN
300 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
301 #undef TARGET_PROMOTE_PROTOTYPES
302 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
303 #undef TARGET_PASS_BY_REFERENCE
304 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
305 #undef TARGET_ARG_PARTIAL_BYTES
306 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
307
308 #undef TARGET_SETUP_INCOMING_VARARGS
309 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
310
311 #undef TARGET_DEFAULT_SHORT_ENUMS
312 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
313
314 #undef TARGET_ALIGN_ANON_BITFIELD
315 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
316
317 #undef TARGET_NARROW_VOLATILE_BITFIELD
318 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
319
320 #undef TARGET_CXX_GUARD_TYPE
321 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
322
323 #undef TARGET_CXX_GUARD_MASK_BIT
324 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
325
326 #undef TARGET_CXX_GET_COOKIE_SIZE
327 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
328
329 #undef TARGET_CXX_COOKIE_HAS_SIZE
330 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
331
332 #undef TARGET_CXX_CDTOR_RETURNS_THIS
333 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
334
335 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
336 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
337
338 #undef TARGET_CXX_USE_AEABI_ATEXIT
339 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
340
341 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
342 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
343 arm_cxx_determine_class_data_visibility
344
345 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
346 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
347
348 #undef TARGET_RETURN_IN_MSB
349 #define TARGET_RETURN_IN_MSB arm_return_in_msb
350
351 #undef TARGET_MUST_PASS_IN_STACK
352 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
353
354 #ifdef TARGET_UNWIND_INFO
355 #undef TARGET_UNWIND_EMIT
356 #define TARGET_UNWIND_EMIT arm_unwind_emit
357
358 /* EABI unwinding tables use a different format for the typeinfo tables. */
359 #undef TARGET_ASM_TTYPE
360 #define TARGET_ASM_TTYPE arm_output_ttype
361
362 #undef TARGET_ARM_EABI_UNWINDER
363 #define TARGET_ARM_EABI_UNWINDER true
364 #endif /* TARGET_UNWIND_INFO */
365
366 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
367 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
368
369 #undef TARGET_CANNOT_COPY_INSN_P
370 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
371
372 #ifdef HAVE_AS_TLS
373 #undef TARGET_HAVE_TLS
374 #define TARGET_HAVE_TLS true
375 #endif
376
377 #undef TARGET_CANNOT_FORCE_CONST_MEM
378 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
379
380 struct gcc_target targetm = TARGET_INITIALIZER;
381 \f
382 /* Obstack for minipool constant handling. */
383 static struct obstack minipool_obstack;
384 static char * minipool_startobj;
385
386 /* The maximum number of insns skipped which
387 will be conditionalised if possible. */
388 static int max_insns_skipped = 5;
389
390 extern FILE * asm_out_file;
391
392 /* True if we are currently building a constant table. */
393 int making_const_table;
394
395 /* Define the information needed to generate branch insns. This is
396 stored from the compare operation. */
397 rtx arm_compare_op0, arm_compare_op1;
398
399 /* The processor for which instructions should be scheduled. */
400 enum processor_type arm_tune = arm_none;
401
402 /* The default processor used if not overridden by commandline. */
403 static enum processor_type arm_default_cpu = arm_none;
404
405 /* Which floating point model to use. */
406 enum arm_fp_model arm_fp_model;
407
408 /* Which floating point hardware is available. */
409 enum fputype arm_fpu_arch;
410
411 /* Which floating point hardware to schedule for. */
412 enum fputype arm_fpu_tune;
413
414 /* Whether to use floating point hardware. */
415 enum float_abi_type arm_float_abi;
416
417 /* Which ABI to use. */
418 enum arm_abi_type arm_abi;
419
420 /* Which thread pointer model to use. */
421 enum arm_tp_type target_thread_pointer = TP_AUTO;
422
423 /* Used to parse -mstructure_size_boundary command line option. */
424 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
425
426 /* Used for Thumb call_via trampolines. */
427 rtx thumb_call_via_label[14];
428 static int thumb_call_reg_needed;
429
430 /* Bit values used to identify processor capabilities. */
431 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
432 #define FL_ARCH3M (1 << 1) /* Extended multiply */
433 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
434 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
435 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
436 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
437 #define FL_THUMB (1 << 6) /* Thumb aware */
438 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
439 #define FL_STRONG (1 << 8) /* StrongARM */
440 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
441 #define FL_XSCALE (1 << 10) /* XScale */
442 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
443 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
444 media instructions. */
445 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
446 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
447 Note: ARM6 & 7 derivatives only. */
448 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
449 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
450 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
451 profile. */
452 #define FL_DIV (1 << 18) /* Hardware divide. */
453
454 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
455
456 #define FL_FOR_ARCH2 FL_NOTM
457 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
458 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
459 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
460 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
461 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
462 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
463 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
464 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
465 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
466 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
467 #define FL_FOR_ARCH6J FL_FOR_ARCH6
468 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
469 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
470 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
471 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
472 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
473 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
474 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
475 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
476
477 /* The bits in this mask specify which
478 instructions we are allowed to generate. */
479 static unsigned long insn_flags = 0;
480
481 /* The bits in this mask specify which instruction scheduling options should
482 be used. */
483 static unsigned long tune_flags = 0;
484
485 /* The following are used in the arm.md file as equivalents to bits
486 in the above two flag variables. */
487
488 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
489 int arm_arch3m = 0;
490
491 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
492 int arm_arch4 = 0;
493
494 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
495 int arm_arch4t = 0;
496
497 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
498 int arm_arch5 = 0;
499
500 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
501 int arm_arch5e = 0;
502
503 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
504 int arm_arch6 = 0;
505
506 /* Nonzero if this chip supports the ARM 6K extensions. */
507 int arm_arch6k = 0;
508
509 /* Nonzero if instructions not present in the 'M' profile can be used. */
510 int arm_arch_notm = 0;
511
512 /* Nonzero if this chip can benefit from load scheduling. */
513 int arm_ld_sched = 0;
514
515 /* Nonzero if this chip is a StrongARM. */
516 int arm_tune_strongarm = 0;
517
518 /* Nonzero if this chip is a Cirrus variant. */
519 int arm_arch_cirrus = 0;
520
521 /* Nonzero if this chip supports Intel Wireless MMX technology. */
522 int arm_arch_iwmmxt = 0;
523
524 /* Nonzero if this chip is an XScale. */
525 int arm_arch_xscale = 0;
526
527 /* Nonzero if tuning for XScale */
528 int arm_tune_xscale = 0;
529
530 /* Nonzero if we want to tune for stores that access the write-buffer.
531 This typically means an ARM6 or ARM7 with MMU or MPU. */
532 int arm_tune_wbuf = 0;
533
534 /* Nonzero if generating Thumb instructions. */
535 int thumb_code = 0;
536
537 /* Nonzero if we should define __THUMB_INTERWORK__ in the
538 preprocessor.
539 XXX This is a bit of a hack, it's intended to help work around
540 problems in GLD which doesn't understand that armv5t code is
541 interworking clean. */
542 int arm_cpp_interwork = 0;
543
544 /* Nonzero if chip supports Thumb 2. */
545 int arm_arch_thumb2;
546
547 /* Nonzero if chip supports integer division instruction. */
548 int arm_arch_hwdiv;
549
550 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
551 must report the mode of the memory reference from PRINT_OPERAND to
552 PRINT_OPERAND_ADDRESS. */
553 enum machine_mode output_memory_reference_mode;
554
555 /* The register number to be used for the PIC offset register. */
556 unsigned arm_pic_register = INVALID_REGNUM;
557
558 /* Set to 1 when a return insn is output, this means that the epilogue
559 is not needed. */
560 int return_used_this_function;
561
562 /* Set to 1 after arm_reorg has started. Reset to start at the start of
563 the next function. */
564 static int after_arm_reorg = 0;
565
566 /* The maximum number of insns to be used when loading a constant. */
567 static int arm_constant_limit = 3;
568
569 /* For an explanation of these variables, see final_prescan_insn below. */
570 int arm_ccfsm_state;
571 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
572 enum arm_cond_code arm_current_cc;
573 rtx arm_target_insn;
574 int arm_target_label;
575 /* The number of conditionally executed insns, including the current insn. */
576 int arm_condexec_count = 0;
577 /* A bitmask specifying the patterns for the IT block.
578 Zero means do not output an IT block before this insn. */
579 int arm_condexec_mask = 0;
580 /* The number of bits used in arm_condexec_mask. */
581 int arm_condexec_masklen = 0;
582
583 /* The condition codes of the ARM, and the inverse function. */
584 static const char * const arm_condition_codes[] =
585 {
586 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
587 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
588 };
589
590 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
591 #define streq(string1, string2) (strcmp (string1, string2) == 0)
592
593 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
594 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
595 | (1 << PIC_OFFSET_TABLE_REGNUM)))
596 \f
597 /* Initialization code. */
598
599 struct processors
600 {
601 const char *const name;
602 enum processor_type core;
603 const char *arch;
604 const unsigned long flags;
605 bool (* rtx_costs) (rtx, int, int, int *);
606 };
607
608 /* Not all of these give usefully different compilation alternatives,
609 but there is no simple way of generalizing them. */
610 static const struct processors all_cores[] =
611 {
612 /* ARM Cores */
613 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
614 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
615 #include "arm-cores.def"
616 #undef ARM_CORE
617 {NULL, arm_none, NULL, 0, NULL}
618 };
619
620 static const struct processors all_architectures[] =
621 {
622 /* ARM Architectures */
623 /* We don't specify rtx_costs here as it will be figured out
624 from the core. */
625
626 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
627 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
628 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
629 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
630 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
631 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
632 implementations that support it, so we will leave it out for now. */
633 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
634 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
635 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
636 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
637 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
638 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
639 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
640 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
641 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
642 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
643 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
644 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
645 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
646 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
647 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
648 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
649 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
650 {NULL, arm_none, NULL, 0 , NULL}
651 };
652
653 struct arm_cpu_select
654 {
655 const char * string;
656 const char * name;
657 const struct processors * processors;
658 };
659
660 /* This is a magic structure. The 'string' field is magically filled in
661 with a pointer to the value specified by the user on the command line
662 assuming that the user has specified such a value. */
663
664 static struct arm_cpu_select arm_select[] =
665 {
666 /* string name processors */
667 { NULL, "-mcpu=", all_cores },
668 { NULL, "-march=", all_architectures },
669 { NULL, "-mtune=", all_cores }
670 };
671
672 /* Defines representing the indexes into the above table. */
673 #define ARM_OPT_SET_CPU 0
674 #define ARM_OPT_SET_ARCH 1
675 #define ARM_OPT_SET_TUNE 2
676
677 /* The name of the preprocessor macro to define for this architecture. */
678
679 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
680
681 struct fpu_desc
682 {
683 const char * name;
684 enum fputype fpu;
685 };
686
687
688 /* Available values for -mfpu=. */
689
690 static const struct fpu_desc all_fpus[] =
691 {
692 {"fpa", FPUTYPE_FPA},
693 {"fpe2", FPUTYPE_FPA_EMU2},
694 {"fpe3", FPUTYPE_FPA_EMU2},
695 {"maverick", FPUTYPE_MAVERICK},
696 {"vfp", FPUTYPE_VFP}
697 };
698
699
700 /* Floating point models used by the different hardware.
701 See fputype in arm.h. */
702
703 static const enum fputype fp_model_for_fpu[] =
704 {
705 /* No FP hardware. */
706 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
707 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
708 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
709 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
710 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
711 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
712 };
713
714
715 struct float_abi
716 {
717 const char * name;
718 enum float_abi_type abi_type;
719 };
720
721
722 /* Available values for -mfloat-abi=. */
723
724 static const struct float_abi all_float_abis[] =
725 {
726 {"soft", ARM_FLOAT_ABI_SOFT},
727 {"softfp", ARM_FLOAT_ABI_SOFTFP},
728 {"hard", ARM_FLOAT_ABI_HARD}
729 };
730
731
732 struct abi_name
733 {
734 const char *name;
735 enum arm_abi_type abi_type;
736 };
737
738
739 /* Available values for -mabi=. */
740
741 static const struct abi_name arm_all_abis[] =
742 {
743 {"apcs-gnu", ARM_ABI_APCS},
744 {"atpcs", ARM_ABI_ATPCS},
745 {"aapcs", ARM_ABI_AAPCS},
746 {"iwmmxt", ARM_ABI_IWMMXT},
747 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
748 };
749
750 /* Supported TLS relocations. */
751
752 enum tls_reloc {
753 TLS_GD32,
754 TLS_LDM32,
755 TLS_LDO32,
756 TLS_IE32,
757 TLS_LE32
758 };
759
760 /* Emit an insn that's a simple single-set. Both the operands must be known
761 to be valid. */
762 inline static rtx
763 emit_set_insn (rtx x, rtx y)
764 {
765 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
766 }
767
768 /* Return the number of bits set in VALUE. */
769 static unsigned
770 bit_count (unsigned long value)
771 {
772 unsigned long count = 0;
773
774 while (value)
775 {
776 count++;
777 value &= value - 1; /* Clear the least-significant set bit. */
778 }
779
780 return count;
781 }
782
783 /* Set up library functions unique to ARM. */
784
785 static void
786 arm_init_libfuncs (void)
787 {
788 /* There are no special library functions unless we are using the
789 ARM BPABI. */
790 if (!TARGET_BPABI)
791 return;
792
793 /* The functions below are described in Section 4 of the "Run-Time
794 ABI for the ARM architecture", Version 1.0. */
795
796 /* Double-precision floating-point arithmetic. Table 2. */
797 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
798 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
799 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
800 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
801 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
802
803 /* Double-precision comparisons. Table 3. */
804 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
805 set_optab_libfunc (ne_optab, DFmode, NULL);
806 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
807 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
808 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
809 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
810 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
811
812 /* Single-precision floating-point arithmetic. Table 4. */
813 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
814 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
815 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
816 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
817 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
818
819 /* Single-precision comparisons. Table 5. */
820 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
821 set_optab_libfunc (ne_optab, SFmode, NULL);
822 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
823 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
824 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
825 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
826 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
827
828 /* Floating-point to integer conversions. Table 6. */
829 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
830 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
831 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
832 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
833 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
834 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
835 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
836 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
837
838 /* Conversions between floating types. Table 7. */
839 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
840 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
841
842 /* Integer to floating-point conversions. Table 8. */
843 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
844 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
845 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
846 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
847 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
848 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
849 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
850 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
851
852 /* Long long. Table 9. */
853 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
854 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
855 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
856 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
857 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
858 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
859 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
860 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
861
862 /* Integer (32/32->32) division. \S 4.3.1. */
863 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
864 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
865
866 /* The divmod functions are designed so that they can be used for
867 plain division, even though they return both the quotient and the
868 remainder. The quotient is returned in the usual location (i.e.,
869 r0 for SImode, {r0, r1} for DImode), just as would be expected
870 for an ordinary division routine. Because the AAPCS calling
871 conventions specify that all of { r0, r1, r2, r3 } are
872 callee-saved registers, there is no need to tell the compiler
873 explicitly that those registers are clobbered by these
874 routines. */
875 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
876 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
877
878 /* For SImode division the ABI provides div-without-mod routines,
879 which are faster. */
880 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
881 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
882
883 /* We don't have mod libcalls. Fortunately gcc knows how to use the
884 divmod libcalls instead. */
885 set_optab_libfunc (smod_optab, DImode, NULL);
886 set_optab_libfunc (umod_optab, DImode, NULL);
887 set_optab_libfunc (smod_optab, SImode, NULL);
888 set_optab_libfunc (umod_optab, SImode, NULL);
889 }
890
891 /* Implement TARGET_HANDLE_OPTION. */
892
893 static bool
894 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
895 {
896 switch (code)
897 {
898 case OPT_march_:
899 arm_select[1].string = arg;
900 return true;
901
902 case OPT_mcpu_:
903 arm_select[0].string = arg;
904 return true;
905
906 case OPT_mhard_float:
907 target_float_abi_name = "hard";
908 return true;
909
910 case OPT_msoft_float:
911 target_float_abi_name = "soft";
912 return true;
913
914 case OPT_mtune_:
915 arm_select[2].string = arg;
916 return true;
917
918 default:
919 return true;
920 }
921 }
922
923 /* Fix up any incompatible options that the user has specified.
924 This has now turned into a maze. */
925 void
926 arm_override_options (void)
927 {
928 unsigned i;
929 enum processor_type target_arch_cpu = arm_none;
930
931 /* Set up the flags based on the cpu/architecture selected by the user. */
932 for (i = ARRAY_SIZE (arm_select); i--;)
933 {
934 struct arm_cpu_select * ptr = arm_select + i;
935
936 if (ptr->string != NULL && ptr->string[0] != '\0')
937 {
938 const struct processors * sel;
939
940 for (sel = ptr->processors; sel->name != NULL; sel++)
941 if (streq (ptr->string, sel->name))
942 {
943 /* Set the architecture define. */
944 if (i != ARM_OPT_SET_TUNE)
945 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
946
947 /* Determine the processor core for which we should
948 tune code-generation. */
949 if (/* -mcpu= is a sensible default. */
950 i == ARM_OPT_SET_CPU
951 /* -mtune= overrides -mcpu= and -march=. */
952 || i == ARM_OPT_SET_TUNE)
953 arm_tune = (enum processor_type) (sel - ptr->processors);
954
955 /* Remember the CPU associated with this architecture.
956 If no other option is used to set the CPU type,
957 we'll use this to guess the most suitable tuning
958 options. */
959 if (i == ARM_OPT_SET_ARCH)
960 target_arch_cpu = sel->core;
961
962 if (i != ARM_OPT_SET_TUNE)
963 {
964 /* If we have been given an architecture and a processor
965 make sure that they are compatible. We only generate
966 a warning though, and we prefer the CPU over the
967 architecture. */
968 if (insn_flags != 0 && (insn_flags ^ sel->flags))
969 warning (0, "switch -mcpu=%s conflicts with -march= switch",
970 ptr->string);
971
972 insn_flags = sel->flags;
973 }
974
975 break;
976 }
977
978 if (sel->name == NULL)
979 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
980 }
981 }
982
983 /* Guess the tuning options from the architecture if necessary. */
984 if (arm_tune == arm_none)
985 arm_tune = target_arch_cpu;
986
987 /* If the user did not specify a processor, choose one for them. */
988 if (insn_flags == 0)
989 {
990 const struct processors * sel;
991 unsigned int sought;
992 enum processor_type cpu;
993
994 cpu = TARGET_CPU_DEFAULT;
995 if (cpu == arm_none)
996 {
997 #ifdef SUBTARGET_CPU_DEFAULT
998 /* Use the subtarget default CPU if none was specified by
999 configure. */
1000 cpu = SUBTARGET_CPU_DEFAULT;
1001 #endif
1002 /* Default to ARM6. */
1003 if (cpu == arm_none)
1004 cpu = arm6;
1005 }
1006 sel = &all_cores[cpu];
1007
1008 insn_flags = sel->flags;
1009
1010 /* Now check to see if the user has specified some command line
1011 switch that require certain abilities from the cpu. */
1012 sought = 0;
1013
1014 if (TARGET_INTERWORK || TARGET_THUMB)
1015 {
1016 sought |= (FL_THUMB | FL_MODE32);
1017
1018 /* There are no ARM processors that support both APCS-26 and
1019 interworking. Therefore we force FL_MODE26 to be removed
1020 from insn_flags here (if it was set), so that the search
1021 below will always be able to find a compatible processor. */
1022 insn_flags &= ~FL_MODE26;
1023 }
1024
1025 if (sought != 0 && ((sought & insn_flags) != sought))
1026 {
1027 /* Try to locate a CPU type that supports all of the abilities
1028 of the default CPU, plus the extra abilities requested by
1029 the user. */
1030 for (sel = all_cores; sel->name != NULL; sel++)
1031 if ((sel->flags & sought) == (sought | insn_flags))
1032 break;
1033
1034 if (sel->name == NULL)
1035 {
1036 unsigned current_bit_count = 0;
1037 const struct processors * best_fit = NULL;
1038
1039 /* Ideally we would like to issue an error message here
1040 saying that it was not possible to find a CPU compatible
1041 with the default CPU, but which also supports the command
1042 line options specified by the programmer, and so they
1043 ought to use the -mcpu=<name> command line option to
1044 override the default CPU type.
1045
1046 If we cannot find a cpu that has both the
1047 characteristics of the default cpu and the given
1048 command line options we scan the array again looking
1049 for a best match. */
1050 for (sel = all_cores; sel->name != NULL; sel++)
1051 if ((sel->flags & sought) == sought)
1052 {
1053 unsigned count;
1054
1055 count = bit_count (sel->flags & insn_flags);
1056
1057 if (count >= current_bit_count)
1058 {
1059 best_fit = sel;
1060 current_bit_count = count;
1061 }
1062 }
1063
1064 gcc_assert (best_fit);
1065 sel = best_fit;
1066 }
1067
1068 insn_flags = sel->flags;
1069 }
1070 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1071 arm_default_cpu = (enum processor_type) (sel - all_cores);
1072 if (arm_tune == arm_none)
1073 arm_tune = arm_default_cpu;
1074 }
1075
1076 /* The processor for which we should tune should now have been
1077 chosen. */
1078 gcc_assert (arm_tune != arm_none);
1079
1080 tune_flags = all_cores[(int)arm_tune].flags;
1081 if (optimize_size)
1082 targetm.rtx_costs = arm_size_rtx_costs;
1083 else
1084 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1085
1086 /* Make sure that the processor choice does not conflict with any of the
1087 other command line choices. */
1088 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1089 error ("target CPU does not support ARM mode");
1090
1091 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1092 {
1093 warning (0, "target CPU does not support interworking" );
1094 target_flags &= ~MASK_INTERWORK;
1095 }
1096
1097 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1098 {
1099 warning (0, "target CPU does not support THUMB instructions");
1100 target_flags &= ~MASK_THUMB;
1101 }
1102
1103 if (TARGET_APCS_FRAME && TARGET_THUMB)
1104 {
1105 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1106 target_flags &= ~MASK_APCS_FRAME;
1107 }
1108
1109 /* Callee super interworking implies thumb interworking. Adding
1110 this to the flags here simplifies the logic elsewhere. */
1111 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1112 target_flags |= MASK_INTERWORK;
1113
1114 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1115 from here where no function is being compiled currently. */
1116 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1117 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1118
1119 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1120 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1121
1122 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1123 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1124
1125 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1126 {
1127 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1128 target_flags |= MASK_APCS_FRAME;
1129 }
1130
1131 if (TARGET_POKE_FUNCTION_NAME)
1132 target_flags |= MASK_APCS_FRAME;
1133
1134 if (TARGET_APCS_REENT && flag_pic)
1135 error ("-fpic and -mapcs-reent are incompatible");
1136
1137 if (TARGET_APCS_REENT)
1138 warning (0, "APCS reentrant code not supported. Ignored");
1139
1140 /* If this target is normally configured to use APCS frames, warn if they
1141 are turned off and debugging is turned on. */
1142 if (TARGET_ARM
1143 && write_symbols != NO_DEBUG
1144 && !TARGET_APCS_FRAME
1145 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1146 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1147
1148 if (TARGET_APCS_FLOAT)
1149 warning (0, "passing floating point arguments in fp regs not yet supported");
1150
1151 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1152 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1153 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1154 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1155 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1156 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1157 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1158 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1159 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1160 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1161 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1162 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1163
1164 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1165 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1166 thumb_code = (TARGET_ARM == 0);
1167 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1168 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1169 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1170 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
1171
1172 /* V5 code we generate is completely interworking capable, so we turn off
1173 TARGET_INTERWORK here to avoid many tests later on. */
1174
1175 /* XXX However, we must pass the right pre-processor defines to CPP
1176 or GLD can get confused. This is a hack. */
1177 if (TARGET_INTERWORK)
1178 arm_cpp_interwork = 1;
1179
1180 if (arm_arch5)
1181 target_flags &= ~MASK_INTERWORK;
1182
1183 if (target_abi_name)
1184 {
1185 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1186 {
1187 if (streq (arm_all_abis[i].name, target_abi_name))
1188 {
1189 arm_abi = arm_all_abis[i].abi_type;
1190 break;
1191 }
1192 }
1193 if (i == ARRAY_SIZE (arm_all_abis))
1194 error ("invalid ABI option: -mabi=%s", target_abi_name);
1195 }
1196 else
1197 arm_abi = ARM_DEFAULT_ABI;
1198
1199 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1200 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1201
1202 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1203 error ("iwmmxt abi requires an iwmmxt capable cpu");
1204
1205 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1206 if (target_fpu_name == NULL && target_fpe_name != NULL)
1207 {
1208 if (streq (target_fpe_name, "2"))
1209 target_fpu_name = "fpe2";
1210 else if (streq (target_fpe_name, "3"))
1211 target_fpu_name = "fpe3";
1212 else
1213 error ("invalid floating point emulation option: -mfpe=%s",
1214 target_fpe_name);
1215 }
1216 if (target_fpu_name != NULL)
1217 {
1218 /* The user specified a FPU. */
1219 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1220 {
1221 if (streq (all_fpus[i].name, target_fpu_name))
1222 {
1223 arm_fpu_arch = all_fpus[i].fpu;
1224 arm_fpu_tune = arm_fpu_arch;
1225 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1226 break;
1227 }
1228 }
1229 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1230 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1231 }
1232 else
1233 {
1234 #ifdef FPUTYPE_DEFAULT
1235 /* Use the default if it is specified for this platform. */
1236 arm_fpu_arch = FPUTYPE_DEFAULT;
1237 arm_fpu_tune = FPUTYPE_DEFAULT;
1238 #else
1239 /* Pick one based on CPU type. */
1240 /* ??? Some targets assume FPA is the default.
1241 if ((insn_flags & FL_VFP) != 0)
1242 arm_fpu_arch = FPUTYPE_VFP;
1243 else
1244 */
1245 if (arm_arch_cirrus)
1246 arm_fpu_arch = FPUTYPE_MAVERICK;
1247 else
1248 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1249 #endif
1250 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1251 arm_fpu_tune = FPUTYPE_FPA;
1252 else
1253 arm_fpu_tune = arm_fpu_arch;
1254 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1255 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1256 }
1257
1258 if (target_float_abi_name != NULL)
1259 {
1260 /* The user specified a FP ABI. */
1261 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1262 {
1263 if (streq (all_float_abis[i].name, target_float_abi_name))
1264 {
1265 arm_float_abi = all_float_abis[i].abi_type;
1266 break;
1267 }
1268 }
1269 if (i == ARRAY_SIZE (all_float_abis))
1270 error ("invalid floating point abi: -mfloat-abi=%s",
1271 target_float_abi_name);
1272 }
1273 else
1274 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1275
1276 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1277 sorry ("-mfloat-abi=hard and VFP");
1278
1279 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1280 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1281 will ever exist. GCC makes no attempt to support this combination. */
1282 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1283 sorry ("iWMMXt and hardware floating point");
1284
1285 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1286 if (TARGET_THUMB2 && TARGET_IWMMXT)
1287 sorry ("Thumb-2 iWMMXt");
1288
1289 /* If soft-float is specified then don't use FPU. */
1290 if (TARGET_SOFT_FLOAT)
1291 arm_fpu_arch = FPUTYPE_NONE;
1292
1293 /* For arm2/3 there is no need to do any scheduling if there is only
1294 a floating point emulator, or we are doing software floating-point. */
1295 if ((TARGET_SOFT_FLOAT
1296 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1297 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1298 && (tune_flags & FL_MODE32) == 0)
1299 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1300
1301 if (target_thread_switch)
1302 {
1303 if (strcmp (target_thread_switch, "soft") == 0)
1304 target_thread_pointer = TP_SOFT;
1305 else if (strcmp (target_thread_switch, "auto") == 0)
1306 target_thread_pointer = TP_AUTO;
1307 else if (strcmp (target_thread_switch, "cp15") == 0)
1308 target_thread_pointer = TP_CP15;
1309 else
1310 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1311 }
1312
1313 /* Use the cp15 method if it is available. */
1314 if (target_thread_pointer == TP_AUTO)
1315 {
1316 if (arm_arch6k && !TARGET_THUMB)
1317 target_thread_pointer = TP_CP15;
1318 else
1319 target_thread_pointer = TP_SOFT;
1320 }
1321
1322 if (TARGET_HARD_TP && TARGET_THUMB1)
1323 error ("can not use -mtp=cp15 with 16-bit Thumb");
1324
1325 /* Override the default structure alignment for AAPCS ABI. */
1326 if (TARGET_AAPCS_BASED)
1327 arm_structure_size_boundary = 8;
1328
1329 if (structure_size_string != NULL)
1330 {
1331 int size = strtol (structure_size_string, NULL, 0);
1332
1333 if (size == 8 || size == 32
1334 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1335 arm_structure_size_boundary = size;
1336 else
1337 warning (0, "structure size boundary can only be set to %s",
1338 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1339 }
1340
1341 /* If stack checking is disabled, we can use r10 as the PIC register,
1342 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1343 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1344 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1345
1346 if (arm_pic_register_string != NULL)
1347 {
1348 int pic_register = decode_reg_name (arm_pic_register_string);
1349
1350 if (!flag_pic)
1351 warning (0, "-mpic-register= is useless without -fpic");
1352
1353 /* Prevent the user from choosing an obviously stupid PIC register. */
1354 else if (pic_register < 0 || call_used_regs[pic_register]
1355 || pic_register == HARD_FRAME_POINTER_REGNUM
1356 || pic_register == STACK_POINTER_REGNUM
1357 || pic_register >= PC_REGNUM)
1358 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1359 else
1360 arm_pic_register = pic_register;
1361 }
1362
1363 /* ??? We might want scheduling for thumb2. */
1364 if (TARGET_THUMB && flag_schedule_insns)
1365 {
1366 /* Don't warn since it's on by default in -O2. */
1367 flag_schedule_insns = 0;
1368 }
1369
1370 if (optimize_size)
1371 {
1372 arm_constant_limit = 1;
1373
1374 /* If optimizing for size, bump the number of instructions that we
1375 are prepared to conditionally execute (even on a StrongARM). */
1376 max_insns_skipped = 6;
1377 }
1378 else
1379 {
1380 /* For processors with load scheduling, it never costs more than
1381 2 cycles to load a constant, and the load scheduler may well
1382 reduce that to 1. */
1383 if (arm_ld_sched)
1384 arm_constant_limit = 1;
1385
1386 /* On XScale the longer latency of a load makes it more difficult
1387 to achieve a good schedule, so it's faster to synthesize
1388 constants that can be done in two insns. */
1389 if (arm_tune_xscale)
1390 arm_constant_limit = 2;
1391
1392 /* StrongARM has early execution of branches, so a sequence
1393 that is worth skipping is shorter. */
1394 if (arm_tune_strongarm)
1395 max_insns_skipped = 3;
1396 }
1397
1398 /* Register global variables with the garbage collector. */
1399 arm_add_gc_roots ();
1400 }
1401
1402 static void
1403 arm_add_gc_roots (void)
1404 {
1405 gcc_obstack_init(&minipool_obstack);
1406 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1407 }
1408 \f
1409 /* A table of known ARM exception types.
1410 For use with the interrupt function attribute. */
1411
1412 typedef struct
1413 {
1414 const char *const arg;
1415 const unsigned long return_value;
1416 }
1417 isr_attribute_arg;
1418
1419 static const isr_attribute_arg isr_attribute_args [] =
1420 {
1421 { "IRQ", ARM_FT_ISR },
1422 { "irq", ARM_FT_ISR },
1423 { "FIQ", ARM_FT_FIQ },
1424 { "fiq", ARM_FT_FIQ },
1425 { "ABORT", ARM_FT_ISR },
1426 { "abort", ARM_FT_ISR },
1427 { "ABORT", ARM_FT_ISR },
1428 { "abort", ARM_FT_ISR },
1429 { "UNDEF", ARM_FT_EXCEPTION },
1430 { "undef", ARM_FT_EXCEPTION },
1431 { "SWI", ARM_FT_EXCEPTION },
1432 { "swi", ARM_FT_EXCEPTION },
1433 { NULL, ARM_FT_NORMAL }
1434 };
1435
1436 /* Returns the (interrupt) function type of the current
1437 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1438
1439 static unsigned long
1440 arm_isr_value (tree argument)
1441 {
1442 const isr_attribute_arg * ptr;
1443 const char * arg;
1444
1445 if (!arm_arch_notm)
1446 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1447
1448 /* No argument - default to IRQ. */
1449 if (argument == NULL_TREE)
1450 return ARM_FT_ISR;
1451
1452 /* Get the value of the argument. */
1453 if (TREE_VALUE (argument) == NULL_TREE
1454 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1455 return ARM_FT_UNKNOWN;
1456
1457 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1458
1459 /* Check it against the list of known arguments. */
1460 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1461 if (streq (arg, ptr->arg))
1462 return ptr->return_value;
1463
1464 /* An unrecognized interrupt type. */
1465 return ARM_FT_UNKNOWN;
1466 }
1467
1468 /* Computes the type of the current function. */
1469
1470 static unsigned long
1471 arm_compute_func_type (void)
1472 {
1473 unsigned long type = ARM_FT_UNKNOWN;
1474 tree a;
1475 tree attr;
1476
1477 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1478
1479 /* Decide if the current function is volatile. Such functions
1480 never return, and many memory cycles can be saved by not storing
1481 register values that will never be needed again. This optimization
1482 was added to speed up context switching in a kernel application. */
1483 if (optimize > 0
1484 && (TREE_NOTHROW (current_function_decl)
1485 || !(flag_unwind_tables
1486 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1487 && TREE_THIS_VOLATILE (current_function_decl))
1488 type |= ARM_FT_VOLATILE;
1489
1490 if (cfun->static_chain_decl != NULL)
1491 type |= ARM_FT_NESTED;
1492
1493 attr = DECL_ATTRIBUTES (current_function_decl);
1494
1495 a = lookup_attribute ("naked", attr);
1496 if (a != NULL_TREE)
1497 type |= ARM_FT_NAKED;
1498
1499 a = lookup_attribute ("isr", attr);
1500 if (a == NULL_TREE)
1501 a = lookup_attribute ("interrupt", attr);
1502
1503 if (a == NULL_TREE)
1504 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1505 else
1506 type |= arm_isr_value (TREE_VALUE (a));
1507
1508 return type;
1509 }
1510
1511 /* Returns the type of the current function. */
1512
1513 unsigned long
1514 arm_current_func_type (void)
1515 {
1516 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1517 cfun->machine->func_type = arm_compute_func_type ();
1518
1519 return cfun->machine->func_type;
1520 }
1521 \f
1522 /* Return 1 if it is possible to return using a single instruction.
1523 If SIBLING is non-null, this is a test for a return before a sibling
1524 call. SIBLING is the call insn, so we can examine its register usage. */
1525
1526 int
1527 use_return_insn (int iscond, rtx sibling)
1528 {
1529 int regno;
1530 unsigned int func_type;
1531 unsigned long saved_int_regs;
1532 unsigned HOST_WIDE_INT stack_adjust;
1533 arm_stack_offsets *offsets;
1534
1535 /* Never use a return instruction before reload has run. */
1536 if (!reload_completed)
1537 return 0;
1538
1539 func_type = arm_current_func_type ();
1540
1541 /* Naked, volatile and stack alignment functions need special
1542 consideration. */
1543 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
1544 return 0;
1545
1546 /* So do interrupt functions that use the frame pointer and Thumb
1547 interrupt functions. */
1548 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
1549 return 0;
1550
1551 offsets = arm_get_frame_offsets ();
1552 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1553
1554 /* As do variadic functions. */
1555 if (current_function_pretend_args_size
1556 || cfun->machine->uses_anonymous_args
1557 /* Or if the function calls __builtin_eh_return () */
1558 || current_function_calls_eh_return
1559 /* Or if the function calls alloca */
1560 || current_function_calls_alloca
1561 /* Or if there is a stack adjustment. However, if the stack pointer
1562 is saved on the stack, we can use a pre-incrementing stack load. */
1563 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1564 return 0;
1565
1566 saved_int_regs = arm_compute_save_reg_mask ();
1567
1568 /* Unfortunately, the insn
1569
1570 ldmib sp, {..., sp, ...}
1571
1572 triggers a bug on most SA-110 based devices, such that the stack
1573 pointer won't be correctly restored if the instruction takes a
1574 page fault. We work around this problem by popping r3 along with
1575 the other registers, since that is never slower than executing
1576 another instruction.
1577
1578 We test for !arm_arch5 here, because code for any architecture
1579 less than this could potentially be run on one of the buggy
1580 chips. */
1581 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
1582 {
1583 /* Validate that r3 is a call-clobbered register (always true in
1584 the default abi) ... */
1585 if (!call_used_regs[3])
1586 return 0;
1587
1588 /* ... that it isn't being used for a return value ... */
1589 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1590 return 0;
1591
1592 /* ... or for a tail-call argument ... */
1593 if (sibling)
1594 {
1595 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1596
1597 if (find_regno_fusage (sibling, USE, 3))
1598 return 0;
1599 }
1600
1601 /* ... and that there are no call-saved registers in r0-r2
1602 (always true in the default ABI). */
1603 if (saved_int_regs & 0x7)
1604 return 0;
1605 }
1606
1607 /* Can't be done if interworking with Thumb, and any registers have been
1608 stacked. */
1609 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
1610 return 0;
1611
1612 /* On StrongARM, conditional returns are expensive if they aren't
1613 taken and multiple registers have been stacked. */
1614 if (iscond && arm_tune_strongarm)
1615 {
1616 /* Conditional return when just the LR is stored is a simple
1617 conditional-load instruction, that's not expensive. */
1618 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1619 return 0;
1620
1621 if (flag_pic
1622 && arm_pic_register != INVALID_REGNUM
1623 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1624 return 0;
1625 }
1626
1627 /* If there are saved registers but the LR isn't saved, then we need
1628 two instructions for the return. */
1629 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1630 return 0;
1631
1632 /* Can't be done if any of the FPA regs are pushed,
1633 since this also requires an insn. */
1634 if (TARGET_HARD_FLOAT && TARGET_FPA)
1635 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1636 if (regs_ever_live[regno] && !call_used_regs[regno])
1637 return 0;
1638
1639 /* Likewise VFP regs. */
1640 if (TARGET_HARD_FLOAT && TARGET_VFP)
1641 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1642 if (regs_ever_live[regno] && !call_used_regs[regno])
1643 return 0;
1644
1645 if (TARGET_REALLY_IWMMXT)
1646 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1647 if (regs_ever_live[regno] && ! call_used_regs [regno])
1648 return 0;
1649
1650 return 1;
1651 }
1652
1653 /* Return TRUE if int I is a valid immediate ARM constant. */
1654
1655 int
1656 const_ok_for_arm (HOST_WIDE_INT i)
1657 {
1658 int lowbit;
1659
1660 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1661 be all zero, or all one. */
1662 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1663 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1664 != ((~(unsigned HOST_WIDE_INT) 0)
1665 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1666 return FALSE;
1667
1668 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1669
1670 /* Fast return for 0 and small values. We must do this for zero, since
1671 the code below can't handle that one case. */
1672 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1673 return TRUE;
1674
1675 /* Get the number of trailing zeros. */
1676 lowbit = ffs((int) i) - 1;
1677
1678 /* Only even shifts are allowed in ARM mode so round down to the
1679 nearest even number. */
1680 if (TARGET_ARM)
1681 lowbit &= ~1;
1682
1683 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1684 return TRUE;
1685
1686 if (TARGET_ARM)
1687 {
1688 /* Allow rotated constants in ARM mode. */
1689 if (lowbit <= 4
1690 && ((i & ~0xc000003f) == 0
1691 || (i & ~0xf000000f) == 0
1692 || (i & ~0xfc000003) == 0))
1693 return TRUE;
1694 }
1695 else
1696 {
1697 HOST_WIDE_INT v;
1698
1699 /* Allow repeated pattern. */
1700 v = i & 0xff;
1701 v |= v << 16;
1702 if (i == v || i == (v | (v << 8)))
1703 return TRUE;
1704 }
1705
1706 return FALSE;
1707 }
1708
1709 /* Return true if I is a valid constant for the operation CODE. */
1710 static int
1711 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1712 {
1713 if (const_ok_for_arm (i))
1714 return 1;
1715
1716 switch (code)
1717 {
1718 case PLUS:
1719 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1720
1721 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1722 case XOR:
1723 case IOR:
1724 return 0;
1725
1726 case AND:
1727 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1728
1729 default:
1730 gcc_unreachable ();
1731 }
1732 }
1733
1734 /* Emit a sequence of insns to handle a large constant.
1735 CODE is the code of the operation required, it can be any of SET, PLUS,
1736 IOR, AND, XOR, MINUS;
1737 MODE is the mode in which the operation is being performed;
1738 VAL is the integer to operate on;
1739 SOURCE is the other operand (a register, or a null-pointer for SET);
1740 SUBTARGETS means it is safe to create scratch registers if that will
1741 either produce a simpler sequence, or we will want to cse the values.
1742 Return value is the number of insns emitted. */
1743
1744 /* ??? Tweak this for thumb2. */
1745 int
1746 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1747 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1748 {
1749 rtx cond;
1750
1751 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1752 cond = COND_EXEC_TEST (PATTERN (insn));
1753 else
1754 cond = NULL_RTX;
1755
1756 if (subtargets || code == SET
1757 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1758 && REGNO (target) != REGNO (source)))
1759 {
1760 /* After arm_reorg has been called, we can't fix up expensive
1761 constants by pushing them into memory so we must synthesize
1762 them in-line, regardless of the cost. This is only likely to
1763 be more costly on chips that have load delay slots and we are
1764 compiling without running the scheduler (so no splitting
1765 occurred before the final instruction emission).
1766
1767 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1768 */
1769 if (!after_arm_reorg
1770 && !cond
1771 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1772 1, 0)
1773 > arm_constant_limit + (code != SET)))
1774 {
1775 if (code == SET)
1776 {
1777 /* Currently SET is the only monadic value for CODE, all
1778 the rest are diadic. */
1779 emit_set_insn (target, GEN_INT (val));
1780 return 1;
1781 }
1782 else
1783 {
1784 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1785
1786 emit_set_insn (temp, GEN_INT (val));
1787 /* For MINUS, the value is subtracted from, since we never
1788 have subtraction of a constant. */
1789 if (code == MINUS)
1790 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1791 else
1792 emit_set_insn (target,
1793 gen_rtx_fmt_ee (code, mode, source, temp));
1794 return 2;
1795 }
1796 }
1797 }
1798
1799 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1800 1);
1801 }
1802
1803 /* Return the number of ARM instructions required to synthesize the given
1804 constant. */
1805 static int
1806 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1807 {
1808 HOST_WIDE_INT temp1;
1809 int num_insns = 0;
1810 do
1811 {
1812 int end;
1813
1814 if (i <= 0)
1815 i += 32;
1816 if (remainder & (3 << (i - 2)))
1817 {
1818 end = i - 8;
1819 if (end < 0)
1820 end += 32;
1821 temp1 = remainder & ((0x0ff << end)
1822 | ((i < end) ? (0xff >> (32 - end)) : 0));
1823 remainder &= ~temp1;
1824 num_insns++;
1825 i -= 6;
1826 }
1827 i -= 2;
1828 } while (remainder);
1829 return num_insns;
1830 }
1831
1832 /* Emit an instruction with the indicated PATTERN. If COND is
1833 non-NULL, conditionalize the execution of the instruction on COND
1834 being true. */
1835
1836 static void
1837 emit_constant_insn (rtx cond, rtx pattern)
1838 {
1839 if (cond)
1840 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1841 emit_insn (pattern);
1842 }
1843
1844 /* As above, but extra parameter GENERATE which, if clear, suppresses
1845 RTL generation. */
1846 /* ??? This needs more work for thumb2. */
1847
1848 static int
1849 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1850 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1851 int generate)
1852 {
1853 int can_invert = 0;
1854 int can_negate = 0;
1855 int can_negate_initial = 0;
1856 int can_shift = 0;
1857 int i;
1858 int num_bits_set = 0;
1859 int set_sign_bit_copies = 0;
1860 int clear_sign_bit_copies = 0;
1861 int clear_zero_bit_copies = 0;
1862 int set_zero_bit_copies = 0;
1863 int insns = 0;
1864 unsigned HOST_WIDE_INT temp1, temp2;
1865 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1866
1867 /* Find out which operations are safe for a given CODE. Also do a quick
1868 check for degenerate cases; these can occur when DImode operations
1869 are split. */
1870 switch (code)
1871 {
1872 case SET:
1873 can_invert = 1;
1874 can_shift = 1;
1875 can_negate = 1;
1876 break;
1877
1878 case PLUS:
1879 can_negate = 1;
1880 can_negate_initial = 1;
1881 break;
1882
1883 case IOR:
1884 if (remainder == 0xffffffff)
1885 {
1886 if (generate)
1887 emit_constant_insn (cond,
1888 gen_rtx_SET (VOIDmode, target,
1889 GEN_INT (ARM_SIGN_EXTEND (val))));
1890 return 1;
1891 }
1892 if (remainder == 0)
1893 {
1894 if (reload_completed && rtx_equal_p (target, source))
1895 return 0;
1896 if (generate)
1897 emit_constant_insn (cond,
1898 gen_rtx_SET (VOIDmode, target, source));
1899 return 1;
1900 }
1901 break;
1902
1903 case AND:
1904 if (remainder == 0)
1905 {
1906 if (generate)
1907 emit_constant_insn (cond,
1908 gen_rtx_SET (VOIDmode, target, const0_rtx));
1909 return 1;
1910 }
1911 if (remainder == 0xffffffff)
1912 {
1913 if (reload_completed && rtx_equal_p (target, source))
1914 return 0;
1915 if (generate)
1916 emit_constant_insn (cond,
1917 gen_rtx_SET (VOIDmode, target, source));
1918 return 1;
1919 }
1920 can_invert = 1;
1921 break;
1922
1923 case XOR:
1924 if (remainder == 0)
1925 {
1926 if (reload_completed && rtx_equal_p (target, source))
1927 return 0;
1928 if (generate)
1929 emit_constant_insn (cond,
1930 gen_rtx_SET (VOIDmode, target, source));
1931 return 1;
1932 }
1933
1934 /* We don't know how to handle other cases yet. */
1935 gcc_assert (remainder == 0xffffffff);
1936
1937 if (generate)
1938 emit_constant_insn (cond,
1939 gen_rtx_SET (VOIDmode, target,
1940 gen_rtx_NOT (mode, source)));
1941 return 1;
1942
1943 case MINUS:
1944 /* We treat MINUS as (val - source), since (source - val) is always
1945 passed as (source + (-val)). */
1946 if (remainder == 0)
1947 {
1948 if (generate)
1949 emit_constant_insn (cond,
1950 gen_rtx_SET (VOIDmode, target,
1951 gen_rtx_NEG (mode, source)));
1952 return 1;
1953 }
1954 if (const_ok_for_arm (val))
1955 {
1956 if (generate)
1957 emit_constant_insn (cond,
1958 gen_rtx_SET (VOIDmode, target,
1959 gen_rtx_MINUS (mode, GEN_INT (val),
1960 source)));
1961 return 1;
1962 }
1963 can_negate = 1;
1964
1965 break;
1966
1967 default:
1968 gcc_unreachable ();
1969 }
1970
1971 /* If we can do it in one insn get out quickly. */
1972 if (const_ok_for_arm (val)
1973 || (can_negate_initial && const_ok_for_arm (-val))
1974 || (can_invert && const_ok_for_arm (~val)))
1975 {
1976 if (generate)
1977 emit_constant_insn (cond,
1978 gen_rtx_SET (VOIDmode, target,
1979 (source
1980 ? gen_rtx_fmt_ee (code, mode, source,
1981 GEN_INT (val))
1982 : GEN_INT (val))));
1983 return 1;
1984 }
1985
1986 /* Calculate a few attributes that may be useful for specific
1987 optimizations. */
1988 for (i = 31; i >= 0; i--)
1989 {
1990 if ((remainder & (1 << i)) == 0)
1991 clear_sign_bit_copies++;
1992 else
1993 break;
1994 }
1995
1996 for (i = 31; i >= 0; i--)
1997 {
1998 if ((remainder & (1 << i)) != 0)
1999 set_sign_bit_copies++;
2000 else
2001 break;
2002 }
2003
2004 for (i = 0; i <= 31; i++)
2005 {
2006 if ((remainder & (1 << i)) == 0)
2007 clear_zero_bit_copies++;
2008 else
2009 break;
2010 }
2011
2012 for (i = 0; i <= 31; i++)
2013 {
2014 if ((remainder & (1 << i)) != 0)
2015 set_zero_bit_copies++;
2016 else
2017 break;
2018 }
2019
2020 switch (code)
2021 {
2022 case SET:
2023 /* See if we can use movw. */
2024 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2025 {
2026 if (generate)
2027 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2028 GEN_INT (val)));
2029 return 1;
2030 }
2031
2032 /* See if we can do this by sign_extending a constant that is known
2033 to be negative. This is a good, way of doing it, since the shift
2034 may well merge into a subsequent insn. */
2035 if (set_sign_bit_copies > 1)
2036 {
2037 if (const_ok_for_arm
2038 (temp1 = ARM_SIGN_EXTEND (remainder
2039 << (set_sign_bit_copies - 1))))
2040 {
2041 if (generate)
2042 {
2043 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2044 emit_constant_insn (cond,
2045 gen_rtx_SET (VOIDmode, new_src,
2046 GEN_INT (temp1)));
2047 emit_constant_insn (cond,
2048 gen_ashrsi3 (target, new_src,
2049 GEN_INT (set_sign_bit_copies - 1)));
2050 }
2051 return 2;
2052 }
2053 /* For an inverted constant, we will need to set the low bits,
2054 these will be shifted out of harm's way. */
2055 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2056 if (const_ok_for_arm (~temp1))
2057 {
2058 if (generate)
2059 {
2060 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2061 emit_constant_insn (cond,
2062 gen_rtx_SET (VOIDmode, new_src,
2063 GEN_INT (temp1)));
2064 emit_constant_insn (cond,
2065 gen_ashrsi3 (target, new_src,
2066 GEN_INT (set_sign_bit_copies - 1)));
2067 }
2068 return 2;
2069 }
2070 }
2071
2072 /* See if we can calculate the value as the difference between two
2073 valid immediates. */
2074 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2075 {
2076 int topshift = clear_sign_bit_copies & ~1;
2077
2078 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2079 & (0xff000000 >> topshift));
2080
2081 /* If temp1 is zero, then that means the 9 most significant
2082 bits of remainder were 1 and we've caused it to overflow.
2083 When topshift is 0 we don't need to do anything since we
2084 can borrow from 'bit 32'. */
2085 if (temp1 == 0 && topshift != 0)
2086 temp1 = 0x80000000 >> (topshift - 1);
2087
2088 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
2089
2090 if (const_ok_for_arm (temp2))
2091 {
2092 if (generate)
2093 {
2094 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2095 emit_constant_insn (cond,
2096 gen_rtx_SET (VOIDmode, new_src,
2097 GEN_INT (temp1)));
2098 emit_constant_insn (cond,
2099 gen_addsi3 (target, new_src,
2100 GEN_INT (-temp2)));
2101 }
2102
2103 return 2;
2104 }
2105 }
2106
2107 /* See if we can generate this by setting the bottom (or the top)
2108 16 bits, and then shifting these into the other half of the
2109 word. We only look for the simplest cases, to do more would cost
2110 too much. Be careful, however, not to generate this when the
2111 alternative would take fewer insns. */
2112 if (val & 0xffff0000)
2113 {
2114 temp1 = remainder & 0xffff0000;
2115 temp2 = remainder & 0x0000ffff;
2116
2117 /* Overlaps outside this range are best done using other methods. */
2118 for (i = 9; i < 24; i++)
2119 {
2120 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2121 && !const_ok_for_arm (temp2))
2122 {
2123 rtx new_src = (subtargets
2124 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2125 : target);
2126 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2127 source, subtargets, generate);
2128 source = new_src;
2129 if (generate)
2130 emit_constant_insn
2131 (cond,
2132 gen_rtx_SET
2133 (VOIDmode, target,
2134 gen_rtx_IOR (mode,
2135 gen_rtx_ASHIFT (mode, source,
2136 GEN_INT (i)),
2137 source)));
2138 return insns + 1;
2139 }
2140 }
2141
2142 /* Don't duplicate cases already considered. */
2143 for (i = 17; i < 24; i++)
2144 {
2145 if (((temp1 | (temp1 >> i)) == remainder)
2146 && !const_ok_for_arm (temp1))
2147 {
2148 rtx new_src = (subtargets
2149 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2150 : target);
2151 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2152 source, subtargets, generate);
2153 source = new_src;
2154 if (generate)
2155 emit_constant_insn
2156 (cond,
2157 gen_rtx_SET (VOIDmode, target,
2158 gen_rtx_IOR
2159 (mode,
2160 gen_rtx_LSHIFTRT (mode, source,
2161 GEN_INT (i)),
2162 source)));
2163 return insns + 1;
2164 }
2165 }
2166 }
2167 break;
2168
2169 case IOR:
2170 case XOR:
2171 /* If we have IOR or XOR, and the constant can be loaded in a
2172 single instruction, and we can find a temporary to put it in,
2173 then this can be done in two instructions instead of 3-4. */
2174 if (subtargets
2175 /* TARGET can't be NULL if SUBTARGETS is 0 */
2176 || (reload_completed && !reg_mentioned_p (target, source)))
2177 {
2178 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2179 {
2180 if (generate)
2181 {
2182 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2183
2184 emit_constant_insn (cond,
2185 gen_rtx_SET (VOIDmode, sub,
2186 GEN_INT (val)));
2187 emit_constant_insn (cond,
2188 gen_rtx_SET (VOIDmode, target,
2189 gen_rtx_fmt_ee (code, mode,
2190 source, sub)));
2191 }
2192 return 2;
2193 }
2194 }
2195
2196 if (code == XOR)
2197 break;
2198
2199 if (set_sign_bit_copies > 8
2200 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2201 {
2202 if (generate)
2203 {
2204 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2205 rtx shift = GEN_INT (set_sign_bit_copies);
2206
2207 emit_constant_insn
2208 (cond,
2209 gen_rtx_SET (VOIDmode, sub,
2210 gen_rtx_NOT (mode,
2211 gen_rtx_ASHIFT (mode,
2212 source,
2213 shift))));
2214 emit_constant_insn
2215 (cond,
2216 gen_rtx_SET (VOIDmode, target,
2217 gen_rtx_NOT (mode,
2218 gen_rtx_LSHIFTRT (mode, sub,
2219 shift))));
2220 }
2221 return 2;
2222 }
2223
2224 if (set_zero_bit_copies > 8
2225 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2226 {
2227 if (generate)
2228 {
2229 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2230 rtx shift = GEN_INT (set_zero_bit_copies);
2231
2232 emit_constant_insn
2233 (cond,
2234 gen_rtx_SET (VOIDmode, sub,
2235 gen_rtx_NOT (mode,
2236 gen_rtx_LSHIFTRT (mode,
2237 source,
2238 shift))));
2239 emit_constant_insn
2240 (cond,
2241 gen_rtx_SET (VOIDmode, target,
2242 gen_rtx_NOT (mode,
2243 gen_rtx_ASHIFT (mode, sub,
2244 shift))));
2245 }
2246 return 2;
2247 }
2248
2249 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2250 {
2251 if (generate)
2252 {
2253 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2254 emit_constant_insn (cond,
2255 gen_rtx_SET (VOIDmode, sub,
2256 gen_rtx_NOT (mode, source)));
2257 source = sub;
2258 if (subtargets)
2259 sub = gen_reg_rtx (mode);
2260 emit_constant_insn (cond,
2261 gen_rtx_SET (VOIDmode, sub,
2262 gen_rtx_AND (mode, source,
2263 GEN_INT (temp1))));
2264 emit_constant_insn (cond,
2265 gen_rtx_SET (VOIDmode, target,
2266 gen_rtx_NOT (mode, sub)));
2267 }
2268 return 3;
2269 }
2270 break;
2271
2272 case AND:
2273 /* See if two shifts will do 2 or more insn's worth of work. */
2274 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2275 {
2276 HOST_WIDE_INT shift_mask = ((0xffffffff
2277 << (32 - clear_sign_bit_copies))
2278 & 0xffffffff);
2279
2280 if ((remainder | shift_mask) != 0xffffffff)
2281 {
2282 if (generate)
2283 {
2284 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2285 insns = arm_gen_constant (AND, mode, cond,
2286 remainder | shift_mask,
2287 new_src, source, subtargets, 1);
2288 source = new_src;
2289 }
2290 else
2291 {
2292 rtx targ = subtargets ? NULL_RTX : target;
2293 insns = arm_gen_constant (AND, mode, cond,
2294 remainder | shift_mask,
2295 targ, source, subtargets, 0);
2296 }
2297 }
2298
2299 if (generate)
2300 {
2301 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2302 rtx shift = GEN_INT (clear_sign_bit_copies);
2303
2304 emit_insn (gen_ashlsi3 (new_src, source, shift));
2305 emit_insn (gen_lshrsi3 (target, new_src, shift));
2306 }
2307
2308 return insns + 2;
2309 }
2310
2311 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2312 {
2313 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2314
2315 if ((remainder | shift_mask) != 0xffffffff)
2316 {
2317 if (generate)
2318 {
2319 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2320
2321 insns = arm_gen_constant (AND, mode, cond,
2322 remainder | shift_mask,
2323 new_src, source, subtargets, 1);
2324 source = new_src;
2325 }
2326 else
2327 {
2328 rtx targ = subtargets ? NULL_RTX : target;
2329
2330 insns = arm_gen_constant (AND, mode, cond,
2331 remainder | shift_mask,
2332 targ, source, subtargets, 0);
2333 }
2334 }
2335
2336 if (generate)
2337 {
2338 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2339 rtx shift = GEN_INT (clear_zero_bit_copies);
2340
2341 emit_insn (gen_lshrsi3 (new_src, source, shift));
2342 emit_insn (gen_ashlsi3 (target, new_src, shift));
2343 }
2344
2345 return insns + 2;
2346 }
2347
2348 break;
2349
2350 default:
2351 break;
2352 }
2353
2354 for (i = 0; i < 32; i++)
2355 if (remainder & (1 << i))
2356 num_bits_set++;
2357
2358 if (code == AND || (can_invert && num_bits_set > 16))
2359 remainder = (~remainder) & 0xffffffff;
2360 else if (code == PLUS && num_bits_set > 16)
2361 remainder = (-remainder) & 0xffffffff;
2362 else
2363 {
2364 can_invert = 0;
2365 can_negate = 0;
2366 }
2367
2368 /* Now try and find a way of doing the job in either two or three
2369 instructions.
2370 We start by looking for the largest block of zeros that are aligned on
2371 a 2-bit boundary, we then fill up the temps, wrapping around to the
2372 top of the word when we drop off the bottom.
2373 In the worst case this code should produce no more than four insns.
2374 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2375 best place to start. */
2376
2377 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2378 the same. */
2379 {
2380 int best_start = 0;
2381 if (!TARGET_THUMB2)
2382 {
2383 int best_consecutive_zeros = 0;
2384
2385 for (i = 0; i < 32; i += 2)
2386 {
2387 int consecutive_zeros = 0;
2388
2389 if (!(remainder & (3 << i)))
2390 {
2391 while ((i < 32) && !(remainder & (3 << i)))
2392 {
2393 consecutive_zeros += 2;
2394 i += 2;
2395 }
2396 if (consecutive_zeros > best_consecutive_zeros)
2397 {
2398 best_consecutive_zeros = consecutive_zeros;
2399 best_start = i - consecutive_zeros;
2400 }
2401 i -= 2;
2402 }
2403 }
2404
2405 /* So long as it won't require any more insns to do so, it's
2406 desirable to emit a small constant (in bits 0...9) in the last
2407 insn. This way there is more chance that it can be combined with
2408 a later addressing insn to form a pre-indexed load or store
2409 operation. Consider:
2410
2411 *((volatile int *)0xe0000100) = 1;
2412 *((volatile int *)0xe0000110) = 2;
2413
2414 We want this to wind up as:
2415
2416 mov rA, #0xe0000000
2417 mov rB, #1
2418 str rB, [rA, #0x100]
2419 mov rB, #2
2420 str rB, [rA, #0x110]
2421
2422 rather than having to synthesize both large constants from scratch.
2423
2424 Therefore, we calculate how many insns would be required to emit
2425 the constant starting from `best_start', and also starting from
2426 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2427 yield a shorter sequence, we may as well use zero. */
2428 if (best_start != 0
2429 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2430 && (count_insns_for_constant (remainder, 0) <=
2431 count_insns_for_constant (remainder, best_start)))
2432 best_start = 0;
2433 }
2434
2435 /* Now start emitting the insns. */
2436 i = best_start;
2437 do
2438 {
2439 int end;
2440
2441 if (i <= 0)
2442 i += 32;
2443 if (remainder & (3 << (i - 2)))
2444 {
2445 end = i - 8;
2446 if (end < 0)
2447 end += 32;
2448 temp1 = remainder & ((0x0ff << end)
2449 | ((i < end) ? (0xff >> (32 - end)) : 0));
2450 remainder &= ~temp1;
2451
2452 if (generate)
2453 {
2454 rtx new_src, temp1_rtx;
2455
2456 if (code == SET || code == MINUS)
2457 {
2458 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2459 if (can_invert && code != MINUS)
2460 temp1 = ~temp1;
2461 }
2462 else
2463 {
2464 if (remainder && subtargets)
2465 new_src = gen_reg_rtx (mode);
2466 else
2467 new_src = target;
2468 if (can_invert)
2469 temp1 = ~temp1;
2470 else if (can_negate)
2471 temp1 = -temp1;
2472 }
2473
2474 temp1 = trunc_int_for_mode (temp1, mode);
2475 temp1_rtx = GEN_INT (temp1);
2476
2477 if (code == SET)
2478 ;
2479 else if (code == MINUS)
2480 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2481 else
2482 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2483
2484 emit_constant_insn (cond,
2485 gen_rtx_SET (VOIDmode, new_src,
2486 temp1_rtx));
2487 source = new_src;
2488 }
2489
2490 if (code == SET)
2491 {
2492 can_invert = 0;
2493 code = PLUS;
2494 }
2495 else if (code == MINUS)
2496 code = PLUS;
2497
2498 insns++;
2499 if (TARGET_ARM)
2500 i -= 6;
2501 else
2502 i -= 7;
2503 }
2504 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
2505 shifts. */
2506 if (TARGET_ARM)
2507 i -= 2;
2508 else
2509 i--;
2510 }
2511 while (remainder);
2512 }
2513
2514 return insns;
2515 }
2516
2517 /* Canonicalize a comparison so that we are more likely to recognize it.
2518 This can be done for a few constant compares, where we can make the
2519 immediate value easier to load. */
2520
2521 enum rtx_code
2522 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2523 rtx * op1)
2524 {
2525 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2526 unsigned HOST_WIDE_INT maxval;
2527 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2528
2529 switch (code)
2530 {
2531 case EQ:
2532 case NE:
2533 return code;
2534
2535 case GT:
2536 case LE:
2537 if (i != maxval
2538 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2539 {
2540 *op1 = GEN_INT (i + 1);
2541 return code == GT ? GE : LT;
2542 }
2543 break;
2544
2545 case GE:
2546 case LT:
2547 if (i != ~maxval
2548 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2549 {
2550 *op1 = GEN_INT (i - 1);
2551 return code == GE ? GT : LE;
2552 }
2553 break;
2554
2555 case GTU:
2556 case LEU:
2557 if (i != ~((unsigned HOST_WIDE_INT) 0)
2558 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2559 {
2560 *op1 = GEN_INT (i + 1);
2561 return code == GTU ? GEU : LTU;
2562 }
2563 break;
2564
2565 case GEU:
2566 case LTU:
2567 if (i != 0
2568 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2569 {
2570 *op1 = GEN_INT (i - 1);
2571 return code == GEU ? GTU : LEU;
2572 }
2573 break;
2574
2575 default:
2576 gcc_unreachable ();
2577 }
2578
2579 return code;
2580 }
2581
2582
2583 /* Define how to find the value returned by a function. */
2584
2585 rtx
2586 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2587 {
2588 enum machine_mode mode;
2589 int unsignedp ATTRIBUTE_UNUSED;
2590 rtx r ATTRIBUTE_UNUSED;
2591
2592 mode = TYPE_MODE (type);
2593 /* Promote integer types. */
2594 if (INTEGRAL_TYPE_P (type))
2595 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2596
2597 /* Promotes small structs returned in a register to full-word size
2598 for big-endian AAPCS. */
2599 if (arm_return_in_msb (type))
2600 {
2601 HOST_WIDE_INT size = int_size_in_bytes (type);
2602 if (size % UNITS_PER_WORD != 0)
2603 {
2604 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2605 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2606 }
2607 }
2608
2609 return LIBCALL_VALUE(mode);
2610 }
2611
2612 /* Determine the amount of memory needed to store the possible return
2613 registers of an untyped call. */
2614 int
2615 arm_apply_result_size (void)
2616 {
2617 int size = 16;
2618
2619 if (TARGET_ARM)
2620 {
2621 if (TARGET_HARD_FLOAT_ABI)
2622 {
2623 if (TARGET_FPA)
2624 size += 12;
2625 if (TARGET_MAVERICK)
2626 size += 8;
2627 }
2628 if (TARGET_IWMMXT_ABI)
2629 size += 8;
2630 }
2631
2632 return size;
2633 }
2634
2635 /* Decide whether a type should be returned in memory (true)
2636 or in a register (false). This is called by the macro
2637 RETURN_IN_MEMORY. */
2638 int
2639 arm_return_in_memory (tree type)
2640 {
2641 HOST_WIDE_INT size;
2642
2643 if (!AGGREGATE_TYPE_P (type) &&
2644 (TREE_CODE (type) != VECTOR_TYPE) &&
2645 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2646 /* All simple types are returned in registers.
2647 For AAPCS, complex types are treated the same as aggregates. */
2648 return 0;
2649
2650 size = int_size_in_bytes (type);
2651
2652 if (arm_abi != ARM_ABI_APCS)
2653 {
2654 /* ATPCS and later return aggregate types in memory only if they are
2655 larger than a word (or are variable size). */
2656 return (size < 0 || size > UNITS_PER_WORD);
2657 }
2658
2659 /* To maximize backwards compatibility with previous versions of gcc,
2660 return vectors up to 4 words in registers. */
2661 if (TREE_CODE (type) == VECTOR_TYPE)
2662 return (size < 0 || size > (4 * UNITS_PER_WORD));
2663
2664 /* For the arm-wince targets we choose to be compatible with Microsoft's
2665 ARM and Thumb compilers, which always return aggregates in memory. */
2666 #ifndef ARM_WINCE
2667 /* All structures/unions bigger than one word are returned in memory.
2668 Also catch the case where int_size_in_bytes returns -1. In this case
2669 the aggregate is either huge or of variable size, and in either case
2670 we will want to return it via memory and not in a register. */
2671 if (size < 0 || size > UNITS_PER_WORD)
2672 return 1;
2673
2674 if (TREE_CODE (type) == RECORD_TYPE)
2675 {
2676 tree field;
2677
2678 /* For a struct the APCS says that we only return in a register
2679 if the type is 'integer like' and every addressable element
2680 has an offset of zero. For practical purposes this means
2681 that the structure can have at most one non bit-field element
2682 and that this element must be the first one in the structure. */
2683
2684 /* Find the first field, ignoring non FIELD_DECL things which will
2685 have been created by C++. */
2686 for (field = TYPE_FIELDS (type);
2687 field && TREE_CODE (field) != FIELD_DECL;
2688 field = TREE_CHAIN (field))
2689 continue;
2690
2691 if (field == NULL)
2692 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2693
2694 /* Check that the first field is valid for returning in a register. */
2695
2696 /* ... Floats are not allowed */
2697 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2698 return 1;
2699
2700 /* ... Aggregates that are not themselves valid for returning in
2701 a register are not allowed. */
2702 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2703 return 1;
2704
2705 /* Now check the remaining fields, if any. Only bitfields are allowed,
2706 since they are not addressable. */
2707 for (field = TREE_CHAIN (field);
2708 field;
2709 field = TREE_CHAIN (field))
2710 {
2711 if (TREE_CODE (field) != FIELD_DECL)
2712 continue;
2713
2714 if (!DECL_BIT_FIELD_TYPE (field))
2715 return 1;
2716 }
2717
2718 return 0;
2719 }
2720
2721 if (TREE_CODE (type) == UNION_TYPE)
2722 {
2723 tree field;
2724
2725 /* Unions can be returned in registers if every element is
2726 integral, or can be returned in an integer register. */
2727 for (field = TYPE_FIELDS (type);
2728 field;
2729 field = TREE_CHAIN (field))
2730 {
2731 if (TREE_CODE (field) != FIELD_DECL)
2732 continue;
2733
2734 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2735 return 1;
2736
2737 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2738 return 1;
2739 }
2740
2741 return 0;
2742 }
2743 #endif /* not ARM_WINCE */
2744
2745 /* Return all other types in memory. */
2746 return 1;
2747 }
2748
2749 /* Indicate whether or not words of a double are in big-endian order. */
2750
2751 int
2752 arm_float_words_big_endian (void)
2753 {
2754 if (TARGET_MAVERICK)
2755 return 0;
2756
2757 /* For FPA, float words are always big-endian. For VFP, floats words
2758 follow the memory system mode. */
2759
2760 if (TARGET_FPA)
2761 {
2762 return 1;
2763 }
2764
2765 if (TARGET_VFP)
2766 return (TARGET_BIG_END ? 1 : 0);
2767
2768 return 1;
2769 }
2770
2771 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2772 for a call to a function whose data type is FNTYPE.
2773 For a library call, FNTYPE is NULL. */
2774 void
2775 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2776 rtx libname ATTRIBUTE_UNUSED,
2777 tree fndecl ATTRIBUTE_UNUSED)
2778 {
2779 /* On the ARM, the offset starts at 0. */
2780 pcum->nregs = 0;
2781 pcum->iwmmxt_nregs = 0;
2782 pcum->can_split = true;
2783
2784 pcum->call_cookie = CALL_NORMAL;
2785
2786 if (TARGET_LONG_CALLS)
2787 pcum->call_cookie = CALL_LONG;
2788
2789 /* Check for long call/short call attributes. The attributes
2790 override any command line option. */
2791 if (fntype)
2792 {
2793 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2794 pcum->call_cookie = CALL_SHORT;
2795 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2796 pcum->call_cookie = CALL_LONG;
2797 }
2798
2799 /* Varargs vectors are treated the same as long long.
2800 named_count avoids having to change the way arm handles 'named' */
2801 pcum->named_count = 0;
2802 pcum->nargs = 0;
2803
2804 if (TARGET_REALLY_IWMMXT && fntype)
2805 {
2806 tree fn_arg;
2807
2808 for (fn_arg = TYPE_ARG_TYPES (fntype);
2809 fn_arg;
2810 fn_arg = TREE_CHAIN (fn_arg))
2811 pcum->named_count += 1;
2812
2813 if (! pcum->named_count)
2814 pcum->named_count = INT_MAX;
2815 }
2816 }
2817
2818
2819 /* Return true if mode/type need doubleword alignment. */
2820 bool
2821 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2822 {
2823 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2824 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2825 }
2826
2827
2828 /* Determine where to put an argument to a function.
2829 Value is zero to push the argument on the stack,
2830 or a hard register in which to store the argument.
2831
2832 MODE is the argument's machine mode.
2833 TYPE is the data type of the argument (as a tree).
2834 This is null for libcalls where that information may
2835 not be available.
2836 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2837 the preceding args and about the function being called.
2838 NAMED is nonzero if this argument is a named parameter
2839 (otherwise it is an extra parameter matching an ellipsis). */
2840
2841 rtx
2842 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2843 tree type, int named)
2844 {
2845 int nregs;
2846
2847 /* Varargs vectors are treated the same as long long.
2848 named_count avoids having to change the way arm handles 'named' */
2849 if (TARGET_IWMMXT_ABI
2850 && arm_vector_mode_supported_p (mode)
2851 && pcum->named_count > pcum->nargs + 1)
2852 {
2853 if (pcum->iwmmxt_nregs <= 9)
2854 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2855 else
2856 {
2857 pcum->can_split = false;
2858 return NULL_RTX;
2859 }
2860 }
2861
2862 /* Put doubleword aligned quantities in even register pairs. */
2863 if (pcum->nregs & 1
2864 && ARM_DOUBLEWORD_ALIGN
2865 && arm_needs_doubleword_align (mode, type))
2866 pcum->nregs++;
2867
2868 if (mode == VOIDmode)
2869 /* Compute operand 2 of the call insn. */
2870 return GEN_INT (pcum->call_cookie);
2871
2872 /* Only allow splitting an arg between regs and memory if all preceding
2873 args were allocated to regs. For args passed by reference we only count
2874 the reference pointer. */
2875 if (pcum->can_split)
2876 nregs = 1;
2877 else
2878 nregs = ARM_NUM_REGS2 (mode, type);
2879
2880 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2881 return NULL_RTX;
2882
2883 return gen_rtx_REG (mode, pcum->nregs);
2884 }
2885
2886 static int
2887 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2888 tree type, bool named ATTRIBUTE_UNUSED)
2889 {
2890 int nregs = pcum->nregs;
2891
2892 if (arm_vector_mode_supported_p (mode))
2893 return 0;
2894
2895 if (NUM_ARG_REGS > nregs
2896 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2897 && pcum->can_split)
2898 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2899
2900 return 0;
2901 }
2902
2903 /* Variable sized types are passed by reference. This is a GCC
2904 extension to the ARM ABI. */
2905
2906 static bool
2907 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2908 enum machine_mode mode ATTRIBUTE_UNUSED,
2909 tree type, bool named ATTRIBUTE_UNUSED)
2910 {
2911 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2912 }
2913 \f
2914 /* Encode the current state of the #pragma [no_]long_calls. */
2915 typedef enum
2916 {
2917 OFF, /* No #pragma [no_]long_calls is in effect. */
2918 LONG, /* #pragma long_calls is in effect. */
2919 SHORT /* #pragma no_long_calls is in effect. */
2920 } arm_pragma_enum;
2921
2922 static arm_pragma_enum arm_pragma_long_calls = OFF;
2923
2924 void
2925 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2926 {
2927 arm_pragma_long_calls = LONG;
2928 }
2929
2930 void
2931 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2932 {
2933 arm_pragma_long_calls = SHORT;
2934 }
2935
2936 void
2937 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2938 {
2939 arm_pragma_long_calls = OFF;
2940 }
2941 \f
2942 /* Table of machine attributes. */
2943 const struct attribute_spec arm_attribute_table[] =
2944 {
2945 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2946 /* Function calls made to this symbol must be done indirectly, because
2947 it may lie outside of the 26 bit addressing range of a normal function
2948 call. */
2949 { "long_call", 0, 0, false, true, true, NULL },
2950 /* Whereas these functions are always known to reside within the 26 bit
2951 addressing range. */
2952 { "short_call", 0, 0, false, true, true, NULL },
2953 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2954 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2955 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2956 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2957 #ifdef ARM_PE
2958 /* ARM/PE has three new attributes:
2959 interfacearm - ?
2960 dllexport - for exporting a function/variable that will live in a dll
2961 dllimport - for importing a function/variable from a dll
2962
2963 Microsoft allows multiple declspecs in one __declspec, separating
2964 them with spaces. We do NOT support this. Instead, use __declspec
2965 multiple times.
2966 */
2967 { "dllimport", 0, 0, true, false, false, NULL },
2968 { "dllexport", 0, 0, true, false, false, NULL },
2969 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2970 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2971 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2972 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2973 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2974 #endif
2975 { NULL, 0, 0, false, false, false, NULL }
2976 };
2977
2978 /* Handle an attribute requiring a FUNCTION_DECL;
2979 arguments as in struct attribute_spec.handler. */
2980 static tree
2981 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2982 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2983 {
2984 if (TREE_CODE (*node) != FUNCTION_DECL)
2985 {
2986 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2987 IDENTIFIER_POINTER (name));
2988 *no_add_attrs = true;
2989 }
2990
2991 return NULL_TREE;
2992 }
2993
2994 /* Handle an "interrupt" or "isr" attribute;
2995 arguments as in struct attribute_spec.handler. */
2996 static tree
2997 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2998 bool *no_add_attrs)
2999 {
3000 if (DECL_P (*node))
3001 {
3002 if (TREE_CODE (*node) != FUNCTION_DECL)
3003 {
3004 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3005 IDENTIFIER_POINTER (name));
3006 *no_add_attrs = true;
3007 }
3008 /* FIXME: the argument if any is checked for type attributes;
3009 should it be checked for decl ones? */
3010 }
3011 else
3012 {
3013 if (TREE_CODE (*node) == FUNCTION_TYPE
3014 || TREE_CODE (*node) == METHOD_TYPE)
3015 {
3016 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3017 {
3018 warning (OPT_Wattributes, "%qs attribute ignored",
3019 IDENTIFIER_POINTER (name));
3020 *no_add_attrs = true;
3021 }
3022 }
3023 else if (TREE_CODE (*node) == POINTER_TYPE
3024 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3025 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3026 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3027 {
3028 *node = build_variant_type_copy (*node);
3029 TREE_TYPE (*node) = build_type_attribute_variant
3030 (TREE_TYPE (*node),
3031 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
3032 *no_add_attrs = true;
3033 }
3034 else
3035 {
3036 /* Possibly pass this attribute on from the type to a decl. */
3037 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3038 | (int) ATTR_FLAG_FUNCTION_NEXT
3039 | (int) ATTR_FLAG_ARRAY_NEXT))
3040 {
3041 *no_add_attrs = true;
3042 return tree_cons (name, args, NULL_TREE);
3043 }
3044 else
3045 {
3046 warning (OPT_Wattributes, "%qs attribute ignored",
3047 IDENTIFIER_POINTER (name));
3048 }
3049 }
3050 }
3051
3052 return NULL_TREE;
3053 }
3054
3055 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3056 /* Handle the "notshared" attribute. This attribute is another way of
3057 requesting hidden visibility. ARM's compiler supports
3058 "__declspec(notshared)"; we support the same thing via an
3059 attribute. */
3060
3061 static tree
3062 arm_handle_notshared_attribute (tree *node,
3063 tree name ATTRIBUTE_UNUSED,
3064 tree args ATTRIBUTE_UNUSED,
3065 int flags ATTRIBUTE_UNUSED,
3066 bool *no_add_attrs)
3067 {
3068 tree decl = TYPE_NAME (*node);
3069
3070 if (decl)
3071 {
3072 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3073 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3074 *no_add_attrs = false;
3075 }
3076 return NULL_TREE;
3077 }
3078 #endif
3079
3080 /* Return 0 if the attributes for two types are incompatible, 1 if they
3081 are compatible, and 2 if they are nearly compatible (which causes a
3082 warning to be generated). */
3083 static int
3084 arm_comp_type_attributes (tree type1, tree type2)
3085 {
3086 int l1, l2, s1, s2;
3087
3088 /* Check for mismatch of non-default calling convention. */
3089 if (TREE_CODE (type1) != FUNCTION_TYPE)
3090 return 1;
3091
3092 /* Check for mismatched call attributes. */
3093 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3094 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3095 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3096 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
3097
3098 /* Only bother to check if an attribute is defined. */
3099 if (l1 | l2 | s1 | s2)
3100 {
3101 /* If one type has an attribute, the other must have the same attribute. */
3102 if ((l1 != l2) || (s1 != s2))
3103 return 0;
3104
3105 /* Disallow mixed attributes. */
3106 if ((l1 & s2) || (l2 & s1))
3107 return 0;
3108 }
3109
3110 /* Check for mismatched ISR attribute. */
3111 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3112 if (! l1)
3113 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3114 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3115 if (! l2)
3116 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3117 if (l1 != l2)
3118 return 0;
3119
3120 return 1;
3121 }
3122
3123 /* Encode long_call or short_call attribute by prefixing
3124 symbol name in DECL with a special character FLAG. */
3125 void
3126 arm_encode_call_attribute (tree decl, int flag)
3127 {
3128 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3129 int len = strlen (str);
3130 char * newstr;
3131
3132 /* Do not allow weak functions to be treated as short call. */
3133 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
3134 return;
3135
3136 newstr = alloca (len + 2);
3137 newstr[0] = flag;
3138 strcpy (newstr + 1, str);
3139
3140 newstr = (char *) ggc_alloc_string (newstr, len + 1);
3141 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3142 }
3143
3144 /* Assigns default attributes to newly defined type. This is used to
3145 set short_call/long_call attributes for function types of
3146 functions defined inside corresponding #pragma scopes. */
3147 static void
3148 arm_set_default_type_attributes (tree type)
3149 {
3150 /* Add __attribute__ ((long_call)) to all functions, when
3151 inside #pragma long_calls or __attribute__ ((short_call)),
3152 when inside #pragma no_long_calls. */
3153 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3154 {
3155 tree type_attr_list, attr_name;
3156 type_attr_list = TYPE_ATTRIBUTES (type);
3157
3158 if (arm_pragma_long_calls == LONG)
3159 attr_name = get_identifier ("long_call");
3160 else if (arm_pragma_long_calls == SHORT)
3161 attr_name = get_identifier ("short_call");
3162 else
3163 return;
3164
3165 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3166 TYPE_ATTRIBUTES (type) = type_attr_list;
3167 }
3168 }
3169 \f
3170 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3171 defined within the current compilation unit. If this cannot be
3172 determined, then 0 is returned. */
3173 static int
3174 current_file_function_operand (rtx sym_ref)
3175 {
3176 /* This is a bit of a fib. A function will have a short call flag
3177 applied to its name if it has the short call attribute, or it has
3178 already been defined within the current compilation unit. */
3179 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
3180 return 1;
3181
3182 /* The current function is always defined within the current compilation
3183 unit. If it s a weak definition however, then this may not be the real
3184 definition of the function, and so we have to say no. */
3185 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
3186 && !DECL_WEAK (current_function_decl))
3187 return 1;
3188
3189 /* We cannot make the determination - default to returning 0. */
3190 return 0;
3191 }
3192
3193 /* Return nonzero if a 32-bit "long_call" should be generated for
3194 this call. We generate a long_call if the function:
3195
3196 a. has an __attribute__((long call))
3197 or b. is within the scope of a #pragma long_calls
3198 or c. the -mlong-calls command line switch has been specified
3199 . and either:
3200 1. -ffunction-sections is in effect
3201 or 2. the current function has __attribute__ ((section))
3202 or 3. the target function has __attribute__ ((section))
3203
3204 However we do not generate a long call if the function:
3205
3206 d. has an __attribute__ ((short_call))
3207 or e. is inside the scope of a #pragma no_long_calls
3208 or f. is defined within the current compilation unit.
3209
3210 This function will be called by C fragments contained in the machine
3211 description file. SYM_REF and CALL_COOKIE correspond to the matched
3212 rtl operands. CALL_SYMBOL is used to distinguish between
3213 two different callers of the function. It is set to 1 in the
3214 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3215 and "call_value" patterns. This is because of the difference in the
3216 SYM_REFs passed by these patterns. */
3217 int
3218 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
3219 {
3220 if (!call_symbol)
3221 {
3222 if (GET_CODE (sym_ref) != MEM)
3223 return 0;
3224
3225 sym_ref = XEXP (sym_ref, 0);
3226 }
3227
3228 if (GET_CODE (sym_ref) != SYMBOL_REF)
3229 return 0;
3230
3231 if (call_cookie & CALL_SHORT)
3232 return 0;
3233
3234 if (TARGET_LONG_CALLS)
3235 {
3236 if (flag_function_sections
3237 || DECL_SECTION_NAME (current_function_decl))
3238 /* c.3 is handled by the definition of the
3239 ARM_DECLARE_FUNCTION_SIZE macro. */
3240 return 1;
3241 }
3242
3243 if (current_file_function_operand (sym_ref))
3244 return 0;
3245
3246 return (call_cookie & CALL_LONG)
3247 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
3248 || TARGET_LONG_CALLS;
3249 }
3250
3251 /* Return nonzero if it is ok to make a tail-call to DECL. */
3252 static bool
3253 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3254 {
3255 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
3256 unsigned long func_type;
3257
3258 if (cfun->machine->sibcall_blocked)
3259 return false;
3260
3261 /* Never tailcall something for which we have no decl, or if we
3262 are in Thumb mode. */
3263 if (decl == NULL || TARGET_THUMB)
3264 return false;
3265
3266 /* Get the calling method. */
3267 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3268 call_type = CALL_SHORT;
3269 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3270 call_type = CALL_LONG;
3271
3272 /* Cannot tail-call to long calls, since these are out of range of
3273 a branch instruction. However, if not compiling PIC, we know
3274 we can reach the symbol if it is in this compilation unit. */
3275 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
3276 return false;
3277
3278 /* If we are interworking and the function is not declared static
3279 then we can't tail-call it unless we know that it exists in this
3280 compilation unit (since it might be a Thumb routine). */
3281 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3282 return false;
3283
3284 func_type = arm_current_func_type ();
3285 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3286 if (IS_INTERRUPT (func_type))
3287 return false;
3288
3289 /* Never tailcall if function may be called with a misaligned SP. */
3290 if (IS_STACKALIGN (func_type))
3291 return false;
3292
3293 /* Everything else is ok. */
3294 return true;
3295 }
3296
3297 \f
3298 /* Addressing mode support functions. */
3299
3300 /* Return nonzero if X is a legitimate immediate operand when compiling
3301 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3302 int
3303 legitimate_pic_operand_p (rtx x)
3304 {
3305 if (GET_CODE (x) == SYMBOL_REF
3306 || (GET_CODE (x) == CONST
3307 && GET_CODE (XEXP (x, 0)) == PLUS
3308 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3309 return 0;
3310
3311 return 1;
3312 }
3313
3314 rtx
3315 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3316 {
3317 if (GET_CODE (orig) == SYMBOL_REF
3318 || GET_CODE (orig) == LABEL_REF)
3319 {
3320 #ifndef AOF_ASSEMBLER
3321 rtx pic_ref, address;
3322 #endif
3323 rtx insn;
3324 int subregs = 0;
3325
3326 /* If this function doesn't have a pic register, create one now.
3327 A lot of the logic here is made obscure by the fact that this
3328 routine gets called as part of the rtx cost estimation
3329 process. We don't want those calls to affect any assumptions
3330 about the real function; and further, we can't call
3331 entry_of_function() until we start the real expansion
3332 process. */
3333 if (!current_function_uses_pic_offset_table)
3334 {
3335 gcc_assert (!no_new_pseudos);
3336 if (arm_pic_register != INVALID_REGNUM)
3337 {
3338 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3339
3340 /* Play games to avoid marking the function as needing pic
3341 if we are being called as part of the cost-estimation
3342 process. */
3343 if (current_ir_type () != IR_GIMPLE)
3344 current_function_uses_pic_offset_table = 1;
3345 }
3346 else
3347 {
3348 rtx seq;
3349
3350 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3351
3352 /* Play games to avoid marking the function as needing pic
3353 if we are being called as part of the cost-estimation
3354 process. */
3355 if (current_ir_type () != IR_GIMPLE)
3356 {
3357 current_function_uses_pic_offset_table = 1;
3358 start_sequence ();
3359
3360 arm_load_pic_register (0UL);
3361
3362 seq = get_insns ();
3363 end_sequence ();
3364 emit_insn_after (seq, entry_of_function ());
3365 }
3366 }
3367 }
3368
3369 if (reg == 0)
3370 {
3371 gcc_assert (!no_new_pseudos);
3372 reg = gen_reg_rtx (Pmode);
3373
3374 subregs = 1;
3375 }
3376
3377 #ifdef AOF_ASSEMBLER
3378 /* The AOF assembler can generate relocations for these directly, and
3379 understands that the PIC register has to be added into the offset. */
3380 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3381 #else
3382 if (subregs)
3383 address = gen_reg_rtx (Pmode);
3384 else
3385 address = reg;
3386
3387 if (TARGET_ARM)
3388 emit_insn (gen_pic_load_addr_arm (address, orig));
3389 else if (TARGET_THUMB2)
3390 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3391 else /* TARGET_THUMB1 */
3392 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
3393
3394 if ((GET_CODE (orig) == LABEL_REF
3395 || (GET_CODE (orig) == SYMBOL_REF &&
3396 SYMBOL_REF_LOCAL_P (orig)))
3397 && NEED_GOT_RELOC)
3398 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3399 else
3400 {
3401 pic_ref = gen_const_mem (Pmode,
3402 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3403 address));
3404 }
3405
3406 insn = emit_move_insn (reg, pic_ref);
3407 #endif
3408 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3409 by loop. */
3410 set_unique_reg_note (insn, REG_EQUAL, orig);
3411
3412 return reg;
3413 }
3414 else if (GET_CODE (orig) == CONST)
3415 {
3416 rtx base, offset;
3417
3418 if (GET_CODE (XEXP (orig, 0)) == PLUS
3419 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3420 return orig;
3421
3422 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3423 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3424 return orig;
3425
3426 if (reg == 0)
3427 {
3428 gcc_assert (!no_new_pseudos);
3429 reg = gen_reg_rtx (Pmode);
3430 }
3431
3432 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3433
3434 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3435 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3436 base == reg ? 0 : reg);
3437
3438 if (GET_CODE (offset) == CONST_INT)
3439 {
3440 /* The base register doesn't really matter, we only want to
3441 test the index for the appropriate mode. */
3442 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3443 {
3444 gcc_assert (!no_new_pseudos);
3445 offset = force_reg (Pmode, offset);
3446 }
3447
3448 if (GET_CODE (offset) == CONST_INT)
3449 return plus_constant (base, INTVAL (offset));
3450 }
3451
3452 if (GET_MODE_SIZE (mode) > 4
3453 && (GET_MODE_CLASS (mode) == MODE_INT
3454 || TARGET_SOFT_FLOAT))
3455 {
3456 emit_insn (gen_addsi3 (reg, base, offset));
3457 return reg;
3458 }
3459
3460 return gen_rtx_PLUS (Pmode, base, offset);
3461 }
3462
3463 return orig;
3464 }
3465
3466
3467 /* Find a spare register to use during the prolog of a function. */
3468
3469 static int
3470 thumb_find_work_register (unsigned long pushed_regs_mask)
3471 {
3472 int reg;
3473
3474 /* Check the argument registers first as these are call-used. The
3475 register allocation order means that sometimes r3 might be used
3476 but earlier argument registers might not, so check them all. */
3477 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3478 if (!regs_ever_live[reg])
3479 return reg;
3480
3481 /* Before going on to check the call-saved registers we can try a couple
3482 more ways of deducing that r3 is available. The first is when we are
3483 pushing anonymous arguments onto the stack and we have less than 4
3484 registers worth of fixed arguments(*). In this case r3 will be part of
3485 the variable argument list and so we can be sure that it will be
3486 pushed right at the start of the function. Hence it will be available
3487 for the rest of the prologue.
3488 (*): ie current_function_pretend_args_size is greater than 0. */
3489 if (cfun->machine->uses_anonymous_args
3490 && current_function_pretend_args_size > 0)
3491 return LAST_ARG_REGNUM;
3492
3493 /* The other case is when we have fixed arguments but less than 4 registers
3494 worth. In this case r3 might be used in the body of the function, but
3495 it is not being used to convey an argument into the function. In theory
3496 we could just check current_function_args_size to see how many bytes are
3497 being passed in argument registers, but it seems that it is unreliable.
3498 Sometimes it will have the value 0 when in fact arguments are being
3499 passed. (See testcase execute/20021111-1.c for an example). So we also
3500 check the args_info.nregs field as well. The problem with this field is
3501 that it makes no allowances for arguments that are passed to the
3502 function but which are not used. Hence we could miss an opportunity
3503 when a function has an unused argument in r3. But it is better to be
3504 safe than to be sorry. */
3505 if (! cfun->machine->uses_anonymous_args
3506 && current_function_args_size >= 0
3507 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3508 && cfun->args_info.nregs < 4)
3509 return LAST_ARG_REGNUM;
3510
3511 /* Otherwise look for a call-saved register that is going to be pushed. */
3512 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3513 if (pushed_regs_mask & (1 << reg))
3514 return reg;
3515
3516 if (TARGET_THUMB2)
3517 {
3518 /* Thumb-2 can use high regs. */
3519 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3520 if (pushed_regs_mask & (1 << reg))
3521 return reg;
3522 }
3523 /* Something went wrong - thumb_compute_save_reg_mask()
3524 should have arranged for a suitable register to be pushed. */
3525 gcc_unreachable ();
3526 }
3527
3528 static GTY(()) int pic_labelno;
3529
3530 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3531 low register. */
3532
3533 void
3534 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3535 {
3536 #ifndef AOF_ASSEMBLER
3537 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx;
3538 rtx global_offset_table;
3539
3540 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3541 return;
3542
3543 gcc_assert (flag_pic);
3544
3545 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3546 in the code stream. */
3547
3548 labelno = GEN_INT (pic_labelno++);
3549 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3550 l1 = gen_rtx_CONST (VOIDmode, l1);
3551
3552 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3553 /* On the ARM the PC register contains 'dot + 8' at the time of the
3554 addition, on the Thumb it is 'dot + 4'. */
3555 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3556 if (GOT_PCREL)
3557 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3558 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3559 else
3560 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3561
3562 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3563
3564 if (TARGET_ARM)
3565 {
3566 emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx));
3567 emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg,
3568 cfun->machine->pic_reg, labelno));
3569 }
3570 else if (TARGET_THUMB2)
3571 {
3572 /* Thumb-2 only allows very limited access to the PC. Calculate the
3573 address in a temporary register. */
3574 if (arm_pic_register != INVALID_REGNUM)
3575 {
3576 pic_tmp = gen_rtx_REG (SImode,
3577 thumb_find_work_register (saved_regs));
3578 }
3579 else
3580 {
3581 gcc_assert (!no_new_pseudos);
3582 pic_tmp = gen_reg_rtx (Pmode);
3583 }
3584
3585 emit_insn (gen_pic_load_addr_thumb2 (cfun->machine->pic_reg, pic_rtx));
3586 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3587 emit_insn (gen_addsi3(cfun->machine->pic_reg, cfun->machine->pic_reg,
3588 pic_tmp));
3589 }
3590 else /* TARGET_THUMB1 */
3591 {
3592 if (arm_pic_register != INVALID_REGNUM
3593 && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM)
3594 {
3595 /* We will have pushed the pic register, so we should always be
3596 able to find a work register. */
3597 pic_tmp = gen_rtx_REG (SImode,
3598 thumb_find_work_register (saved_regs));
3599 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3600 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3601 }
3602 else
3603 emit_insn (gen_pic_load_addr_thumb1 (cfun->machine->pic_reg, pic_rtx));
3604 emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg,
3605 cfun->machine->pic_reg, labelno));
3606 }
3607
3608 /* Need to emit this whether or not we obey regdecls,
3609 since setjmp/longjmp can cause life info to screw up. */
3610 emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg));
3611 #endif /* AOF_ASSEMBLER */
3612 }
3613
3614
3615 /* Return nonzero if X is valid as an ARM state addressing register. */
3616 static int
3617 arm_address_register_rtx_p (rtx x, int strict_p)
3618 {
3619 int regno;
3620
3621 if (GET_CODE (x) != REG)
3622 return 0;
3623
3624 regno = REGNO (x);
3625
3626 if (strict_p)
3627 return ARM_REGNO_OK_FOR_BASE_P (regno);
3628
3629 return (regno <= LAST_ARM_REGNUM
3630 || regno >= FIRST_PSEUDO_REGISTER
3631 || regno == FRAME_POINTER_REGNUM
3632 || regno == ARG_POINTER_REGNUM);
3633 }
3634
3635 /* Return TRUE if this rtx is the difference of a symbol and a label,
3636 and will reduce to a PC-relative relocation in the object file.
3637 Expressions like this can be left alone when generating PIC, rather
3638 than forced through the GOT. */
3639 static int
3640 pcrel_constant_p (rtx x)
3641 {
3642 if (GET_CODE (x) == MINUS)
3643 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3644
3645 return FALSE;
3646 }
3647
3648 /* Return nonzero if X is a valid ARM state address operand. */
3649 int
3650 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3651 int strict_p)
3652 {
3653 bool use_ldrd;
3654 enum rtx_code code = GET_CODE (x);
3655
3656 if (arm_address_register_rtx_p (x, strict_p))
3657 return 1;
3658
3659 use_ldrd = (TARGET_LDRD
3660 && (mode == DImode
3661 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3662
3663 if (code == POST_INC || code == PRE_DEC
3664 || ((code == PRE_INC || code == POST_DEC)
3665 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3666 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3667
3668 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3669 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3670 && GET_CODE (XEXP (x, 1)) == PLUS
3671 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3672 {
3673 rtx addend = XEXP (XEXP (x, 1), 1);
3674
3675 /* Don't allow ldrd post increment by register because it's hard
3676 to fixup invalid register choices. */
3677 if (use_ldrd
3678 && GET_CODE (x) == POST_MODIFY
3679 && GET_CODE (addend) == REG)
3680 return 0;
3681
3682 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3683 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3684 }
3685
3686 /* After reload constants split into minipools will have addresses
3687 from a LABEL_REF. */
3688 else if (reload_completed
3689 && (code == LABEL_REF
3690 || (code == CONST
3691 && GET_CODE (XEXP (x, 0)) == PLUS
3692 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3693 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3694 return 1;
3695
3696 else if (mode == TImode)
3697 return 0;
3698
3699 else if (code == PLUS)
3700 {
3701 rtx xop0 = XEXP (x, 0);
3702 rtx xop1 = XEXP (x, 1);
3703
3704 return ((arm_address_register_rtx_p (xop0, strict_p)
3705 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3706 || (arm_address_register_rtx_p (xop1, strict_p)
3707 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3708 }
3709
3710 #if 0
3711 /* Reload currently can't handle MINUS, so disable this for now */
3712 else if (GET_CODE (x) == MINUS)
3713 {
3714 rtx xop0 = XEXP (x, 0);
3715 rtx xop1 = XEXP (x, 1);
3716
3717 return (arm_address_register_rtx_p (xop0, strict_p)
3718 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3719 }
3720 #endif
3721
3722 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3723 && code == SYMBOL_REF
3724 && CONSTANT_POOL_ADDRESS_P (x)
3725 && ! (flag_pic
3726 && symbol_mentioned_p (get_pool_constant (x))
3727 && ! pcrel_constant_p (get_pool_constant (x))))
3728 return 1;
3729
3730 return 0;
3731 }
3732
3733 /* Return nonzero if X is a valid Thumb-2 address operand. */
3734 int
3735 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3736 {
3737 bool use_ldrd;
3738 enum rtx_code code = GET_CODE (x);
3739
3740 if (arm_address_register_rtx_p (x, strict_p))
3741 return 1;
3742
3743 use_ldrd = (TARGET_LDRD
3744 && (mode == DImode
3745 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3746
3747 if (code == POST_INC || code == PRE_DEC
3748 || ((code == PRE_INC || code == POST_DEC)
3749 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3750 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3751
3752 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3753 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3754 && GET_CODE (XEXP (x, 1)) == PLUS
3755 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3756 {
3757 /* Thumb-2 only has autoincrement by constant. */
3758 rtx addend = XEXP (XEXP (x, 1), 1);
3759 HOST_WIDE_INT offset;
3760
3761 if (GET_CODE (addend) != CONST_INT)
3762 return 0;
3763
3764 offset = INTVAL(addend);
3765 if (GET_MODE_SIZE (mode) <= 4)
3766 return (offset > -256 && offset < 256);
3767
3768 return (use_ldrd && offset > -1024 && offset < 1024
3769 && (offset & 3) == 0);
3770 }
3771
3772 /* After reload constants split into minipools will have addresses
3773 from a LABEL_REF. */
3774 else if (reload_completed
3775 && (code == LABEL_REF
3776 || (code == CONST
3777 && GET_CODE (XEXP (x, 0)) == PLUS
3778 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3779 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3780 return 1;
3781
3782 else if (mode == TImode)
3783 return 0;
3784
3785 else if (code == PLUS)
3786 {
3787 rtx xop0 = XEXP (x, 0);
3788 rtx xop1 = XEXP (x, 1);
3789
3790 return ((arm_address_register_rtx_p (xop0, strict_p)
3791 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3792 || (arm_address_register_rtx_p (xop1, strict_p)
3793 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3794 }
3795
3796 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3797 && code == SYMBOL_REF
3798 && CONSTANT_POOL_ADDRESS_P (x)
3799 && ! (flag_pic
3800 && symbol_mentioned_p (get_pool_constant (x))
3801 && ! pcrel_constant_p (get_pool_constant (x))))
3802 return 1;
3803
3804 return 0;
3805 }
3806
3807 /* Return nonzero if INDEX is valid for an address index operand in
3808 ARM state. */
3809 static int
3810 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3811 int strict_p)
3812 {
3813 HOST_WIDE_INT range;
3814 enum rtx_code code = GET_CODE (index);
3815
3816 /* Standard coprocessor addressing modes. */
3817 if (TARGET_HARD_FLOAT
3818 && (TARGET_FPA || TARGET_MAVERICK)
3819 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3820 || (TARGET_MAVERICK && mode == DImode)))
3821 return (code == CONST_INT && INTVAL (index) < 1024
3822 && INTVAL (index) > -1024
3823 && (INTVAL (index) & 3) == 0);
3824
3825 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3826 return (code == CONST_INT
3827 && INTVAL (index) < 1024
3828 && INTVAL (index) > -1024
3829 && (INTVAL (index) & 3) == 0);
3830
3831 if (arm_address_register_rtx_p (index, strict_p)
3832 && (GET_MODE_SIZE (mode) <= 4))
3833 return 1;
3834
3835 if (mode == DImode || mode == DFmode)
3836 {
3837 if (code == CONST_INT)
3838 {
3839 HOST_WIDE_INT val = INTVAL (index);
3840
3841 if (TARGET_LDRD)
3842 return val > -256 && val < 256;
3843 else
3844 return val > -4096 && val < 4092;
3845 }
3846
3847 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3848 }
3849
3850 if (GET_MODE_SIZE (mode) <= 4
3851 && ! (arm_arch4
3852 && (mode == HImode
3853 || (mode == QImode && outer == SIGN_EXTEND))))
3854 {
3855 if (code == MULT)
3856 {
3857 rtx xiop0 = XEXP (index, 0);
3858 rtx xiop1 = XEXP (index, 1);
3859
3860 return ((arm_address_register_rtx_p (xiop0, strict_p)
3861 && power_of_two_operand (xiop1, SImode))
3862 || (arm_address_register_rtx_p (xiop1, strict_p)
3863 && power_of_two_operand (xiop0, SImode)));
3864 }
3865 else if (code == LSHIFTRT || code == ASHIFTRT
3866 || code == ASHIFT || code == ROTATERT)
3867 {
3868 rtx op = XEXP (index, 1);
3869
3870 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3871 && GET_CODE (op) == CONST_INT
3872 && INTVAL (op) > 0
3873 && INTVAL (op) <= 31);
3874 }
3875 }
3876
3877 /* For ARM v4 we may be doing a sign-extend operation during the
3878 load. */
3879 if (arm_arch4)
3880 {
3881 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3882 range = 256;
3883 else
3884 range = 4096;
3885 }
3886 else
3887 range = (mode == HImode) ? 4095 : 4096;
3888
3889 return (code == CONST_INT
3890 && INTVAL (index) < range
3891 && INTVAL (index) > -range);
3892 }
3893
3894 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3895 index operand. i.e. 1, 2, 4 or 8. */
3896 static bool
3897 thumb2_index_mul_operand (rtx op)
3898 {
3899 HOST_WIDE_INT val;
3900
3901 if (GET_CODE(op) != CONST_INT)
3902 return false;
3903
3904 val = INTVAL(op);
3905 return (val == 1 || val == 2 || val == 4 || val == 8);
3906 }
3907
3908 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
3909 static int
3910 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
3911 {
3912 enum rtx_code code = GET_CODE (index);
3913
3914 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
3915 /* Standard coprocessor addressing modes. */
3916 if (TARGET_HARD_FLOAT
3917 && (TARGET_FPA || TARGET_MAVERICK)
3918 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3919 || (TARGET_MAVERICK && mode == DImode)))
3920 return (code == CONST_INT && INTVAL (index) < 1024
3921 && INTVAL (index) > -1024
3922 && (INTVAL (index) & 3) == 0);
3923
3924 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3925 {
3926 /* For DImode assume values will usually live in core regs
3927 and only allow LDRD addressing modes. */
3928 if (!TARGET_LDRD || mode != DImode)
3929 return (code == CONST_INT
3930 && INTVAL (index) < 1024
3931 && INTVAL (index) > -1024
3932 && (INTVAL (index) & 3) == 0);
3933 }
3934
3935 if (arm_address_register_rtx_p (index, strict_p)
3936 && (GET_MODE_SIZE (mode) <= 4))
3937 return 1;
3938
3939 if (mode == DImode || mode == DFmode)
3940 {
3941 HOST_WIDE_INT val = INTVAL (index);
3942 /* ??? Can we assume ldrd for thumb2? */
3943 /* Thumb-2 ldrd only has reg+const addressing modes. */
3944 if (code != CONST_INT)
3945 return 0;
3946
3947 /* ldrd supports offsets of +-1020.
3948 However the ldr fallback does not. */
3949 return val > -256 && val < 256 && (val & 3) == 0;
3950 }
3951
3952 if (code == MULT)
3953 {
3954 rtx xiop0 = XEXP (index, 0);
3955 rtx xiop1 = XEXP (index, 1);
3956
3957 return ((arm_address_register_rtx_p (xiop0, strict_p)
3958 && thumb2_index_mul_operand (xiop1))
3959 || (arm_address_register_rtx_p (xiop1, strict_p)
3960 && thumb2_index_mul_operand (xiop0)));
3961 }
3962 else if (code == ASHIFT)
3963 {
3964 rtx op = XEXP (index, 1);
3965
3966 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3967 && GET_CODE (op) == CONST_INT
3968 && INTVAL (op) > 0
3969 && INTVAL (op) <= 3);
3970 }
3971
3972 return (code == CONST_INT
3973 && INTVAL (index) < 4096
3974 && INTVAL (index) > -256);
3975 }
3976
3977 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
3978 static int
3979 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3980 {
3981 int regno;
3982
3983 if (GET_CODE (x) != REG)
3984 return 0;
3985
3986 regno = REGNO (x);
3987
3988 if (strict_p)
3989 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3990
3991 return (regno <= LAST_LO_REGNUM
3992 || regno > LAST_VIRTUAL_REGISTER
3993 || regno == FRAME_POINTER_REGNUM
3994 || (GET_MODE_SIZE (mode) >= 4
3995 && (regno == STACK_POINTER_REGNUM
3996 || regno >= FIRST_PSEUDO_REGISTER
3997 || x == hard_frame_pointer_rtx
3998 || x == arg_pointer_rtx)));
3999 }
4000
4001 /* Return nonzero if x is a legitimate index register. This is the case
4002 for any base register that can access a QImode object. */
4003 inline static int
4004 thumb1_index_register_rtx_p (rtx x, int strict_p)
4005 {
4006 return thumb1_base_register_rtx_p (x, QImode, strict_p);
4007 }
4008
4009 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
4010
4011 The AP may be eliminated to either the SP or the FP, so we use the
4012 least common denominator, e.g. SImode, and offsets from 0 to 64.
4013
4014 ??? Verify whether the above is the right approach.
4015
4016 ??? Also, the FP may be eliminated to the SP, so perhaps that
4017 needs special handling also.
4018
4019 ??? Look at how the mips16 port solves this problem. It probably uses
4020 better ways to solve some of these problems.
4021
4022 Although it is not incorrect, we don't accept QImode and HImode
4023 addresses based on the frame pointer or arg pointer until the
4024 reload pass starts. This is so that eliminating such addresses
4025 into stack based ones won't produce impossible code. */
4026 int
4027 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
4028 {
4029 /* ??? Not clear if this is right. Experiment. */
4030 if (GET_MODE_SIZE (mode) < 4
4031 && !(reload_in_progress || reload_completed)
4032 && (reg_mentioned_p (frame_pointer_rtx, x)
4033 || reg_mentioned_p (arg_pointer_rtx, x)
4034 || reg_mentioned_p (virtual_incoming_args_rtx, x)
4035 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
4036 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
4037 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
4038 return 0;
4039
4040 /* Accept any base register. SP only in SImode or larger. */
4041 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
4042 return 1;
4043
4044 /* This is PC relative data before arm_reorg runs. */
4045 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
4046 && GET_CODE (x) == SYMBOL_REF
4047 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
4048 return 1;
4049
4050 /* This is PC relative data after arm_reorg runs. */
4051 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
4052 && (GET_CODE (x) == LABEL_REF
4053 || (GET_CODE (x) == CONST
4054 && GET_CODE (XEXP (x, 0)) == PLUS
4055 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4056 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4057 return 1;
4058
4059 /* Post-inc indexing only supported for SImode and larger. */
4060 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
4061 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
4062 return 1;
4063
4064 else if (GET_CODE (x) == PLUS)
4065 {
4066 /* REG+REG address can be any two index registers. */
4067 /* We disallow FRAME+REG addressing since we know that FRAME
4068 will be replaced with STACK, and SP relative addressing only
4069 permits SP+OFFSET. */
4070 if (GET_MODE_SIZE (mode) <= 4
4071 && XEXP (x, 0) != frame_pointer_rtx
4072 && XEXP (x, 1) != frame_pointer_rtx
4073 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4074 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
4075 return 1;
4076
4077 /* REG+const has 5-7 bit offset for non-SP registers. */
4078 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4079 || XEXP (x, 0) == arg_pointer_rtx)
4080 && GET_CODE (XEXP (x, 1)) == CONST_INT
4081 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4082 return 1;
4083
4084 /* REG+const has 10-bit offset for SP, but only SImode and
4085 larger is supported. */
4086 /* ??? Should probably check for DI/DFmode overflow here
4087 just like GO_IF_LEGITIMATE_OFFSET does. */
4088 else if (GET_CODE (XEXP (x, 0)) == REG
4089 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4090 && GET_MODE_SIZE (mode) >= 4
4091 && GET_CODE (XEXP (x, 1)) == CONST_INT
4092 && INTVAL (XEXP (x, 1)) >= 0
4093 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4094 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4095 return 1;
4096
4097 else if (GET_CODE (XEXP (x, 0)) == REG
4098 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4099 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4100 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4101 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
4102 && GET_MODE_SIZE (mode) >= 4
4103 && GET_CODE (XEXP (x, 1)) == CONST_INT
4104 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4105 return 1;
4106 }
4107
4108 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
4109 && GET_MODE_SIZE (mode) == 4
4110 && GET_CODE (x) == SYMBOL_REF
4111 && CONSTANT_POOL_ADDRESS_P (x)
4112 && ! (flag_pic
4113 && symbol_mentioned_p (get_pool_constant (x))
4114 && ! pcrel_constant_p (get_pool_constant (x))))
4115 return 1;
4116
4117 return 0;
4118 }
4119
4120 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4121 instruction of mode MODE. */
4122 int
4123 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
4124 {
4125 switch (GET_MODE_SIZE (mode))
4126 {
4127 case 1:
4128 return val >= 0 && val < 32;
4129
4130 case 2:
4131 return val >= 0 && val < 64 && (val & 1) == 0;
4132
4133 default:
4134 return (val >= 0
4135 && (val + GET_MODE_SIZE (mode)) <= 128
4136 && (val & 3) == 0);
4137 }
4138 }
4139
4140 /* Build the SYMBOL_REF for __tls_get_addr. */
4141
4142 static GTY(()) rtx tls_get_addr_libfunc;
4143
4144 static rtx
4145 get_tls_get_addr (void)
4146 {
4147 if (!tls_get_addr_libfunc)
4148 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4149 return tls_get_addr_libfunc;
4150 }
4151
4152 static rtx
4153 arm_load_tp (rtx target)
4154 {
4155 if (!target)
4156 target = gen_reg_rtx (SImode);
4157
4158 if (TARGET_HARD_TP)
4159 {
4160 /* Can return in any reg. */
4161 emit_insn (gen_load_tp_hard (target));
4162 }
4163 else
4164 {
4165 /* Always returned in r0. Immediately copy the result into a pseudo,
4166 otherwise other uses of r0 (e.g. setting up function arguments) may
4167 clobber the value. */
4168
4169 rtx tmp;
4170
4171 emit_insn (gen_load_tp_soft ());
4172
4173 tmp = gen_rtx_REG (SImode, 0);
4174 emit_move_insn (target, tmp);
4175 }
4176 return target;
4177 }
4178
4179 static rtx
4180 load_tls_operand (rtx x, rtx reg)
4181 {
4182 rtx tmp;
4183
4184 if (reg == NULL_RTX)
4185 reg = gen_reg_rtx (SImode);
4186
4187 tmp = gen_rtx_CONST (SImode, x);
4188
4189 emit_move_insn (reg, tmp);
4190
4191 return reg;
4192 }
4193
4194 static rtx
4195 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4196 {
4197 rtx insns, label, labelno, sum;
4198
4199 start_sequence ();
4200
4201 labelno = GEN_INT (pic_labelno++);
4202 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4203 label = gen_rtx_CONST (VOIDmode, label);
4204
4205 sum = gen_rtx_UNSPEC (Pmode,
4206 gen_rtvec (4, x, GEN_INT (reloc), label,
4207 GEN_INT (TARGET_ARM ? 8 : 4)),
4208 UNSPEC_TLS);
4209 reg = load_tls_operand (sum, reg);
4210
4211 if (TARGET_ARM)
4212 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
4213 else if (TARGET_THUMB2)
4214 {
4215 rtx tmp;
4216 /* Thumb-2 only allows very limited access to the PC. Calculate
4217 the address in a temporary register. */
4218 tmp = gen_reg_rtx (SImode);
4219 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4220 emit_insn (gen_addsi3(reg, reg, tmp));
4221 }
4222 else /* TARGET_THUMB1 */
4223 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4224
4225 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4226 Pmode, 1, reg, Pmode);
4227
4228 insns = get_insns ();
4229 end_sequence ();
4230
4231 return insns;
4232 }
4233
4234 rtx
4235 legitimize_tls_address (rtx x, rtx reg)
4236 {
4237 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
4238 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4239
4240 switch (model)
4241 {
4242 case TLS_MODEL_GLOBAL_DYNAMIC:
4243 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4244 dest = gen_reg_rtx (Pmode);
4245 emit_libcall_block (insns, dest, ret, x);
4246 return dest;
4247
4248 case TLS_MODEL_LOCAL_DYNAMIC:
4249 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4250
4251 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4252 share the LDM result with other LD model accesses. */
4253 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4254 UNSPEC_TLS);
4255 dest = gen_reg_rtx (Pmode);
4256 emit_libcall_block (insns, dest, ret, eqv);
4257
4258 /* Load the addend. */
4259 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4260 UNSPEC_TLS);
4261 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4262 return gen_rtx_PLUS (Pmode, dest, addend);
4263
4264 case TLS_MODEL_INITIAL_EXEC:
4265 labelno = GEN_INT (pic_labelno++);
4266 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4267 label = gen_rtx_CONST (VOIDmode, label);
4268 sum = gen_rtx_UNSPEC (Pmode,
4269 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
4270 GEN_INT (TARGET_ARM ? 8 : 4)),
4271 UNSPEC_TLS);
4272 reg = load_tls_operand (sum, reg);
4273
4274 if (TARGET_ARM)
4275 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
4276 else if (TARGET_THUMB2)
4277 {
4278 rtx tmp;
4279 /* Thumb-2 only allows very limited access to the PC. Calculate
4280 the address in a temporary register. */
4281 tmp = gen_reg_rtx (SImode);
4282 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4283 emit_insn (gen_addsi3(reg, reg, tmp));
4284 emit_move_insn (reg, gen_const_mem (SImode, reg));
4285 }
4286 else
4287 {
4288 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4289 emit_move_insn (reg, gen_const_mem (SImode, reg));
4290 }
4291
4292 tp = arm_load_tp (NULL_RTX);
4293
4294 return gen_rtx_PLUS (Pmode, tp, reg);
4295
4296 case TLS_MODEL_LOCAL_EXEC:
4297 tp = arm_load_tp (NULL_RTX);
4298
4299 reg = gen_rtx_UNSPEC (Pmode,
4300 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4301 UNSPEC_TLS);
4302 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4303
4304 return gen_rtx_PLUS (Pmode, tp, reg);
4305
4306 default:
4307 abort ();
4308 }
4309 }
4310
4311 /* Try machine-dependent ways of modifying an illegitimate address
4312 to be legitimate. If we find one, return the new, valid address. */
4313 rtx
4314 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4315 {
4316 if (arm_tls_symbol_p (x))
4317 return legitimize_tls_address (x, NULL_RTX);
4318
4319 if (GET_CODE (x) == PLUS)
4320 {
4321 rtx xop0 = XEXP (x, 0);
4322 rtx xop1 = XEXP (x, 1);
4323
4324 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4325 xop0 = force_reg (SImode, xop0);
4326
4327 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4328 xop1 = force_reg (SImode, xop1);
4329
4330 if (ARM_BASE_REGISTER_RTX_P (xop0)
4331 && GET_CODE (xop1) == CONST_INT)
4332 {
4333 HOST_WIDE_INT n, low_n;
4334 rtx base_reg, val;
4335 n = INTVAL (xop1);
4336
4337 /* VFP addressing modes actually allow greater offsets, but for
4338 now we just stick with the lowest common denominator. */
4339 if (mode == DImode
4340 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4341 {
4342 low_n = n & 0x0f;
4343 n &= ~0x0f;
4344 if (low_n > 4)
4345 {
4346 n += 16;
4347 low_n -= 16;
4348 }
4349 }
4350 else
4351 {
4352 low_n = ((mode) == TImode ? 0
4353 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4354 n -= low_n;
4355 }
4356
4357 base_reg = gen_reg_rtx (SImode);
4358 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4359 emit_move_insn (base_reg, val);
4360 x = plus_constant (base_reg, low_n);
4361 }
4362 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4363 x = gen_rtx_PLUS (SImode, xop0, xop1);
4364 }
4365
4366 /* XXX We don't allow MINUS any more -- see comment in
4367 arm_legitimate_address_p (). */
4368 else if (GET_CODE (x) == MINUS)
4369 {
4370 rtx xop0 = XEXP (x, 0);
4371 rtx xop1 = XEXP (x, 1);
4372
4373 if (CONSTANT_P (xop0))
4374 xop0 = force_reg (SImode, xop0);
4375
4376 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4377 xop1 = force_reg (SImode, xop1);
4378
4379 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4380 x = gen_rtx_MINUS (SImode, xop0, xop1);
4381 }
4382
4383 /* Make sure to take full advantage of the pre-indexed addressing mode
4384 with absolute addresses which often allows for the base register to
4385 be factorized for multiple adjacent memory references, and it might
4386 even allows for the mini pool to be avoided entirely. */
4387 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4388 {
4389 unsigned int bits;
4390 HOST_WIDE_INT mask, base, index;
4391 rtx base_reg;
4392
4393 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4394 use a 8-bit index. So let's use a 12-bit index for SImode only and
4395 hope that arm_gen_constant will enable ldrb to use more bits. */
4396 bits = (mode == SImode) ? 12 : 8;
4397 mask = (1 << bits) - 1;
4398 base = INTVAL (x) & ~mask;
4399 index = INTVAL (x) & mask;
4400 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4401 {
4402 /* It'll most probably be more efficient to generate the base
4403 with more bits set and use a negative index instead. */