?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
* config/arm/arm.c (arm_override_options): Update error message.
[official-gcc.git] / gcc / config / arm / arm.h
blob0ba70f9b9234af9c48a5fc759ac64c67104dbf78
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The archetecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
87 NAME,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##NAME,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Run-time compilation parameters selecting different hardware subsets. */
121 extern int target_flags;
122 /* The floating point mode. */
123 extern const char *target_fpu_name;
124 /* For backwards compatibility. */
125 extern const char *target_fpe_name;
126 /* Whether to use floating point hardware. */
127 extern const char *target_float_abi_name;
128 /* Which ABI to use. */
129 extern const char *target_abi_name;
130 /* Define the information needed to generate branch insns. This is
131 stored from the compare operation. */
132 extern GTY(()) rtx arm_compare_op0;
133 extern GTY(()) rtx arm_compare_op1;
134 /* The label of the current constant pool. */
135 extern rtx pool_vector_label;
136 /* Set to 1 when a return insn is output, this means that the epilogue
137 is not needed. */
138 extern int return_used_this_function;
139 /* Used to produce AOF syntax assembler. */
140 extern GTY(()) rtx aof_pic_label;
141 \f
142 /* Just in case configure has failed to define anything. */
143 #ifndef TARGET_CPU_DEFAULT
144 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
145 #endif
146
147
148 #undef CPP_SPEC
149 #define CPP_SPEC "%(subtarget_cpp_spec) \
150 %{msoft-float:%{mhard-float: \
151 %e-msoft-float and -mhard_float may not be used together}} \
152 %{mbig-endian:%{mlittle-endian: \
153 %e-mbig-endian and -mlittle-endian may not be used together}}"
154
155 #ifndef CC1_SPEC
156 #define CC1_SPEC ""
157 #endif
158
159 /* This macro defines names of additional specifications to put in the specs
160 that can be used in various specifications like CC1_SPEC. Its definition
161 is an initializer with a subgrouping for each command option.
162
163 Each subgrouping contains a string constant, that defines the
164 specification name, and a string constant that used by the GCC driver
165 program.
166
167 Do not define this macro if it does not need to do anything. */
168 #define EXTRA_SPECS \
169 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
170 SUBTARGET_EXTRA_SPECS
171
172 #ifndef SUBTARGET_EXTRA_SPECS
173 #define SUBTARGET_EXTRA_SPECS
174 #endif
175
176 #ifndef SUBTARGET_CPP_SPEC
177 #define SUBTARGET_CPP_SPEC ""
178 #endif
179 \f
180 /* Run-time Target Specification. */
181 #ifndef TARGET_VERSION
182 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
183 #endif
184
185 /* Nonzero if the function prologue (and epilogue) should obey
186 the ARM Procedure Call Standard. */
187 #define ARM_FLAG_APCS_FRAME (1 << 0)
188
189 /* Nonzero if the function prologue should output the function name to enable
190 the post mortem debugger to print a backtrace (very useful on RISCOS,
191 unused on RISCiX). Specifying this flag also enables
192 -fno-omit-frame-pointer.
193 XXX Must still be implemented in the prologue. */
194 #define ARM_FLAG_POKE (1 << 1)
195
196 /* Nonzero if floating point instructions are emulated by the FPE, in which
197 case instruction scheduling becomes very uninteresting. */
198 #define ARM_FLAG_FPE (1 << 2)
199
200 /* FLAG 0x0008 now spare (used to be apcs-32 selection). */
201
202 /* Nonzero if stack checking should be performed on entry to each function
203 which allocates temporary variables on the stack. */
204 #define ARM_FLAG_APCS_STACK (1 << 4)
205
206 /* Nonzero if floating point parameters should be passed to functions in
207 floating point registers. */
208 #define ARM_FLAG_APCS_FLOAT (1 << 5)
209
210 /* Nonzero if re-entrant, position independent code should be generated.
211 This is equivalent to -fpic. */
212 #define ARM_FLAG_APCS_REENT (1 << 6)
213
214 /* FLAG 0x0080 now spare (used to be alignment traps). */
215 /* Nonzero if all floating point instructions are missing (and there is no
216 emulator either). Generate function calls for all ops in this case. */
217 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
218
219 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
220 #define ARM_FLAG_BIG_END (1 << 9)
221
222 /* Nonzero if we should compile for Thumb interworking. */
223 #define ARM_FLAG_INTERWORK (1 << 10)
224
225 /* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
227 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
228
229 /* Nonzero if we need to protect the prolog from scheduling */
230 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
231
232 /* Nonzero if a call to abort should be generated if a noreturn
233 function tries to return. */
234 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
235
236 /* Nonzero if function prologues should not load the PIC register. */
237 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
238
239 /* Nonzero if all call instructions should be indirect. */
240 #define ARM_FLAG_LONG_CALLS (1 << 15)
241
242 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
243 #define ARM_FLAG_THUMB (1 << 16)
244
245 /* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247 #define THUMB_FLAG_BACKTRACE (1 << 17)
248
249 /* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
252
253 /* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
256
257 /* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
260
261 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
262 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
263
264 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
265 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
267 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
270 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
271 /* Use hardware floating point instructions. */
272 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
273 /* Use hardware floating point calling convention. */
274 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
275 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
276 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
277 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
278 #define TARGET_IWMMXT (arm_arch_iwmmxt)
279 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
280 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
281 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
282 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
283 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
284 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
285 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
286 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
287 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
288 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
289 #define TARGET_ARM (! TARGET_THUMB)
290 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
291 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
292 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
293 #define TARGET_BACKTRACE (leaf_function_p () \
294 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
295 : (target_flags & THUMB_FLAG_BACKTRACE))
296 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
297 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
298 #define TARGET_AAPCS_BASED \
299 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
300
301 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
302 then TARGET_AAPCS_BASED must be true -- but the converse does not
303 hold. TARGET_BPABI implies the use of the BPABI runtime library,
304 etc., in addition to just the AAPCS calling conventions. */
305 #ifndef TARGET_BPABI
306 #define TARGET_BPABI false
307 #endif
308
309 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
310 #ifndef SUBTARGET_SWITCHES
311 #define SUBTARGET_SWITCHES
312 #endif
313
314 #define TARGET_SWITCHES \
315 { \
316 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
317 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
318 N_("Generate APCS conformant stack frames") }, \
319 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
320 {"poke-function-name", ARM_FLAG_POKE, \
321 N_("Store function names in object code") }, \
322 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
323 {"fpe", ARM_FLAG_FPE, "" }, \
324 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
325 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
326 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
327 N_("Pass FP arguments in FP registers") }, \
328 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
329 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
330 N_("Generate re-entrant, PIC code") }, \
331 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
332 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
333 N_("Use library calls to perform FP operations") }, \
334 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
335 N_("Use hardware floating point instructions") }, \
336 {"big-endian", ARM_FLAG_BIG_END, \
337 N_("Assume target CPU is configured as big endian") }, \
338 {"little-endian", -ARM_FLAG_BIG_END, \
339 N_("Assume target CPU is configured as little endian") }, \
340 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
341 N_("Assume big endian bytes, little endian words") }, \
342 {"thumb-interwork", ARM_FLAG_INTERWORK, \
343 N_("Support calls between Thumb and ARM instruction sets") }, \
344 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
345 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
346 N_("Generate a call to abort if a noreturn function returns")}, \
347 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
348 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
349 N_("Do not move instructions into a function's prologue") }, \
350 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
351 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
352 N_("Do not load the PIC register in function prologues") }, \
353 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
354 {"long-calls", ARM_FLAG_LONG_CALLS, \
355 N_("Generate call insns as indirect calls, if necessary") }, \
356 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
357 {"thumb", ARM_FLAG_THUMB, \
358 N_("Compile for the Thumb not the ARM") }, \
359 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
360 {"arm", -ARM_FLAG_THUMB, "" }, \
361 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
362 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
363 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
364 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
365 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
366 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
367 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
368 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
369 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
370 "" }, \
371 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
372 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
373 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
374 "" }, \
375 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
376 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
377 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
378 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
379 SUBTARGET_SWITCHES \
380 {"", TARGET_DEFAULT, "" } \
381 }
382
383 #define TARGET_OPTIONS \
384 { \
385 {"cpu=", & arm_select[0].string, \
386 N_("Specify the name of the target CPU"), 0}, \
387 {"arch=", & arm_select[1].string, \
388 N_("Specify the name of the target architecture"), 0}, \
389 {"tune=", & arm_select[2].string, "", 0}, \
390 {"fpe=", & target_fpe_name, "", 0}, \
391 {"fp=", & target_fpe_name, "", 0}, \
392 {"fpu=", & target_fpu_name, \
393 N_("Specify the name of the target floating point hardware/format"), 0}, \
394 {"float-abi=", & target_float_abi_name, \
395 N_("Specify if floating point hardware should be used"), 0}, \
396 {"structure-size-boundary=", & structure_size_string, \
397 N_("Specify the minimum bit alignment of structures"), 0}, \
398 {"pic-register=", & arm_pic_register_string, \
399 N_("Specify the register to be used for PIC addressing"), 0}, \
400 {"abi=", &target_abi_name, N_("Specify an ABI"), 0} \
401 }
402
403 /* Support for a compile-time default CPU, et cetera. The rules are:
404 --with-arch is ignored if -march or -mcpu are specified.
405 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
406 by --with-arch.
407 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
408 by -march).
409 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
410 specified.
411 --with-fpu is ignored if -mfpu is specified.
412 --with-abi is ignored is -mabi is specified. */
413 #define OPTION_DEFAULT_SPECS \
414 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
415 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
416 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
417 {"float", \
418 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
419 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
420 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
421
422 struct arm_cpu_select
423 {
424 const char * string;
425 const char * name;
426 const struct processors * processors;
427 };
428
429 /* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
432 extern struct arm_cpu_select arm_select[];
433
434 /* Which floating point model to use. */
435 enum arm_fp_model
436 {
437 ARM_FP_MODEL_UNKNOWN,
438 /* FPA model (Hardware or software). */
439 ARM_FP_MODEL_FPA,
440 /* Cirrus Maverick floating point model. */
441 ARM_FP_MODEL_MAVERICK,
442 /* VFP floating point model. */
443 ARM_FP_MODEL_VFP
444 };
445
446 extern enum arm_fp_model arm_fp_model;
447
448 /* Which floating point hardware is available. Also update
449 fp_model_for_fpu in arm.c when adding entries to this list. */
450 enum fputype
451 {
452 /* No FP hardware. */
453 FPUTYPE_NONE,
454 /* Full FPA support. */
455 FPUTYPE_FPA,
456 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
457 FPUTYPE_FPA_EMU2,
458 /* Emulated FPA hardware, Issue 3 emulator. */
459 FPUTYPE_FPA_EMU3,
460 /* Cirrus Maverick floating point co-processor. */
461 FPUTYPE_MAVERICK,
462 /* VFP. */
463 FPUTYPE_VFP
464 };
465
466 /* Recast the floating point class to be the floating point attribute. */
467 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
468
469 /* What type of floating point to tune for */
470 extern enum fputype arm_fpu_tune;
471
472 /* What type of floating point instructions are available */
473 extern enum fputype arm_fpu_arch;
474
475 enum float_abi_type
476 {
477 ARM_FLOAT_ABI_SOFT,
478 ARM_FLOAT_ABI_SOFTFP,
479 ARM_FLOAT_ABI_HARD
480 };
481
482 extern enum float_abi_type arm_float_abi;
483
484 /* Which ABI to use. */
485 enum arm_abi_type
486 {
487 ARM_ABI_APCS,
488 ARM_ABI_ATPCS,
489 ARM_ABI_AAPCS,
490 ARM_ABI_IWMMXT
491 };
492
493 extern enum arm_abi_type arm_abi;
494
495 #ifndef ARM_DEFAULT_ABI
496 #define ARM_DEFAULT_ABI ARM_ABI_APCS
497 #endif
498
499 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
500 extern int arm_arch3m;
501
502 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
503 extern int arm_arch4;
504
505 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
506 extern int arm_arch4t;
507
508 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
509 extern int arm_arch5;
510
511 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
512 extern int arm_arch5e;
513
514 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
515 extern int arm_arch6;
516
517 /* Nonzero if this chip can benefit from load scheduling. */
518 extern int arm_ld_sched;
519
520 /* Nonzero if generating thumb code. */
521 extern int thumb_code;
522
523 /* Nonzero if this chip is a StrongARM. */
524 extern int arm_is_strong;
525
526 /* Nonzero if this chip is a Cirrus variant. */
527 extern int arm_arch_cirrus;
528
529 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
530 extern int arm_arch_iwmmxt;
531
532 /* Nonzero if this chip is an XScale. */
533 extern int arm_arch_xscale;
534
535 /* Nonzero if tuning for XScale */
536 extern int arm_tune_xscale;
537
538 /* Nonzero if this chip is an ARM6 or an ARM7. */
539 extern int arm_is_6_or_7;
540
541 /* Nonzero if we should define __THUMB_INTERWORK__ in the
542 preprocessor.
543 XXX This is a bit of a hack, it's intended to help work around
544 problems in GLD which doesn't understand that armv5t code is
545 interworking clean. */
546 extern int arm_cpp_interwork;
547
548 #ifndef TARGET_DEFAULT
549 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
550 #endif
551
552 /* The frame pointer register used in gcc has nothing to do with debugging;
553 that is controlled by the APCS-FRAME option. */
554 #define CAN_DEBUG_WITHOUT_FP
555
556 #define OVERRIDE_OPTIONS arm_override_options ()
557
558 /* Nonzero if PIC code requires explicit qualifiers to generate
559 PLT and GOT relocs rather than the assembler doing so implicitly.
560 Subtargets can override these if required. */
561 #ifndef NEED_GOT_RELOC
562 #define NEED_GOT_RELOC 0
563 #endif
564 #ifndef NEED_PLT_RELOC
565 #define NEED_PLT_RELOC 0
566 #endif
567
568 /* Nonzero if we need to refer to the GOT with a PC-relative
569 offset. In other words, generate
570
571 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
572
573 rather than
574
575 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
576
577 The default is true, which matches NetBSD. Subtargets can
578 override this if required. */
579 #ifndef GOT_PCREL
580 #define GOT_PCREL 1
581 #endif
582 \f
583 /* Target machine storage Layout. */
584
585
586 /* Define this macro if it is advisable to hold scalars in registers
587 in a wider mode than that declared by the program. In such cases,
588 the value is constrained to be within the bounds of the declared
589 type, but kept valid in the wider mode. The signedness of the
590 extension may differ from that of the type. */
591
592 /* It is far faster to zero extend chars than to sign extend them */
593
594 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
595 if (GET_MODE_CLASS (MODE) == MODE_INT \
596 && GET_MODE_SIZE (MODE) < 4) \
597 { \
598 if (MODE == QImode) \
599 UNSIGNEDP = 1; \
600 else if (MODE == HImode) \
601 UNSIGNEDP = 1; \
602 (MODE) = SImode; \
603 }
604
605 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
606 if (GET_MODE_CLASS (MODE) == MODE_INT \
607 && GET_MODE_SIZE (MODE) < 4) \
608 (MODE) = SImode; \
609
610 /* Define this if most significant bit is lowest numbered
611 in instructions that operate on numbered bit-fields. */
612 #define BITS_BIG_ENDIAN 0
613
614 /* Define this if most significant byte of a word is the lowest numbered.
615 Most ARM processors are run in little endian mode, so that is the default.
616 If you want to have it run-time selectable, change the definition in a
617 cover file to be TARGET_BIG_ENDIAN. */
618 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
619
620 /* Define this if most significant word of a multiword number is the lowest
621 numbered.
622 This is always false, even when in big-endian mode. */
623 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
624
625 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
626 on processor pre-defineds when compiling libgcc2.c. */
627 #if defined(__ARMEB__) && !defined(__ARMWEL__)
628 #define LIBGCC2_WORDS_BIG_ENDIAN 1
629 #else
630 #define LIBGCC2_WORDS_BIG_ENDIAN 0
631 #endif
632
633 /* Define this if most significant word of doubles is the lowest numbered.
634 The rules are different based on whether or not we use FPA-format,
635 VFP-format or some other floating point co-processor's format doubles. */
636 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
637
638 #define UNITS_PER_WORD 4
639
640 /* True if natural alignment is used for doubleword types. */
641 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
642
643 #define DOUBLEWORD_ALIGNMENT 64
644
645 #define PARM_BOUNDARY 32
646
647 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
648
649 #define PREFERRED_STACK_BOUNDARY \
650 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
651
652 #define FUNCTION_BOUNDARY 32
653
654 /* The lowest bit is used to indicate Thumb-mode functions, so the
655 vbit must go into the delta field of pointers to member
656 functions. */
657 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
658
659 #define EMPTY_FIELD_BOUNDARY 32
660
661 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
662
663 /* XXX Blah -- this macro is used directly by libobjc. Since it
664 supports no vector modes, cut out the complexity and fall back
665 on BIGGEST_FIELD_ALIGNMENT. */
666 #ifdef IN_TARGET_LIBS
667 #define BIGGEST_FIELD_ALIGNMENT 64
668 #endif
669
670 /* Make strings word-aligned so strcpy from constants will be faster. */
671 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
672
673 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
674 ((TREE_CODE (EXP) == STRING_CST \
675 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
676 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
677
678 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
679 value set in previous versions of this toolchain was 8, which produces more
680 compact structures. The command line option -mstructure_size_boundary=<n>
681 can be used to change this value. For compatibility with the ARM SDK
682 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
683 0020D) page 2-20 says "Structures are aligned on word boundaries".
684 The AAPCS specifies a value of 8. */
685 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
686 extern int arm_structure_size_boundary;
687
688 /* This is the value used to initialize arm_structure_size_boundary. If a
689 particular arm target wants to change the default value it should change
690 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
691 for an example of this. */
692 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
693 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
694 #endif
695
696 /* Used when parsing command line option -mstructure_size_boundary. */
697 extern const char * structure_size_string;
698
699 /* Nonzero if move instructions will actually fail to work
700 when given unaligned data. */
701 #define STRICT_ALIGNMENT 1
702
703 /* wchar_t is unsigned under the AAPCS. */
704 #ifndef WCHAR_TYPE
705 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
706
707 #define WCHAR_TYPE_SIZE BITS_PER_WORD
708 #endif
709
710 #ifndef SIZE_TYPE
711 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
712 #endif
713
714 /* AAPCS requires that structure alignment is affected by bitfields. */
715 #ifndef PCC_BITFIELD_TYPE_MATTERS
716 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
717 #endif
718
719 \f
720 /* Standard register usage. */
721
722 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
723 (S - saved over call).
724
725 r0 * argument word/integer result
726 r1-r3 argument word
727
728 r4-r8 S register variable
729 r9 S (rfp) register variable (real frame pointer)
730
731 r10 F S (sl) stack limit (used by -mapcs-stack-check)
732 r11 F S (fp) argument pointer
733 r12 (ip) temp workspace
734 r13 F S (sp) lower end of current stack frame
735 r14 (lr) link address/workspace
736 r15 F (pc) program counter
737
738 f0 floating point result
739 f1-f3 floating point scratch
740
741 f4-f7 S floating point variable
742
743 cc This is NOT a real register, but is used internally
744 to represent things that use or set the condition
745 codes.
746 sfp This isn't either. It is used during rtl generation
747 since the offset between the frame pointer and the
748 auto's isn't known until after register allocation.
749 afp Nor this, we only need this because of non-local
750 goto. Without it fp appears to be used and the
751 elimination code won't get rid of sfp. It tracks
752 fp exactly at all times.
753
754 *: See CONDITIONAL_REGISTER_USAGE */
755
756 /*
757 mvf0 Cirrus floating point result
758 mvf1-mvf3 Cirrus floating point scratch
759 mvf4-mvf15 S Cirrus floating point variable. */
760
761 /* s0-s15 VFP scratch (aka d0-d7).
762 s16-s31 S VFP variable (aka d8-d15).
763 vfpcc Not a real register. Represents the VFP condition
764 code flags. */
765
766 /* The stack backtrace structure is as follows:
767 fp points to here: | save code pointer | [fp]
768 | return link value | [fp, #-4]
769 | return sp value | [fp, #-8]
770 | return fp value | [fp, #-12]
771 [| saved r10 value |]
772 [| saved r9 value |]
773 [| saved r8 value |]
774 [| saved r7 value |]
775 [| saved r6 value |]
776 [| saved r5 value |]
777 [| saved r4 value |]
778 [| saved r3 value |]
779 [| saved r2 value |]
780 [| saved r1 value |]
781 [| saved r0 value |]
782 [| saved f7 value |] three words
783 [| saved f6 value |] three words
784 [| saved f5 value |] three words
785 [| saved f4 value |] three words
786 r0-r3 are not normally saved in a C function. */
787
788 /* 1 for registers that have pervasive standard uses
789 and are not available for the register allocator. */
790 #define FIXED_REGISTERS \
791 { \
792 0,0,0,0,0,0,0,0, \
793 0,0,0,0,0,1,0,1, \
794 0,0,0,0,0,0,0,0, \
795 1,1,1, \
796 1,1,1,1,1,1,1,1, \
797 1,1,1,1,1,1,1,1, \
798 1,1,1,1,1,1,1,1, \
799 1,1,1,1,1,1,1,1, \
800 1,1,1,1, \
801 1,1,1,1,1,1,1,1, \
802 1,1,1,1,1,1,1,1, \
803 1,1,1,1,1,1,1,1, \
804 1,1,1,1,1,1,1,1, \
805 1 \
806 }
807
808 /* 1 for registers not available across function calls.
809 These must include the FIXED_REGISTERS and also any
810 registers that can be used without being saved.
811 The latter must include the registers where values are returned
812 and the register where structure-value addresses are passed.
813 Aside from that, you can include as many other registers as you like.
814 The CC is not preserved over function calls on the ARM 6, so it is
815 easier to assume this for all. SFP is preserved, since FP is. */
816 #define CALL_USED_REGISTERS \
817 { \
818 1,1,1,1,0,0,0,0, \
819 0,0,0,0,1,1,1,1, \
820 1,1,1,1,0,0,0,0, \
821 1,1,1, \
822 1,1,1,1,1,1,1,1, \
823 1,1,1,1,1,1,1,1, \
824 1,1,1,1,1,1,1,1, \
825 1,1,1,1,1,1,1,1, \
826 1,1,1,1, \
827 1,1,1,1,1,1,1,1, \
828 1,1,1,1,1,1,1,1, \
829 1,1,1,1,1,1,1,1, \
830 1,1,1,1,1,1,1,1, \
831 1 \
832 }
833
834 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
835 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
836 #endif
837
838 #define CONDITIONAL_REGISTER_USAGE \
839 { \
840 int regno; \
841 \
842 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
843 { \
844 for (regno = FIRST_FPA_REGNUM; \
845 regno <= LAST_FPA_REGNUM; ++regno) \
846 fixed_regs[regno] = call_used_regs[regno] = 1; \
847 } \
848 \
849 if (TARGET_THUMB && optimize_size) \
850 { \
851 /* When optimizing for size, it's better not to use \
852 the HI regs, because of the overhead of stacking \
853 them. */ \
854 for (regno = FIRST_HI_REGNUM; \
855 regno <= LAST_HI_REGNUM; ++regno) \
856 fixed_regs[regno] = call_used_regs[regno] = 1; \
857 } \
858 \
859 /* The link register can be clobbered by any branch insn, \
860 but we have no way to track that at present, so mark \
861 it as unavailable. */ \
862 if (TARGET_THUMB) \
863 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
864 \
865 if (TARGET_ARM && TARGET_HARD_FLOAT) \
866 { \
867 if (TARGET_MAVERICK) \
868 { \
869 for (regno = FIRST_FPA_REGNUM; \
870 regno <= LAST_FPA_REGNUM; ++ regno) \
871 fixed_regs[regno] = call_used_regs[regno] = 1; \
872 for (regno = FIRST_CIRRUS_FP_REGNUM; \
873 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
874 { \
875 fixed_regs[regno] = 0; \
876 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
877 } \
878 } \
879 if (TARGET_VFP) \
880 { \
881 for (regno = FIRST_VFP_REGNUM; \
882 regno <= LAST_VFP_REGNUM; ++ regno) \
883 { \
884 fixed_regs[regno] = 0; \
885 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
886 } \
887 } \
888 } \
889 \
890 if (TARGET_REALLY_IWMMXT) \
891 { \
892 regno = FIRST_IWMMXT_GR_REGNUM; \
893 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
894 and wCG1 as call-preserved registers. The 2002/11/21 \
895 revision changed this so that all wCG registers are \
896 scratch registers. */ \
897 for (regno = FIRST_IWMMXT_GR_REGNUM; \
898 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
899 fixed_regs[regno] = call_used_regs[regno] = 0; \
900 /* The XScale ABI has wR0 - wR9 as scratch registers, \
901 the rest as call-preserved registers. */ \
902 for (regno = FIRST_IWMMXT_REGNUM; \
903 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
904 { \
905 fixed_regs[regno] = 0; \
906 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
907 } \
908 } \
909 \
910 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
911 { \
912 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
913 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
914 } \
915 else if (TARGET_APCS_STACK) \
916 { \
917 fixed_regs[10] = 1; \
918 call_used_regs[10] = 1; \
919 } \
920 if (TARGET_APCS_FRAME) \
921 { \
922 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
923 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
924 } \
925 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
926 }
927
928 /* These are a couple of extensions to the formats accepted
929 by asm_fprintf:
930 %@ prints out ASM_COMMENT_START
931 %r prints out REGISTER_PREFIX reg_names[arg] */
932 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
933 case '@': \
934 fputs (ASM_COMMENT_START, FILE); \
935 break; \
936 \
937 case 'r': \
938 fputs (REGISTER_PREFIX, FILE); \
939 fputs (reg_names [va_arg (ARGS, int)], FILE); \
940 break;
941
942 /* Round X up to the nearest word. */
943 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
944
945 /* Convert fron bytes to ints. */
946 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
947
948 /* The number of (integer) registers required to hold a quantity of type MODE.
949 Also used for VFP registers. */
950 #define ARM_NUM_REGS(MODE) \
951 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
952
953 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
954 #define ARM_NUM_REGS2(MODE, TYPE) \
955 ARM_NUM_INTS ((MODE) == BLKmode ? \
956 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
957
958 /* The number of (integer) argument register available. */
959 #define NUM_ARG_REGS 4
960
961 /* Return the register number of the N'th (integer) argument. */
962 #define ARG_REGISTER(N) (N - 1)
963
964 /* Specify the registers used for certain standard purposes.
965 The values of these macros are register numbers. */
966
967 /* The number of the last argument register. */
968 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
969
970 /* The numbers of the Thumb register ranges. */
971 #define FIRST_LO_REGNUM 0
972 #define LAST_LO_REGNUM 7
973 #define FIRST_HI_REGNUM 8
974 #define LAST_HI_REGNUM 11
975
976 /* We use sjlj exceptions for backwards compatibility. */
977 #define MUST_USE_SJLJ_EXCEPTIONS 1
978 /* We can generate DWARF2 Unwind info, even though we don't use it. */
979 #define DWARF2_UNWIND_INFO 1
980
981 /* Use r0 and r1 to pass exception handling information. */
982 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
983
984 /* The register that holds the return address in exception handlers. */
985 #define ARM_EH_STACKADJ_REGNUM 2
986 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
987
988 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
989 as an invisible last argument (possible since varargs don't exist in
990 Pascal), so the following is not true. */
991 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
992
993 /* Define this to be where the real frame pointer is if it is not possible to
994 work out the offset between the frame pointer and the automatic variables
995 until after register allocation has taken place. FRAME_POINTER_REGNUM
996 should point to a special register that we will make sure is eliminated.
997
998 For the Thumb we have another problem. The TPCS defines the frame pointer
999 as r11, and GCC believes that it is always possible to use the frame pointer
1000 as base register for addressing purposes. (See comments in
1001 find_reloads_address()). But - the Thumb does not allow high registers,
1002 including r11, to be used as base address registers. Hence our problem.
1003
1004 The solution used here, and in the old thumb port is to use r7 instead of
1005 r11 as the hard frame pointer and to have special code to generate
1006 backtrace structures on the stack (if required to do so via a command line
1007 option) using r11. This is the only 'user visible' use of r11 as a frame
1008 pointer. */
1009 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1010 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1011
1012 #define HARD_FRAME_POINTER_REGNUM \
1013 (TARGET_ARM \
1014 ? ARM_HARD_FRAME_POINTER_REGNUM \
1015 : THUMB_HARD_FRAME_POINTER_REGNUM)
1016
1017 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1018
1019 /* Register to use for pushing function arguments. */
1020 #define STACK_POINTER_REGNUM SP_REGNUM
1021
1022 /* ARM floating pointer registers. */
1023 #define FIRST_FPA_REGNUM 16
1024 #define LAST_FPA_REGNUM 23
1025
1026 #define FIRST_IWMMXT_GR_REGNUM 43
1027 #define LAST_IWMMXT_GR_REGNUM 46
1028 #define FIRST_IWMMXT_REGNUM 47
1029 #define LAST_IWMMXT_REGNUM 62
1030 #define IS_IWMMXT_REGNUM(REGNUM) \
1031 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1032 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1033 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1034
1035 /* Base register for access to local variables of the function. */
1036 #define FRAME_POINTER_REGNUM 25
1037
1038 /* Base register for access to arguments of the function. */
1039 #define ARG_POINTER_REGNUM 26
1040
1041 #define FIRST_CIRRUS_FP_REGNUM 27
1042 #define LAST_CIRRUS_FP_REGNUM 42
1043 #define IS_CIRRUS_REGNUM(REGNUM) \
1044 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1045
1046 #define FIRST_VFP_REGNUM 63
1047 #define LAST_VFP_REGNUM 94
1048 #define IS_VFP_REGNUM(REGNUM) \
1049 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1050
1051 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1052 /* + 16 Cirrus registers take us up to 43. */
1053 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1054 /* VFP adds 32 + 1 more. */
1055 #define FIRST_PSEUDO_REGISTER 96
1056
1057 /* Value should be nonzero if functions must have frame pointers.
1058 Zero means the frame pointer need not be set up (and parms may be accessed
1059 via the stack pointer) in functions that seem suitable.
1060 If we have to have a frame pointer we might as well make use of it.
1061 APCS says that the frame pointer does not need to be pushed in leaf
1062 functions, or simple tail call functions. */
1063 #define FRAME_POINTER_REQUIRED \
1064 (current_function_has_nonlocal_label \
1065 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1066
1067 /* Return number of consecutive hard regs needed starting at reg REGNO
1068 to hold something of mode MODE.
1069 This is ordinarily the length in words of a value of mode MODE
1070 but can be less for certain modes in special long registers.
1071
1072 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1073 mode. */
1074 #define HARD_REGNO_NREGS(REGNO, MODE) \
1075 ((TARGET_ARM \
1076 && REGNO >= FIRST_FPA_REGNUM \
1077 && REGNO != FRAME_POINTER_REGNUM \
1078 && REGNO != ARG_POINTER_REGNUM) \
1079 && !IS_VFP_REGNUM (REGNO) \
1080 ? 1 : ARM_NUM_REGS (MODE))
1081
1082 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1083 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1084 arm_hard_regno_mode_ok ((REGNO), (MODE))
1085
1086 /* Value is 1 if it is a good idea to tie two pseudo registers
1087 when one has mode MODE1 and one has mode MODE2.
1088 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1089 for any hard reg, then this must be 0 for correct output. */
1090 #define MODES_TIEABLE_P(MODE1, MODE2) \
1091 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1092
1093 #define VALID_IWMMXT_REG_MODE(MODE) \
1094 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1095
1096 /* The order in which register should be allocated. It is good to use ip
1097 since no saving is required (though calls clobber it) and it never contains
1098 function parameters. It is quite good to use lr since other calls may
1099 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1100 least likely to contain a function parameter; in addition results are
1101 returned in r0. */
1102
1103 #define REG_ALLOC_ORDER \
1104 { \
1105 3, 2, 1, 0, 12, 14, 4, 5, \
1106 6, 7, 8, 10, 9, 11, 13, 15, \
1107 16, 17, 18, 19, 20, 21, 22, 23, \
1108 27, 28, 29, 30, 31, 32, 33, 34, \
1109 35, 36, 37, 38, 39, 40, 41, 42, \
1110 43, 44, 45, 46, 47, 48, 49, 50, \
1111 51, 52, 53, 54, 55, 56, 57, 58, \
1112 59, 60, 61, 62, \
1113 24, 25, 26, \
1114 78, 77, 76, 75, 74, 73, 72, 71, \
1115 70, 69, 68, 67, 66, 65, 64, 63, \
1116 79, 80, 81, 82, 83, 84, 85, 86, \
1117 87, 88, 89, 90, 91, 92, 93, 94, \
1118 95 \
1119 }
1120
1121 /* Interrupt functions can only use registers that have already been
1122 saved by the prologue, even if they would normally be
1123 call-clobbered. */
1124 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1125 (! IS_INTERRUPT (cfun->machine->func_type) || \
1126 regs_ever_live[DST])
1127 \f
1128 /* Register and constant classes. */
1129
1130 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1131 Now that the Thumb is involved it has become more complicated. */
1132 enum reg_class
1133 {
1134 NO_REGS,
1135 FPA_REGS,
1136 CIRRUS_REGS,
1137 VFP_REGS,
1138 IWMMXT_GR_REGS,
1139 IWMMXT_REGS,
1140 LO_REGS,
1141 STACK_REG,
1142 BASE_REGS,
1143 HI_REGS,
1144 CC_REG,
1145 VFPCC_REG,
1146 GENERAL_REGS,
1147 ALL_REGS,
1148 LIM_REG_CLASSES
1149 };
1150
1151 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1152
1153 /* Give names of register classes as strings for dump file. */
1154 #define REG_CLASS_NAMES \
1155 { \
1156 "NO_REGS", \
1157 "FPA_REGS", \
1158 "CIRRUS_REGS", \
1159 "VFP_REGS", \
1160 "IWMMXT_GR_REGS", \
1161 "IWMMXT_REGS", \
1162 "LO_REGS", \
1163 "STACK_REG", \
1164 "BASE_REGS", \
1165 "HI_REGS", \
1166 "CC_REG", \
1167 "VFPCC_REG", \
1168 "GENERAL_REGS", \
1169 "ALL_REGS", \
1170 }
1171
1172 /* Define which registers fit in which classes.
1173 This is an initializer for a vector of HARD_REG_SET
1174 of length N_REG_CLASSES. */
1175 #define REG_CLASS_CONTENTS \
1176 { \
1177 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1178 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1179 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1180 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1181 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1182 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1183 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1184 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1185 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1186 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1187 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1188 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1189 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1190 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1191 }
1192
1193 /* The same information, inverted:
1194 Return the class number of the smallest class containing
1195 reg number REGNO. This could be a conditional expression
1196 or could index an array. */
1197 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1198
1199 /* FPA registers can't do subreg as all values are reformatted to internal
1200 precision. VFP registers may only be accessed in the mode they
1201 were set. */
1202 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1203 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1204 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1205 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1206 : 0)
1207
1208 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1209 using r0-r4 for function arguments, r7 for the stack frame and don't
1210 have enough left over to do doubleword arithmetic. */
1211 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1212 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1213 || (CLASS) == CC_REG)
1214
1215 /* The class value for index registers, and the one for base regs. */
1216 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1217 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1218
1219 /* For the Thumb the high registers cannot be used as base registers
1220 when addressing quantities in QI or HI mode; if we don't know the
1221 mode, then we must be conservative. After reload we must also be
1222 conservative, since we can't support SP+reg addressing, and we
1223 can't fix up any bad substitutions. */
1224 #define MODE_BASE_REG_CLASS(MODE) \
1225 (TARGET_ARM ? GENERAL_REGS : \
1226 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1227
1228 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1229 registers explicitly used in the rtl to be used as spill registers
1230 but prevents the compiler from extending the lifetime of these
1231 registers. */
1232 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1233
1234 /* Get reg_class from a letter such as appears in the machine description.
1235 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1236 ARM, but several more letters for the Thumb. */
1237 #define REG_CLASS_FROM_LETTER(C) \
1238 ( (C) == 'f' ? FPA_REGS \
1239 : (C) == 'v' ? CIRRUS_REGS \
1240 : (C) == 'w' ? VFP_REGS \
1241 : (C) == 'y' ? IWMMXT_REGS \
1242 : (C) == 'z' ? IWMMXT_GR_REGS \
1243 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1244 : TARGET_ARM ? NO_REGS \
1245 : (C) == 'h' ? HI_REGS \
1246 : (C) == 'b' ? BASE_REGS \
1247 : (C) == 'k' ? STACK_REG \
1248 : (C) == 'c' ? CC_REG \
1249 : NO_REGS)
1250
1251 /* The letters I, J, K, L and M in a register constraint string
1252 can be used to stand for particular ranges of immediate operands.
1253 This macro defines what the ranges are.
1254 C is the letter, and VALUE is a constant value.
1255 Return 1 if VALUE is in the range specified by C.
1256 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1257 J: valid indexing constants.
1258 K: ~value ok in rhs argument of data operand.
1259 L: -value ok in rhs argument of data operand.
1260 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1261 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1262 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1263 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1264 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1265 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1266 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1267 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1268 : 0)
1269
1270 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1271 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1272 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1273 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1274 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1275 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1276 && ((VAL) & 3) == 0) : \
1277 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1278 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1279 : 0)
1280
1281 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1282 (TARGET_ARM ? \
1283 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1284
1285 /* Constant letter 'G' for the FP immediate constants.
1286 'H' means the same constant negated. */
1287 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1288 ((C) == 'G' ? arm_const_double_rtx (X) : \
1289 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1290
1291 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1292 (TARGET_ARM ? \
1293 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1294
1295 /* For the ARM, `Q' means that this is a memory operand that is just
1296 an offset from a register.
1297 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1298 address. This means that the symbol is in the text segment and can be
1299 accessed without using a load.
1300 'U' Prefixes an extended memory constraint where:
1301 'Uv' is an address valid for VFP load/store insns.
1302 'Uy' is an address valid for iwmmxt load/store insns.
1303 'Uq' is an address valid for ldrsb. */
1304
1305 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1306 (((C) == 'Q') ? (GET_CODE (OP) == MEM \
1307 && GET_CODE (XEXP (OP, 0)) == REG) : \
1308 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1309 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1310 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1311 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1312 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1313 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1314 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1315 ((C) == 'U' && (STR)[1] == 'q') \
1316 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1317 : 0)
1318
1319 #define CONSTRAINT_LEN(C,STR) \
1320 ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1321
1322 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1323 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1324 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1325
1326 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1327 (TARGET_ARM \
1328 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1329 : EXTRA_CONSTRAINT_THUMB (X, C))
1330
1331 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1332
1333 /* Given an rtx X being reloaded into a reg required to be
1334 in class CLASS, return the class of reg to actually use.
1335 In general this is just CLASS, but for the Thumb we prefer
1336 a LO_REGS class or a subset. */
1337 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1338 (TARGET_ARM ? (CLASS) : \
1339 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1340
1341 /* Must leave BASE_REGS reloads alone */
1342 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1343 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1344 ? ((true_regnum (X) == -1 ? LO_REGS \
1345 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1346 : NO_REGS)) \
1347 : NO_REGS)
1348
1349 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1350 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1351 ? ((true_regnum (X) == -1 ? LO_REGS \
1352 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1353 : NO_REGS)) \
1354 : NO_REGS)
1355
1356 /* Return the register class of a scratch register needed to copy IN into
1357 or out of a register in CLASS in MODE. If it can be done directly,
1358 NO_REGS is returned. */
1359 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1360 /* Restrict which direct reloads are allowed for VFP regs. */ \
1361 ((TARGET_VFP && TARGET_HARD_FLOAT \
1362 && (CLASS) == VFP_REGS) \
1363 ? vfp_secondary_reload_class (MODE, X) \
1364 : TARGET_ARM \
1365 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1366 ? GENERAL_REGS : NO_REGS) \
1367 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1368
1369 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1370 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1371 /* Restrict which direct reloads are allowed for VFP regs. */ \
1372 ((TARGET_VFP && TARGET_HARD_FLOAT \
1373 && (CLASS) == VFP_REGS) \
1374 ? vfp_secondary_reload_class (MODE, X) : \
1375 /* Cannot load constants into Cirrus registers. */ \
1376 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1377 && (CLASS) == CIRRUS_REGS \
1378 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1379 ? GENERAL_REGS : \
1380 (TARGET_ARM ? \
1381 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1382 && CONSTANT_P (X)) \
1383 ? GENERAL_REGS : \
1384 (((MODE) == HImode && ! arm_arch4 \
1385 && (GET_CODE (X) == MEM \
1386 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1387 && true_regnum (X) == -1))) \
1388 ? GENERAL_REGS : NO_REGS) \
1389 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1390
1391 /* Try a machine-dependent way of reloading an illegitimate address
1392 operand. If we find one, push the reload and jump to WIN. This
1393 macro is used in only one place: `find_reloads_address' in reload.c.
1394
1395 For the ARM, we wish to handle large displacements off a base
1396 register by splitting the addend across a MOV and the mem insn.
1397 This can cut the number of reloads needed. */
1398 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1399 do \
1400 { \
1401 if (GET_CODE (X) == PLUS \
1402 && GET_CODE (XEXP (X, 0)) == REG \
1403 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1404 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1405 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1406 { \
1407 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1408 HOST_WIDE_INT low, high; \
1409 \
1410 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1411 low = ((val & 0xf) ^ 0x8) - 0x8; \
1412 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1413 /* Need to be careful, -256 is not a valid offset. */ \
1414 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1415 else if (MODE == SImode \
1416 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1417 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1418 /* Need to be careful, -4096 is not a valid offset. */ \
1419 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1420 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1421 /* Need to be careful, -256 is not a valid offset. */ \
1422 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1423 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1424 && TARGET_HARD_FLOAT && TARGET_FPA) \
1425 /* Need to be careful, -1024 is not a valid offset. */ \
1426 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1427 else \
1428 break; \
1429 \
1430 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1431 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1432 - (unsigned HOST_WIDE_INT) 0x80000000); \
1433 /* Check for overflow or zero */ \
1434 if (low == 0 || high == 0 || (high + low != val)) \
1435 break; \
1436 \
1437 /* Reload the high part into a base reg; leave the low part \
1438 in the mem. */ \
1439 X = gen_rtx_PLUS (GET_MODE (X), \
1440 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1441 GEN_INT (high)), \
1442 GEN_INT (low)); \
1443 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1444 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1445 VOIDmode, 0, 0, OPNUM, TYPE); \
1446 goto WIN; \
1447 } \
1448 } \
1449 while (0)
1450
1451 /* XXX If an HImode FP+large_offset address is converted to an HImode
1452 SP+large_offset address, then reload won't know how to fix it. It sees
1453 only that SP isn't valid for HImode, and so reloads the SP into an index
1454 register, but the resulting address is still invalid because the offset
1455 is too big. We fix it here instead by reloading the entire address. */
1456 /* We could probably achieve better results by defining PROMOTE_MODE to help
1457 cope with the variances between the Thumb's signed and unsigned byte and
1458 halfword load instructions. */
1459 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1460 { \
1461 if (GET_CODE (X) == PLUS \
1462 && GET_MODE_SIZE (MODE) < 4 \
1463 && GET_CODE (XEXP (X, 0)) == REG \
1464 && XEXP (X, 0) == stack_pointer_rtx \
1465 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1466 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1467 { \
1468 rtx orig_X = X; \
1469 X = copy_rtx (X); \
1470 push_reload (orig_X, NULL_RTX, &X, NULL, \
1471 MODE_BASE_REG_CLASS (MODE), \
1472 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1473 goto WIN; \
1474 } \
1475 }
1476
1477 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1478 if (TARGET_ARM) \
1479 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1480 else \
1481 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1482
1483 /* Return the maximum number of consecutive registers
1484 needed to represent mode MODE in a register of class CLASS.
1485 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1486 #define CLASS_MAX_NREGS(CLASS, MODE) \
1487 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1488
1489 /* If defined, gives a class of registers that cannot be used as the
1490 operand of a SUBREG that changes the mode of the object illegally. */
1491
1492 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1493 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1494 (TARGET_ARM ? \
1495 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1496 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1497 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1498 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1499 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1500 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1501 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1502 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1503 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1504 2) \
1505 : \
1506 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1507 \f
1508 /* Stack layout; function entry, exit and calling. */
1509
1510 /* Define this if pushing a word on the stack
1511 makes the stack pointer a smaller address. */
1512 #define STACK_GROWS_DOWNWARD 1
1513
1514 /* Define this if the nominal address of the stack frame
1515 is at the high-address end of the local variables;
1516 that is, each additional local variable allocated
1517 goes at a more negative offset in the frame. */
1518 #define FRAME_GROWS_DOWNWARD 1
1519
1520 /* Offset within stack frame to start allocating local variables at.
1521 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1522 first local allocated. Otherwise, it is the offset to the BEGINNING
1523 of the first local allocated. */
1524 #define STARTING_FRAME_OFFSET 0
1525
1526 /* If we generate an insn to push BYTES bytes,
1527 this says how many the stack pointer really advances by. */
1528 /* The push insns do not do this rounding implicitly.
1529 So don't define this. */
1530 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1531
1532 /* Define this if the maximum size of all the outgoing args is to be
1533 accumulated and pushed during the prologue. The amount can be
1534 found in the variable current_function_outgoing_args_size. */
1535 #define ACCUMULATE_OUTGOING_ARGS 1
1536
1537 /* Offset of first parameter from the argument pointer register value. */
1538 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1539
1540 /* Value is the number of byte of arguments automatically
1541 popped when returning from a subroutine call.
1542 FUNDECL is the declaration node of the function (as a tree),
1543 FUNTYPE is the data type of the function (as a tree),
1544 or for a library call it is an identifier node for the subroutine name.
1545 SIZE is the number of bytes of arguments passed on the stack.
1546
1547 On the ARM, the caller does not pop any of its arguments that were passed
1548 on the stack. */
1549 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1550
1551 /* Define how to find the value returned by a library function
1552 assuming the value has mode MODE. */
1553 #define LIBCALL_VALUE(MODE) \
1554 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1555 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1556 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1557 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1558 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1559 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1560 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1561 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1562 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1563
1564 /* Define how to find the value returned by a function.
1565 VALTYPE is the data type of the value (as a tree).
1566 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1567 otherwise, FUNC is 0. */
1568 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1569 arm_function_value (VALTYPE, FUNC);
1570
1571 /* 1 if N is a possible register number for a function value.
1572 On the ARM, only r0 and f0 can return results. */
1573 /* On a Cirrus chip, mvf0 can return results. */
1574 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1575 ((REGNO) == ARG_REGISTER (1) \
1576 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1577 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1578 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1579 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1580 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1581
1582 /* How large values are returned */
1583 /* A C expression which can inhibit the returning of certain function values
1584 in registers, based on the type of value. */
1585 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1586
1587 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1588 values must be in memory. On the ARM, they need only do so if larger
1589 than a word, or if they contain elements offset from zero in the struct. */
1590 #define DEFAULT_PCC_STRUCT_RETURN 0
1591
1592 /* Flags for the call/call_value rtl operations set up by function_arg. */
1593 #define CALL_NORMAL 0x00000000 /* No special processing. */
1594 #define CALL_LONG 0x00000001 /* Always call indirect. */
1595 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1596
1597 /* These bits describe the different types of function supported
1598 by the ARM backend. They are exclusive. ie a function cannot be both a
1599 normal function and an interworked function, for example. Knowing the
1600 type of a function is important for determining its prologue and
1601 epilogue sequences.
1602 Note value 7 is currently unassigned. Also note that the interrupt
1603 function types all have bit 2 set, so that they can be tested for easily.
1604 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1605 machine_function structure is initialized (to zero) func_type will
1606 default to unknown. This will force the first use of arm_current_func_type
1607 to call arm_compute_func_type. */
1608 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1609 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1610 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1611 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1612 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1613 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1614
1615 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1616
1617 /* In addition functions can have several type modifiers,
1618 outlined by these bit masks: */
1619 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1620 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1621 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1622 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1623
1624 /* Some macros to test these flags. */
1625 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1626 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1627 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1628 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1629 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1630
1631
1632 /* Structure used to hold the function stack frame layout. Offsets are
1633 relative to the stack pointer on function entry. Positive offsets are
1634 in the direction of stack growth.
1635 Only soft_frame is used in thumb mode. */
1636
1637 typedef struct arm_stack_offsets GTY(())
1638 {
1639 int saved_args; /* ARG_POINTER_REGNUM. */
1640 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1641 int saved_regs;
1642 int soft_frame; /* FRAME_POINTER_REGNUM. */
1643 int outgoing_args; /* STACK_POINTER_REGNUM. */
1644 }
1645 arm_stack_offsets;
1646
1647 /* A C structure for machine-specific, per-function data.
1648 This is added to the cfun structure. */
1649 typedef struct machine_function GTY(())
1650 {
1651 /* Additional stack adjustment in __builtin_eh_throw. */
1652 rtx eh_epilogue_sp_ofs;
1653 /* Records if LR has to be saved for far jumps. */
1654 int far_jump_used;
1655 /* Records if ARG_POINTER was ever live. */
1656 int arg_pointer_live;
1657 /* Records if the save of LR has been eliminated. */
1658 int lr_save_eliminated;
1659 /* The size of the stack frame. Only valid after reload. */
1660 arm_stack_offsets stack_offsets;
1661 /* Records the type of the current function. */
1662 unsigned long func_type;
1663 /* Record if the function has a variable argument list. */
1664 int uses_anonymous_args;
1665 /* Records if sibcalls are blocked because an argument
1666 register is needed to preserve stack alignment. */
1667 int sibcall_blocked;
1668 }
1669 machine_function;
1670
1671 /* A C type for declaring a variable that is used as the first argument of
1672 `FUNCTION_ARG' and other related values. For some target machines, the
1673 type `int' suffices and can hold the number of bytes of argument so far. */
1674 typedef struct
1675 {
1676 /* This is the number of registers of arguments scanned so far. */
1677 int nregs;
1678 /* This is the number of iWMMXt register arguments scanned so far. */
1679 int iwmmxt_nregs;
1680 int named_count;
1681 int nargs;
1682 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1683 int call_cookie;
1684 int can_split;
1685 } CUMULATIVE_ARGS;
1686
1687 /* Define where to put the arguments to a function.
1688 Value is zero to push the argument on the stack,
1689 or a hard register in which to store the argument.
1690
1691 MODE is the argument's machine mode.
1692 TYPE is the data type of the argument (as a tree).
1693 This is null for libcalls where that information may
1694 not be available.
1695 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1696 the preceding args and about the function being called.
1697 NAMED is nonzero if this argument is a named parameter
1698 (otherwise it is an extra parameter matching an ellipsis).
1699
1700 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1701 other arguments are passed on the stack. If (NAMED == 0) (which happens
1702 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1703 defined), say it is passed in the stack (function_prologue will
1704 indeed make it pass in the stack if necessary). */
1705 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1706 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1707
1708 /* For an arg passed partly in registers and partly in memory,
1709 this is the number of registers used.
1710 For args passed entirely in registers or entirely in memory, zero. */
1711 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1712 (arm_vector_mode_supported_p (MODE) ? 0 : \
1713 NUM_ARG_REGS > (CUM).nregs \
1714 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE)) \
1715 && (CUM).can_split) \
1716 ? NUM_ARG_REGS - (CUM).nregs : 0)
1717
1718 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1719 for a call to a function whose data type is FNTYPE.
1720 For a library call, FNTYPE is 0.
1721 On the ARM, the offset starts at 0. */
1722 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1723 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1724
1725 /* Update the data in CUM to advance over an argument
1726 of mode MODE and data type TYPE.
1727 (TYPE is null for libcalls where that information may not be available.) */
1728 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1729 (CUM).nargs += 1; \
1730 if (arm_vector_mode_supported_p (MODE) \
1731 && (CUM).named_count > (CUM).nargs) \
1732 (CUM).iwmmxt_nregs += 1; \
1733 else \
1734 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1735
1736 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1737 argument with the specified mode and type. If it is not defined,
1738 `PARM_BOUNDARY' is used for all arguments. */
1739 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1740 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1741 ? DOUBLEWORD_ALIGNMENT \
1742 : PARM_BOUNDARY )
1743
1744 /* 1 if N is a possible register number for function argument passing.
1745 On the ARM, r0-r3 are used to pass args. */
1746 #define FUNCTION_ARG_REGNO_P(REGNO) \
1747 (IN_RANGE ((REGNO), 0, 3) \
1748 || (TARGET_IWMMXT_ABI \
1749 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1750
1751 \f
1752 /* If your target environment doesn't prefix user functions with an
1753 underscore, you may wish to re-define this to prevent any conflicts.
1754 e.g. AOF may prefix mcount with an underscore. */
1755 #ifndef ARM_MCOUNT_NAME
1756 #define ARM_MCOUNT_NAME "*mcount"
1757 #endif
1758
1759 /* Call the function profiler with a given profile label. The Acorn
1760 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1761 On the ARM the full profile code will look like:
1762 .data
1763 LP1
1764 .word 0
1765 .text
1766 mov ip, lr
1767 bl mcount
1768 .word LP1
1769
1770 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1771 will output the .text section.
1772
1773 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1774 ``prof'' doesn't seem to mind about this!
1775
1776 Note - this version of the code is designed to work in both ARM and
1777 Thumb modes. */
1778 #ifndef ARM_FUNCTION_PROFILER
1779 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1780 { \
1781 char temp[20]; \
1782 rtx sym; \
1783 \
1784 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1785 IP_REGNUM, LR_REGNUM); \
1786 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1787 fputc ('\n', STREAM); \
1788 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1789 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1790 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1791 }
1792 #endif
1793
1794 #ifdef THUMB_FUNCTION_PROFILER
1795 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1796 if (TARGET_ARM) \
1797 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1798 else \
1799 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1800 #else
1801 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1802 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1803 #endif
1804
1805 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1806 the stack pointer does not matter. The value is tested only in
1807 functions that have frame pointers.
1808 No definition is equivalent to always zero.
1809
1810 On the ARM, the function epilogue recovers the stack pointer from the
1811 frame. */
1812 #define EXIT_IGNORE_STACK 1
1813
1814 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1815
1816 /* Determine if the epilogue should be output as RTL.
1817 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1818 #define USE_RETURN_INSN(ISCOND) \
1819 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1820
1821 /* Definitions for register eliminations.
1822
1823 This is an array of structures. Each structure initializes one pair
1824 of eliminable registers. The "from" register number is given first,
1825 followed by "to". Eliminations of the same "from" register are listed
1826 in order of preference.
1827
1828 We have two registers that can be eliminated on the ARM. First, the
1829 arg pointer register can often be eliminated in favor of the stack
1830 pointer register. Secondly, the pseudo frame pointer register can always
1831 be eliminated; it is replaced with either the stack or the real frame
1832 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1833 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1834
1835 #define ELIMINABLE_REGS \
1836 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1837 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1838 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1839 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1840 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1841 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1842 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1843
1844 /* Given FROM and TO register numbers, say whether this elimination is
1845 allowed. Frame pointer elimination is automatically handled.
1846
1847 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1848 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1849 pointer, we must eliminate FRAME_POINTER_REGNUM into
1850 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1851 ARG_POINTER_REGNUM. */
1852 #define CAN_ELIMINATE(FROM, TO) \
1853 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1854 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1855 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1856 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1857 1)
1858
1859 /* Define the offset between two registers, one to be eliminated, and the
1860 other its replacement, at the start of a routine. */
1861 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1862 if (TARGET_ARM) \
1863 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1864 else \
1865 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1866
1867 /* Special case handling of the location of arguments passed on the stack. */
1868 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1869
1870 /* Initialize data used by insn expanders. This is called from insn_emit,
1871 once for every function before code is generated. */
1872 #define INIT_EXPANDERS arm_init_expanders ()
1873
1874 /* Output assembler code for a block containing the constant parts
1875 of a trampoline, leaving space for the variable parts.
1876
1877 On the ARM, (if r8 is the static chain regnum, and remembering that
1878 referencing pc adds an offset of 8) the trampoline looks like:
1879 ldr r8, [pc, #0]
1880 ldr pc, [pc]
1881 .word static chain value
1882 .word function's address
1883 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1884 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1885 { \
1886 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1887 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1888 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1889 PC_REGNUM, PC_REGNUM); \
1890 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1891 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1892 }
1893
1894 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1895 Why - because it is easier. This code will always be branched to via
1896 a BX instruction and since the compiler magically generates the address
1897 of the function the linker has no opportunity to ensure that the
1898 bottom bit is set. Thus the processor will be in ARM mode when it
1899 reaches this code. So we duplicate the ARM trampoline code and add
1900 a switch into Thumb mode as well. */
1901 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1902 { \
1903 fprintf (FILE, "\t.code 32\n"); \
1904 fprintf (FILE, ".Ltrampoline_start:\n"); \
1905 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1906 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1907 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1908 IP_REGNUM, PC_REGNUM); \
1909 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1910 IP_REGNUM, IP_REGNUM); \
1911 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1912 fprintf (FILE, "\t.word\t0\n"); \
1913 fprintf (FILE, "\t.word\t0\n"); \
1914 fprintf (FILE, "\t.code 16\n"); \
1915 }
1916
1917 #define TRAMPOLINE_TEMPLATE(FILE) \
1918 if (TARGET_ARM) \
1919 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1920 else \
1921 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1922
1923 /* Length in units of the trampoline for entering a nested function. */
1924 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1925
1926 /* Alignment required for a trampoline in bits. */
1927 #define TRAMPOLINE_ALIGNMENT 32
1928
1929 /* Emit RTL insns to initialize the variable parts of a trampoline.
1930 FNADDR is an RTX for the address of the function's pure code.
1931 CXT is an RTX for the static chain value for the function. */
1932 #ifndef INITIALIZE_TRAMPOLINE
1933 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1934 { \
1935 emit_move_insn (gen_rtx_MEM (SImode, \
1936 plus_constant (TRAMP, \
1937 TARGET_ARM ? 8 : 16)), \
1938 CXT); \
1939 emit_move_insn (gen_rtx_MEM (SImode, \
1940 plus_constant (TRAMP, \
1941 TARGET_ARM ? 12 : 20)), \
1942 FNADDR); \
1943 }
1944 #endif
1945
1946 \f
1947 /* Addressing modes, and classification of registers for them. */
1948 #define HAVE_POST_INCREMENT 1
1949 #define HAVE_PRE_INCREMENT TARGET_ARM
1950 #define HAVE_POST_DECREMENT TARGET_ARM
1951 #define HAVE_PRE_DECREMENT TARGET_ARM
1952 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1953 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1954 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1955 #define HAVE_POST_MODIFY_REG TARGET_ARM
1956
1957 /* Macros to check register numbers against specific register classes. */
1958
1959 /* These assume that REGNO is a hard or pseudo reg number.
1960 They give nonzero only if REGNO is a hard reg of the suitable class
1961 or a pseudo reg currently allocated to a suitable hard reg.
1962 Since they use reg_renumber, they are safe only once reg_renumber
1963 has been allocated, which happens in local-alloc.c. */
1964 #define TEST_REGNO(R, TEST, VALUE) \
1965 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1966
1967 /* On the ARM, don't allow the pc to be used. */
1968 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1969 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1970 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1971 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1972
1973 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1974 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1975 || (GET_MODE_SIZE (MODE) >= 4 \
1976 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1977
1978 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1979 (TARGET_THUMB \
1980 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1981 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1982
1983 /* For ARM code, we don't care about the mode, but for Thumb, the index
1984 must be suitable for use in a QImode load. */
1985 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1986 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1987
1988 /* Maximum number of registers that can appear in a valid memory address.
1989 Shifts in addresses can't be by a register. */
1990 #define MAX_REGS_PER_ADDRESS 2
1991
1992 /* Recognize any constant value that is a valid address. */
1993 /* XXX We can address any constant, eventually... */
1994
1995 #ifdef AOF_ASSEMBLER
1996
1997 #define CONSTANT_ADDRESS_P(X) \
1998 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1999
2000 #else
2001
2002 #define CONSTANT_ADDRESS_P(X) \
2003 (GET_CODE (X) == SYMBOL_REF \
2004 && (CONSTANT_POOL_ADDRESS_P (X) \
2005 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2006
2007 #endif /* AOF_ASSEMBLER */
2008
2009 /* Nonzero if the constant value X is a legitimate general operand.
2010 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2011
2012 On the ARM, allow any integer (invalid ones are removed later by insn
2013 patterns), nice doubles and symbol_refs which refer to the function's
2014 constant pool XXX.
2015
2016 When generating pic allow anything. */
2017 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2018
2019 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2020 ( GET_CODE (X) == CONST_INT \
2021 || GET_CODE (X) == CONST_DOUBLE \
2022 || CONSTANT_ADDRESS_P (X) \
2023 || flag_pic)
2024
2025 #define LEGITIMATE_CONSTANT_P(X) \
2026 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2027
2028 /* Special characters prefixed to function names
2029 in order to encode attribute like information.
2030 Note, '@' and '*' have already been taken. */
2031 #define SHORT_CALL_FLAG_CHAR '^'
2032 #define LONG_CALL_FLAG_CHAR '#'
2033
2034 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2035 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2036
2037 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2038 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2039
2040 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2041 #define SUBTARGET_NAME_ENCODING_LENGTHS
2042 #endif
2043
2044 /* This is a C fragment for the inside of a switch statement.
2045 Each case label should return the number of characters to
2046 be stripped from the start of a function's name, if that
2047 name starts with the indicated character. */
2048 #define ARM_NAME_ENCODING_LENGTHS \
2049 case SHORT_CALL_FLAG_CHAR: return 1; \
2050 case LONG_CALL_FLAG_CHAR: return 1; \
2051 case '*': return 1; \
2052 SUBTARGET_NAME_ENCODING_LENGTHS
2053
2054 /* This is how to output a reference to a user-level label named NAME.
2055 `assemble_name' uses this. */
2056 #undef ASM_OUTPUT_LABELREF
2057 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2058 arm_asm_output_labelref (FILE, NAME)
2059
2060 /* Set the short-call flag for any function compiled in the current
2061 compilation unit. We skip this for functions with the section
2062 attirubte when long-calls are in effect as this tells the compiler
2063 that the section might be placed a long way from the caller.
2064 See arm_is_longcall_p() for more information. */
2065 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2066 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
2067 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2068
2069 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2070 and check its validity for a certain class.
2071 We have two alternate definitions for each of them.
2072 The usual definition accepts all pseudo regs; the other rejects
2073 them unless they have been allocated suitable hard regs.
2074 The symbol REG_OK_STRICT causes the latter definition to be used. */
2075 #ifndef REG_OK_STRICT
2076
2077 #define ARM_REG_OK_FOR_BASE_P(X) \
2078 (REGNO (X) <= LAST_ARM_REGNUM \
2079 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2080 || REGNO (X) == FRAME_POINTER_REGNUM \
2081 || REGNO (X) == ARG_POINTER_REGNUM)
2082
2083 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2084 (REGNO (X) <= LAST_LO_REGNUM \
2085 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2086 || (GET_MODE_SIZE (MODE) >= 4 \
2087 && (REGNO (X) == STACK_POINTER_REGNUM \
2088 || (X) == hard_frame_pointer_rtx \
2089 || (X) == arg_pointer_rtx)))
2090
2091 #define REG_STRICT_P 0
2092
2093 #else /* REG_OK_STRICT */
2094
2095 #define ARM_REG_OK_FOR_BASE_P(X) \
2096 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2097
2098 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2099 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2100
2101 #define REG_STRICT_P 1
2102
2103 #endif /* REG_OK_STRICT */
2104
2105 /* Now define some helpers in terms of the above. */
2106
2107 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2108 (TARGET_THUMB \
2109 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2110 : ARM_REG_OK_FOR_BASE_P (X))
2111
2112 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2113
2114 /* For Thumb, a valid index register is anything that can be used in
2115 a byte load instruction. */
2116 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2117
2118 /* Nonzero if X is a hard reg that can be used as an index
2119 or if it is a pseudo reg. On the Thumb, the stack pointer
2120 is not suitable. */
2121 #define REG_OK_FOR_INDEX_P(X) \
2122 (TARGET_THUMB \
2123 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2124 : ARM_REG_OK_FOR_INDEX_P (X))
2125
2126 \f
2127 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2128 that is a valid memory address for an instruction.
2129 The MODE argument is the machine mode for the MEM expression
2130 that wants to use this address. */
2131
2132 #define ARM_BASE_REGISTER_RTX_P(X) \
2133 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2134
2135 #define ARM_INDEX_REGISTER_RTX_P(X) \
2136 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2137
2138 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2139 { \
2140 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2141 goto WIN; \
2142 }
2143
2144 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2145 { \
2146 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2147 goto WIN; \
2148 }
2149
2150 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2151 if (TARGET_ARM) \
2152 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2153 else /* if (TARGET_THUMB) */ \
2154 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2155
2156 \f
2157 /* Try machine-dependent ways of modifying an illegitimate address
2158 to be legitimate. If we find one, return the new, valid address. */
2159 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2160 do { \
2161 X = arm_legitimize_address (X, OLDX, MODE); \
2162 } while (0)
2163
2164 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2165 do { \
2166 X = thumb_legitimize_address (X, OLDX, MODE); \
2167 } while (0)
2168
2169 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2170 do { \
2171 if (TARGET_ARM) \
2172 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2173 else \
2174 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2175 \
2176 if (memory_address_p (MODE, X)) \
2177 goto WIN; \
2178 } while (0)
2179
2180 /* Go to LABEL if ADDR (a legitimate address expression)
2181 has an effect that depends on the machine mode it is used for. */
2182 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2183 { \
2184 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2185 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2186 goto LABEL; \
2187 }
2188
2189 /* Nothing helpful to do for the Thumb */
2190 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2191 if (TARGET_ARM) \
2192 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2193 \f
2194
2195 /* Specify the machine mode that this machine uses
2196 for the index in the tablejump instruction. */
2197 #define CASE_VECTOR_MODE Pmode
2198
2199 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2200 unsigned is probably best, but may break some code. */
2201 #ifndef DEFAULT_SIGNED_CHAR
2202 #define DEFAULT_SIGNED_CHAR 0
2203 #endif
2204
2205 /* Max number of bytes we can move from memory to memory
2206 in one reasonably fast instruction. */
2207 #define MOVE_MAX 4
2208
2209 #undef MOVE_RATIO
2210 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2211
2212 /* Define if operations between registers always perform the operation
2213 on the full register even if a narrower mode is specified. */
2214 #define WORD_REGISTER_OPERATIONS
2215
2216 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2217 will either zero-extend or sign-extend. The value of this macro should
2218 be the code that says which one of the two operations is implicitly
2219 done, UNKNOWN if none. */
2220 #define LOAD_EXTEND_OP(MODE) \
2221 (TARGET_THUMB ? ZERO_EXTEND : \
2222 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2223 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2224
2225 /* Nonzero if access to memory by bytes is slow and undesirable. */
2226 #define SLOW_BYTE_ACCESS 0
2227
2228 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2229
2230 /* Immediate shift counts are truncated by the output routines (or was it
2231 the assembler?). Shift counts in a register are truncated by ARM. Note
2232 that the native compiler puts too large (> 32) immediate shift counts
2233 into a register and shifts by the register, letting the ARM decide what
2234 to do instead of doing that itself. */
2235 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2236 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2237 On the arm, Y in a register is used modulo 256 for the shift. Only for
2238 rotates is modulo 32 used. */
2239 /* #define SHIFT_COUNT_TRUNCATED 1 */
2240
2241 /* All integers have the same format so truncation is easy. */
2242 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2243
2244 /* Calling from registers is a massive pain. */
2245 #define NO_FUNCTION_CSE 1
2246
2247 /* The machine modes of pointers and functions */
2248 #define Pmode SImode
2249 #define FUNCTION_MODE Pmode
2250
2251 #define ARM_FRAME_RTX(X) \
2252 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2253 || (X) == arg_pointer_rtx)
2254
2255 /* Moves to and from memory are quite expensive */
2256 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2257 (TARGET_ARM ? 10 : \
2258 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2259 * (CLASS == LO_REGS ? 1 : 2)))
2260
2261 /* Try to generate sequences that don't involve branches, we can then use
2262 conditional instructions */
2263 #define BRANCH_COST \
2264 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2265 \f
2266 /* Position Independent Code. */
2267 /* We decide which register to use based on the compilation options and
2268 the assembler in use; this is more general than the APCS restriction of
2269 using sb (r9) all the time. */
2270 extern int arm_pic_register;
2271
2272 /* Used when parsing command line option -mpic-register=. */
2273 extern const char * arm_pic_register_string;
2274
2275 /* The register number of the register used to address a table of static
2276 data addresses in memory. */
2277 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2278
2279 /* We can't directly access anything that contains a symbol,
2280 nor can we indirect via the constant pool. */
2281 #define LEGITIMATE_PIC_OPERAND_P(X) \
2282 (!(symbol_mentioned_p (X) \
2283 || label_mentioned_p (X) \
2284 || (GET_CODE (X) == SYMBOL_REF \
2285 && CONSTANT_POOL_ADDRESS_P (X) \
2286 && (symbol_mentioned_p (get_pool_constant (X)) \
2287 || label_mentioned_p (get_pool_constant (X))))))
2288
2289 /* We need to know when we are making a constant pool; this determines
2290 whether data needs to be in the GOT or can be referenced via a GOT
2291 offset. */
2292 extern int making_const_table;
2293 \f
2294 /* Handle pragmas for compatibility with Intel's compilers. */
2295 #define REGISTER_TARGET_PRAGMAS() do { \
2296 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2297 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2298 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2299 } while (0)
2300
2301 /* Condition code information. */
2302 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2303 return the mode to be used for the comparison. */
2304
2305 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2306
2307 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2308
2309 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2310 do \
2311 { \
2312 if (GET_CODE (OP1) == CONST_INT \
2313 && ! (const_ok_for_arm (INTVAL (OP1)) \
2314 || (const_ok_for_arm (- INTVAL (OP1))))) \
2315 { \
2316 rtx const_op = OP1; \
2317 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2318 OP1 = const_op; \
2319 } \
2320 } \
2321 while (0)
2322
2323 /* The arm5 clz instruction returns 32. */
2324 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2325 \f
2326 #undef ASM_APP_OFF
2327 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2328
2329 /* Output a push or a pop instruction (only used when profiling). */
2330 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2331 do \
2332 { \
2333 if (TARGET_ARM) \
2334 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2335 STACK_POINTER_REGNUM, REGNO); \
2336 else \
2337 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2338 } while (0)
2339
2340
2341 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2342 do \
2343 { \
2344 if (TARGET_ARM) \
2345 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2346 STACK_POINTER_REGNUM, REGNO); \
2347 else \
2348 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2349 } while (0)
2350
2351 /* This is how to output a label which precedes a jumptable. Since
2352 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2353 #undef ASM_OUTPUT_CASE_LABEL
2354 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2355 do \
2356 { \
2357 if (TARGET_THUMB) \
2358 ASM_OUTPUT_ALIGN (FILE, 2); \
2359 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2360 } \
2361 while (0)
2362
2363 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2364 do \
2365 { \
2366 if (TARGET_THUMB) \
2367 { \
2368 if (is_called_in_ARM_mode (DECL) \
2369 || current_function_is_thunk) \
2370 fprintf (STREAM, "\t.code 32\n") ; \
2371 else \
2372 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2373 } \
2374 if (TARGET_POKE_FUNCTION_NAME) \
2375 arm_poke_function_name (STREAM, (char *) NAME); \
2376 } \
2377 while (0)
2378
2379 /* For aliases of functions we use .thumb_set instead. */
2380 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2381 do \
2382 { \
2383 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2384 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2385 \
2386 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2387 { \
2388 fprintf (FILE, "\t.thumb_set "); \
2389 assemble_name (FILE, LABEL1); \
2390 fprintf (FILE, ","); \
2391 assemble_name (FILE, LABEL2); \
2392 fprintf (FILE, "\n"); \
2393 } \
2394 else \
2395 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2396 } \
2397 while (0)
2398
2399 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2400 /* To support -falign-* switches we need to use .p2align so
2401 that alignment directives in code sections will be padded
2402 with no-op instructions, rather than zeroes. */
2403 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2404 if ((LOG) != 0) \
2405 { \
2406 if ((MAX_SKIP) == 0) \
2407 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2408 else \
2409 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2410 (int) (LOG), (int) (MAX_SKIP)); \
2411 }
2412 #endif
2413 \f
2414 /* Only perform branch elimination (by making instructions conditional) if
2415 we're optimizing. Otherwise it's of no use anyway. */
2416 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2417 if (TARGET_ARM && optimize) \
2418 arm_final_prescan_insn (INSN); \
2419 else if (TARGET_THUMB) \
2420 thumb_final_prescan_insn (INSN)
2421
2422 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2423 (CODE == '@' || CODE == '|' \
2424 || (TARGET_ARM && (CODE == '?')) \
2425 || (TARGET_THUMB && (CODE == '_')))
2426
2427 /* Output an operand of an instruction. */
2428 #define PRINT_OPERAND(STREAM, X, CODE) \
2429 arm_print_operand (STREAM, X, CODE)
2430
2431 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2432 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2433 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2434 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2435 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2436 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2437 : 0))))
2438
2439 /* Output the address of an operand. */
2440 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2441 { \
2442 int is_minus = GET_CODE (X) == MINUS; \
2443 \
2444 if (GET_CODE (X) == REG) \
2445 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2446 else if (GET_CODE (X) == PLUS || is_minus) \
2447 { \
2448 rtx base = XEXP (X, 0); \
2449 rtx index = XEXP (X, 1); \
2450 HOST_WIDE_INT offset = 0; \
2451 if (GET_CODE (base) != REG) \
2452 { \
2453 /* Ensure that BASE is a register. */ \
2454 /* (one of them must be). */ \
2455 rtx temp = base; \
2456 base = index; \
2457 index = temp; \
2458 } \
2459 switch (GET_CODE (index)) \
2460 { \
2461 case CONST_INT: \
2462 offset = INTVAL (index); \
2463 if (is_minus) \
2464 offset = -offset; \
2465 asm_fprintf (STREAM, "[%r, #%wd]", \
2466 REGNO (base), offset); \
2467 break; \
2468 \
2469 case REG: \
2470 asm_fprintf (STREAM, "[%r, %s%r]", \
2471 REGNO (base), is_minus ? "-" : "", \
2472 REGNO (index)); \
2473 break; \
2474 \
2475 case MULT: \
2476 case ASHIFTRT: \
2477 case LSHIFTRT: \
2478 case ASHIFT: \
2479 case ROTATERT: \
2480 { \
2481 asm_fprintf (STREAM, "[%r, %s%r", \
2482 REGNO (base), is_minus ? "-" : "", \
2483 REGNO (XEXP (index, 0))); \
2484 arm_print_operand (STREAM, index, 'S'); \
2485 fputs ("]", STREAM); \
2486 break; \
2487 } \
2488 \
2489 default: \
2490 abort(); \
2491 } \
2492 } \
2493 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2494 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2495 { \
2496 extern enum machine_mode output_memory_reference_mode; \
2497 \
2498 if (GET_CODE (XEXP (X, 0)) != REG) \
2499 abort (); \
2500 \
2501 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2502 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2503 REGNO (XEXP (X, 0)), \
2504 GET_CODE (X) == PRE_DEC ? "-" : "", \
2505 GET_MODE_SIZE (output_memory_reference_mode)); \
2506 else \
2507 asm_fprintf (STREAM, "[%r], #%s%d", \
2508 REGNO (XEXP (X, 0)), \
2509 GET_CODE (X) == POST_DEC ? "-" : "", \
2510 GET_MODE_SIZE (output_memory_reference_mode)); \
2511 } \
2512 else if (GET_CODE (X) == PRE_MODIFY) \
2513 { \
2514 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2515 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2516 asm_fprintf (STREAM, "#%wd]!", \
2517 INTVAL (XEXP (XEXP (X, 1), 1))); \
2518 else \
2519 asm_fprintf (STREAM, "%r]!", \
2520 REGNO (XEXP (XEXP (X, 1), 1))); \
2521 } \
2522 else if (GET_CODE (X) == POST_MODIFY) \
2523 { \
2524 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2525 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2526 asm_fprintf (STREAM, "#%wd", \
2527 INTVAL (XEXP (XEXP (X, 1), 1))); \
2528 else \
2529 asm_fprintf (STREAM, "%r", \
2530 REGNO (XEXP (XEXP (X, 1), 1))); \
2531 } \
2532 else output_addr_const (STREAM, X); \
2533 }
2534
2535 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2536 { \
2537 if (GET_CODE (X) == REG) \
2538 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2539 else if (GET_CODE (X) == POST_INC) \
2540 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2541 else if (GET_CODE (X) == PLUS) \
2542 { \
2543 if (GET_CODE (XEXP (X, 0)) != REG) \
2544 abort (); \
2545 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2546 asm_fprintf (STREAM, "[%r, #%wd]", \
2547 REGNO (XEXP (X, 0)), \
2548 INTVAL (XEXP (X, 1))); \
2549 else \
2550 asm_fprintf (STREAM, "[%r, %r]", \
2551 REGNO (XEXP (X, 0)), \
2552 REGNO (XEXP (X, 1))); \
2553 } \
2554 else \
2555 output_addr_const (STREAM, X); \
2556 }
2557
2558 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2559 if (TARGET_ARM) \
2560 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2561 else \
2562 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2563
2564 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2565 if (GET_CODE (X) != CONST_VECTOR \
2566 || ! arm_emit_vector_const (FILE, X)) \
2567 goto FAIL;
2568
2569 /* A C expression whose value is RTL representing the value of the return
2570 address for the frame COUNT steps up from the current frame. */
2571
2572 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2573 arm_return_addr (COUNT, FRAME)
2574
2575 /* Mask of the bits in the PC that contain the real return address
2576 when running in 26-bit mode. */
2577 #define RETURN_ADDR_MASK26 (0x03fffffc)
2578
2579 /* Pick up the return address upon entry to a procedure. Used for
2580 dwarf2 unwind information. This also enables the table driven
2581 mechanism. */
2582 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2583 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2584
2585 /* Used to mask out junk bits from the return address, such as
2586 processor state, interrupt status, condition codes and the like. */
2587 #define MASK_RETURN_ADDR \
2588 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2589 in 26 bit mode, the condition codes must be masked out of the \
2590 return address. This does not apply to ARM6 and later processors \
2591 when running in 32 bit mode. */ \
2592 ((arm_arch4 || TARGET_THUMB) \
2593 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2594 : arm_gen_return_addr_mask ())
2595
2596 \f
2597 /* Define the codes that are matched by predicates in arm.c */
2598 #define PREDICATE_CODES \
2599 {"s_register_operand", {SUBREG, REG}}, \
2600 {"arm_general_register_operand", {SUBREG, REG}}, \
2601 {"arm_hard_register_operand", {REG}}, \
2602 {"f_register_operand", {SUBREG, REG}}, \
2603 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2604 {"arm_addimm_operand", {CONST_INT}}, \
2605 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2606 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2607 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2608 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2609 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2610 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2611 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2612 {"thumb_cmpneg_operand", {CONST_INT}}, \
2613 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2614 {"offsettable_memory_operand", {MEM}}, \
2615 {"alignable_memory_operand", {MEM}}, \
2616 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2617 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2618 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2619 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2620 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2621 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2622 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2623 {"load_multiple_operation", {PARALLEL}}, \
2624 {"store_multiple_operation", {PARALLEL}}, \
2625 {"equality_operator", {EQ, NE}}, \
2626 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2627 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2628 UNGE, UNGT}}, \
2629 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2630 {"const_shift_operand", {CONST_INT}}, \
2631 {"multi_register_push", {PARALLEL}}, \
2632 {"cc_register", {REG}}, \
2633 {"logical_binary_operator", {AND, IOR, XOR}}, \
2634 {"cirrus_register_operand", {REG}}, \
2635 {"cirrus_fp_register", {REG}}, \
2636 {"cirrus_shift_const", {CONST_INT}}, \
2637 {"dominant_cc_register", {REG}}, \
2638 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2639 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2640
2641 /* Define this if you have special predicates that know special things
2642 about modes. Genrecog will warn about certain forms of
2643 match_operand without a mode; if the operand predicate is listed in
2644 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2645 #define SPECIAL_MODE_PREDICATES \
2646 "cc_register", "dominant_cc_register",
2647
2648 enum arm_builtins
2649 {
2650 ARM_BUILTIN_GETWCX,
2651 ARM_BUILTIN_SETWCX,
2652
2653 ARM_BUILTIN_WZERO,
2654
2655 ARM_BUILTIN_WAVG2BR,
2656 ARM_BUILTIN_WAVG2HR,
2657 ARM_BUILTIN_WAVG2B,
2658 ARM_BUILTIN_WAVG2H,
2659
2660 ARM_BUILTIN_WACCB,
2661 ARM_BUILTIN_WACCH,
2662 ARM_BUILTIN_WACCW,
2663
2664 ARM_BUILTIN_WMACS,
2665 ARM_BUILTIN_WMACSZ,
2666 ARM_BUILTIN_WMACU,
2667 ARM_BUILTIN_WMACUZ,
2668
2669 ARM_BUILTIN_WSADB,
2670 ARM_BUILTIN_WSADBZ,
2671 ARM_BUILTIN_WSADH,
2672 ARM_BUILTIN_WSADHZ,
2673
2674 ARM_BUILTIN_WALIGN,
2675
2676 ARM_BUILTIN_TMIA,
2677 ARM_BUILTIN_TMIAPH,
2678 ARM_BUILTIN_TMIABB,
2679 ARM_BUILTIN_TMIABT,
2680 ARM_BUILTIN_TMIATB,
2681 ARM_BUILTIN_TMIATT,
2682
2683 ARM_BUILTIN_TMOVMSKB,
2684 ARM_BUILTIN_TMOVMSKH,
2685 ARM_BUILTIN_TMOVMSKW,
2686
2687 ARM_BUILTIN_TBCSTB,
2688 ARM_BUILTIN_TBCSTH,
2689 ARM_BUILTIN_TBCSTW,
2690
2691 ARM_BUILTIN_WMADDS,
2692 ARM_BUILTIN_WMADDU,
2693
2694 ARM_BUILTIN_WPACKHSS,
2695 ARM_BUILTIN_WPACKWSS,
2696 ARM_BUILTIN_WPACKDSS,
2697 ARM_BUILTIN_WPACKHUS,
2698 ARM_BUILTIN_WPACKWUS,
2699 ARM_BUILTIN_WPACKDUS,
2700
2701 ARM_BUILTIN_WADDB,
2702 ARM_BUILTIN_WADDH,
2703 ARM_BUILTIN_WADDW,
2704 ARM_BUILTIN_WADDSSB,
2705 ARM_BUILTIN_WADDSSH,
2706 ARM_BUILTIN_WADDSSW,
2707 ARM_BUILTIN_WADDUSB,
2708 ARM_BUILTIN_WADDUSH,
2709 ARM_BUILTIN_WADDUSW,
2710 ARM_BUILTIN_WSUBB,
2711 ARM_BUILTIN_WSUBH,
2712 ARM_BUILTIN_WSUBW,
2713 ARM_BUILTIN_WSUBSSB,
2714 ARM_BUILTIN_WSUBSSH,
2715 ARM_BUILTIN_WSUBSSW,
2716 ARM_BUILTIN_WSUBUSB,
2717 ARM_BUILTIN_WSUBUSH,
2718 ARM_BUILTIN_WSUBUSW,
2719
2720 ARM_BUILTIN_WAND,
2721 ARM_BUILTIN_WANDN,
2722 ARM_BUILTIN_WOR,
2723 ARM_BUILTIN_WXOR,
2724
2725 ARM_BUILTIN_WCMPEQB,
2726 ARM_BUILTIN_WCMPEQH,
2727 ARM_BUILTIN_WCMPEQW,
2728 ARM_BUILTIN_WCMPGTUB,
2729 ARM_BUILTIN_WCMPGTUH,
2730 ARM_BUILTIN_WCMPGTUW,
2731 ARM_BUILTIN_WCMPGTSB,
2732 ARM_BUILTIN_WCMPGTSH,
2733 ARM_BUILTIN_WCMPGTSW,
2734
2735 ARM_BUILTIN_TEXTRMSB,
2736 ARM_BUILTIN_TEXTRMSH,
2737 ARM_BUILTIN_TEXTRMSW,
2738 ARM_BUILTIN_TEXTRMUB,
2739 ARM_BUILTIN_TEXTRMUH,
2740 ARM_BUILTIN_TEXTRMUW,
2741 ARM_BUILTIN_TINSRB,
2742 ARM_BUILTIN_TINSRH,
2743 ARM_BUILTIN_TINSRW,
2744
2745 ARM_BUILTIN_WMAXSW,
2746 ARM_BUILTIN_WMAXSH,
2747 ARM_BUILTIN_WMAXSB,
2748 ARM_BUILTIN_WMAXUW,
2749 ARM_BUILTIN_WMAXUH,
2750 ARM_BUILTIN_WMAXUB,
2751 ARM_BUILTIN_WMINSW,
2752 ARM_BUILTIN_WMINSH,
2753 ARM_BUILTIN_WMINSB,
2754 ARM_BUILTIN_WMINUW,
2755 ARM_BUILTIN_WMINUH,
2756 ARM_BUILTIN_WMINUB,
2757
2758 ARM_BUILTIN_WMULUM,
2759 ARM_BUILTIN_WMULSM,
2760 ARM_BUILTIN_WMULUL,
2761
2762 ARM_BUILTIN_PSADBH,
2763 ARM_BUILTIN_WSHUFH,
2764
2765 ARM_BUILTIN_WSLLH,
2766 ARM_BUILTIN_WSLLW,
2767 ARM_BUILTIN_WSLLD,
2768 ARM_BUILTIN_WSRAH,
2769 ARM_BUILTIN_WSRAW,
2770 ARM_BUILTIN_WSRAD,
2771 ARM_BUILTIN_WSRLH,
2772 ARM_BUILTIN_WSRLW,
2773 ARM_BUILTIN_WSRLD,
2774 ARM_BUILTIN_WRORH,
2775 ARM_BUILTIN_WRORW,
2776 ARM_BUILTIN_WRORD,
2777 ARM_BUILTIN_WSLLHI,
2778 ARM_BUILTIN_WSLLWI,
2779 ARM_BUILTIN_WSLLDI,
2780 ARM_BUILTIN_WSRAHI,
2781 ARM_BUILTIN_WSRAWI,
2782 ARM_BUILTIN_WSRADI,
2783 ARM_BUILTIN_WSRLHI,
2784 ARM_BUILTIN_WSRLWI,
2785 ARM_BUILTIN_WSRLDI,
2786 ARM_BUILTIN_WRORHI,
2787 ARM_BUILTIN_WRORWI,
2788 ARM_BUILTIN_WRORDI,
2789
2790 ARM_BUILTIN_WUNPCKIHB,
2791 ARM_BUILTIN_WUNPCKIHH,
2792 ARM_BUILTIN_WUNPCKIHW,
2793 ARM_BUILTIN_WUNPCKILB,
2794 ARM_BUILTIN_WUNPCKILH,
2795 ARM_BUILTIN_WUNPCKILW,
2796
2797 ARM_BUILTIN_WUNPCKEHSB,
2798 ARM_BUILTIN_WUNPCKEHSH,
2799 ARM_BUILTIN_WUNPCKEHSW,
2800 ARM_BUILTIN_WUNPCKEHUB,
2801 ARM_BUILTIN_WUNPCKEHUH,
2802 ARM_BUILTIN_WUNPCKEHUW,
2803 ARM_BUILTIN_WUNPCKELSB,
2804 ARM_BUILTIN_WUNPCKELSH,
2805 ARM_BUILTIN_WUNPCKELSW,
2806 ARM_BUILTIN_WUNPCKELUB,
2807 ARM_BUILTIN_WUNPCKELUH,
2808 ARM_BUILTIN_WUNPCKELUW,
2809
2810 ARM_BUILTIN_MAX
2811 };
2812 #endif /* ! GCC_ARM_H */
Mirror of the offical gcc git repository hosted at gcc.gnu.org