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* defaults.h (FRAME_GROWS_DOWNWARD): Define to 0 if not defined.
[official-gcc.git] / gcc / config / arm / arm.h
blob65b4bad144be3534447d290d14d541e6d38ded3d
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The architecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 extern GTY(()) rtx arm_compare_op0;
123 extern GTY(()) rtx arm_compare_op1;
124 /* The label of the current constant pool. */
125 extern rtx pool_vector_label;
126 /* Set to 1 when a return insn is output, this means that the epilogue
127 is not needed. */
128 extern int return_used_this_function;
129 /* Used to produce AOF syntax assembler. */
130 extern GTY(()) rtx aof_pic_label;
131 \f
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
135 #endif
136
137
138 #undef CPP_SPEC
139 #define CPP_SPEC "%(subtarget_cpp_spec) \
140 %{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142 %{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
144
145 #ifndef CC1_SPEC
146 #define CC1_SPEC ""
147 #endif
148
149 /* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
152
153 Each subgrouping contains a string constant, that defines the
154 specification name, and a string constant that used by the GCC driver
155 program.
156
157 Do not define this macro if it does not need to do anything. */
158 #define EXTRA_SPECS \
159 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
160 SUBTARGET_EXTRA_SPECS
161
162 #ifndef SUBTARGET_EXTRA_SPECS
163 #define SUBTARGET_EXTRA_SPECS
164 #endif
165
166 #ifndef SUBTARGET_CPP_SPEC
167 #define SUBTARGET_CPP_SPEC ""
168 #endif
169 \f
170 /* Run-time Target Specification. */
171 #ifndef TARGET_VERSION
172 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
173 #endif
174
175 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
176 /* Use hardware floating point instructions. */
177 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point calling convention. */
179 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
180 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
183 #define TARGET_IWMMXT (arm_arch_iwmmxt)
184 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
185 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
186 #define TARGET_ARM (! TARGET_THUMB)
187 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
188 #define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
190 : TARGET_TPCS_FRAME)
191 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
192 #define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
194
195 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
196 then TARGET_AAPCS_BASED must be true -- but the converse does not
197 hold. TARGET_BPABI implies the use of the BPABI runtime library,
198 etc., in addition to just the AAPCS calling conventions. */
199 #ifndef TARGET_BPABI
200 #define TARGET_BPABI false
201 #endif
202
203 /* Support for a compile-time default CPU, et cetera. The rules are:
204 --with-arch is ignored if -march or -mcpu are specified.
205 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
206 by --with-arch.
207 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
208 by -march).
209 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
210 specified.
211 --with-fpu is ignored if -mfpu is specified.
212 --with-abi is ignored is -mabi is specified. */
213 #define OPTION_DEFAULT_SPECS \
214 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
215 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
216 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
217 {"float", \
218 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
219 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
220 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
221
222 /* Which floating point model to use. */
223 enum arm_fp_model
224 {
225 ARM_FP_MODEL_UNKNOWN,
226 /* FPA model (Hardware or software). */
227 ARM_FP_MODEL_FPA,
228 /* Cirrus Maverick floating point model. */
229 ARM_FP_MODEL_MAVERICK,
230 /* VFP floating point model. */
231 ARM_FP_MODEL_VFP
232 };
233
234 extern enum arm_fp_model arm_fp_model;
235
236 /* Which floating point hardware is available. Also update
237 fp_model_for_fpu in arm.c when adding entries to this list. */
238 enum fputype
239 {
240 /* No FP hardware. */
241 FPUTYPE_NONE,
242 /* Full FPA support. */
243 FPUTYPE_FPA,
244 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
245 FPUTYPE_FPA_EMU2,
246 /* Emulated FPA hardware, Issue 3 emulator. */
247 FPUTYPE_FPA_EMU3,
248 /* Cirrus Maverick floating point co-processor. */
249 FPUTYPE_MAVERICK,
250 /* VFP. */
251 FPUTYPE_VFP
252 };
253
254 /* Recast the floating point class to be the floating point attribute. */
255 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
256
257 /* What type of floating point to tune for */
258 extern enum fputype arm_fpu_tune;
259
260 /* What type of floating point instructions are available */
261 extern enum fputype arm_fpu_arch;
262
263 enum float_abi_type
264 {
265 ARM_FLOAT_ABI_SOFT,
266 ARM_FLOAT_ABI_SOFTFP,
267 ARM_FLOAT_ABI_HARD
268 };
269
270 extern enum float_abi_type arm_float_abi;
271
272 #ifndef TARGET_DEFAULT_FLOAT_ABI
273 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
274 #endif
275
276 /* Which ABI to use. */
277 enum arm_abi_type
278 {
279 ARM_ABI_APCS,
280 ARM_ABI_ATPCS,
281 ARM_ABI_AAPCS,
282 ARM_ABI_IWMMXT
283 };
284
285 extern enum arm_abi_type arm_abi;
286
287 #ifndef ARM_DEFAULT_ABI
288 #define ARM_DEFAULT_ABI ARM_ABI_APCS
289 #endif
290
291 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
292 extern int arm_arch3m;
293
294 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
295 extern int arm_arch4;
296
297 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
298 extern int arm_arch4t;
299
300 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
301 extern int arm_arch5;
302
303 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
304 extern int arm_arch5e;
305
306 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
307 extern int arm_arch6;
308
309 /* Nonzero if this chip can benefit from load scheduling. */
310 extern int arm_ld_sched;
311
312 /* Nonzero if generating thumb code. */
313 extern int thumb_code;
314
315 /* Nonzero if this chip is a StrongARM. */
316 extern int arm_tune_strongarm;
317
318 /* Nonzero if this chip is a Cirrus variant. */
319 extern int arm_arch_cirrus;
320
321 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
322 extern int arm_arch_iwmmxt;
323
324 /* Nonzero if this chip is an XScale. */
325 extern int arm_arch_xscale;
326
327 /* Nonzero if tuning for XScale. */
328 extern int arm_tune_xscale;
329
330 /* Nonzero if tuning for stores via the write buffer. */
331 extern int arm_tune_wbuf;
332
333 /* Nonzero if we should define __THUMB_INTERWORK__ in the
334 preprocessor.
335 XXX This is a bit of a hack, it's intended to help work around
336 problems in GLD which doesn't understand that armv5t code is
337 interworking clean. */
338 extern int arm_cpp_interwork;
339
340 #ifndef TARGET_DEFAULT
341 #define TARGET_DEFAULT (MASK_APCS_FRAME)
342 #endif
343
344 /* The frame pointer register used in gcc has nothing to do with debugging;
345 that is controlled by the APCS-FRAME option. */
346 #define CAN_DEBUG_WITHOUT_FP
347
348 #define OVERRIDE_OPTIONS arm_override_options ()
349
350 /* Nonzero if PIC code requires explicit qualifiers to generate
351 PLT and GOT relocs rather than the assembler doing so implicitly.
352 Subtargets can override these if required. */
353 #ifndef NEED_GOT_RELOC
354 #define NEED_GOT_RELOC 0
355 #endif
356 #ifndef NEED_PLT_RELOC
357 #define NEED_PLT_RELOC 0
358 #endif
359
360 /* Nonzero if we need to refer to the GOT with a PC-relative
361 offset. In other words, generate
362
363 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
364
365 rather than
366
367 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
368
369 The default is true, which matches NetBSD. Subtargets can
370 override this if required. */
371 #ifndef GOT_PCREL
372 #define GOT_PCREL 1
373 #endif
374 \f
375 /* Target machine storage Layout. */
376
377
378 /* Define this macro if it is advisable to hold scalars in registers
379 in a wider mode than that declared by the program. In such cases,
380 the value is constrained to be within the bounds of the declared
381 type, but kept valid in the wider mode. The signedness of the
382 extension may differ from that of the type. */
383
384 /* It is far faster to zero extend chars than to sign extend them */
385
386 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
387 if (GET_MODE_CLASS (MODE) == MODE_INT \
388 && GET_MODE_SIZE (MODE) < 4) \
389 { \
390 if (MODE == QImode) \
391 UNSIGNEDP = 1; \
392 else if (MODE == HImode) \
393 UNSIGNEDP = 1; \
394 (MODE) = SImode; \
395 }
396
397 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
398 if ((GET_MODE_CLASS (MODE) == MODE_INT \
399 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
400 && GET_MODE_SIZE (MODE) < 4) \
401 (MODE) = SImode; \
402
403 /* Define this if most significant bit is lowest numbered
404 in instructions that operate on numbered bit-fields. */
405 #define BITS_BIG_ENDIAN 0
406
407 /* Define this if most significant byte of a word is the lowest numbered.
408 Most ARM processors are run in little endian mode, so that is the default.
409 If you want to have it run-time selectable, change the definition in a
410 cover file to be TARGET_BIG_ENDIAN. */
411 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
412
413 /* Define this if most significant word of a multiword number is the lowest
414 numbered.
415 This is always false, even when in big-endian mode. */
416 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
417
418 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
419 on processor pre-defineds when compiling libgcc2.c. */
420 #if defined(__ARMEB__) && !defined(__ARMWEL__)
421 #define LIBGCC2_WORDS_BIG_ENDIAN 1
422 #else
423 #define LIBGCC2_WORDS_BIG_ENDIAN 0
424 #endif
425
426 /* Define this if most significant word of doubles is the lowest numbered.
427 The rules are different based on whether or not we use FPA-format,
428 VFP-format or some other floating point co-processor's format doubles. */
429 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
430
431 #define UNITS_PER_WORD 4
432
433 /* True if natural alignment is used for doubleword types. */
434 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
435
436 #define DOUBLEWORD_ALIGNMENT 64
437
438 #define PARM_BOUNDARY 32
439
440 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
441
442 #define PREFERRED_STACK_BOUNDARY \
443 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
444
445 #define FUNCTION_BOUNDARY 32
446
447 /* The lowest bit is used to indicate Thumb-mode functions, so the
448 vbit must go into the delta field of pointers to member
449 functions. */
450 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
451
452 #define EMPTY_FIELD_BOUNDARY 32
453
454 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
455
456 /* XXX Blah -- this macro is used directly by libobjc. Since it
457 supports no vector modes, cut out the complexity and fall back
458 on BIGGEST_FIELD_ALIGNMENT. */
459 #ifdef IN_TARGET_LIBS
460 #define BIGGEST_FIELD_ALIGNMENT 64
461 #endif
462
463 /* Make strings word-aligned so strcpy from constants will be faster. */
464 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
465
466 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
467 ((TREE_CODE (EXP) == STRING_CST \
468 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
469 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
470
471 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
472 value set in previous versions of this toolchain was 8, which produces more
473 compact structures. The command line option -mstructure_size_boundary=<n>
474 can be used to change this value. For compatibility with the ARM SDK
475 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
476 0020D) page 2-20 says "Structures are aligned on word boundaries".
477 The AAPCS specifies a value of 8. */
478 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
479 extern int arm_structure_size_boundary;
480
481 /* This is the value used to initialize arm_structure_size_boundary. If a
482 particular arm target wants to change the default value it should change
483 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
484 for an example of this. */
485 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
486 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
487 #endif
488
489 /* Nonzero if move instructions will actually fail to work
490 when given unaligned data. */
491 #define STRICT_ALIGNMENT 1
492
493 /* wchar_t is unsigned under the AAPCS. */
494 #ifndef WCHAR_TYPE
495 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
496
497 #define WCHAR_TYPE_SIZE BITS_PER_WORD
498 #endif
499
500 #ifndef SIZE_TYPE
501 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
502 #endif
503
504 /* AAPCS requires that structure alignment is affected by bitfields. */
505 #ifndef PCC_BITFIELD_TYPE_MATTERS
506 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
507 #endif
508
509 \f
510 /* Standard register usage. */
511
512 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
513 (S - saved over call).
514
515 r0 * argument word/integer result
516 r1-r3 argument word
517
518 r4-r8 S register variable
519 r9 S (rfp) register variable (real frame pointer)
520
521 r10 F S (sl) stack limit (used by -mapcs-stack-check)
522 r11 F S (fp) argument pointer
523 r12 (ip) temp workspace
524 r13 F S (sp) lower end of current stack frame
525 r14 (lr) link address/workspace
526 r15 F (pc) program counter
527
528 f0 floating point result
529 f1-f3 floating point scratch
530
531 f4-f7 S floating point variable
532
533 cc This is NOT a real register, but is used internally
534 to represent things that use or set the condition
535 codes.
536 sfp This isn't either. It is used during rtl generation
537 since the offset between the frame pointer and the
538 auto's isn't known until after register allocation.
539 afp Nor this, we only need this because of non-local
540 goto. Without it fp appears to be used and the
541 elimination code won't get rid of sfp. It tracks
542 fp exactly at all times.
543
544 *: See CONDITIONAL_REGISTER_USAGE */
545
546 /*
547 mvf0 Cirrus floating point result
548 mvf1-mvf3 Cirrus floating point scratch
549 mvf4-mvf15 S Cirrus floating point variable. */
550
551 /* s0-s15 VFP scratch (aka d0-d7).
552 s16-s31 S VFP variable (aka d8-d15).
553 vfpcc Not a real register. Represents the VFP condition
554 code flags. */
555
556 /* The stack backtrace structure is as follows:
557 fp points to here: | save code pointer | [fp]
558 | return link value | [fp, #-4]
559 | return sp value | [fp, #-8]
560 | return fp value | [fp, #-12]
561 [| saved r10 value |]
562 [| saved r9 value |]
563 [| saved r8 value |]
564 [| saved r7 value |]
565 [| saved r6 value |]
566 [| saved r5 value |]
567 [| saved r4 value |]
568 [| saved r3 value |]
569 [| saved r2 value |]
570 [| saved r1 value |]
571 [| saved r0 value |]
572 [| saved f7 value |] three words
573 [| saved f6 value |] three words
574 [| saved f5 value |] three words
575 [| saved f4 value |] three words
576 r0-r3 are not normally saved in a C function. */
577
578 /* 1 for registers that have pervasive standard uses
579 and are not available for the register allocator. */
580 #define FIXED_REGISTERS \
581 { \
582 0,0,0,0,0,0,0,0, \
583 0,0,0,0,0,1,0,1, \
584 0,0,0,0,0,0,0,0, \
585 1,1,1, \
586 1,1,1,1,1,1,1,1, \
587 1,1,1,1,1,1,1,1, \
588 1,1,1,1,1,1,1,1, \
589 1,1,1,1,1,1,1,1, \
590 1,1,1,1, \
591 1,1,1,1,1,1,1,1, \
592 1,1,1,1,1,1,1,1, \
593 1,1,1,1,1,1,1,1, \
594 1,1,1,1,1,1,1,1, \
595 1 \
596 }
597
598 /* 1 for registers not available across function calls.
599 These must include the FIXED_REGISTERS and also any
600 registers that can be used without being saved.
601 The latter must include the registers where values are returned
602 and the register where structure-value addresses are passed.
603 Aside from that, you can include as many other registers as you like.
604 The CC is not preserved over function calls on the ARM 6, so it is
605 easier to assume this for all. SFP is preserved, since FP is. */
606 #define CALL_USED_REGISTERS \
607 { \
608 1,1,1,1,0,0,0,0, \
609 0,0,0,0,1,1,1,1, \
610 1,1,1,1,0,0,0,0, \
611 1,1,1, \
612 1,1,1,1,1,1,1,1, \
613 1,1,1,1,1,1,1,1, \
614 1,1,1,1,1,1,1,1, \
615 1,1,1,1,1,1,1,1, \
616 1,1,1,1, \
617 1,1,1,1,1,1,1,1, \
618 1,1,1,1,1,1,1,1, \
619 1,1,1,1,1,1,1,1, \
620 1,1,1,1,1,1,1,1, \
621 1 \
622 }
623
624 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
625 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
626 #endif
627
628 #define CONDITIONAL_REGISTER_USAGE \
629 { \
630 int regno; \
631 \
632 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
633 { \
634 for (regno = FIRST_FPA_REGNUM; \
635 regno <= LAST_FPA_REGNUM; ++regno) \
636 fixed_regs[regno] = call_used_regs[regno] = 1; \
637 } \
638 \
639 if (TARGET_THUMB && optimize_size) \
640 { \
641 /* When optimizing for size, it's better not to use \
642 the HI regs, because of the overhead of stacking \
643 them. */ \
644 for (regno = FIRST_HI_REGNUM; \
645 regno <= LAST_HI_REGNUM; ++regno) \
646 fixed_regs[regno] = call_used_regs[regno] = 1; \
647 } \
648 \
649 /* The link register can be clobbered by any branch insn, \
650 but we have no way to track that at present, so mark \
651 it as unavailable. */ \
652 if (TARGET_THUMB) \
653 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
654 \
655 if (TARGET_ARM && TARGET_HARD_FLOAT) \
656 { \
657 if (TARGET_MAVERICK) \
658 { \
659 for (regno = FIRST_FPA_REGNUM; \
660 regno <= LAST_FPA_REGNUM; ++ regno) \
661 fixed_regs[regno] = call_used_regs[regno] = 1; \
662 for (regno = FIRST_CIRRUS_FP_REGNUM; \
663 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
664 { \
665 fixed_regs[regno] = 0; \
666 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
667 } \
668 } \
669 if (TARGET_VFP) \
670 { \
671 for (regno = FIRST_VFP_REGNUM; \
672 regno <= LAST_VFP_REGNUM; ++ regno) \
673 { \
674 fixed_regs[regno] = 0; \
675 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
676 } \
677 } \
678 } \
679 \
680 if (TARGET_REALLY_IWMMXT) \
681 { \
682 regno = FIRST_IWMMXT_GR_REGNUM; \
683 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
684 and wCG1 as call-preserved registers. The 2002/11/21 \
685 revision changed this so that all wCG registers are \
686 scratch registers. */ \
687 for (regno = FIRST_IWMMXT_GR_REGNUM; \
688 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
689 fixed_regs[regno] = 0; \
690 /* The XScale ABI has wR0 - wR9 as scratch registers, \
691 the rest as call-preserved registers. */ \
692 for (regno = FIRST_IWMMXT_REGNUM; \
693 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
694 { \
695 fixed_regs[regno] = 0; \
696 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
697 } \
698 } \
699 \
700 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
701 { \
702 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
703 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
704 } \
705 else if (TARGET_APCS_STACK) \
706 { \
707 fixed_regs[10] = 1; \
708 call_used_regs[10] = 1; \
709 } \
710 /* -mcaller-super-interworking reserves r11 for calls to \
711 _interwork_r11_call_via_rN(). Making the register global \
712 is an easy way of ensuring that it remains valid for all \
713 calls. */ \
714 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
715 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
716 { \
717 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
718 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
719 if (TARGET_CALLER_INTERWORKING) \
720 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
721 } \
722 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
723 }
724
725 /* These are a couple of extensions to the formats accepted
726 by asm_fprintf:
727 %@ prints out ASM_COMMENT_START
728 %r prints out REGISTER_PREFIX reg_names[arg] */
729 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
730 case '@': \
731 fputs (ASM_COMMENT_START, FILE); \
732 break; \
733 \
734 case 'r': \
735 fputs (REGISTER_PREFIX, FILE); \
736 fputs (reg_names [va_arg (ARGS, int)], FILE); \
737 break;
738
739 /* Round X up to the nearest word. */
740 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
741
742 /* Convert fron bytes to ints. */
743 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
744
745 /* The number of (integer) registers required to hold a quantity of type MODE.
746 Also used for VFP registers. */
747 #define ARM_NUM_REGS(MODE) \
748 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
749
750 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
751 #define ARM_NUM_REGS2(MODE, TYPE) \
752 ARM_NUM_INTS ((MODE) == BLKmode ? \
753 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
754
755 /* The number of (integer) argument register available. */
756 #define NUM_ARG_REGS 4
757
758 /* Return the register number of the N'th (integer) argument. */
759 #define ARG_REGISTER(N) (N - 1)
760
761 /* Specify the registers used for certain standard purposes.
762 The values of these macros are register numbers. */
763
764 /* The number of the last argument register. */
765 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
766
767 /* The numbers of the Thumb register ranges. */
768 #define FIRST_LO_REGNUM 0
769 #define LAST_LO_REGNUM 7
770 #define FIRST_HI_REGNUM 8
771 #define LAST_HI_REGNUM 11
772
773 /* We use sjlj exceptions for backwards compatibility. */
774 #define MUST_USE_SJLJ_EXCEPTIONS 1
775 /* We can generate DWARF2 Unwind info, even though we don't use it. */
776 #define DWARF2_UNWIND_INFO 1
777
778 /* Use r0 and r1 to pass exception handling information. */
779 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
780
781 /* The register that holds the return address in exception handlers. */
782 #define ARM_EH_STACKADJ_REGNUM 2
783 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
784
785 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
786 as an invisible last argument (possible since varargs don't exist in
787 Pascal), so the following is not true. */
788 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
789
790 /* Define this to be where the real frame pointer is if it is not possible to
791 work out the offset between the frame pointer and the automatic variables
792 until after register allocation has taken place. FRAME_POINTER_REGNUM
793 should point to a special register that we will make sure is eliminated.
794
795 For the Thumb we have another problem. The TPCS defines the frame pointer
796 as r11, and GCC believes that it is always possible to use the frame pointer
797 as base register for addressing purposes. (See comments in
798 find_reloads_address()). But - the Thumb does not allow high registers,
799 including r11, to be used as base address registers. Hence our problem.
800
801 The solution used here, and in the old thumb port is to use r7 instead of
802 r11 as the hard frame pointer and to have special code to generate
803 backtrace structures on the stack (if required to do so via a command line
804 option) using r11. This is the only 'user visible' use of r11 as a frame
805 pointer. */
806 #define ARM_HARD_FRAME_POINTER_REGNUM 11
807 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
808
809 #define HARD_FRAME_POINTER_REGNUM \
810 (TARGET_ARM \
811 ? ARM_HARD_FRAME_POINTER_REGNUM \
812 : THUMB_HARD_FRAME_POINTER_REGNUM)
813
814 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
815
816 /* Register to use for pushing function arguments. */
817 #define STACK_POINTER_REGNUM SP_REGNUM
818
819 /* ARM floating pointer registers. */
820 #define FIRST_FPA_REGNUM 16
821 #define LAST_FPA_REGNUM 23
822 #define IS_FPA_REGNUM(REGNUM) \
823 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
824
825 #define FIRST_IWMMXT_GR_REGNUM 43
826 #define LAST_IWMMXT_GR_REGNUM 46
827 #define FIRST_IWMMXT_REGNUM 47
828 #define LAST_IWMMXT_REGNUM 62
829 #define IS_IWMMXT_REGNUM(REGNUM) \
830 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
831 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
832 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
833
834 /* Base register for access to local variables of the function. */
835 #define FRAME_POINTER_REGNUM 25
836
837 /* Base register for access to arguments of the function. */
838 #define ARG_POINTER_REGNUM 26
839
840 #define FIRST_CIRRUS_FP_REGNUM 27
841 #define LAST_CIRRUS_FP_REGNUM 42
842 #define IS_CIRRUS_REGNUM(REGNUM) \
843 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
844
845 #define FIRST_VFP_REGNUM 63
846 #define LAST_VFP_REGNUM 94
847 #define IS_VFP_REGNUM(REGNUM) \
848 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
849
850 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
851 /* + 16 Cirrus registers take us up to 43. */
852 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
853 /* VFP adds 32 + 1 more. */
854 #define FIRST_PSEUDO_REGISTER 96
855
856 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
857
858 /* Value should be nonzero if functions must have frame pointers.
859 Zero means the frame pointer need not be set up (and parms may be accessed
860 via the stack pointer) in functions that seem suitable.
861 If we have to have a frame pointer we might as well make use of it.
862 APCS says that the frame pointer does not need to be pushed in leaf
863 functions, or simple tail call functions. */
864
865 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
866 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
867 #endif
868
869 #define FRAME_POINTER_REQUIRED \
870 (current_function_has_nonlocal_label \
871 || SUBTARGET_FRAME_POINTER_REQUIRED \
872 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
873
874 /* Return number of consecutive hard regs needed starting at reg REGNO
875 to hold something of mode MODE.
876 This is ordinarily the length in words of a value of mode MODE
877 but can be less for certain modes in special long registers.
878
879 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
880 mode. */
881 #define HARD_REGNO_NREGS(REGNO, MODE) \
882 ((TARGET_ARM \
883 && REGNO >= FIRST_FPA_REGNUM \
884 && REGNO != FRAME_POINTER_REGNUM \
885 && REGNO != ARG_POINTER_REGNUM) \
886 && !IS_VFP_REGNUM (REGNO) \
887 ? 1 : ARM_NUM_REGS (MODE))
888
889 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
890 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
891 arm_hard_regno_mode_ok ((REGNO), (MODE))
892
893 /* Value is 1 if it is a good idea to tie two pseudo registers
894 when one has mode MODE1 and one has mode MODE2.
895 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
896 for any hard reg, then this must be 0 for correct output. */
897 #define MODES_TIEABLE_P(MODE1, MODE2) \
898 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
899
900 #define VALID_IWMMXT_REG_MODE(MODE) \
901 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
902
903 /* The order in which register should be allocated. It is good to use ip
904 since no saving is required (though calls clobber it) and it never contains
905 function parameters. It is quite good to use lr since other calls may
906 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
907 least likely to contain a function parameter; in addition results are
908 returned in r0. */
909
910 #define REG_ALLOC_ORDER \
911 { \
912 3, 2, 1, 0, 12, 14, 4, 5, \
913 6, 7, 8, 10, 9, 11, 13, 15, \
914 16, 17, 18, 19, 20, 21, 22, 23, \
915 27, 28, 29, 30, 31, 32, 33, 34, \
916 35, 36, 37, 38, 39, 40, 41, 42, \
917 43, 44, 45, 46, 47, 48, 49, 50, \
918 51, 52, 53, 54, 55, 56, 57, 58, \
919 59, 60, 61, 62, \
920 24, 25, 26, \
921 78, 77, 76, 75, 74, 73, 72, 71, \
922 70, 69, 68, 67, 66, 65, 64, 63, \
923 79, 80, 81, 82, 83, 84, 85, 86, \
924 87, 88, 89, 90, 91, 92, 93, 94, \
925 95 \
926 }
927
928 /* Interrupt functions can only use registers that have already been
929 saved by the prologue, even if they would normally be
930 call-clobbered. */
931 #define HARD_REGNO_RENAME_OK(SRC, DST) \
932 (! IS_INTERRUPT (cfun->machine->func_type) || \
933 regs_ever_live[DST])
934 \f
935 /* Register and constant classes. */
936
937 /* Register classes: used to be simple, just all ARM regs or all FPA regs
938 Now that the Thumb is involved it has become more complicated. */
939 enum reg_class
940 {
941 NO_REGS,
942 FPA_REGS,
943 CIRRUS_REGS,
944 VFP_REGS,
945 IWMMXT_GR_REGS,
946 IWMMXT_REGS,
947 LO_REGS,
948 STACK_REG,
949 BASE_REGS,
950 HI_REGS,
951 CC_REG,
952 VFPCC_REG,
953 GENERAL_REGS,
954 ALL_REGS,
955 LIM_REG_CLASSES
956 };
957
958 #define N_REG_CLASSES (int) LIM_REG_CLASSES
959
960 /* Give names of register classes as strings for dump file. */
961 #define REG_CLASS_NAMES \
962 { \
963 "NO_REGS", \
964 "FPA_REGS", \
965 "CIRRUS_REGS", \
966 "VFP_REGS", \
967 "IWMMXT_GR_REGS", \
968 "IWMMXT_REGS", \
969 "LO_REGS", \
970 "STACK_REG", \
971 "BASE_REGS", \
972 "HI_REGS", \
973 "CC_REG", \
974 "VFPCC_REG", \
975 "GENERAL_REGS", \
976 "ALL_REGS", \
977 }
978
979 /* Define which registers fit in which classes.
980 This is an initializer for a vector of HARD_REG_SET
981 of length N_REG_CLASSES. */
982 #define REG_CLASS_CONTENTS \
983 { \
984 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
985 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
986 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
987 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
988 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
989 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
990 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
991 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
992 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
993 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
994 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
995 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
996 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
997 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
998 }
999
1000 /* The same information, inverted:
1001 Return the class number of the smallest class containing
1002 reg number REGNO. This could be a conditional expression
1003 or could index an array. */
1004 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1005
1006 /* FPA registers can't do subreg as all values are reformatted to internal
1007 precision. VFP registers may only be accessed in the mode they
1008 were set. */
1009 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1010 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1011 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1012 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1013 : 0)
1014
1015 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1016 using r0-r4 for function arguments, r7 for the stack frame and don't
1017 have enough left over to do doubleword arithmetic. */
1018 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1019 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1020 || (CLASS) == CC_REG)
1021
1022 /* The class value for index registers, and the one for base regs. */
1023 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1024 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1025
1026 /* For the Thumb the high registers cannot be used as base registers
1027 when addressing quantities in QI or HI mode; if we don't know the
1028 mode, then we must be conservative. */
1029 #define MODE_BASE_REG_CLASS(MODE) \
1030 (TARGET_ARM ? GENERAL_REGS : \
1031 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1032
1033 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1034 instead of BASE_REGS. */
1035 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1036
1037 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1038 registers explicitly used in the rtl to be used as spill registers
1039 but prevents the compiler from extending the lifetime of these
1040 registers. */
1041 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1042
1043 /* Get reg_class from a letter such as appears in the machine description.
1044 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1045 ARM, but several more letters for the Thumb. */
1046 #define REG_CLASS_FROM_LETTER(C) \
1047 ( (C) == 'f' ? FPA_REGS \
1048 : (C) == 'v' ? CIRRUS_REGS \
1049 : (C) == 'w' ? VFP_REGS \
1050 : (C) == 'y' ? IWMMXT_REGS \
1051 : (C) == 'z' ? IWMMXT_GR_REGS \
1052 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1053 : TARGET_ARM ? NO_REGS \
1054 : (C) == 'h' ? HI_REGS \
1055 : (C) == 'b' ? BASE_REGS \
1056 : (C) == 'k' ? STACK_REG \
1057 : (C) == 'c' ? CC_REG \
1058 : NO_REGS)
1059
1060 /* The letters I, J, K, L and M in a register constraint string
1061 can be used to stand for particular ranges of immediate operands.
1062 This macro defines what the ranges are.
1063 C is the letter, and VALUE is a constant value.
1064 Return 1 if VALUE is in the range specified by C.
1065 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1066 J: valid indexing constants.
1067 K: ~value ok in rhs argument of data operand.
1068 L: -value ok in rhs argument of data operand.
1069 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1070 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1071 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1072 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1073 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1074 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1075 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1076 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1077 : 0)
1078
1079 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1080 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1081 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1082 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1083 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1084 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1085 && ((VAL) & 3) == 0) : \
1086 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1087 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1088 : 0)
1089
1090 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1091 (TARGET_ARM ? \
1092 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1093
1094 /* Constant letter 'G' for the FP immediate constants.
1095 'H' means the same constant negated. */
1096 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1097 ((C) == 'G' ? arm_const_double_rtx (X) : \
1098 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1099
1100 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1101 (TARGET_ARM ? \
1102 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1103
1104 /* For the ARM, `Q' means that this is a memory operand that is just
1105 an offset from a register.
1106 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1107 address. This means that the symbol is in the text segment and can be
1108 accessed without using a load.
1109 'D' Prefixes a number of const_double operands where:
1110 'Da' is a constant that takes two ARM insns to load.
1111 'Db' takes three ARM insns.
1112 'Dc' takes four ARM insns, if we allow that in this compilation.
1113 'U' Prefixes an extended memory constraint where:
1114 'Uv' is an address valid for VFP load/store insns.
1115 'Uy' is an address valid for iwmmxt load/store insns.
1116 'Uq' is an address valid for ldrsb. */
1117
1118 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1119 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1120 || GET_CODE (OP) == CONST_INT \
1121 || GET_CODE (OP) == CONST_VECTOR) \
1122 && (((STR)[1] == 'a' \
1123 && arm_const_double_inline_cost (OP) == 2) \
1124 || ((STR)[1] == 'b' \
1125 && arm_const_double_inline_cost (OP) == 3) \
1126 || ((STR)[1] == 'c' \
1127 && arm_const_double_inline_cost (OP) == 4 \
1128 && !(optimize_size || arm_ld_sched)))) : \
1129 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1130 && GET_CODE (XEXP (OP, 0)) == REG) : \
1131 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1132 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1133 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1134 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1135 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1136 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1137 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1138 ((C) == 'U' && (STR)[1] == 'q') \
1139 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1140 : 0)
1141
1142 #define CONSTRAINT_LEN(C,STR) \
1143 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1144
1145 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1146 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1147 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1148
1149 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1150 (TARGET_ARM \
1151 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1152 : EXTRA_CONSTRAINT_THUMB (X, C))
1153
1154 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1155
1156 /* Given an rtx X being reloaded into a reg required to be
1157 in class CLASS, return the class of reg to actually use.
1158 In general this is just CLASS, but for the Thumb we prefer
1159 a LO_REGS class or a subset. */
1160 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1161 (TARGET_ARM ? (CLASS) : \
1162 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1163
1164 /* Must leave BASE_REGS reloads alone */
1165 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1166 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1167 ? ((true_regnum (X) == -1 ? LO_REGS \
1168 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1169 : NO_REGS)) \
1170 : NO_REGS)
1171
1172 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1173 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1174 ? ((true_regnum (X) == -1 ? LO_REGS \
1175 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1176 : NO_REGS)) \
1177 : NO_REGS)
1178
1179 /* Return the register class of a scratch register needed to copy IN into
1180 or out of a register in CLASS in MODE. If it can be done directly,
1181 NO_REGS is returned. */
1182 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1183 /* Restrict which direct reloads are allowed for VFP regs. */ \
1184 ((TARGET_VFP && TARGET_HARD_FLOAT \
1185 && (CLASS) == VFP_REGS) \
1186 ? vfp_secondary_reload_class (MODE, X) \
1187 : TARGET_ARM \
1188 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1189 ? GENERAL_REGS : NO_REGS) \
1190 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1191
1192 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1193 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1194 /* Restrict which direct reloads are allowed for VFP regs. */ \
1195 ((TARGET_VFP && TARGET_HARD_FLOAT \
1196 && (CLASS) == VFP_REGS) \
1197 ? vfp_secondary_reload_class (MODE, X) : \
1198 /* Cannot load constants into Cirrus registers. */ \
1199 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1200 && (CLASS) == CIRRUS_REGS \
1201 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1202 ? GENERAL_REGS : \
1203 (TARGET_ARM ? \
1204 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1205 && CONSTANT_P (X)) \
1206 ? GENERAL_REGS : \
1207 (((MODE) == HImode && ! arm_arch4 \
1208 && (GET_CODE (X) == MEM \
1209 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1210 && true_regnum (X) == -1))) \
1211 ? GENERAL_REGS : NO_REGS) \
1212 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1213
1214 /* Try a machine-dependent way of reloading an illegitimate address
1215 operand. If we find one, push the reload and jump to WIN. This
1216 macro is used in only one place: `find_reloads_address' in reload.c.
1217
1218 For the ARM, we wish to handle large displacements off a base
1219 register by splitting the addend across a MOV and the mem insn.
1220 This can cut the number of reloads needed. */
1221 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1222 do \
1223 { \
1224 if (GET_CODE (X) == PLUS \
1225 && GET_CODE (XEXP (X, 0)) == REG \
1226 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1227 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1228 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1229 { \
1230 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1231 HOST_WIDE_INT low, high; \
1232 \
1233 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1234 low = ((val & 0xf) ^ 0x8) - 0x8; \
1235 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1236 /* Need to be careful, -256 is not a valid offset. */ \
1237 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1238 else if (MODE == SImode \
1239 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1240 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1241 /* Need to be careful, -4096 is not a valid offset. */ \
1242 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1243 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1244 /* Need to be careful, -256 is not a valid offset. */ \
1245 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1246 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1247 && TARGET_HARD_FLOAT && TARGET_FPA) \
1248 /* Need to be careful, -1024 is not a valid offset. */ \
1249 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1250 else \
1251 break; \
1252 \
1253 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1254 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1255 - (unsigned HOST_WIDE_INT) 0x80000000); \
1256 /* Check for overflow or zero */ \
1257 if (low == 0 || high == 0 || (high + low != val)) \
1258 break; \
1259 \
1260 /* Reload the high part into a base reg; leave the low part \
1261 in the mem. */ \
1262 X = gen_rtx_PLUS (GET_MODE (X), \
1263 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1264 GEN_INT (high)), \
1265 GEN_INT (low)); \
1266 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1267 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1268 VOIDmode, 0, 0, OPNUM, TYPE); \
1269 goto WIN; \
1270 } \
1271 } \
1272 while (0)
1273
1274 /* XXX If an HImode FP+large_offset address is converted to an HImode
1275 SP+large_offset address, then reload won't know how to fix it. It sees
1276 only that SP isn't valid for HImode, and so reloads the SP into an index
1277 register, but the resulting address is still invalid because the offset
1278 is too big. We fix it here instead by reloading the entire address. */
1279 /* We could probably achieve better results by defining PROMOTE_MODE to help
1280 cope with the variances between the Thumb's signed and unsigned byte and
1281 halfword load instructions. */
1282 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1283 { \
1284 if (GET_CODE (X) == PLUS \
1285 && GET_MODE_SIZE (MODE) < 4 \
1286 && GET_CODE (XEXP (X, 0)) == REG \
1287 && XEXP (X, 0) == stack_pointer_rtx \
1288 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1289 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1290 { \
1291 rtx orig_X = X; \
1292 X = copy_rtx (X); \
1293 push_reload (orig_X, NULL_RTX, &X, NULL, \
1294 MODE_BASE_REG_CLASS (MODE), \
1295 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1296 goto WIN; \
1297 } \
1298 }
1299
1300 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1301 if (TARGET_ARM) \
1302 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1303 else \
1304 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1305
1306 /* Return the maximum number of consecutive registers
1307 needed to represent mode MODE in a register of class CLASS.
1308 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1309 #define CLASS_MAX_NREGS(CLASS, MODE) \
1310 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1311
1312 /* If defined, gives a class of registers that cannot be used as the
1313 operand of a SUBREG that changes the mode of the object illegally. */
1314
1315 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1316 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1317 (TARGET_ARM ? \
1318 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1319 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1320 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1321 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1322 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1323 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1324 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1325 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1326 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1327 2) \
1328 : \
1329 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1330 \f
1331 /* Stack layout; function entry, exit and calling. */
1332
1333 /* Define this if pushing a word on the stack
1334 makes the stack pointer a smaller address. */
1335 #define STACK_GROWS_DOWNWARD 1
1336
1337 /* Define this to non-zero if the nominal address of the stack frame
1338 is at the high-address end of the local variables;
1339 that is, each additional local variable allocated
1340 goes at a more negative offset in the frame. */
1341 #define FRAME_GROWS_DOWNWARD 1
1342
1343 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1344 When present, it is one word in size, and sits at the top of the frame,
1345 between the soft frame pointer and either r7 or r11.
1346
1347 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1348 and only then if some outgoing arguments are passed on the stack. It would
1349 be tempting to also check whether the stack arguments are passed by indirect
1350 calls, but there seems to be no reason in principle why a post-reload pass
1351 couldn't convert a direct call into an indirect one. */
1352 #define CALLER_INTERWORKING_SLOT_SIZE \
1353 (TARGET_CALLER_INTERWORKING \
1354 && current_function_outgoing_args_size != 0 \
1355 ? UNITS_PER_WORD : 0)
1356
1357 /* Offset within stack frame to start allocating local variables at.
1358 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1359 first local allocated. Otherwise, it is the offset to the BEGINNING
1360 of the first local allocated. */
1361 #define STARTING_FRAME_OFFSET 0
1362
1363 /* If we generate an insn to push BYTES bytes,
1364 this says how many the stack pointer really advances by. */
1365 /* The push insns do not do this rounding implicitly.
1366 So don't define this. */
1367 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1368
1369 /* Define this if the maximum size of all the outgoing args is to be
1370 accumulated and pushed during the prologue. The amount can be
1371 found in the variable current_function_outgoing_args_size. */
1372 #define ACCUMULATE_OUTGOING_ARGS 1
1373
1374 /* Offset of first parameter from the argument pointer register value. */
1375 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1376
1377 /* Value is the number of byte of arguments automatically
1378 popped when returning from a subroutine call.
1379 FUNDECL is the declaration node of the function (as a tree),
1380 FUNTYPE is the data type of the function (as a tree),
1381 or for a library call it is an identifier node for the subroutine name.
1382 SIZE is the number of bytes of arguments passed on the stack.
1383
1384 On the ARM, the caller does not pop any of its arguments that were passed
1385 on the stack. */
1386 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1387
1388 /* Define how to find the value returned by a library function
1389 assuming the value has mode MODE. */
1390 #define LIBCALL_VALUE(MODE) \
1391 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1392 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1393 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1394 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1395 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1396 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1397 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1398 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1399 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1400
1401 /* Define how to find the value returned by a function.
1402 VALTYPE is the data type of the value (as a tree).
1403 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1404 otherwise, FUNC is 0. */
1405 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1406 arm_function_value (VALTYPE, FUNC);
1407
1408 /* 1 if N is a possible register number for a function value.
1409 On the ARM, only r0 and f0 can return results. */
1410 /* On a Cirrus chip, mvf0 can return results. */
1411 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1412 ((REGNO) == ARG_REGISTER (1) \
1413 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1414 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1415 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1416 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1417 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1418
1419 /* Amount of memory needed for an untyped call to save all possible return
1420 registers. */
1421 #define APPLY_RESULT_SIZE arm_apply_result_size()
1422
1423 /* How large values are returned */
1424 /* A C expression which can inhibit the returning of certain function values
1425 in registers, based on the type of value. */
1426 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1427
1428 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1429 values must be in memory. On the ARM, they need only do so if larger
1430 than a word, or if they contain elements offset from zero in the struct. */
1431 #define DEFAULT_PCC_STRUCT_RETURN 0
1432
1433 /* Flags for the call/call_value rtl operations set up by function_arg. */
1434 #define CALL_NORMAL 0x00000000 /* No special processing. */
1435 #define CALL_LONG 0x00000001 /* Always call indirect. */
1436 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1437
1438 /* These bits describe the different types of function supported
1439 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1440 normal function and an interworked function, for example. Knowing the
1441 type of a function is important for determining its prologue and
1442 epilogue sequences.
1443 Note value 7 is currently unassigned. Also note that the interrupt
1444 function types all have bit 2 set, so that they can be tested for easily.
1445 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1446 machine_function structure is initialized (to zero) func_type will
1447 default to unknown. This will force the first use of arm_current_func_type
1448 to call arm_compute_func_type. */
1449 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1450 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1451 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1452 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1453 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1454 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1455
1456 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1457
1458 /* In addition functions can have several type modifiers,
1459 outlined by these bit masks: */
1460 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1461 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1462 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1463 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1464
1465 /* Some macros to test these flags. */
1466 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1467 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1468 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1469 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1470 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1471
1472
1473 /* Structure used to hold the function stack frame layout. Offsets are
1474 relative to the stack pointer on function entry. Positive offsets are
1475 in the direction of stack growth.
1476 Only soft_frame is used in thumb mode. */
1477
1478 typedef struct arm_stack_offsets GTY(())
1479 {
1480 int saved_args; /* ARG_POINTER_REGNUM. */
1481 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1482 int saved_regs;
1483 int soft_frame; /* FRAME_POINTER_REGNUM. */
1484 int outgoing_args; /* STACK_POINTER_REGNUM. */
1485 }
1486 arm_stack_offsets;
1487
1488 /* A C structure for machine-specific, per-function data.
1489 This is added to the cfun structure. */
1490 typedef struct machine_function GTY(())
1491 {
1492 /* Additional stack adjustment in __builtin_eh_throw. */
1493 rtx eh_epilogue_sp_ofs;
1494 /* Records if LR has to be saved for far jumps. */
1495 int far_jump_used;
1496 /* Records if ARG_POINTER was ever live. */
1497 int arg_pointer_live;
1498 /* Records if the save of LR has been eliminated. */
1499 int lr_save_eliminated;
1500 /* The size of the stack frame. Only valid after reload. */
1501 arm_stack_offsets stack_offsets;
1502 /* Records the type of the current function. */
1503 unsigned long func_type;
1504 /* Record if the function has a variable argument list. */
1505 int uses_anonymous_args;
1506 /* Records if sibcalls are blocked because an argument
1507 register is needed to preserve stack alignment. */
1508 int sibcall_blocked;
1509 /* Labels for per-function Thumb call-via stubs. One per potential calling
1510 register. We can never call via LR or PC. We can call via SP if a
1511 trampoline happens to be on the top of the stack. */
1512 rtx call_via[14];
1513 }
1514 machine_function;
1515
1516 /* As in the machine_function, a global set of call-via labels, for code
1517 that is in text_section(). */
1518 extern GTY(()) rtx thumb_call_via_label[14];
1519
1520 /* A C type for declaring a variable that is used as the first argument of
1521 `FUNCTION_ARG' and other related values. For some target machines, the
1522 type `int' suffices and can hold the number of bytes of argument so far. */
1523 typedef struct
1524 {
1525 /* This is the number of registers of arguments scanned so far. */
1526 int nregs;
1527 /* This is the number of iWMMXt register arguments scanned so far. */
1528 int iwmmxt_nregs;
1529 int named_count;
1530 int nargs;
1531 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1532 int call_cookie;
1533 int can_split;
1534 } CUMULATIVE_ARGS;
1535
1536 /* Define where to put the arguments to a function.
1537 Value is zero to push the argument on the stack,
1538 or a hard register in which to store the argument.
1539
1540 MODE is the argument's machine mode.
1541 TYPE is the data type of the argument (as a tree).
1542 This is null for libcalls where that information may
1543 not be available.
1544 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1545 the preceding args and about the function being called.
1546 NAMED is nonzero if this argument is a named parameter
1547 (otherwise it is an extra parameter matching an ellipsis).
1548
1549 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1550 other arguments are passed on the stack. If (NAMED == 0) (which happens
1551 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1552 defined), say it is passed in the stack (function_prologue will
1553 indeed make it pass in the stack if necessary). */
1554 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1555 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1556
1557 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1558 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1559
1560 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1561 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1562
1563 /* For AAPCS, padding should never be below the argument. For other ABIs,
1564 * mimic the default. */
1565 #define PAD_VARARGS_DOWN \
1566 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1567
1568 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1569 for a call to a function whose data type is FNTYPE.
1570 For a library call, FNTYPE is 0.
1571 On the ARM, the offset starts at 0. */
1572 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1573 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1574
1575 /* Update the data in CUM to advance over an argument
1576 of mode MODE and data type TYPE.
1577 (TYPE is null for libcalls where that information may not be available.) */
1578 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1579 (CUM).nargs += 1; \
1580 if (arm_vector_mode_supported_p (MODE) \
1581 && (CUM).named_count > (CUM).nargs) \
1582 (CUM).iwmmxt_nregs += 1; \
1583 else \
1584 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1585
1586 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1587 argument with the specified mode and type. If it is not defined,
1588 `PARM_BOUNDARY' is used for all arguments. */
1589 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1590 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1591 ? DOUBLEWORD_ALIGNMENT \
1592 : PARM_BOUNDARY )
1593
1594 /* 1 if N is a possible register number for function argument passing.
1595 On the ARM, r0-r3 are used to pass args. */
1596 #define FUNCTION_ARG_REGNO_P(REGNO) \
1597 (IN_RANGE ((REGNO), 0, 3) \
1598 || (TARGET_IWMMXT_ABI \
1599 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1600
1601 \f
1602 /* If your target environment doesn't prefix user functions with an
1603 underscore, you may wish to re-define this to prevent any conflicts.
1604 e.g. AOF may prefix mcount with an underscore. */
1605 #ifndef ARM_MCOUNT_NAME
1606 #define ARM_MCOUNT_NAME "*mcount"
1607 #endif
1608
1609 /* Call the function profiler with a given profile label. The Acorn
1610 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1611 On the ARM the full profile code will look like:
1612 .data
1613 LP1
1614 .word 0
1615 .text
1616 mov ip, lr
1617 bl mcount
1618 .word LP1
1619
1620 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1621 will output the .text section.
1622
1623 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1624 ``prof'' doesn't seem to mind about this!
1625
1626 Note - this version of the code is designed to work in both ARM and
1627 Thumb modes. */
1628 #ifndef ARM_FUNCTION_PROFILER
1629 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1630 { \
1631 char temp[20]; \
1632 rtx sym; \
1633 \
1634 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1635 IP_REGNUM, LR_REGNUM); \
1636 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1637 fputc ('\n', STREAM); \
1638 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1639 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1640 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1641 }
1642 #endif
1643
1644 #ifdef THUMB_FUNCTION_PROFILER
1645 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1646 if (TARGET_ARM) \
1647 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1648 else \
1649 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1650 #else
1651 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1652 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1653 #endif
1654
1655 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1656 the stack pointer does not matter. The value is tested only in
1657 functions that have frame pointers.
1658 No definition is equivalent to always zero.
1659
1660 On the ARM, the function epilogue recovers the stack pointer from the
1661 frame. */
1662 #define EXIT_IGNORE_STACK 1
1663
1664 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1665
1666 /* Determine if the epilogue should be output as RTL.
1667 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1668 #define USE_RETURN_INSN(ISCOND) \
1669 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1670
1671 /* Definitions for register eliminations.
1672
1673 This is an array of structures. Each structure initializes one pair
1674 of eliminable registers. The "from" register number is given first,
1675 followed by "to". Eliminations of the same "from" register are listed
1676 in order of preference.
1677
1678 We have two registers that can be eliminated on the ARM. First, the
1679 arg pointer register can often be eliminated in favor of the stack
1680 pointer register. Secondly, the pseudo frame pointer register can always
1681 be eliminated; it is replaced with either the stack or the real frame
1682 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1683 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1684
1685 #define ELIMINABLE_REGS \
1686 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1687 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1688 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1689 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1690 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1691 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1692 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1693
1694 /* Given FROM and TO register numbers, say whether this elimination is
1695 allowed. Frame pointer elimination is automatically handled.
1696
1697 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1698 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1699 pointer, we must eliminate FRAME_POINTER_REGNUM into
1700 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1701 ARG_POINTER_REGNUM. */
1702 #define CAN_ELIMINATE(FROM, TO) \
1703 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1704 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1705 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1706 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1707 1)
1708
1709 /* Define the offset between two registers, one to be eliminated, and the
1710 other its replacement, at the start of a routine. */
1711 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1712 if (TARGET_ARM) \
1713 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1714 else \
1715 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1716
1717 /* Special case handling of the location of arguments passed on the stack. */
1718 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1719
1720 /* Initialize data used by insn expanders. This is called from insn_emit,
1721 once for every function before code is generated. */
1722 #define INIT_EXPANDERS arm_init_expanders ()
1723
1724 /* Output assembler code for a block containing the constant parts
1725 of a trampoline, leaving space for the variable parts.
1726
1727 On the ARM, (if r8 is the static chain regnum, and remembering that
1728 referencing pc adds an offset of 8) the trampoline looks like:
1729 ldr r8, [pc, #0]
1730 ldr pc, [pc]
1731 .word static chain value
1732 .word function's address
1733 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1734 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1735 { \
1736 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1737 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1738 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1739 PC_REGNUM, PC_REGNUM); \
1740 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1741 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1742 }
1743
1744 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1745 Why - because it is easier. This code will always be branched to via
1746 a BX instruction and since the compiler magically generates the address
1747 of the function the linker has no opportunity to ensure that the
1748 bottom bit is set. Thus the processor will be in ARM mode when it
1749 reaches this code. So we duplicate the ARM trampoline code and add
1750 a switch into Thumb mode as well. */
1751 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1752 { \
1753 fprintf (FILE, "\t.code 32\n"); \
1754 fprintf (FILE, ".Ltrampoline_start:\n"); \
1755 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1756 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1757 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1758 IP_REGNUM, PC_REGNUM); \
1759 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1760 IP_REGNUM, IP_REGNUM); \
1761 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1762 fprintf (FILE, "\t.word\t0\n"); \
1763 fprintf (FILE, "\t.word\t0\n"); \
1764 fprintf (FILE, "\t.code 16\n"); \
1765 }
1766
1767 #define TRAMPOLINE_TEMPLATE(FILE) \
1768 if (TARGET_ARM) \
1769 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1770 else \
1771 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1772
1773 /* Length in units of the trampoline for entering a nested function. */
1774 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1775
1776 /* Alignment required for a trampoline in bits. */
1777 #define TRAMPOLINE_ALIGNMENT 32
1778
1779
1780 /* Emit RTL insns to initialize the variable parts of a trampoline.
1781 FNADDR is an RTX for the address of the function's pure code.
1782 CXT is an RTX for the static chain value for the function. */
1783 #ifndef INITIALIZE_TRAMPOLINE
1784 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1785 { \
1786 emit_move_insn (gen_rtx_MEM (SImode, \
1787 plus_constant (TRAMP, \
1788 TARGET_ARM ? 8 : 16)), \
1789 CXT); \
1790 emit_move_insn (gen_rtx_MEM (SImode, \
1791 plus_constant (TRAMP, \
1792 TARGET_ARM ? 12 : 20)), \
1793 FNADDR); \
1794 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1795 0, VOIDmode, 2, TRAMP, Pmode, \
1796 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1797 }
1798 #endif
1799
1800 \f
1801 /* Addressing modes, and classification of registers for them. */
1802 #define HAVE_POST_INCREMENT 1
1803 #define HAVE_PRE_INCREMENT TARGET_ARM
1804 #define HAVE_POST_DECREMENT TARGET_ARM
1805 #define HAVE_PRE_DECREMENT TARGET_ARM
1806 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1807 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1808 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1809 #define HAVE_POST_MODIFY_REG TARGET_ARM
1810
1811 /* Macros to check register numbers against specific register classes. */
1812
1813 /* These assume that REGNO is a hard or pseudo reg number.
1814 They give nonzero only if REGNO is a hard reg of the suitable class
1815 or a pseudo reg currently allocated to a suitable hard reg.
1816 Since they use reg_renumber, they are safe only once reg_renumber
1817 has been allocated, which happens in local-alloc.c. */
1818 #define TEST_REGNO(R, TEST, VALUE) \
1819 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1820
1821 /* On the ARM, don't allow the pc to be used. */
1822 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1823 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1824 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1825 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1826
1827 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1828 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1829 || (GET_MODE_SIZE (MODE) >= 4 \
1830 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1831
1832 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1833 (TARGET_THUMB \
1834 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1835 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1836
1837 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1838 For Thumb, we can not use SP + reg, so reject SP. */
1839 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1840 REGNO_OK_FOR_INDEX_P (X)
1841
1842 /* For ARM code, we don't care about the mode, but for Thumb, the index
1843 must be suitable for use in a QImode load. */
1844 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1845 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1846
1847 /* Maximum number of registers that can appear in a valid memory address.
1848 Shifts in addresses can't be by a register. */
1849 #define MAX_REGS_PER_ADDRESS 2
1850
1851 /* Recognize any constant value that is a valid address. */
1852 /* XXX We can address any constant, eventually... */
1853
1854 #ifdef AOF_ASSEMBLER
1855
1856 #define CONSTANT_ADDRESS_P(X) \
1857 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1858
1859 #else
1860
1861 #define CONSTANT_ADDRESS_P(X) \
1862 (GET_CODE (X) == SYMBOL_REF \
1863 && (CONSTANT_POOL_ADDRESS_P (X) \
1864 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1865
1866 #endif /* AOF_ASSEMBLER */
1867
1868 /* Nonzero if the constant value X is a legitimate general operand.
1869 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1870
1871 On the ARM, allow any integer (invalid ones are removed later by insn
1872 patterns), nice doubles and symbol_refs which refer to the function's
1873 constant pool XXX.
1874
1875 When generating pic allow anything. */
1876 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1877
1878 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1879 ( GET_CODE (X) == CONST_INT \
1880 || GET_CODE (X) == CONST_DOUBLE \
1881 || CONSTANT_ADDRESS_P (X) \
1882 || flag_pic)
1883
1884 #define LEGITIMATE_CONSTANT_P(X) \
1885 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1886
1887 /* Special characters prefixed to function names
1888 in order to encode attribute like information.
1889 Note, '@' and '*' have already been taken. */
1890 #define SHORT_CALL_FLAG_CHAR '^'
1891 #define LONG_CALL_FLAG_CHAR '#'
1892
1893 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1894 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1895
1896 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1897 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1898
1899 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1900 #define SUBTARGET_NAME_ENCODING_LENGTHS
1901 #endif
1902
1903 /* This is a C fragment for the inside of a switch statement.
1904 Each case label should return the number of characters to
1905 be stripped from the start of a function's name, if that
1906 name starts with the indicated character. */
1907 #define ARM_NAME_ENCODING_LENGTHS \
1908 case SHORT_CALL_FLAG_CHAR: return 1; \
1909 case LONG_CALL_FLAG_CHAR: return 1; \
1910 case '*': return 1; \
1911 SUBTARGET_NAME_ENCODING_LENGTHS
1912
1913 /* This is how to output a reference to a user-level label named NAME.
1914 `assemble_name' uses this. */
1915 #undef ASM_OUTPUT_LABELREF
1916 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1917 arm_asm_output_labelref (FILE, NAME)
1918
1919 /* The EABI specifies that constructors should go in .init_array.
1920 Other targets use .ctors for compatibility. */
1921 #ifndef ARM_EABI_CTORS_SECTION_OP
1922 #define ARM_EABI_CTORS_SECTION_OP \
1923 "\t.section\t.init_array,\"aw\",%init_array"
1924 #endif
1925 #ifndef ARM_EABI_DTORS_SECTION_OP
1926 #define ARM_EABI_DTORS_SECTION_OP \
1927 "\t.section\t.fini_array,\"aw\",%fini_array"
1928 #endif
1929 #define ARM_CTORS_SECTION_OP \
1930 "\t.section\t.ctors,\"aw\",%progbits"
1931 #define ARM_DTORS_SECTION_OP \
1932 "\t.section\t.dtors,\"aw\",%progbits"
1933
1934 /* Define CTORS_SECTION_ASM_OP. */
1935 #undef CTORS_SECTION_ASM_OP
1936 #undef DTORS_SECTION_ASM_OP
1937 #ifndef IN_LIBGCC2
1938 # define CTORS_SECTION_ASM_OP \
1939 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1940 # define DTORS_SECTION_ASM_OP \
1941 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1942 #else /* !defined (IN_LIBGCC2) */
1943 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1944 so we cannot use the definition above. */
1945 # ifdef __ARM_EABI__
1946 /* The .ctors section is not part of the EABI, so we do not define
1947 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1948 from trying to use it. We do define it when doing normal
1949 compilation, as .init_array can be used instead of .ctors. */
1950 /* There is no need to emit begin or end markers when using
1951 init_array; the dynamic linker will compute the size of the
1952 array itself based on special symbols created by the static
1953 linker. However, we do need to arrange to set up
1954 exception-handling here. */
1955 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1956 # define CTOR_LIST_END /* empty */
1957 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1958 # define DTOR_LIST_END /* empty */
1959 # else /* !defined (__ARM_EABI__) */
1960 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1961 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1962 # endif /* !defined (__ARM_EABI__) */
1963 #endif /* !defined (IN_LIBCC2) */
1964
1965 /* True if the operating system can merge entities with vague linkage
1966 (e.g., symbols in COMDAT group) during dynamic linking. */
1967 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1968 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1969 #endif
1970
1971 /* Set the short-call flag for any function compiled in the current
1972 compilation unit. We skip this for functions with the section
1973 attribute when long-calls are in effect as this tells the compiler
1974 that the section might be placed a long way from the caller.
1975 See arm_is_longcall_p() for more information. */
1976 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1977 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1978 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1979
1980 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1981 and check its validity for a certain class.
1982 We have two alternate definitions for each of them.
1983 The usual definition accepts all pseudo regs; the other rejects
1984 them unless they have been allocated suitable hard regs.
1985 The symbol REG_OK_STRICT causes the latter definition to be used. */
1986 #ifndef REG_OK_STRICT
1987
1988 #define ARM_REG_OK_FOR_BASE_P(X) \
1989 (REGNO (X) <= LAST_ARM_REGNUM \
1990 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1991 || REGNO (X) == FRAME_POINTER_REGNUM \
1992 || REGNO (X) == ARG_POINTER_REGNUM)
1993
1994 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1995 (REGNO (X) <= LAST_LO_REGNUM \
1996 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1997 || (GET_MODE_SIZE (MODE) >= 4 \
1998 && (REGNO (X) == STACK_POINTER_REGNUM \
1999 || (X) == hard_frame_pointer_rtx \
2000 || (X) == arg_pointer_rtx)))
2001
2002 #define REG_STRICT_P 0
2003
2004 #else /* REG_OK_STRICT */
2005
2006 #define ARM_REG_OK_FOR_BASE_P(X) \
2007 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2008
2009 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2010 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2011
2012 #define REG_STRICT_P 1
2013
2014 #endif /* REG_OK_STRICT */
2015
2016 /* Now define some helpers in terms of the above. */
2017
2018 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2019 (TARGET_THUMB \
2020 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2021 : ARM_REG_OK_FOR_BASE_P (X))
2022
2023 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2024
2025 /* For Thumb, a valid index register is anything that can be used in
2026 a byte load instruction. */
2027 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2028
2029 /* Nonzero if X is a hard reg that can be used as an index
2030 or if it is a pseudo reg. On the Thumb, the stack pointer
2031 is not suitable. */
2032 #define REG_OK_FOR_INDEX_P(X) \
2033 (TARGET_THUMB \
2034 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2035 : ARM_REG_OK_FOR_INDEX_P (X))
2036
2037 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2038 For Thumb, we can not use SP + reg, so reject SP. */
2039 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2040 REG_OK_FOR_INDEX_P (X)
2041 \f
2042 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2043 that is a valid memory address for an instruction.
2044 The MODE argument is the machine mode for the MEM expression
2045 that wants to use this address. */
2046
2047 #define ARM_BASE_REGISTER_RTX_P(X) \
2048 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2049
2050 #define ARM_INDEX_REGISTER_RTX_P(X) \
2051 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2052
2053 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2054 { \
2055 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2056 goto WIN; \
2057 }
2058
2059 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2060 { \
2061 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2062 goto WIN; \
2063 }
2064
2065 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2066 if (TARGET_ARM) \
2067 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2068 else /* if (TARGET_THUMB) */ \
2069 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2070
2071 \f
2072 /* Try machine-dependent ways of modifying an illegitimate address
2073 to be legitimate. If we find one, return the new, valid address. */
2074 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2075 do { \
2076 X = arm_legitimize_address (X, OLDX, MODE); \
2077 } while (0)
2078
2079 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2080 do { \
2081 X = thumb_legitimize_address (X, OLDX, MODE); \
2082 } while (0)
2083
2084 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2085 do { \
2086 if (TARGET_ARM) \
2087 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2088 else \
2089 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2090 \
2091 if (memory_address_p (MODE, X)) \
2092 goto WIN; \
2093 } while (0)
2094
2095 /* Go to LABEL if ADDR (a legitimate address expression)
2096 has an effect that depends on the machine mode it is used for. */
2097 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2098 { \
2099 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2100 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2101 goto LABEL; \
2102 }
2103
2104 /* Nothing helpful to do for the Thumb */
2105 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2106 if (TARGET_ARM) \
2107 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2108 \f
2109
2110 /* Specify the machine mode that this machine uses
2111 for the index in the tablejump instruction. */
2112 #define CASE_VECTOR_MODE Pmode
2113
2114 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2115 unsigned is probably best, but may break some code. */
2116 #ifndef DEFAULT_SIGNED_CHAR
2117 #define DEFAULT_SIGNED_CHAR 0
2118 #endif
2119
2120 /* Max number of bytes we can move from memory to memory
2121 in one reasonably fast instruction. */
2122 #define MOVE_MAX 4
2123
2124 #undef MOVE_RATIO
2125 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2126
2127 /* Define if operations between registers always perform the operation
2128 on the full register even if a narrower mode is specified. */
2129 #define WORD_REGISTER_OPERATIONS
2130
2131 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2132 will either zero-extend or sign-extend. The value of this macro should
2133 be the code that says which one of the two operations is implicitly
2134 done, UNKNOWN if none. */
2135 #define LOAD_EXTEND_OP(MODE) \
2136 (TARGET_THUMB ? ZERO_EXTEND : \
2137 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2138 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2139
2140 /* Nonzero if access to memory by bytes is slow and undesirable. */
2141 #define SLOW_BYTE_ACCESS 0
2142
2143 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2144
2145 /* Immediate shift counts are truncated by the output routines (or was it
2146 the assembler?). Shift counts in a register are truncated by ARM. Note
2147 that the native compiler puts too large (> 32) immediate shift counts
2148 into a register and shifts by the register, letting the ARM decide what
2149 to do instead of doing that itself. */
2150 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2151 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2152 On the arm, Y in a register is used modulo 256 for the shift. Only for
2153 rotates is modulo 32 used. */
2154 /* #define SHIFT_COUNT_TRUNCATED 1 */
2155
2156 /* All integers have the same format so truncation is easy. */
2157 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2158
2159 /* Calling from registers is a massive pain. */
2160 #define NO_FUNCTION_CSE 1
2161
2162 /* The machine modes of pointers and functions */
2163 #define Pmode SImode
2164 #define FUNCTION_MODE Pmode
2165
2166 #define ARM_FRAME_RTX(X) \
2167 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2168 || (X) == arg_pointer_rtx)
2169
2170 /* Moves to and from memory are quite expensive */
2171 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2172 (TARGET_ARM ? 10 : \
2173 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2174 * (CLASS == LO_REGS ? 1 : 2)))
2175
2176 /* Try to generate sequences that don't involve branches, we can then use
2177 conditional instructions */
2178 #define BRANCH_COST \
2179 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2180 \f
2181 /* Position Independent Code. */
2182 /* We decide which register to use based on the compilation options and
2183 the assembler in use; this is more general than the APCS restriction of
2184 using sb (r9) all the time. */
2185 extern int arm_pic_register;
2186
2187 /* The register number of the register used to address a table of static
2188 data addresses in memory. */
2189 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2190
2191 /* We can't directly access anything that contains a symbol,
2192 nor can we indirect via the constant pool. */
2193 #define LEGITIMATE_PIC_OPERAND_P(X) \
2194 (!(symbol_mentioned_p (X) \
2195 || label_mentioned_p (X) \
2196 || (GET_CODE (X) == SYMBOL_REF \
2197 && CONSTANT_POOL_ADDRESS_P (X) \
2198 && (symbol_mentioned_p (get_pool_constant (X)) \
2199 || label_mentioned_p (get_pool_constant (X))))))
2200
2201 /* We need to know when we are making a constant pool; this determines
2202 whether data needs to be in the GOT or can be referenced via a GOT
2203 offset. */
2204 extern int making_const_table;
2205 \f
2206 /* Handle pragmas for compatibility with Intel's compilers. */
2207 #define REGISTER_TARGET_PRAGMAS() do { \
2208 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2209 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2210 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2211 } while (0)
2212
2213 /* Condition code information. */
2214 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2215 return the mode to be used for the comparison. */
2216
2217 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2218
2219 #define REVERSIBLE_CC_MODE(MODE) 1
2220
2221 #define REVERSE_CONDITION(CODE,MODE) \
2222 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2223 ? reverse_condition_maybe_unordered (code) \
2224 : reverse_condition (code))
2225
2226 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2227 do \
2228 { \
2229 if (GET_CODE (OP1) == CONST_INT \
2230 && ! (const_ok_for_arm (INTVAL (OP1)) \
2231 || (const_ok_for_arm (- INTVAL (OP1))))) \
2232 { \
2233 rtx const_op = OP1; \
2234 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2235 OP1 = const_op; \
2236 } \
2237 } \
2238 while (0)
2239
2240 /* The arm5 clz instruction returns 32. */
2241 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2242 \f
2243 #undef ASM_APP_OFF
2244 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2245
2246 /* Output a push or a pop instruction (only used when profiling). */
2247 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2248 do \
2249 { \
2250 if (TARGET_ARM) \
2251 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2252 STACK_POINTER_REGNUM, REGNO); \
2253 else \
2254 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2255 } while (0)
2256
2257
2258 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2259 do \
2260 { \
2261 if (TARGET_ARM) \
2262 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2263 STACK_POINTER_REGNUM, REGNO); \
2264 else \
2265 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2266 } while (0)
2267
2268 /* This is how to output a label which precedes a jumptable. Since
2269 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2270 #undef ASM_OUTPUT_CASE_LABEL
2271 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2272 do \
2273 { \
2274 if (TARGET_THUMB) \
2275 ASM_OUTPUT_ALIGN (FILE, 2); \
2276 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2277 } \
2278 while (0)
2279
2280 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2281 do \
2282 { \
2283 if (TARGET_THUMB) \
2284 { \
2285 if (is_called_in_ARM_mode (DECL) \
2286 || current_function_is_thunk) \
2287 fprintf (STREAM, "\t.code 32\n") ; \
2288 else \
2289 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2290 } \
2291 if (TARGET_POKE_FUNCTION_NAME) \
2292 arm_poke_function_name (STREAM, (char *) NAME); \
2293 } \
2294 while (0)
2295
2296 /* For aliases of functions we use .thumb_set instead. */
2297 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2298 do \
2299 { \
2300 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2301 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2302 \
2303 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2304 { \
2305 fprintf (FILE, "\t.thumb_set "); \
2306 assemble_name (FILE, LABEL1); \
2307 fprintf (FILE, ","); \
2308 assemble_name (FILE, LABEL2); \
2309 fprintf (FILE, "\n"); \
2310 } \
2311 else \
2312 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2313 } \
2314 while (0)
2315
2316 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2317 /* To support -falign-* switches we need to use .p2align so
2318 that alignment directives in code sections will be padded
2319 with no-op instructions, rather than zeroes. */
2320 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2321 if ((LOG) != 0) \
2322 { \
2323 if ((MAX_SKIP) == 0) \
2324 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2325 else \
2326 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2327 (int) (LOG), (int) (MAX_SKIP)); \
2328 }
2329 #endif
2330 \f
2331 /* Only perform branch elimination (by making instructions conditional) if
2332 we're optimizing. Otherwise it's of no use anyway. */
2333 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2334 if (TARGET_ARM && optimize) \
2335 arm_final_prescan_insn (INSN); \
2336 else if (TARGET_THUMB) \
2337 thumb_final_prescan_insn (INSN)
2338
2339 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2340 (CODE == '@' || CODE == '|' \
2341 || (TARGET_ARM && (CODE == '?')) \
2342 || (TARGET_THUMB && (CODE == '_')))
2343
2344 /* Output an operand of an instruction. */
2345 #define PRINT_OPERAND(STREAM, X, CODE) \
2346 arm_print_operand (STREAM, X, CODE)
2347
2348 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2349 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2350 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2351 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2352 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2353 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2354 : 0))))
2355
2356 /* Output the address of an operand. */
2357 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2358 { \
2359 int is_minus = GET_CODE (X) == MINUS; \
2360 \
2361 if (GET_CODE (X) == REG) \
2362 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2363 else if (GET_CODE (X) == PLUS || is_minus) \
2364 { \
2365 rtx base = XEXP (X, 0); \
2366 rtx index = XEXP (X, 1); \
2367 HOST_WIDE_INT offset = 0; \
2368 if (GET_CODE (base) != REG) \
2369 { \
2370 /* Ensure that BASE is a register. */ \
2371 /* (one of them must be). */ \
2372 rtx temp = base; \
2373 base = index; \
2374 index = temp; \
2375 } \
2376 switch (GET_CODE (index)) \
2377 { \
2378 case CONST_INT: \
2379 offset = INTVAL (index); \
2380 if (is_minus) \
2381 offset = -offset; \
2382 asm_fprintf (STREAM, "[%r, #%wd]", \
2383 REGNO (base), offset); \
2384 break; \
2385 \
2386 case REG: \
2387 asm_fprintf (STREAM, "[%r, %s%r]", \
2388 REGNO (base), is_minus ? "-" : "", \
2389 REGNO (index)); \
2390 break; \
2391 \
2392 case MULT: \
2393 case ASHIFTRT: \
2394 case LSHIFTRT: \
2395 case ASHIFT: \
2396 case ROTATERT: \
2397 { \
2398 asm_fprintf (STREAM, "[%r, %s%r", \
2399 REGNO (base), is_minus ? "-" : "", \
2400 REGNO (XEXP (index, 0))); \
2401 arm_print_operand (STREAM, index, 'S'); \
2402 fputs ("]", STREAM); \
2403 break; \
2404 } \
2405 \
2406 default: \
2407 gcc_unreachable (); \
2408 } \
2409 } \
2410 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2411 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2412 { \
2413 extern enum machine_mode output_memory_reference_mode; \
2414 \
2415 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2416 \
2417 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2418 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2419 REGNO (XEXP (X, 0)), \
2420 GET_CODE (X) == PRE_DEC ? "-" : "", \
2421 GET_MODE_SIZE (output_memory_reference_mode)); \
2422 else \
2423 asm_fprintf (STREAM, "[%r], #%s%d", \
2424 REGNO (XEXP (X, 0)), \
2425 GET_CODE (X) == POST_DEC ? "-" : "", \
2426 GET_MODE_SIZE (output_memory_reference_mode)); \
2427 } \
2428 else if (GET_CODE (X) == PRE_MODIFY) \
2429 { \
2430 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2431 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2432 asm_fprintf (STREAM, "#%wd]!", \
2433 INTVAL (XEXP (XEXP (X, 1), 1))); \
2434 else \
2435 asm_fprintf (STREAM, "%r]!", \
2436 REGNO (XEXP (XEXP (X, 1), 1))); \
2437 } \
2438 else if (GET_CODE (X) == POST_MODIFY) \
2439 { \
2440 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2441 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2442 asm_fprintf (STREAM, "#%wd", \
2443 INTVAL (XEXP (XEXP (X, 1), 1))); \
2444 else \
2445 asm_fprintf (STREAM, "%r", \
2446 REGNO (XEXP (XEXP (X, 1), 1))); \
2447 } \
2448 else output_addr_const (STREAM, X); \
2449 }
2450
2451 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2452 { \
2453 if (GET_CODE (X) == REG) \
2454 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2455 else if (GET_CODE (X) == POST_INC) \
2456 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2457 else if (GET_CODE (X) == PLUS) \
2458 { \
2459 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2460 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2461 asm_fprintf (STREAM, "[%r, #%wd]", \
2462 REGNO (XEXP (X, 0)), \
2463 INTVAL (XEXP (X, 1))); \
2464 else \
2465 asm_fprintf (STREAM, "[%r, %r]", \
2466 REGNO (XEXP (X, 0)), \
2467 REGNO (XEXP (X, 1))); \
2468 } \
2469 else \
2470 output_addr_const (STREAM, X); \
2471 }
2472
2473 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2474 if (TARGET_ARM) \
2475 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2476 else \
2477 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2478
2479 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2480 if (GET_CODE (X) != CONST_VECTOR \
2481 || ! arm_emit_vector_const (FILE, X)) \
2482 goto FAIL;
2483
2484 /* A C expression whose value is RTL representing the value of the return
2485 address for the frame COUNT steps up from the current frame. */
2486
2487 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2488 arm_return_addr (COUNT, FRAME)
2489
2490 /* Mask of the bits in the PC that contain the real return address
2491 when running in 26-bit mode. */
2492 #define RETURN_ADDR_MASK26 (0x03fffffc)
2493
2494 /* Pick up the return address upon entry to a procedure. Used for
2495 dwarf2 unwind information. This also enables the table driven
2496 mechanism. */
2497 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2498 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2499
2500 /* Used to mask out junk bits from the return address, such as
2501 processor state, interrupt status, condition codes and the like. */
2502 #define MASK_RETURN_ADDR \
2503 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2504 in 26 bit mode, the condition codes must be masked out of the \
2505 return address. This does not apply to ARM6 and later processors \
2506 when running in 32 bit mode. */ \
2507 ((arm_arch4 || TARGET_THUMB) \
2508 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2509 : arm_gen_return_addr_mask ())
2510
2511 \f
2512 enum arm_builtins
2513 {
2514 ARM_BUILTIN_GETWCX,
2515 ARM_BUILTIN_SETWCX,
2516
2517 ARM_BUILTIN_WZERO,
2518
2519 ARM_BUILTIN_WAVG2BR,
2520 ARM_BUILTIN_WAVG2HR,
2521 ARM_BUILTIN_WAVG2B,
2522 ARM_BUILTIN_WAVG2H,
2523
2524 ARM_BUILTIN_WACCB,
2525 ARM_BUILTIN_WACCH,
2526 ARM_BUILTIN_WACCW,
2527
2528 ARM_BUILTIN_WMACS,
2529 ARM_BUILTIN_WMACSZ,
2530 ARM_BUILTIN_WMACU,
2531 ARM_BUILTIN_WMACUZ,
2532
2533 ARM_BUILTIN_WSADB,
2534 ARM_BUILTIN_WSADBZ,
2535 ARM_BUILTIN_WSADH,
2536 ARM_BUILTIN_WSADHZ,
2537
2538 ARM_BUILTIN_WALIGN,
2539
2540 ARM_BUILTIN_TMIA,
2541 ARM_BUILTIN_TMIAPH,
2542 ARM_BUILTIN_TMIABB,
2543 ARM_BUILTIN_TMIABT,
2544 ARM_BUILTIN_TMIATB,
2545 ARM_BUILTIN_TMIATT,
2546
2547 ARM_BUILTIN_TMOVMSKB,
2548 ARM_BUILTIN_TMOVMSKH,
2549 ARM_BUILTIN_TMOVMSKW,
2550
2551 ARM_BUILTIN_TBCSTB,
2552 ARM_BUILTIN_TBCSTH,
2553 ARM_BUILTIN_TBCSTW,
2554
2555 ARM_BUILTIN_WMADDS,
2556 ARM_BUILTIN_WMADDU,
2557
2558 ARM_BUILTIN_WPACKHSS,
2559 ARM_BUILTIN_WPACKWSS,
2560 ARM_BUILTIN_WPACKDSS,
2561 ARM_BUILTIN_WPACKHUS,
2562 ARM_BUILTIN_WPACKWUS,
2563 ARM_BUILTIN_WPACKDUS,
2564
2565 ARM_BUILTIN_WADDB,
2566 ARM_BUILTIN_WADDH,
2567 ARM_BUILTIN_WADDW,
2568 ARM_BUILTIN_WADDSSB,
2569 ARM_BUILTIN_WADDSSH,
2570 ARM_BUILTIN_WADDSSW,
2571 ARM_BUILTIN_WADDUSB,
2572 ARM_BUILTIN_WADDUSH,
2573 ARM_BUILTIN_WADDUSW,
2574 ARM_BUILTIN_WSUBB,
2575 ARM_BUILTIN_WSUBH,
2576 ARM_BUILTIN_WSUBW,
2577 ARM_BUILTIN_WSUBSSB,
2578 ARM_BUILTIN_WSUBSSH,
2579 ARM_BUILTIN_WSUBSSW,
2580 ARM_BUILTIN_WSUBUSB,
2581 ARM_BUILTIN_WSUBUSH,
2582 ARM_BUILTIN_WSUBUSW,
2583
2584 ARM_BUILTIN_WAND,
2585 ARM_BUILTIN_WANDN,
2586 ARM_BUILTIN_WOR,
2587 ARM_BUILTIN_WXOR,
2588
2589 ARM_BUILTIN_WCMPEQB,
2590 ARM_BUILTIN_WCMPEQH,
2591 ARM_BUILTIN_WCMPEQW,
2592 ARM_BUILTIN_WCMPGTUB,
2593 ARM_BUILTIN_WCMPGTUH,
2594 ARM_BUILTIN_WCMPGTUW,
2595 ARM_BUILTIN_WCMPGTSB,
2596 ARM_BUILTIN_WCMPGTSH,
2597 ARM_BUILTIN_WCMPGTSW,
2598
2599 ARM_BUILTIN_TEXTRMSB,
2600 ARM_BUILTIN_TEXTRMSH,
2601 ARM_BUILTIN_TEXTRMSW,
2602 ARM_BUILTIN_TEXTRMUB,
2603 ARM_BUILTIN_TEXTRMUH,
2604 ARM_BUILTIN_TEXTRMUW,
2605 ARM_BUILTIN_TINSRB,
2606 ARM_BUILTIN_TINSRH,
2607 ARM_BUILTIN_TINSRW,
2608
2609 ARM_BUILTIN_WMAXSW,
2610 ARM_BUILTIN_WMAXSH,
2611 ARM_BUILTIN_WMAXSB,
2612 ARM_BUILTIN_WMAXUW,
2613 ARM_BUILTIN_WMAXUH,
2614 ARM_BUILTIN_WMAXUB,
2615 ARM_BUILTIN_WMINSW,
2616 ARM_BUILTIN_WMINSH,
2617 ARM_BUILTIN_WMINSB,
2618 ARM_BUILTIN_WMINUW,
2619 ARM_BUILTIN_WMINUH,
2620 ARM_BUILTIN_WMINUB,
2621
2622 ARM_BUILTIN_WMULUM,
2623 ARM_BUILTIN_WMULSM,
2624 ARM_BUILTIN_WMULUL,
2625
2626 ARM_BUILTIN_PSADBH,
2627 ARM_BUILTIN_WSHUFH,
2628
2629 ARM_BUILTIN_WSLLH,
2630 ARM_BUILTIN_WSLLW,
2631 ARM_BUILTIN_WSLLD,
2632 ARM_BUILTIN_WSRAH,
2633 ARM_BUILTIN_WSRAW,
2634 ARM_BUILTIN_WSRAD,
2635 ARM_BUILTIN_WSRLH,
2636 ARM_BUILTIN_WSRLW,
2637 ARM_BUILTIN_WSRLD,
2638 ARM_BUILTIN_WRORH,
2639 ARM_BUILTIN_WRORW,
2640 ARM_BUILTIN_WRORD,
2641 ARM_BUILTIN_WSLLHI,
2642 ARM_BUILTIN_WSLLWI,
2643 ARM_BUILTIN_WSLLDI,
2644 ARM_BUILTIN_WSRAHI,
2645 ARM_BUILTIN_WSRAWI,
2646 ARM_BUILTIN_WSRADI,
2647 ARM_BUILTIN_WSRLHI,
2648 ARM_BUILTIN_WSRLWI,
2649 ARM_BUILTIN_WSRLDI,
2650 ARM_BUILTIN_WRORHI,
2651 ARM_BUILTIN_WRORWI,
2652 ARM_BUILTIN_WRORDI,
2653
2654 ARM_BUILTIN_WUNPCKIHB,
2655 ARM_BUILTIN_WUNPCKIHH,
2656 ARM_BUILTIN_WUNPCKIHW,
2657 ARM_BUILTIN_WUNPCKILB,
2658 ARM_BUILTIN_WUNPCKILH,
2659 ARM_BUILTIN_WUNPCKILW,
2660
2661 ARM_BUILTIN_WUNPCKEHSB,
2662 ARM_BUILTIN_WUNPCKEHSH,
2663 ARM_BUILTIN_WUNPCKEHSW,
2664 ARM_BUILTIN_WUNPCKEHUB,
2665 ARM_BUILTIN_WUNPCKEHUH,
2666 ARM_BUILTIN_WUNPCKEHUW,
2667 ARM_BUILTIN_WUNPCKELSB,
2668 ARM_BUILTIN_WUNPCKELSH,
2669 ARM_BUILTIN_WUNPCKELSW,
2670 ARM_BUILTIN_WUNPCKELUB,
2671 ARM_BUILTIN_WUNPCKELUH,
2672 ARM_BUILTIN_WUNPCKELUW,
2673
2674 ARM_BUILTIN_MAX
2675 };
2676 #endif /* ! GCC_ARM_H */
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