?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
* arm.h (CLASS_LIKELY_SPILLED_P): Define.
[official-gcc.git] / gcc / config / arm / arm.h
blob8af53df8c8893501d369deb2b7a94b817cd474bf
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 /* Define __arm__ even when in thumb mode, for \
34 consistency with armcc. */ \
35 builtin_define ("__arm__"); \
36 if (TARGET_THUMB) \
37 builtin_define ("__thumb__"); \
38 \
39 if (TARGET_BIG_END) \
40 { \
41 builtin_define ("__ARMEB__"); \
42 if (TARGET_THUMB) \
43 builtin_define ("__THUMBEB__"); \
44 if (TARGET_LITTLE_WORDS) \
45 builtin_define ("__ARMWEL__"); \
46 } \
47 else \
48 { \
49 builtin_define ("__ARMEL__"); \
50 if (TARGET_THUMB) \
51 builtin_define ("__THUMBEL__"); \
52 } \
53 \
54 if (TARGET_APCS_32) \
55 builtin_define ("__APCS_32__"); \
56 else \
57 builtin_define ("__APCS_26__"); \
58 \
59 if (TARGET_SOFT_FLOAT) \
60 builtin_define ("__SOFTFP__"); \
61 \
62 if (TARGET_VFP) \
63 builtin_define ("__VFP_FP__"); \
64 \
65 /* Add a define for interworking. \
66 Needed when building libgcc.a. */ \
67 if (TARGET_INTERWORK) \
68 builtin_define ("__THUMB_INTERWORK__"); \
69 \
70 builtin_assert ("cpu=arm"); \
71 builtin_assert ("machine=arm"); \
72 } while (0)
73
74 #define TARGET_CPU_arm2 0x0000
75 #define TARGET_CPU_arm250 0x0000
76 #define TARGET_CPU_arm3 0x0000
77 #define TARGET_CPU_arm6 0x0001
78 #define TARGET_CPU_arm600 0x0001
79 #define TARGET_CPU_arm610 0x0002
80 #define TARGET_CPU_arm7 0x0001
81 #define TARGET_CPU_arm7m 0x0004
82 #define TARGET_CPU_arm7dm 0x0004
83 #define TARGET_CPU_arm7dmi 0x0004
84 #define TARGET_CPU_arm700 0x0001
85 #define TARGET_CPU_arm710 0x0002
86 #define TARGET_CPU_arm7100 0x0002
87 #define TARGET_CPU_arm7500 0x0002
88 #define TARGET_CPU_arm7500fe 0x1001
89 #define TARGET_CPU_arm7tdmi 0x0008
90 #define TARGET_CPU_arm8 0x0010
91 #define TARGET_CPU_arm810 0x0020
92 #define TARGET_CPU_strongarm 0x0040
93 #define TARGET_CPU_strongarm110 0x0040
94 #define TARGET_CPU_strongarm1100 0x0040
95 #define TARGET_CPU_arm9 0x0080
96 #define TARGET_CPU_arm9tdmi 0x0080
97 #define TARGET_CPU_xscale 0x0100
98 #define TARGET_CPU_ep9312 0x0200
99 #define TARGET_CPU_iwmmxt 0x0400
100 #define TARGET_CPU_arm926ejs 0x0800
101 #define TARGET_CPU_arm1026ejs 0x1000
102 #define TARGET_CPU_arm1136js 0x2000
103 #define TARGET_CPU_arm1136jfs 0x4000
104 /* Configure didn't specify. */
105 #define TARGET_CPU_generic 0x8000
106
107 /* The various ARM cores. */
108 enum processor_type
109 {
110 #define ARM_CORE(NAME, FLAGS, COSTS) \
111 NAME,
112 #include "arm-cores.def"
113 #undef ARM_CORE
114 /* Used to indicate that no processor has been specified. */
115 arm_none
116 };
117
118 /* The processor for which instructions should be scheduled. */
119 extern enum processor_type arm_tune;
120
121 typedef enum arm_cond_code
122 {
123 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
124 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
125 }
126 arm_cc;
127
128 extern arm_cc arm_current_cc;
129
130 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
131
132 extern int arm_target_label;
133 extern int arm_ccfsm_state;
134 extern GTY(()) rtx arm_target_insn;
135 /* Run-time compilation parameters selecting different hardware subsets. */
136 extern int target_flags;
137 /* The floating point mode. */
138 extern const char *target_fpu_name;
139 /* For backwards compatibility. */
140 extern const char *target_fpe_name;
141 /* Whether to use floating point hardware. */
142 extern const char *target_float_abi_name;
143 /* Which ABI to use. */
144 extern const char *target_abi_name;
145 /* Define the information needed to generate branch insns. This is
146 stored from the compare operation. */
147 extern GTY(()) rtx arm_compare_op0;
148 extern GTY(()) rtx arm_compare_op1;
149 /* The label of the current constant pool. */
150 extern rtx pool_vector_label;
151 /* Set to 1 when a return insn is output, this means that the epilogue
152 is not needed. */
153 extern int return_used_this_function;
154 /* Used to produce AOF syntax assembler. */
155 extern GTY(()) rtx aof_pic_label;
156 \f
157 /* Just in case configure has failed to define anything. */
158 #ifndef TARGET_CPU_DEFAULT
159 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
160 #endif
161
162 /* If the configuration file doesn't specify the cpu, the subtarget may
163 override it. If it doesn't, then default to an ARM6. */
164 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
165 #undef TARGET_CPU_DEFAULT
166
167 #ifdef SUBTARGET_CPU_DEFAULT
168 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
169 #else
170 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
171 #endif
172 #endif
173
174 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
175 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
176 #else
177 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
178 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
179 #else
180 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
181 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
182 #else
183 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
184 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
185 #else
186 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
187 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
188 #else
189 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
190 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
191 #else
192 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
193 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__"
194 /* Set TARGET_DEFAULT to the default, but without soft-float. */
195 #ifdef TARGET_DEFAULT
196 #undef TARGET_DEFAULT
197 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
198 #endif
199 #else
200 #if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
201 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__"
202 #else
203 #if (TARGET_CPU_DEFAULT == TARGET_CPU_arm926ejs || \
204 TARGET_CPU_DEFAULT == TARGET_CPU_arm1026ejs)
205 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TEJ__"
206 #else
207 #if (TARGET_CPU_DEFAULT == TARGET_CPU_arm1136js || \
208 TARGET_CPU_DEFAULT == TARGET_CPU_arm1136jfs)
209 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_6J__"
210 #else
211 #error Unrecognized value in TARGET_CPU_DEFAULT.
212 #endif
213 #endif
214 #endif
215 #endif
216 #endif
217 #endif
218 #endif
219 #endif
220 #endif
221 #endif
222
223 #undef CPP_SPEC
224 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
225 %{mapcs-32:%{mapcs-26: \
226 %e-mapcs-26 and -mapcs-32 may not be used together}} \
227 %{msoft-float:%{mhard-float: \
228 %e-msoft-float and -mhard_float may not be used together}} \
229 %{mbig-endian:%{mlittle-endian: \
230 %e-mbig-endian and -mlittle-endian may not be used together}}"
231
232 /* Set the architecture define -- if -march= is set, then it overrides
233 the -mcpu= setting. */
234 #define CPP_CPU_ARCH_SPEC "\
235 %{march=arm2:-D__ARM_ARCH_2__} \
236 %{march=arm250:-D__ARM_ARCH_2__} \
237 %{march=arm3:-D__ARM_ARCH_2__} \
238 %{march=arm6:-D__ARM_ARCH_3__} \
239 %{march=arm600:-D__ARM_ARCH_3__} \
240 %{march=arm610:-D__ARM_ARCH_3__} \
241 %{march=arm7:-D__ARM_ARCH_3__} \
242 %{march=arm700:-D__ARM_ARCH_3__} \
243 %{march=arm710:-D__ARM_ARCH_3__} \
244 %{march=arm720:-D__ARM_ARCH_3__} \
245 %{march=arm7100:-D__ARM_ARCH_3__} \
246 %{march=arm7500:-D__ARM_ARCH_3__} \
247 %{march=arm7500fe:-D__ARM_ARCH_3__} \
248 %{march=arm7m:-D__ARM_ARCH_3M__} \
249 %{march=arm7dm:-D__ARM_ARCH_3M__} \
250 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
251 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
252 %{march=arm8:-D__ARM_ARCH_4__} \
253 %{march=arm810:-D__ARM_ARCH_4__} \
254 %{march=arm9:-D__ARM_ARCH_4T__} \
255 %{march=arm920:-D__ARM_ARCH_4__} \
256 %{march=arm920t:-D__ARM_ARCH_4T__} \
257 %{march=arm926ejs:-D__ARM_ARCH_5TEJ__} \
258 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
259 %{march=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
260 %{march=arm1136js:-D__ARM_ARCH_6J__} \
261 %{march=arm1136jfs:-D__ARM_ARCH_6J__} \
262 %{march=strongarm:-D__ARM_ARCH_4__} \
263 %{march=strongarm110:-D__ARM_ARCH_4__} \
264 %{march=strongarm1100:-D__ARM_ARCH_4__} \
265 %{march=xscale:-D__ARM_ARCH_5TE__} \
266 %{march=xscale:-D__XSCALE__} \
267 %{march=ep9312:-D__ARM_ARCH_4T__} \
268 %{march=ep9312:-D__MAVERICK__} \
269 %{march=armv2:-D__ARM_ARCH_2__} \
270 %{march=armv2a:-D__ARM_ARCH_2__} \
271 %{march=armv3:-D__ARM_ARCH_3__} \
272 %{march=armv3m:-D__ARM_ARCH_3M__} \
273 %{march=armv4:-D__ARM_ARCH_4__} \
274 %{march=armv4t:-D__ARM_ARCH_4T__} \
275 %{march=armv5:-D__ARM_ARCH_5__} \
276 %{march=armv5t:-D__ARM_ARCH_5T__} \
277 %{march=armv5e:-D__ARM_ARCH_5E__} \
278 %{march=armv5te:-D__ARM_ARCH_5TE__} \
279 %{march=armv6:-D__ARM_ARCH6__} \
280 %{march=armv6j:-D__ARM_ARCH6J__} \
281 %{!march=*: \
282 %{mcpu=arm2:-D__ARM_ARCH_2__} \
283 %{mcpu=arm250:-D__ARM_ARCH_2__} \
284 %{mcpu=arm3:-D__ARM_ARCH_2__} \
285 %{mcpu=arm6:-D__ARM_ARCH_3__} \
286 %{mcpu=arm600:-D__ARM_ARCH_3__} \
287 %{mcpu=arm610:-D__ARM_ARCH_3__} \
288 %{mcpu=arm7:-D__ARM_ARCH_3__} \
289 %{mcpu=arm700:-D__ARM_ARCH_3__} \
290 %{mcpu=arm710:-D__ARM_ARCH_3__} \
291 %{mcpu=arm720:-D__ARM_ARCH_3__} \
292 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
293 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
294 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
295 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
296 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
297 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
298 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
299 %{mcpu=arm8:-D__ARM_ARCH_4__} \
300 %{mcpu=arm810:-D__ARM_ARCH_4__} \
301 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
302 %{mcpu=arm920:-D__ARM_ARCH_4__} \
303 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
304 %{mcpu=arm926ejs:-D__ARM_ARCH_5TEJ__} \
305 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
306 %{mcpu=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
307 %{mcpu=arm1136js:-D__ARM_ARCH_6J__} \
308 %{mcpu=arm1136jfs:-D__ARM_ARCH_6J__} \
309 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
310 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
311 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
312 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
313 %{mcpu=xscale:-D__XSCALE__} \
314 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
315 %{mcpu=ep9312:-D__MAVERICK__} \
316 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
317 %{mcpu=iwmmxt:-D__XSCALE__} \
318 %{mcpu=iwmmxt:-D__IWMMXT__} \
319 %{!mcpu*:%(cpp_cpu_arch_default)}} \
320 "
321
322 #ifndef CC1_SPEC
323 #define CC1_SPEC ""
324 #endif
325
326 /* This macro defines names of additional specifications to put in the specs
327 that can be used in various specifications like CC1_SPEC. Its definition
328 is an initializer with a subgrouping for each command option.
329
330 Each subgrouping contains a string constant, that defines the
331 specification name, and a string constant that used by the GCC driver
332 program.
333
334 Do not define this macro if it does not need to do anything. */
335 #define EXTRA_SPECS \
336 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
337 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
338 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
339 SUBTARGET_EXTRA_SPECS
340
341 #ifndef SUBTARGET_EXTRA_SPECS
342 #define SUBTARGET_EXTRA_SPECS
343 #endif
344
345 #ifndef SUBTARGET_CPP_SPEC
346 #define SUBTARGET_CPP_SPEC ""
347 #endif
348 \f
349 /* Run-time Target Specification. */
350 #ifndef TARGET_VERSION
351 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
352 #endif
353
354 /* Nonzero if the function prologue (and epilogue) should obey
355 the ARM Procedure Call Standard. */
356 #define ARM_FLAG_APCS_FRAME (1 << 0)
357
358 /* Nonzero if the function prologue should output the function name to enable
359 the post mortem debugger to print a backtrace (very useful on RISCOS,
360 unused on RISCiX). Specifying this flag also enables
361 -fno-omit-frame-pointer.
362 XXX Must still be implemented in the prologue. */
363 #define ARM_FLAG_POKE (1 << 1)
364
365 /* Nonzero if floating point instructions are emulated by the FPE, in which
366 case instruction scheduling becomes very uninteresting. */
367 #define ARM_FLAG_FPE (1 << 2)
368
369 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
370 that assume restoration of the condition flags when returning from a
371 branch and link (ie a function). */
372 #define ARM_FLAG_APCS_32 (1 << 3)
373
374 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
375
376 /* Nonzero if stack checking should be performed on entry to each function
377 which allocates temporary variables on the stack. */
378 #define ARM_FLAG_APCS_STACK (1 << 4)
379
380 /* Nonzero if floating point parameters should be passed to functions in
381 floating point registers. */
382 #define ARM_FLAG_APCS_FLOAT (1 << 5)
383
384 /* Nonzero if re-entrant, position independent code should be generated.
385 This is equivalent to -fpic. */
386 #define ARM_FLAG_APCS_REENT (1 << 6)
387
388 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
389 be loaded using either LDRH or LDRB instructions. */
390 #define ARM_FLAG_MMU_TRAPS (1 << 7)
391
392 /* Nonzero if all floating point instructions are missing (and there is no
393 emulator either). Generate function calls for all ops in this case. */
394 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
395
396 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
397 #define ARM_FLAG_BIG_END (1 << 9)
398
399 /* Nonzero if we should compile for Thumb interworking. */
400 #define ARM_FLAG_INTERWORK (1 << 10)
401
402 /* Nonzero if we should have little-endian words even when compiling for
403 big-endian (for backwards compatibility with older versions of GCC). */
404 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
405
406 /* Nonzero if we need to protect the prolog from scheduling */
407 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
408
409 /* Nonzero if a call to abort should be generated if a noreturn
410 function tries to return. */
411 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
412
413 /* Nonzero if function prologues should not load the PIC register. */
414 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
415
416 /* Nonzero if all call instructions should be indirect. */
417 #define ARM_FLAG_LONG_CALLS (1 << 15)
418
419 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
420 #define ARM_FLAG_THUMB (1 << 16)
421
422 /* Set if a TPCS style stack frame should be generated, for non-leaf
423 functions, even if they do not need one. */
424 #define THUMB_FLAG_BACKTRACE (1 << 17)
425
426 /* Set if a TPCS style stack frame should be generated, for leaf
427 functions, even if they do not need one. */
428 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
429
430 /* Set if externally visible functions should assume that they
431 might be called in ARM mode, from a non-thumb aware code. */
432 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
433
434 /* Set if calls via function pointers should assume that their
435 destination is non-Thumb aware. */
436 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
437
438 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
439 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
440
441 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
442 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
443 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
444 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
445 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
446 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
447 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
448 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
449 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
450 #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
451 #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
452 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
453 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
454 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
455 #define TARGET_IWMMXT (arm_arch_iwmmxt)
456 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
457 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
458 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
459 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
460 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
461 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
462 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
463 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
464 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
465 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
466 #define TARGET_ARM (! TARGET_THUMB)
467 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
468 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
469 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
470 #define TARGET_BACKTRACE (leaf_function_p () \
471 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
472 : (target_flags & THUMB_FLAG_BACKTRACE))
473 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
474
475 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
476 #ifndef SUBTARGET_SWITCHES
477 #define SUBTARGET_SWITCHES
478 #endif
479
480 #define TARGET_SWITCHES \
481 { \
482 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
483 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
484 N_("Generate APCS conformant stack frames") }, \
485 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
486 {"poke-function-name", ARM_FLAG_POKE, \
487 N_("Store function names in object code") }, \
488 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
489 {"fpe", ARM_FLAG_FPE, "" }, \
490 {"apcs-32", ARM_FLAG_APCS_32, \
491 N_("Use the 32-bit version of the APCS") }, \
492 {"apcs-26", -ARM_FLAG_APCS_32, \
493 N_("Use the 26-bit version of the APCS") }, \
494 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
495 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
496 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
497 N_("Pass FP arguments in FP registers") }, \
498 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
499 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
500 N_("Generate re-entrant, PIC code") }, \
501 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
502 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
503 N_("The MMU will trap on unaligned accesses") }, \
504 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
505 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
506 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
507 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
508 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
509 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
510 N_("Use library calls to perform FP operations") }, \
511 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
512 N_("Use hardware floating point instructions") }, \
513 {"big-endian", ARM_FLAG_BIG_END, \
514 N_("Assume target CPU is configured as big endian") }, \
515 {"little-endian", -ARM_FLAG_BIG_END, \
516 N_("Assume target CPU is configured as little endian") }, \
517 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
518 N_("Assume big endian bytes, little endian words") }, \
519 {"thumb-interwork", ARM_FLAG_INTERWORK, \
520 N_("Support calls between Thumb and ARM instruction sets") }, \
521 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
522 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
523 N_("Generate a call to abort if a noreturn function returns")}, \
524 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
525 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
526 N_("Do not move instructions into a function's prologue") }, \
527 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
528 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
529 N_("Do not load the PIC register in function prologues") }, \
530 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
531 {"long-calls", ARM_FLAG_LONG_CALLS, \
532 N_("Generate call insns as indirect calls, if necessary") }, \
533 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
534 {"thumb", ARM_FLAG_THUMB, \
535 N_("Compile for the Thumb not the ARM") }, \
536 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
537 {"arm", -ARM_FLAG_THUMB, "" }, \
538 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
539 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
540 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
541 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
542 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
543 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
544 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
545 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
546 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
547 "" }, \
548 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
549 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
550 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
551 "" }, \
552 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
553 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
554 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
555 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
556 SUBTARGET_SWITCHES \
557 {"", TARGET_DEFAULT, "" } \
558 }
559
560 #define TARGET_OPTIONS \
561 { \
562 {"cpu=", & arm_select[0].string, \
563 N_("Specify the name of the target CPU"), 0}, \
564 {"arch=", & arm_select[1].string, \
565 N_("Specify the name of the target architecture"), 0}, \
566 {"tune=", & arm_select[2].string, "", 0}, \
567 {"fpe=", & target_fpe_name, "", 0}, \
568 {"fp=", & target_fpe_name, "", 0}, \
569 {"fpu=", & target_fpu_name, \
570 N_("Specify the name of the target floating point hardware/format"), 0}, \
571 {"float-abi=", & target_float_abi_name, \
572 N_("Specify if floating point hardware should be used"), 0}, \
573 {"structure-size-boundary=", & structure_size_string, \
574 N_("Specify the minimum bit alignment of structures"), 0}, \
575 {"pic-register=", & arm_pic_register_string, \
576 N_("Specify the register to be used for PIC addressing"), 0}, \
577 {"abi=", &target_abi_name, N_("Specify an ABI"), 0} \
578 }
579
580 /* Support for a compile-time default CPU, et cetera. The rules are:
581 --with-arch is ignored if -march or -mcpu are specified.
582 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
583 by --with-arch.
584 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
585 by -march).
586 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
587 specified.
588 --with-fpu is ignored if -mfpu is specified.
589 --with-abi is ignored is -mabi is specified. */
590 #define OPTION_DEFAULT_SPECS \
591 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
592 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
593 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
594 {"float", \
595 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
596 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
597 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
598
599 struct arm_cpu_select
600 {
601 const char * string;
602 const char * name;
603 const struct processors * processors;
604 };
605
606 /* This is a magic array. If the user specifies a command line switch
607 which matches one of the entries in TARGET_OPTIONS then the corresponding
608 string pointer will be set to the value specified by the user. */
609 extern struct arm_cpu_select arm_select[];
610
611 enum prog_mode_type
612 {
613 prog_mode26,
614 prog_mode32
615 };
616
617 /* Recast the program mode class to be the prog_mode attribute. */
618 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
619
620 extern enum prog_mode_type arm_prgmode;
621
622 /* Which floating point model to use. */
623 enum arm_fp_model
624 {
625 ARM_FP_MODEL_UNKNOWN,
626 /* FPA model (Hardware or software). */
627 ARM_FP_MODEL_FPA,
628 /* Cirrus Maverick floating point model. */
629 ARM_FP_MODEL_MAVERICK,
630 /* VFP floating point model. */
631 ARM_FP_MODEL_VFP
632 };
633
634 extern enum arm_fp_model arm_fp_model;
635
636 /* Which floating point hardware is available. Also update
637 fp_model_for_fpu in arm.c when adding entries to this list. */
638 enum fputype
639 {
640 /* No FP hardware. */
641 FPUTYPE_NONE,
642 /* Full FPA support. */
643 FPUTYPE_FPA,
644 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
645 FPUTYPE_FPA_EMU2,
646 /* Emulated FPA hardware, Issue 3 emulator. */
647 FPUTYPE_FPA_EMU3,
648 /* Cirrus Maverick floating point co-processor. */
649 FPUTYPE_MAVERICK,
650 /* VFP. */
651 FPUTYPE_VFP
652 };
653
654 /* Recast the floating point class to be the floating point attribute. */
655 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
656
657 /* What type of floating point to tune for */
658 extern enum fputype arm_fpu_tune;
659
660 /* What type of floating point instructions are available */
661 extern enum fputype arm_fpu_arch;
662
663 enum float_abi_type
664 {
665 ARM_FLOAT_ABI_SOFT,
666 ARM_FLOAT_ABI_SOFTFP,
667 ARM_FLOAT_ABI_HARD
668 };
669
670 extern enum float_abi_type arm_float_abi;
671
672 /* Default floating point architecture. Override in sub-target if
673 necessary.
674 FIXME: Is this still necessary/desirable? Do we want VFP chips to
675 default to VFP unless overridden by a subtarget? If so it would be best
676 to remove these definitions. It also assumes there is only one cpu model
677 with a Maverick fpu. */
678 #ifndef FPUTYPE_DEFAULT
679 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
680 #endif
681
682 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
683 #undef FPUTYPE_DEFAULT
684 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
685 #endif
686
687 /* Which ABI to use. */
688 enum arm_abi_type
689 {
690 ARM_ABI_APCS,
691 ARM_ABI_ATPCS,
692 ARM_ABI_AAPCS,
693 ARM_ABI_IWMMXT
694 };
695
696 extern enum arm_abi_type arm_abi;
697
698 #ifndef ARM_DEFAULT_ABI
699 #define ARM_DEFAULT_ABI ARM_ABI_APCS
700 #endif
701
702 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
703 extern int arm_arch3m;
704
705 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
706 extern int arm_arch4;
707
708 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
709 extern int arm_arch5;
710
711 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
712 extern int arm_arch5e;
713
714 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
715 extern int arm_arch6;
716
717 /* Nonzero if this chip can benefit from load scheduling. */
718 extern int arm_ld_sched;
719
720 /* Nonzero if generating thumb code. */
721 extern int thumb_code;
722
723 /* Nonzero if this chip is a StrongARM. */
724 extern int arm_is_strong;
725
726 /* Nonzero if this chip is a Cirrus variant. */
727 extern int arm_is_cirrus;
728
729 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
730 extern int arm_arch_iwmmxt;
731
732 /* Nonzero if this chip is an XScale. */
733 extern int arm_arch_xscale;
734
735 /* Nonzero if tuning for XScale */
736 extern int arm_tune_xscale;
737
738 /* Nonzero if this chip is an ARM6 or an ARM7. */
739 extern int arm_is_6_or_7;
740
741 #ifndef TARGET_DEFAULT
742 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
743 #endif
744
745 /* The frame pointer register used in gcc has nothing to do with debugging;
746 that is controlled by the APCS-FRAME option. */
747 #define CAN_DEBUG_WITHOUT_FP
748
749 #undef TARGET_MEM_FUNCTIONS
750 #define TARGET_MEM_FUNCTIONS 1
751
752 #define OVERRIDE_OPTIONS arm_override_options ()
753
754 /* Nonzero if PIC code requires explicit qualifiers to generate
755 PLT and GOT relocs rather than the assembler doing so implicitly.
756 Subtargets can override these if required. */
757 #ifndef NEED_GOT_RELOC
758 #define NEED_GOT_RELOC 0
759 #endif
760 #ifndef NEED_PLT_RELOC
761 #define NEED_PLT_RELOC 0
762 #endif
763
764 /* Nonzero if we need to refer to the GOT with a PC-relative
765 offset. In other words, generate
766
767 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
768
769 rather than
770
771 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
772
773 The default is true, which matches NetBSD. Subtargets can
774 override this if required. */
775 #ifndef GOT_PCREL
776 #define GOT_PCREL 1
777 #endif
778 \f
779 /* Target machine storage Layout. */
780
781
782 /* Define this macro if it is advisable to hold scalars in registers
783 in a wider mode than that declared by the program. In such cases,
784 the value is constrained to be within the bounds of the declared
785 type, but kept valid in the wider mode. The signedness of the
786 extension may differ from that of the type. */
787
788 /* It is far faster to zero extend chars than to sign extend them */
789
790 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
791 if (GET_MODE_CLASS (MODE) == MODE_INT \
792 && GET_MODE_SIZE (MODE) < 4) \
793 { \
794 if (MODE == QImode) \
795 UNSIGNEDP = 1; \
796 else if (MODE == HImode) \
797 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
798 (MODE) = SImode; \
799 }
800
801 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
802 if (GET_MODE_CLASS (MODE) == MODE_INT \
803 && GET_MODE_SIZE (MODE) < 4) \
804 (MODE) = SImode; \
805
806 /* Define this if most significant bit is lowest numbered
807 in instructions that operate on numbered bit-fields. */
808 #define BITS_BIG_ENDIAN 0
809
810 /* Define this if most significant byte of a word is the lowest numbered.
811 Most ARM processors are run in little endian mode, so that is the default.
812 If you want to have it run-time selectable, change the definition in a
813 cover file to be TARGET_BIG_ENDIAN. */
814 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
815
816 /* Define this if most significant word of a multiword number is the lowest
817 numbered.
818 This is always false, even when in big-endian mode. */
819 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
820
821 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
822 on processor pre-defineds when compiling libgcc2.c. */
823 #if defined(__ARMEB__) && !defined(__ARMWEL__)
824 #define LIBGCC2_WORDS_BIG_ENDIAN 1
825 #else
826 #define LIBGCC2_WORDS_BIG_ENDIAN 0
827 #endif
828
829 /* Define this if most significant word of doubles is the lowest numbered.
830 The rules are different based on whether or not we use FPA-format,
831 VFP-format or some other floating point co-processor's format doubles. */
832 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
833
834 #define UNITS_PER_WORD 4
835
836 /* True if natural alignment is used for doubleword types. */
837 #define ARM_DOUBLEWORD_ALIGN \
838 (arm_abi == ARM_ABI_AAPCS || arm_abi == ARM_ABI_IWMMXT)
839 #define DOUBLEWORD_ALIGNMENT 64
840
841 #define PARM_BOUNDARY 32
842
843 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
844
845 #define PREFERRED_STACK_BOUNDARY \
846 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
847
848 #define FUNCTION_BOUNDARY 32
849
850 /* The lowest bit is used to indicate Thumb-mode functions, so the
851 vbit must go into the delta field of pointers to member
852 functions. */
853 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
854
855 #define EMPTY_FIELD_BOUNDARY 32
856
857 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
858
859 /* XXX Blah -- this macro is used directly by libobjc. Since it
860 supports no vector modes, cut out the complexity and fall back
861 on BIGGEST_FIELD_ALIGNMENT. */
862 #ifdef IN_TARGET_LIBS
863 #define BIGGEST_FIELD_ALIGNMENT 64
864 #endif
865
866 /* Make strings word-aligned so strcpy from constants will be faster. */
867 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
868
869 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
870 ((TREE_CODE (EXP) == STRING_CST \
871 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
872 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
873
874 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
875 value set in previous versions of this toolchain was 8, which produces more
876 compact structures. The command line option -mstructure_size_boundary=<n>
877 can be used to change this value. For compatibility with the ARM SDK
878 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
879 0020D) page 2-20 says "Structures are aligned on word boundaries".
880 The AAPCS specifies a value of 8. */
881 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
882 extern int arm_structure_size_boundary;
883
884 /* This is the value used to initialize arm_structure_size_boundary. If a
885 particular arm target wants to change the default value it should change
886 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
887 for an example of this. */
888 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
889 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
890 #endif
891
892 /* Used when parsing command line option -mstructure_size_boundary. */
893 extern const char * structure_size_string;
894
895 /* Nonzero if move instructions will actually fail to work
896 when given unaligned data. */
897 #define STRICT_ALIGNMENT 1
898 \f
899 /* Standard register usage. */
900
901 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
902 (S - saved over call).
903
904 r0 * argument word/integer result
905 r1-r3 argument word
906
907 r4-r8 S register variable
908 r9 S (rfp) register variable (real frame pointer)
909
910 r10 F S (sl) stack limit (used by -mapcs-stack-check)
911 r11 F S (fp) argument pointer
912 r12 (ip) temp workspace
913 r13 F S (sp) lower end of current stack frame
914 r14 (lr) link address/workspace
915 r15 F (pc) program counter
916
917 f0 floating point result
918 f1-f3 floating point scratch
919
920 f4-f7 S floating point variable
921
922 cc This is NOT a real register, but is used internally
923 to represent things that use or set the condition
924 codes.
925 sfp This isn't either. It is used during rtl generation
926 since the offset between the frame pointer and the
927 auto's isn't known until after register allocation.
928 afp Nor this, we only need this because of non-local
929 goto. Without it fp appears to be used and the
930 elimination code won't get rid of sfp. It tracks
931 fp exactly at all times.
932
933 *: See CONDITIONAL_REGISTER_USAGE */
934
935 /*
936 mvf0 Cirrus floating point result
937 mvf1-mvf3 Cirrus floating point scratch
938 mvf4-mvf15 S Cirrus floating point variable. */
939
940 /* s0-s15 VFP scratch (aka d0-d7).
941 s16-s31 S VFP variable (aka d8-d15).
942 vfpcc Not a real register. Represents the VFP condition
943 code flags. */
944
945 /* The stack backtrace structure is as follows:
946 fp points to here: | save code pointer | [fp]
947 | return link value | [fp, #-4]
948 | return sp value | [fp, #-8]
949 | return fp value | [fp, #-12]
950 [| saved r10 value |]
951 [| saved r9 value |]
952 [| saved r8 value |]
953 [| saved r7 value |]
954 [| saved r6 value |]
955 [| saved r5 value |]
956 [| saved r4 value |]
957 [| saved r3 value |]
958 [| saved r2 value |]
959 [| saved r1 value |]
960 [| saved r0 value |]
961 [| saved f7 value |] three words
962 [| saved f6 value |] three words
963 [| saved f5 value |] three words
964 [| saved f4 value |] three words
965 r0-r3 are not normally saved in a C function. */
966
967 /* 1 for registers that have pervasive standard uses
968 and are not available for the register allocator. */
969 #define FIXED_REGISTERS \
970 { \
971 0,0,0,0,0,0,0,0, \
972 0,0,0,0,0,1,0,1, \
973 0,0,0,0,0,0,0,0, \
974 1,1,1, \
975 1,1,1,1,1,1,1,1, \
976 1,1,1,1,1,1,1,1, \
977 1,1,1,1,1,1,1,1, \
978 1,1,1,1,1,1,1,1, \
979 1,1,1,1, \
980 1,1,1,1,1,1,1,1, \
981 1,1,1,1,1,1,1,1, \
982 1,1,1,1,1,1,1,1, \
983 1,1,1,1,1,1,1,1, \
984 1 \
985 }
986
987 /* 1 for registers not available across function calls.
988 These must include the FIXED_REGISTERS and also any
989 registers that can be used without being saved.
990 The latter must include the registers where values are returned
991 and the register where structure-value addresses are passed.
992 Aside from that, you can include as many other registers as you like.
993 The CC is not preserved over function calls on the ARM 6, so it is
994 easier to assume this for all. SFP is preserved, since FP is. */
995 #define CALL_USED_REGISTERS \
996 { \
997 1,1,1,1,0,0,0,0, \
998 0,0,0,0,1,1,1,1, \
999 1,1,1,1,0,0,0,0, \
1000 1,1,1, \
1001 1,1,1,1,1,1,1,1, \
1002 1,1,1,1,1,1,1,1, \
1003 1,1,1,1,1,1,1,1, \
1004 1,1,1,1,1,1,1,1, \
1005 1,1,1,1, \
1006 1,1,1,1,1,1,1,1, \
1007 1,1,1,1,1,1,1,1, \
1008 1,1,1,1,1,1,1,1, \
1009 1,1,1,1,1,1,1,1, \
1010 1 \
1011 }
1012
1013 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
1014 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
1015 #endif
1016
1017 #define CONDITIONAL_REGISTER_USAGE \
1018 { \
1019 int regno; \
1020 \
1021 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
1022 { \
1023 for (regno = FIRST_FPA_REGNUM; \
1024 regno <= LAST_FPA_REGNUM; ++regno) \
1025 fixed_regs[regno] = call_used_regs[regno] = 1; \
1026 } \
1027 \
1028 if (TARGET_THUMB && optimize_size) \
1029 { \
1030 /* When optimizing for size, it's better not to use \
1031 the HI regs, because of the overhead of stacking \
1032 them. */ \
1033 for (regno = FIRST_HI_REGNUM; \
1034 regno <= LAST_HI_REGNUM; ++regno) \
1035 fixed_regs[regno] = call_used_regs[regno] = 1; \
1036 } \
1037 \
1038 /* The link register can be clobbered by any branch insn, \
1039 but we have no way to track that at present, so mark \
1040 it as unavailable. */ \
1041 if (TARGET_THUMB) \
1042 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
1043 \
1044 if (TARGET_ARM && TARGET_HARD_FLOAT) \
1045 { \
1046 if (TARGET_MAVERICK) \
1047 { \
1048 for (regno = FIRST_FPA_REGNUM; \
1049 regno <= LAST_FPA_REGNUM; ++ regno) \
1050 fixed_regs[regno] = call_used_regs[regno] = 1; \
1051 for (regno = FIRST_CIRRUS_FP_REGNUM; \
1052 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
1053 { \
1054 fixed_regs[regno] = 0; \
1055 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
1056 } \
1057 } \
1058 if (TARGET_VFP) \
1059 { \
1060 for (regno = FIRST_VFP_REGNUM; \
1061 regno <= LAST_VFP_REGNUM; ++ regno) \
1062 { \
1063 fixed_regs[regno] = 0; \
1064 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
1065 } \
1066 } \
1067 } \
1068 \
1069 if (TARGET_REALLY_IWMMXT) \
1070 { \
1071 regno = FIRST_IWMMXT_GR_REGNUM; \
1072 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
1073 and wCG1 as call-preserved registers. The 2002/11/21 \
1074 revision changed this so that all wCG registers are \
1075 scratch registers. */ \
1076 for (regno = FIRST_IWMMXT_GR_REGNUM; \
1077 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
1078 fixed_regs[regno] = call_used_regs[regno] = 0; \
1079 /* The XScale ABI has wR0 - wR9 as scratch registers, \
1080 the rest as call-preserved registers. */ \
1081 for (regno = FIRST_IWMMXT_REGNUM; \
1082 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
1083 { \
1084 fixed_regs[regno] = 0; \
1085 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
1086 } \
1087 } \
1088 \
1089 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1090 { \
1091 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1092 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1093 } \
1094 else if (TARGET_APCS_STACK) \
1095 { \
1096 fixed_regs[10] = 1; \
1097 call_used_regs[10] = 1; \
1098 } \
1099 if (TARGET_APCS_FRAME) \
1100 { \
1101 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1102 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1103 } \
1104 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
1105 }
1106
1107 /* These are a couple of extensions to the formats accepted
1108 by asm_fprintf:
1109 %@ prints out ASM_COMMENT_START
1110 %r prints out REGISTER_PREFIX reg_names[arg] */
1111 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
1112 case '@': \
1113 fputs (ASM_COMMENT_START, FILE); \
1114 break; \
1115 \
1116 case 'r': \
1117 fputs (REGISTER_PREFIX, FILE); \
1118 fputs (reg_names [va_arg (ARGS, int)], FILE); \
1119 break;
1120
1121 /* Round X up to the nearest word. */
1122 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
1123
1124 /* Convert fron bytes to ints. */
1125 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1126
1127 /* The number of (integer) registers required to hold a quantity of type MODE.
1128 Also used for VFP registers. */
1129 #define ARM_NUM_REGS(MODE) \
1130 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
1131
1132 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
1133 #define ARM_NUM_REGS2(MODE, TYPE) \
1134 ARM_NUM_INTS ((MODE) == BLKmode ? \
1135 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1136
1137 /* The number of (integer) argument register available. */
1138 #define NUM_ARG_REGS 4
1139
1140 /* Return the register number of the N'th (integer) argument. */
1141 #define ARG_REGISTER(N) (N - 1)
1142
1143 /* Specify the registers used for certain standard purposes.
1144 The values of these macros are register numbers. */
1145
1146 /* The number of the last argument register. */
1147 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
1148
1149 /* The numbers of the Thumb register ranges. */
1150 #define FIRST_LO_REGNUM 0
1151 #define LAST_LO_REGNUM 7
1152 #define FIRST_HI_REGNUM 8
1153 #define LAST_HI_REGNUM 11
1154
1155 /* The register that holds the return address in exception handlers. */
1156 #define EXCEPTION_LR_REGNUM 2
1157
1158 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1159 as an invisible last argument (possible since varargs don't exist in
1160 Pascal), so the following is not true. */
1161 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1162
1163 /* Define this to be where the real frame pointer is if it is not possible to
1164 work out the offset between the frame pointer and the automatic variables
1165 until after register allocation has taken place. FRAME_POINTER_REGNUM
1166 should point to a special register that we will make sure is eliminated.
1167
1168 For the Thumb we have another problem. The TPCS defines the frame pointer
1169 as r11, and GCC believes that it is always possible to use the frame pointer
1170 as base register for addressing purposes. (See comments in
1171 find_reloads_address()). But - the Thumb does not allow high registers,
1172 including r11, to be used as base address registers. Hence our problem.
1173
1174 The solution used here, and in the old thumb port is to use r7 instead of
1175 r11 as the hard frame pointer and to have special code to generate
1176 backtrace structures on the stack (if required to do so via a command line
1177 option) using r11. This is the only 'user visible' use of r11 as a frame
1178 pointer. */
1179 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1180 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1181
1182 #define HARD_FRAME_POINTER_REGNUM \
1183 (TARGET_ARM \
1184 ? ARM_HARD_FRAME_POINTER_REGNUM \
1185 : THUMB_HARD_FRAME_POINTER_REGNUM)
1186
1187 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1188
1189 /* Register to use for pushing function arguments. */
1190 #define STACK_POINTER_REGNUM SP_REGNUM
1191
1192 /* ARM floating pointer registers. */
1193 #define FIRST_FPA_REGNUM 16
1194 #define LAST_FPA_REGNUM 23
1195
1196 #define FIRST_IWMMXT_GR_REGNUM 43
1197 #define LAST_IWMMXT_GR_REGNUM 46
1198 #define FIRST_IWMMXT_REGNUM 47
1199 #define LAST_IWMMXT_REGNUM 62
1200 #define IS_IWMMXT_REGNUM(REGNUM) \
1201 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1202 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1203 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1204
1205 /* Base register for access to local variables of the function. */
1206 #define FRAME_POINTER_REGNUM 25
1207
1208 /* Base register for access to arguments of the function. */
1209 #define ARG_POINTER_REGNUM 26
1210
1211 #define FIRST_CIRRUS_FP_REGNUM 27
1212 #define LAST_CIRRUS_FP_REGNUM 42
1213 #define IS_CIRRUS_REGNUM(REGNUM) \
1214 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1215
1216 #define FIRST_VFP_REGNUM 63
1217 #define LAST_VFP_REGNUM 94
1218 #define IS_VFP_REGNUM(REGNUM) \
1219 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1220
1221 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1222 /* + 16 Cirrus registers take us up to 43. */
1223 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1224 /* VFP adds 32 + 1 more. */
1225 #define FIRST_PSEUDO_REGISTER 96
1226
1227 /* Value should be nonzero if functions must have frame pointers.
1228 Zero means the frame pointer need not be set up (and parms may be accessed
1229 via the stack pointer) in functions that seem suitable.
1230 If we have to have a frame pointer we might as well make use of it.
1231 APCS says that the frame pointer does not need to be pushed in leaf
1232 functions, or simple tail call functions. */
1233 #define FRAME_POINTER_REQUIRED \
1234 (current_function_has_nonlocal_label \
1235 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1236
1237 /* Return number of consecutive hard regs needed starting at reg REGNO
1238 to hold something of mode MODE.
1239 This is ordinarily the length in words of a value of mode MODE
1240 but can be less for certain modes in special long registers.
1241
1242 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1243 mode. */
1244 #define HARD_REGNO_NREGS(REGNO, MODE) \
1245 ((TARGET_ARM \
1246 && REGNO >= FIRST_FPA_REGNUM \
1247 && REGNO != FRAME_POINTER_REGNUM \
1248 && REGNO != ARG_POINTER_REGNUM) \
1249 && !IS_VFP_REGNUM (REGNO) \
1250 ? 1 : ARM_NUM_REGS (MODE))
1251
1252 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1253 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1254 arm_hard_regno_mode_ok ((REGNO), (MODE))
1255
1256 /* Value is 1 if it is a good idea to tie two pseudo registers
1257 when one has mode MODE1 and one has mode MODE2.
1258 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1259 for any hard reg, then this must be 0 for correct output. */
1260 #define MODES_TIEABLE_P(MODE1, MODE2) \
1261 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1262
1263 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1264 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1265
1266 #define VALID_IWMMXT_REG_MODE(MODE) \
1267 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1268
1269 /* The order in which register should be allocated. It is good to use ip
1270 since no saving is required (though calls clobber it) and it never contains
1271 function parameters. It is quite good to use lr since other calls may
1272 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1273 least likely to contain a function parameter; in addition results are
1274 returned in r0. */
1275
1276 #define REG_ALLOC_ORDER \
1277 { \
1278 3, 2, 1, 0, 12, 14, 4, 5, \
1279 6, 7, 8, 10, 9, 11, 13, 15, \
1280 16, 17, 18, 19, 20, 21, 22, 23, \
1281 27, 28, 29, 30, 31, 32, 33, 34, \
1282 35, 36, 37, 38, 39, 40, 41, 42, \
1283 43, 44, 45, 46, 47, 48, 49, 50, \
1284 51, 52, 53, 54, 55, 56, 57, 58, \
1285 59, 60, 61, 62, \
1286 24, 25, 26, \
1287 78, 77, 76, 75, 74, 73, 72, 71, \
1288 70, 69, 68, 67, 66, 65, 64, 63, \
1289 79, 80, 81, 82, 83, 84, 85, 86, \
1290 87, 88, 89, 90, 91, 92, 93, 94, \
1291 95 \
1292 }
1293
1294 /* Interrupt functions can only use registers that have already been
1295 saved by the prologue, even if they would normally be
1296 call-clobbered. */
1297 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1298 (! IS_INTERRUPT (cfun->machine->func_type) || \
1299 regs_ever_live[DST])
1300 \f
1301 /* Register and constant classes. */
1302
1303 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1304 Now that the Thumb is involved it has become more complicated. */
1305 enum reg_class
1306 {
1307 NO_REGS,
1308 FPA_REGS,
1309 CIRRUS_REGS,
1310 VFP_REGS,
1311 IWMMXT_GR_REGS,
1312 IWMMXT_REGS,
1313 LO_REGS,
1314 STACK_REG,
1315 BASE_REGS,
1316 HI_REGS,
1317 CC_REG,
1318 VFPCC_REG,
1319 GENERAL_REGS,
1320 ALL_REGS,
1321 LIM_REG_CLASSES
1322 };
1323
1324 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1325
1326 /* Give names of register classes as strings for dump file. */
1327 #define REG_CLASS_NAMES \
1328 { \
1329 "NO_REGS", \
1330 "FPA_REGS", \
1331 "CIRRUS_REGS", \
1332 "VFP_REGS", \
1333 "IWMMXT_GR_REGS", \
1334 "IWMMXT_REGS", \
1335 "LO_REGS", \
1336 "STACK_REG", \
1337 "BASE_REGS", \
1338 "HI_REGS", \
1339 "CC_REG", \
1340 "VFPCC_REG", \
1341 "GENERAL_REGS", \
1342 "ALL_REGS", \
1343 }
1344
1345 /* Define which registers fit in which classes.
1346 This is an initializer for a vector of HARD_REG_SET
1347 of length N_REG_CLASSES. */
1348 #define REG_CLASS_CONTENTS \
1349 { \
1350 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1351 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1352 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1353 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1354 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1355 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1356 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1357 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1358 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1359 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1360 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1361 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1362 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1363 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1364 }
1365
1366 /* The same information, inverted:
1367 Return the class number of the smallest class containing
1368 reg number REGNO. This could be a conditional expression
1369 or could index an array. */
1370 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1371
1372 /* FPA registers can't do subreg as all values are reformatted to internal
1373 precision. VFP registers may only be accessed in the mode they
1374 were set. */
1375 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1376 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1377 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1378 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1379 : 0)
1380
1381 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1382 using r0-r4 for function arguments, r7 for the stack frame and don't
1383 have enough left over to do doubleword arithmetic. */
1384 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1385 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1386 || (CLASS) == CC_REG)
1387
1388 /* The class value for index registers, and the one for base regs. */
1389 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1390 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1391
1392 /* For the Thumb the high registers cannot be used as base registers
1393 when addressing quantities in QI or HI mode; if we don't know the
1394 mode, then we must be conservative. After reload we must also be
1395 conservative, since we can't support SP+reg addressing, and we
1396 can't fix up any bad substitutions. */
1397 #define MODE_BASE_REG_CLASS(MODE) \
1398 (TARGET_ARM ? GENERAL_REGS : \
1399 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1400
1401 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1402 registers explicitly used in the rtl to be used as spill registers
1403 but prevents the compiler from extending the lifetime of these
1404 registers. */
1405 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1406
1407 /* Get reg_class from a letter such as appears in the machine description.
1408 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1409 ARM, but several more letters for the Thumb. */
1410 #define REG_CLASS_FROM_LETTER(C) \
1411 ( (C) == 'f' ? FPA_REGS \
1412 : (C) == 'v' ? CIRRUS_REGS \
1413 : (C) == 'w' ? VFP_REGS \
1414 : (C) == 'y' ? IWMMXT_REGS \
1415 : (C) == 'z' ? IWMMXT_GR_REGS \
1416 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1417 : TARGET_ARM ? NO_REGS \
1418 : (C) == 'h' ? HI_REGS \
1419 : (C) == 'b' ? BASE_REGS \
1420 : (C) == 'k' ? STACK_REG \
1421 : (C) == 'c' ? CC_REG \
1422 : NO_REGS)
1423
1424 /* The letters I, J, K, L and M in a register constraint string
1425 can be used to stand for particular ranges of immediate operands.
1426 This macro defines what the ranges are.
1427 C is the letter, and VALUE is a constant value.
1428 Return 1 if VALUE is in the range specified by C.
1429 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1430 J: valid indexing constants.
1431 K: ~value ok in rhs argument of data operand.
1432 L: -value ok in rhs argument of data operand.
1433 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1434 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1435 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1436 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1437 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1438 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1439 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1440 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1441 : 0)
1442
1443 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1444 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1445 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1446 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1447 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1448 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1449 && ((VAL) & 3) == 0) : \
1450 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1451 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1452 : 0)
1453
1454 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1455 (TARGET_ARM ? \
1456 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1457
1458 /* Constant letter 'G' for the FP immediate constants.
1459 'H' means the same constant negated. */
1460 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1461 ((C) == 'G' ? arm_const_double_rtx (X) : \
1462 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1463
1464 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1465 (TARGET_ARM ? \
1466 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1467
1468 /* For the ARM, `Q' means that this is a memory operand that is just
1469 an offset from a register.
1470 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1471 address. This means that the symbol is in the text segment and can be
1472 accessed without using a load.
1473 'U' Prefixes an extended memory constraint where:
1474 'Uv' is an address valid for VFP load/store insns.
1475 'Uq' is an address valid for ldrsb. */
1476
1477 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1478 (((C) == 'Q') ? (GET_CODE (OP) == MEM \
1479 && GET_CODE (XEXP (OP, 0)) == REG) : \
1480 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1481 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1482 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1483 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1484 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1485 ((C) == 'U' && (STR)[1] == 'v') ? vfp_mem_operand (OP) : \
1486 ((C) == 'U' && (STR)[1] == 'q') \
1487 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1488 : 0)
1489
1490 #define CONSTRAINT_LEN(C,STR) \
1491 ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1492
1493 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1494 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1495 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1496
1497 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1498 (TARGET_ARM \
1499 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1500 : EXTRA_CONSTRAINT_THUMB (X, C))
1501
1502 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1503
1504 /* Given an rtx X being reloaded into a reg required to be
1505 in class CLASS, return the class of reg to actually use.
1506 In general this is just CLASS, but for the Thumb we prefer
1507 a LO_REGS class or a subset. */
1508 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1509 (TARGET_ARM ? (CLASS) : \
1510 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1511
1512 /* Must leave BASE_REGS reloads alone */
1513 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1514 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1515 ? ((true_regnum (X) == -1 ? LO_REGS \
1516 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1517 : NO_REGS)) \
1518 : NO_REGS)
1519
1520 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1521 ((CLASS) != LO_REGS \
1522 ? ((true_regnum (X) == -1 ? LO_REGS \
1523 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1524 : NO_REGS)) \
1525 : NO_REGS)
1526
1527 /* Return the register class of a scratch register needed to copy IN into
1528 or out of a register in CLASS in MODE. If it can be done directly,
1529 NO_REGS is returned. */
1530 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1531 /* Restrict which direct reloads are allowed for VFP regs. */ \
1532 ((TARGET_VFP && TARGET_HARD_FLOAT \
1533 && (CLASS) == VFP_REGS) \
1534 ? vfp_secondary_reload_class (MODE, X) \
1535 : TARGET_ARM \
1536 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1537 ? GENERAL_REGS : NO_REGS) \
1538 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1539
1540 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1541 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1542 /* Restrict which direct reloads are allowed for VFP regs. */ \
1543 ((TARGET_VFP && TARGET_HARD_FLOAT \
1544 && (CLASS) == VFP_REGS) \
1545 ? vfp_secondary_reload_class (MODE, X) : \
1546 /* Cannot load constants into Cirrus registers. */ \
1547 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1548 && (CLASS) == CIRRUS_REGS \
1549 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1550 ? GENERAL_REGS : \
1551 (TARGET_ARM ? \
1552 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1553 && CONSTANT_P (X)) \
1554 ? GENERAL_REGS : \
1555 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1556 && (GET_CODE (X) == MEM \
1557 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1558 && true_regnum (X) == -1))) \
1559 ? GENERAL_REGS : NO_REGS) \
1560 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1561
1562 /* Try a machine-dependent way of reloading an illegitimate address
1563 operand. If we find one, push the reload and jump to WIN. This
1564 macro is used in only one place: `find_reloads_address' in reload.c.
1565
1566 For the ARM, we wish to handle large displacements off a base
1567 register by splitting the addend across a MOV and the mem insn.
1568 This can cut the number of reloads needed. */
1569 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1570 do \
1571 { \
1572 if (GET_CODE (X) == PLUS \
1573 && GET_CODE (XEXP (X, 0)) == REG \
1574 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1575 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1576 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1577 { \
1578 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1579 HOST_WIDE_INT low, high; \
1580 \
1581 if (MODE == DImode || (TARGET_SOFT_FLOAT && TARGET_FPA \
1582 && MODE == DFmode)) \
1583 low = ((val & 0xf) ^ 0x8) - 0x8; \
1584 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1585 /* Need to be careful, -256 is not a valid offset. */ \
1586 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1587 else if (MODE == SImode \
1588 || (MODE == SFmode && TARGET_SOFT_FLOAT && TARGET_FPA) \
1589 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1590 /* Need to be careful, -4096 is not a valid offset. */ \
1591 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1592 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1593 /* Need to be careful, -256 is not a valid offset. */ \
1594 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1595 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1596 && TARGET_HARD_FLOAT && TARGET_FPA) \
1597 /* Need to be careful, -1024 is not a valid offset. */ \
1598 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1599 else \
1600 break; \
1601 \
1602 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1603 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1604 - (unsigned HOST_WIDE_INT) 0x80000000); \
1605 /* Check for overflow or zero */ \
1606 if (low == 0 || high == 0 || (high + low != val)) \
1607 break; \
1608 \
1609 /* Reload the high part into a base reg; leave the low part \
1610 in the mem. */ \
1611 X = gen_rtx_PLUS (GET_MODE (X), \
1612 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1613 GEN_INT (high)), \
1614 GEN_INT (low)); \
1615 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1616 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1617 VOIDmode, 0, 0, OPNUM, TYPE); \
1618 goto WIN; \
1619 } \
1620 } \
1621 while (0)
1622
1623 /* XXX If an HImode FP+large_offset address is converted to an HImode
1624 SP+large_offset address, then reload won't know how to fix it. It sees
1625 only that SP isn't valid for HImode, and so reloads the SP into an index
1626 register, but the resulting address is still invalid because the offset
1627 is too big. We fix it here instead by reloading the entire address. */
1628 /* We could probably achieve better results by defining PROMOTE_MODE to help
1629 cope with the variances between the Thumb's signed and unsigned byte and
1630 halfword load instructions. */
1631 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1632 { \
1633 if (GET_CODE (X) == PLUS \
1634 && GET_MODE_SIZE (MODE) < 4 \
1635 && GET_CODE (XEXP (X, 0)) == REG \
1636 && XEXP (X, 0) == stack_pointer_rtx \
1637 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1638 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1639 { \
1640 rtx orig_X = X; \
1641 X = copy_rtx (X); \
1642 push_reload (orig_X, NULL_RTX, &X, NULL, \
1643 MODE_BASE_REG_CLASS (MODE), \
1644 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1645 goto WIN; \
1646 } \
1647 }
1648
1649 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1650 if (TARGET_ARM) \
1651 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1652 else \
1653 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1654
1655 /* Return the maximum number of consecutive registers
1656 needed to represent mode MODE in a register of class CLASS.
1657 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1658 #define CLASS_MAX_NREGS(CLASS, MODE) \
1659 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1660
1661 /* If defined, gives a class of registers that cannot be used as the
1662 operand of a SUBREG that changes the mode of the object illegally. */
1663
1664 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1665 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1666 (TARGET_ARM ? \
1667 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1668 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1669 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1670 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1671 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1672 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1673 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1674 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1675 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1676 2) \
1677 : \
1678 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1679 \f
1680 /* Stack layout; function entry, exit and calling. */
1681
1682 /* Define this if pushing a word on the stack
1683 makes the stack pointer a smaller address. */
1684 #define STACK_GROWS_DOWNWARD 1
1685
1686 /* Define this if the nominal address of the stack frame
1687 is at the high-address end of the local variables;
1688 that is, each additional local variable allocated
1689 goes at a more negative offset in the frame. */
1690 #define FRAME_GROWS_DOWNWARD 1
1691
1692 /* Offset within stack frame to start allocating local variables at.
1693 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1694 first local allocated. Otherwise, it is the offset to the BEGINNING
1695 of the first local allocated. */
1696 #define STARTING_FRAME_OFFSET 0
1697
1698 /* If we generate an insn to push BYTES bytes,
1699 this says how many the stack pointer really advances by. */
1700 /* The push insns do not do this rounding implicitly.
1701 So don't define this. */
1702 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1703
1704 /* Define this if the maximum size of all the outgoing args is to be
1705 accumulated and pushed during the prologue. The amount can be
1706 found in the variable current_function_outgoing_args_size. */
1707 #define ACCUMULATE_OUTGOING_ARGS 1
1708
1709 /* Offset of first parameter from the argument pointer register value. */
1710 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1711
1712 /* Value is the number of byte of arguments automatically
1713 popped when returning from a subroutine call.
1714 FUNDECL is the declaration node of the function (as a tree),
1715 FUNTYPE is the data type of the function (as a tree),
1716 or for a library call it is an identifier node for the subroutine name.
1717 SIZE is the number of bytes of arguments passed on the stack.
1718
1719 On the ARM, the caller does not pop any of its arguments that were passed
1720 on the stack. */
1721 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1722
1723 /* Define how to find the value returned by a library function
1724 assuming the value has mode MODE. */
1725 #define LIBCALL_VALUE(MODE) \
1726 (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
1727 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1728 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1729 : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
1730 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1731 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1732 : TARGET_IWMMXT_ABI && VECTOR_MODE_SUPPORTED_P (MODE) \
1733 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1734 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1735
1736 /* Define how to find the value returned by a function.
1737 VALTYPE is the data type of the value (as a tree).
1738 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1739 otherwise, FUNC is 0. */
1740 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1741 arm_function_value (VALTYPE, FUNC);
1742
1743 /* 1 if N is a possible register number for a function value.
1744 On the ARM, only r0 and f0 can return results. */
1745 /* On a Cirrus chip, mvf0 can return results. */
1746 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1747 ((REGNO) == ARG_REGISTER (1) \
1748 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1749 && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
1750 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1751 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1752 && TARGET_HARD_FLOAT && TARGET_FPA))
1753
1754 /* How large values are returned */
1755 /* A C expression which can inhibit the returning of certain function values
1756 in registers, based on the type of value. */
1757 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1758
1759 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1760 values must be in memory. On the ARM, they need only do so if larger
1761 than a word, or if they contain elements offset from zero in the struct. */
1762 #define DEFAULT_PCC_STRUCT_RETURN 0
1763
1764 /* Flags for the call/call_value rtl operations set up by function_arg. */
1765 #define CALL_NORMAL 0x00000000 /* No special processing. */
1766 #define CALL_LONG 0x00000001 /* Always call indirect. */
1767 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1768
1769 /* These bits describe the different types of function supported
1770 by the ARM backend. They are exclusive. ie a function cannot be both a
1771 normal function and an interworked function, for example. Knowing the
1772 type of a function is important for determining its prologue and
1773 epilogue sequences.
1774 Note value 7 is currently unassigned. Also note that the interrupt
1775 function types all have bit 2 set, so that they can be tested for easily.
1776 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1777 machine_function structure is initialized (to zero) func_type will
1778 default to unknown. This will force the first use of arm_current_func_type
1779 to call arm_compute_func_type. */
1780 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1781 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1782 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1783 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1784 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1785 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1786 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1787
1788 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1789
1790 /* In addition functions can have several type modifiers,
1791 outlined by these bit masks: */
1792 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1793 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1794 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1795 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1796
1797 /* Some macros to test these flags. */
1798 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1799 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1800 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1801 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1802 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1803
1804
1805 /* Structure used to hold the function stack frame layout. Offsets are
1806 relative to the stack pointer on function entry. Positive offsets are
1807 in the direction of stack growth.
1808 Only soft_frame is used in thumb mode. */
1809
1810 typedef struct arm_stack_offsets GTY(())
1811 {
1812 int saved_args; /* ARG_POINTER_REGNUM. */
1813 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1814 int saved_regs;
1815 int soft_frame; /* FRAME_POINTER_REGNUM. */
1816 int outgoing_args; /* STACK_POINTER_REGNUM. */
1817 }
1818 arm_stack_offsets;
1819
1820 /* A C structure for machine-specific, per-function data.
1821 This is added to the cfun structure. */
1822 typedef struct machine_function GTY(())
1823 {
1824 /* Additional stack adjustment in __builtin_eh_throw. */
1825 rtx eh_epilogue_sp_ofs;
1826 /* Records if LR has to be saved for far jumps. */
1827 int far_jump_used;
1828 /* Records if ARG_POINTER was ever live. */
1829 int arg_pointer_live;
1830 /* Records if the save of LR has been eliminated. */
1831 int lr_save_eliminated;
1832 /* The size of the stack frame. Only valid after reload. */
1833 arm_stack_offsets stack_offsets;
1834 /* Records the type of the current function. */
1835 unsigned long func_type;
1836 /* Record if the function has a variable argument list. */
1837 int uses_anonymous_args;
1838 /* Records if sibcalls are blocked because an argument
1839 register is needed to preserve stack alignment. */
1840 int sibcall_blocked;
1841 }
1842 machine_function;
1843
1844 /* A C type for declaring a variable that is used as the first argument of
1845 `FUNCTION_ARG' and other related values. For some target machines, the
1846 type `int' suffices and can hold the number of bytes of argument so far. */
1847 typedef struct
1848 {
1849 /* This is the number of registers of arguments scanned so far. */
1850 int nregs;
1851 /* This is the number of iWMMXt register arguments scanned so far. */
1852 int iwmmxt_nregs;
1853 int named_count;
1854 int nargs;
1855 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1856 int call_cookie;
1857 int can_split;
1858 } CUMULATIVE_ARGS;
1859
1860 /* Define where to put the arguments to a function.
1861 Value is zero to push the argument on the stack,
1862 or a hard register in which to store the argument.
1863
1864 MODE is the argument's machine mode.
1865 TYPE is the data type of the argument (as a tree).
1866 This is null for libcalls where that information may
1867 not be available.
1868 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1869 the preceding args and about the function being called.
1870 NAMED is nonzero if this argument is a named parameter
1871 (otherwise it is an extra parameter matching an ellipsis).
1872
1873 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1874 other arguments are passed on the stack. If (NAMED == 0) (which happens
1875 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1876 defined), say it is passed in the stack (function_prologue will
1877 indeed make it pass in the stack if necessary). */
1878 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1879 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1880
1881 /* For an arg passed partly in registers and partly in memory,
1882 this is the number of registers used.
1883 For args passed entirely in registers or entirely in memory, zero. */
1884 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1885 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1886 NUM_ARG_REGS > (CUM).nregs \
1887 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE)) \
1888 && (CUM).can_split) \
1889 ? NUM_ARG_REGS - (CUM).nregs : 0)
1890
1891 /* A C expression that indicates when an argument must be passed by
1892 reference. If nonzero for an argument, a copy of that argument is
1893 made in memory and a pointer to the argument is passed instead of
1894 the argument itself. The pointer is passed in whatever way is
1895 appropriate for passing a pointer to that type. */
1896 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1897 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1898
1899 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1900 for a call to a function whose data type is FNTYPE.
1901 For a library call, FNTYPE is 0.
1902 On the ARM, the offset starts at 0. */
1903 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1904 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1905
1906 /* Update the data in CUM to advance over an argument
1907 of mode MODE and data type TYPE.
1908 (TYPE is null for libcalls where that information may not be available.) */
1909 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1910 (CUM).nargs += 1; \
1911 if (VECTOR_MODE_SUPPORTED_P (MODE) \
1912 && (CUM).named_count > (CUM).nargs) \
1913 (CUM).iwmmxt_nregs += 1; \
1914 else \
1915 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1916
1917 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1918 argument with the specified mode and type. If it is not defined,
1919 `PARM_BOUNDARY' is used for all arguments. */
1920 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1921 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1922 ? DOUBLEWORD_ALIGNMENT \
1923 : PARM_BOUNDARY )
1924
1925 /* 1 if N is a possible register number for function argument passing.
1926 On the ARM, r0-r3 are used to pass args. */
1927 #define FUNCTION_ARG_REGNO_P(REGNO) \
1928 (IN_RANGE ((REGNO), 0, 3) \
1929 || (TARGET_IWMMXT_ABI \
1930 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1931
1932 /* Implement `va_arg'. */
1933 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1934 arm_va_arg (valist, type)
1935
1936 \f
1937 /* If your target environment doesn't prefix user functions with an
1938 underscore, you may wish to re-define this to prevent any conflicts.
1939 e.g. AOF may prefix mcount with an underscore. */
1940 #ifndef ARM_MCOUNT_NAME
1941 #define ARM_MCOUNT_NAME "*mcount"
1942 #endif
1943
1944 /* Call the function profiler with a given profile label. The Acorn
1945 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1946 On the ARM the full profile code will look like:
1947 .data
1948 LP1
1949 .word 0
1950 .text
1951 mov ip, lr
1952 bl mcount
1953 .word LP1
1954
1955 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1956 will output the .text section.
1957
1958 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1959 ``prof'' doesn't seem to mind about this!
1960
1961 Note - this version of the code is designed to work in both ARM and
1962 Thumb modes. */
1963 #ifndef ARM_FUNCTION_PROFILER
1964 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1965 { \
1966 char temp[20]; \
1967 rtx sym; \
1968 \
1969 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1970 IP_REGNUM, LR_REGNUM); \
1971 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1972 fputc ('\n', STREAM); \
1973 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1974 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1975 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1976 }
1977 #endif
1978
1979 #ifdef THUMB_FUNCTION_PROFILER
1980 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1981 if (TARGET_ARM) \
1982 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1983 else \
1984 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1985 #else
1986 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1987 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1988 #endif
1989
1990 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1991 the stack pointer does not matter. The value is tested only in
1992 functions that have frame pointers.
1993 No definition is equivalent to always zero.
1994
1995 On the ARM, the function epilogue recovers the stack pointer from the
1996 frame. */
1997 #define EXIT_IGNORE_STACK 1
1998
1999 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
2000
2001 /* Determine if the epilogue should be output as RTL.
2002 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
2003 #define USE_RETURN_INSN(ISCOND) \
2004 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
2005
2006 /* Definitions for register eliminations.
2007
2008 This is an array of structures. Each structure initializes one pair
2009 of eliminable registers. The "from" register number is given first,
2010 followed by "to". Eliminations of the same "from" register are listed
2011 in order of preference.
2012
2013 We have two registers that can be eliminated on the ARM. First, the
2014 arg pointer register can often be eliminated in favor of the stack
2015 pointer register. Secondly, the pseudo frame pointer register can always
2016 be eliminated; it is replaced with either the stack or the real frame
2017 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
2018 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
2019
2020 #define ELIMINABLE_REGS \
2021 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
2022 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
2023 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
2024 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
2025 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
2026 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
2027 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
2028
2029 /* Given FROM and TO register numbers, say whether this elimination is
2030 allowed. Frame pointer elimination is automatically handled.
2031
2032 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
2033 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
2034 pointer, we must eliminate FRAME_POINTER_REGNUM into
2035 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
2036 ARG_POINTER_REGNUM. */
2037 #define CAN_ELIMINATE(FROM, TO) \
2038 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
2039 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
2040 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
2041 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
2042 1)
2043
2044 #define THUMB_REG_PUSHED_P(reg) \
2045 (regs_ever_live [reg] \
2046 && (! call_used_regs [reg] \
2047 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
2048 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
2049
2050 /* Define the offset between two registers, one to be eliminated, and the
2051 other its replacement, at the start of a routine. */
2052 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2053 if (TARGET_ARM) \
2054 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
2055 else \
2056 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
2057
2058 /* Special case handling of the location of arguments passed on the stack. */
2059 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
2060
2061 /* Initialize data used by insn expanders. This is called from insn_emit,
2062 once for every function before code is generated. */
2063 #define INIT_EXPANDERS arm_init_expanders ()
2064
2065 /* Output assembler code for a block containing the constant parts
2066 of a trampoline, leaving space for the variable parts.
2067
2068 On the ARM, (if r8 is the static chain regnum, and remembering that
2069 referencing pc adds an offset of 8) the trampoline looks like:
2070 ldr r8, [pc, #0]
2071 ldr pc, [pc]
2072 .word static chain value
2073 .word function's address
2074 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
2075 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
2076 { \
2077 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
2078 STATIC_CHAIN_REGNUM, PC_REGNUM); \
2079 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
2080 PC_REGNUM, PC_REGNUM); \
2081 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
2082 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
2083 }
2084
2085 /* On the Thumb we always switch into ARM mode to execute the trampoline.
2086 Why - because it is easier. This code will always be branched to via
2087 a BX instruction and since the compiler magically generates the address
2088 of the function the linker has no opportunity to ensure that the
2089 bottom bit is set. Thus the processor will be in ARM mode when it
2090 reaches this code. So we duplicate the ARM trampoline code and add
2091 a switch into Thumb mode as well. */
2092 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
2093 { \
2094 fprintf (FILE, "\t.code 32\n"); \
2095 fprintf (FILE, ".Ltrampoline_start:\n"); \
2096 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2097 STATIC_CHAIN_REGNUM, PC_REGNUM); \
2098 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2099 IP_REGNUM, PC_REGNUM); \
2100 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
2101 IP_REGNUM, IP_REGNUM); \
2102 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
2103 fprintf (FILE, "\t.word\t0\n"); \
2104 fprintf (FILE, "\t.word\t0\n"); \
2105 fprintf (FILE, "\t.code 16\n"); \
2106 }
2107
2108 #define TRAMPOLINE_TEMPLATE(FILE) \
2109 if (TARGET_ARM) \
2110 ARM_TRAMPOLINE_TEMPLATE (FILE) \
2111 else \
2112 THUMB_TRAMPOLINE_TEMPLATE (FILE)
2113
2114 /* Length in units of the trampoline for entering a nested function. */
2115 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
2116
2117 /* Alignment required for a trampoline in bits. */
2118 #define TRAMPOLINE_ALIGNMENT 32
2119
2120 /* Emit RTL insns to initialize the variable parts of a trampoline.
2121 FNADDR is an RTX for the address of the function's pure code.
2122 CXT is an RTX for the static chain value for the function. */
2123 #ifndef INITIALIZE_TRAMPOLINE
2124 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2125 { \
2126 emit_move_insn (gen_rtx_MEM (SImode, \
2127 plus_constant (TRAMP, \
2128 TARGET_ARM ? 8 : 16)), \
2129 CXT); \
2130 emit_move_insn (gen_rtx_MEM (SImode, \
2131 plus_constant (TRAMP, \
2132 TARGET_ARM ? 12 : 20)), \
2133 FNADDR); \
2134 }
2135 #endif
2136
2137 \f
2138 /* Addressing modes, and classification of registers for them. */
2139 #define HAVE_POST_INCREMENT 1
2140 #define HAVE_PRE_INCREMENT TARGET_ARM
2141 #define HAVE_POST_DECREMENT TARGET_ARM
2142 #define HAVE_PRE_DECREMENT TARGET_ARM
2143 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2144 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2145 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2146 #define HAVE_POST_MODIFY_REG TARGET_ARM
2147
2148 /* Macros to check register numbers against specific register classes. */
2149
2150 /* These assume that REGNO is a hard or pseudo reg number.
2151 They give nonzero only if REGNO is a hard reg of the suitable class
2152 or a pseudo reg currently allocated to a suitable hard reg.
2153 Since they use reg_renumber, they are safe only once reg_renumber
2154 has been allocated, which happens in local-alloc.c. */
2155 #define TEST_REGNO(R, TEST, VALUE) \
2156 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2157
2158 /* On the ARM, don't allow the pc to be used. */
2159 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2160 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2161 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2162 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2163
2164 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2165 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2166 || (GET_MODE_SIZE (MODE) >= 4 \
2167 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2168
2169 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2170 (TARGET_THUMB \
2171 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2172 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2173
2174 /* For ARM code, we don't care about the mode, but for Thumb, the index
2175 must be suitable for use in a QImode load. */
2176 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2177 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2178
2179 /* Maximum number of registers that can appear in a valid memory address.
2180 Shifts in addresses can't be by a register. */
2181 #define MAX_REGS_PER_ADDRESS 2
2182
2183 /* Recognize any constant value that is a valid address. */
2184 /* XXX We can address any constant, eventually... */
2185
2186 #ifdef AOF_ASSEMBLER
2187
2188 #define CONSTANT_ADDRESS_P(X) \
2189 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2190
2191 #else
2192
2193 #define CONSTANT_ADDRESS_P(X) \
2194 (GET_CODE (X) == SYMBOL_REF \
2195 && (CONSTANT_POOL_ADDRESS_P (X) \
2196 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2197
2198 #endif /* AOF_ASSEMBLER */
2199
2200 /* Nonzero if the constant value X is a legitimate general operand.
2201 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2202
2203 On the ARM, allow any integer (invalid ones are removed later by insn
2204 patterns), nice doubles and symbol_refs which refer to the function's
2205 constant pool XXX.
2206
2207 When generating pic allow anything. */
2208 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2209
2210 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2211 ( GET_CODE (X) == CONST_INT \
2212 || GET_CODE (X) == CONST_DOUBLE \
2213 || GET_CODE (X) == CONSTANT_P_RTX \
2214 || CONSTANT_ADDRESS_P (X) \
2215 || flag_pic)
2216
2217 #define LEGITIMATE_CONSTANT_P(X) \
2218 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2219
2220 /* Special characters prefixed to function names
2221 in order to encode attribute like information.
2222 Note, '@' and '*' have already been taken. */
2223 #define SHORT_CALL_FLAG_CHAR '^'
2224 #define LONG_CALL_FLAG_CHAR '#'
2225
2226 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2227 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2228
2229 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2230 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2231
2232 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2233 #define SUBTARGET_NAME_ENCODING_LENGTHS
2234 #endif
2235
2236 /* This is a C fragment for the inside of a switch statement.
2237 Each case label should return the number of characters to
2238 be stripped from the start of a function's name, if that
2239 name starts with the indicated character. */
2240 #define ARM_NAME_ENCODING_LENGTHS \
2241 case SHORT_CALL_FLAG_CHAR: return 1; \
2242 case LONG_CALL_FLAG_CHAR: return 1; \
2243 case '*': return 1; \
2244 SUBTARGET_NAME_ENCODING_LENGTHS
2245
2246 /* This is how to output a reference to a user-level label named NAME.
2247 `assemble_name' uses this. */
2248 #undef ASM_OUTPUT_LABELREF
2249 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2250 arm_asm_output_labelref (FILE, NAME)
2251
2252 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2253 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2254
2255 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2256 and check its validity for a certain class.
2257 We have two alternate definitions for each of them.
2258 The usual definition accepts all pseudo regs; the other rejects
2259 them unless they have been allocated suitable hard regs.
2260 The symbol REG_OK_STRICT causes the latter definition to be used. */
2261 #ifndef REG_OK_STRICT
2262
2263 #define ARM_REG_OK_FOR_BASE_P(X) \
2264 (REGNO (X) <= LAST_ARM_REGNUM \
2265 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2266 || REGNO (X) == FRAME_POINTER_REGNUM \
2267 || REGNO (X) == ARG_POINTER_REGNUM)
2268
2269 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2270 (REGNO (X) <= LAST_LO_REGNUM \
2271 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2272 || (GET_MODE_SIZE (MODE) >= 4 \
2273 && (REGNO (X) == STACK_POINTER_REGNUM \
2274 || (X) == hard_frame_pointer_rtx \
2275 || (X) == arg_pointer_rtx)))
2276
2277 #define REG_STRICT_P 0
2278
2279 #else /* REG_OK_STRICT */
2280
2281 #define ARM_REG_OK_FOR_BASE_P(X) \
2282 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2283
2284 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2285 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2286
2287 #define REG_STRICT_P 1
2288
2289 #endif /* REG_OK_STRICT */
2290
2291 /* Now define some helpers in terms of the above. */
2292
2293 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2294 (TARGET_THUMB \
2295 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2296 : ARM_REG_OK_FOR_BASE_P (X))
2297
2298 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2299
2300 /* For Thumb, a valid index register is anything that can be used in
2301 a byte load instruction. */
2302 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2303
2304 /* Nonzero if X is a hard reg that can be used as an index
2305 or if it is a pseudo reg. On the Thumb, the stack pointer
2306 is not suitable. */
2307 #define REG_OK_FOR_INDEX_P(X) \
2308 (TARGET_THUMB \
2309 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2310 : ARM_REG_OK_FOR_INDEX_P (X))
2311
2312 \f
2313 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2314 that is a valid memory address for an instruction.
2315 The MODE argument is the machine mode for the MEM expression
2316 that wants to use this address. */
2317
2318 #define ARM_BASE_REGISTER_RTX_P(X) \
2319 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2320
2321 #define ARM_INDEX_REGISTER_RTX_P(X) \
2322 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2323
2324 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2325 { \
2326 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2327 goto WIN; \
2328 }
2329
2330 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2331 { \
2332 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2333 goto WIN; \
2334 }
2335
2336 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2337 if (TARGET_ARM) \
2338 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2339 else /* if (TARGET_THUMB) */ \
2340 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2341
2342 \f
2343 /* Try machine-dependent ways of modifying an illegitimate address
2344 to be legitimate. If we find one, return the new, valid address. */
2345 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2346 do { \
2347 X = arm_legitimize_address (X, OLDX, MODE); \
2348 } while (0)
2349
2350 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2351 do { \
2352 X = thumb_legitimize_address (X, OLDX, MODE); \
2353 } while (0)
2354
2355 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2356 do { \
2357 if (TARGET_ARM) \
2358 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2359 else \
2360 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2361 \
2362 if (memory_address_p (MODE, X)) \
2363 goto WIN; \
2364 } while (0)
2365
2366 /* Go to LABEL if ADDR (a legitimate address expression)
2367 has an effect that depends on the machine mode it is used for. */
2368 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2369 { \
2370 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2371 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2372 goto LABEL; \
2373 }
2374
2375 /* Nothing helpful to do for the Thumb */
2376 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2377 if (TARGET_ARM) \
2378 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2379 \f
2380
2381 /* Specify the machine mode that this machine uses
2382 for the index in the tablejump instruction. */
2383 #define CASE_VECTOR_MODE Pmode
2384
2385 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2386 unsigned is probably best, but may break some code. */
2387 #ifndef DEFAULT_SIGNED_CHAR
2388 #define DEFAULT_SIGNED_CHAR 0
2389 #endif
2390
2391 /* Don't cse the address of the function being compiled. */
2392 #define NO_RECURSIVE_FUNCTION_CSE 1
2393
2394 /* Max number of bytes we can move from memory to memory
2395 in one reasonably fast instruction. */
2396 #define MOVE_MAX 4
2397
2398 #undef MOVE_RATIO
2399 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2400
2401 /* Define if operations between registers always perform the operation
2402 on the full register even if a narrower mode is specified. */
2403 #define WORD_REGISTER_OPERATIONS
2404
2405 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2406 will either zero-extend or sign-extend. The value of this macro should
2407 be the code that says which one of the two operations is implicitly
2408 done, NIL if none. */
2409 #define LOAD_EXTEND_OP(MODE) \
2410 (TARGET_THUMB ? ZERO_EXTEND : \
2411 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2412 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2413
2414 /* Nonzero if access to memory by bytes is slow and undesirable. */
2415 #define SLOW_BYTE_ACCESS 0
2416
2417 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2418
2419 /* Immediate shift counts are truncated by the output routines (or was it
2420 the assembler?). Shift counts in a register are truncated by ARM. Note
2421 that the native compiler puts too large (> 32) immediate shift counts
2422 into a register and shifts by the register, letting the ARM decide what
2423 to do instead of doing that itself. */
2424 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2425 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2426 On the arm, Y in a register is used modulo 256 for the shift. Only for
2427 rotates is modulo 32 used. */
2428 /* #define SHIFT_COUNT_TRUNCATED 1 */
2429
2430 /* All integers have the same format so truncation is easy. */
2431 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2432
2433 /* Calling from registers is a massive pain. */
2434 #define NO_FUNCTION_CSE 1
2435
2436 /* The machine modes of pointers and functions */
2437 #define Pmode SImode
2438 #define FUNCTION_MODE Pmode
2439
2440 #define ARM_FRAME_RTX(X) \
2441 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2442 || (X) == arg_pointer_rtx)
2443
2444 /* Moves to and from memory are quite expensive */
2445 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2446 (TARGET_ARM ? 10 : \
2447 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2448 * (CLASS == LO_REGS ? 1 : 2)))
2449
2450 /* Try to generate sequences that don't involve branches, we can then use
2451 conditional instructions */
2452 #define BRANCH_COST \
2453 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2454 \f
2455 /* Position Independent Code. */
2456 /* We decide which register to use based on the compilation options and
2457 the assembler in use; this is more general than the APCS restriction of
2458 using sb (r9) all the time. */
2459 extern int arm_pic_register;
2460
2461 /* Used when parsing command line option -mpic-register=. */
2462 extern const char * arm_pic_register_string;
2463
2464 /* The register number of the register used to address a table of static
2465 data addresses in memory. */
2466 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2467
2468 #define FINALIZE_PIC arm_finalize_pic (1)
2469
2470 /* We can't directly access anything that contains a symbol,
2471 nor can we indirect via the constant pool. */
2472 #define LEGITIMATE_PIC_OPERAND_P(X) \
2473 (!(symbol_mentioned_p (X) \
2474 || label_mentioned_p (X) \
2475 || (GET_CODE (X) == SYMBOL_REF \
2476 && CONSTANT_POOL_ADDRESS_P (X) \
2477 && (symbol_mentioned_p (get_pool_constant (X)) \
2478 || label_mentioned_p (get_pool_constant (X))))))
2479
2480 /* We need to know when we are making a constant pool; this determines
2481 whether data needs to be in the GOT or can be referenced via a GOT
2482 offset. */
2483 extern int making_const_table;
2484 \f
2485 /* Handle pragmas for compatibility with Intel's compilers. */
2486 #define REGISTER_TARGET_PRAGMAS() do { \
2487 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2488 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2489 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2490 } while (0)
2491
2492 /* Condition code information. */
2493 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2494 return the mode to be used for the comparison. */
2495
2496 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2497
2498 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2499
2500 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2501 do \
2502 { \
2503 if (GET_CODE (OP1) == CONST_INT \
2504 && ! (const_ok_for_arm (INTVAL (OP1)) \
2505 || (const_ok_for_arm (- INTVAL (OP1))))) \
2506 { \
2507 rtx const_op = OP1; \
2508 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2509 OP1 = const_op; \
2510 } \
2511 } \
2512 while (0)
2513
2514 /* The arm5 clz instruction returns 32. */
2515 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2516 \f
2517 #undef ASM_APP_OFF
2518 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2519
2520 /* Output a push or a pop instruction (only used when profiling). */
2521 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2522 do \
2523 { \
2524 if (TARGET_ARM) \
2525 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2526 STACK_POINTER_REGNUM, REGNO); \
2527 else \
2528 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2529 } while (0)
2530
2531
2532 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2533 do \
2534 { \
2535 if (TARGET_ARM) \
2536 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2537 STACK_POINTER_REGNUM, REGNO); \
2538 else \
2539 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2540 } while (0)
2541
2542 /* This is how to output a label which precedes a jumptable. Since
2543 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2544 #undef ASM_OUTPUT_CASE_LABEL
2545 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2546 do \
2547 { \
2548 if (TARGET_THUMB) \
2549 ASM_OUTPUT_ALIGN (FILE, 2); \
2550 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2551 } \
2552 while (0)
2553
2554 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2555 do \
2556 { \
2557 if (TARGET_THUMB) \
2558 { \
2559 if (is_called_in_ARM_mode (DECL) \
2560 || current_function_is_thunk) \
2561 fprintf (STREAM, "\t.code 32\n") ; \
2562 else \
2563 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2564 } \
2565 if (TARGET_POKE_FUNCTION_NAME) \
2566 arm_poke_function_name (STREAM, (char *) NAME); \
2567 } \
2568 while (0)
2569
2570 /* For aliases of functions we use .thumb_set instead. */
2571 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2572 do \
2573 { \
2574 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2575 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2576 \
2577 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2578 { \
2579 fprintf (FILE, "\t.thumb_set "); \
2580 assemble_name (FILE, LABEL1); \
2581 fprintf (FILE, ","); \
2582 assemble_name (FILE, LABEL2); \
2583 fprintf (FILE, "\n"); \
2584 } \
2585 else \
2586 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2587 } \
2588 while (0)
2589
2590 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2591 /* To support -falign-* switches we need to use .p2align so
2592 that alignment directives in code sections will be padded
2593 with no-op instructions, rather than zeroes. */
2594 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2595 if ((LOG) != 0) \
2596 { \
2597 if ((MAX_SKIP) == 0) \
2598 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2599 else \
2600 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2601 (int) (LOG), (int) (MAX_SKIP)); \
2602 }
2603 #endif
2604 \f
2605 /* Only perform branch elimination (by making instructions conditional) if
2606 we're optimizing. Otherwise it's of no use anyway. */
2607 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2608 if (TARGET_ARM && optimize) \
2609 arm_final_prescan_insn (INSN); \
2610 else if (TARGET_THUMB) \
2611 thumb_final_prescan_insn (INSN)
2612
2613 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2614 (CODE == '@' || CODE == '|' \
2615 || (TARGET_ARM && (CODE == '?')) \
2616 || (TARGET_THUMB && (CODE == '_')))
2617
2618 /* Output an operand of an instruction. */
2619 #define PRINT_OPERAND(STREAM, X, CODE) \
2620 arm_print_operand (STREAM, X, CODE)
2621
2622 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2623 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2624 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2625 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2626 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2627 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2628 : 0))))
2629
2630 /* Output the address of an operand. */
2631 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2632 { \
2633 int is_minus = GET_CODE (X) == MINUS; \
2634 \
2635 if (GET_CODE (X) == REG) \
2636 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2637 else if (GET_CODE (X) == PLUS || is_minus) \
2638 { \
2639 rtx base = XEXP (X, 0); \
2640 rtx index = XEXP (X, 1); \
2641 HOST_WIDE_INT offset = 0; \
2642 if (GET_CODE (base) != REG) \
2643 { \
2644 /* Ensure that BASE is a register. */ \
2645 /* (one of them must be). */ \
2646 rtx temp = base; \
2647 base = index; \
2648 index = temp; \
2649 } \
2650 switch (GET_CODE (index)) \
2651 { \
2652 case CONST_INT: \
2653 offset = INTVAL (index); \
2654 if (is_minus) \
2655 offset = -offset; \
2656 asm_fprintf (STREAM, "[%r, #%wd]", \
2657 REGNO (base), offset); \
2658 break; \
2659 \
2660 case REG: \
2661 asm_fprintf (STREAM, "[%r, %s%r]", \
2662 REGNO (base), is_minus ? "-" : "", \
2663 REGNO (index)); \
2664 break; \
2665 \
2666 case MULT: \
2667 case ASHIFTRT: \
2668 case LSHIFTRT: \
2669 case ASHIFT: \
2670 case ROTATERT: \
2671 { \
2672 asm_fprintf (STREAM, "[%r, %s%r", \
2673 REGNO (base), is_minus ? "-" : "", \
2674 REGNO (XEXP (index, 0))); \
2675 arm_print_operand (STREAM, index, 'S'); \
2676 fputs ("]", STREAM); \
2677 break; \
2678 } \
2679 \
2680 default: \
2681 abort(); \
2682 } \
2683 } \
2684 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2685 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2686 { \
2687 extern enum machine_mode output_memory_reference_mode; \
2688 \
2689 if (GET_CODE (XEXP (X, 0)) != REG) \
2690 abort (); \
2691 \
2692 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2693 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2694 REGNO (XEXP (X, 0)), \
2695 GET_CODE (X) == PRE_DEC ? "-" : "", \
2696 GET_MODE_SIZE (output_memory_reference_mode)); \
2697 else \
2698 asm_fprintf (STREAM, "[%r], #%s%d", \
2699 REGNO (XEXP (X, 0)), \
2700 GET_CODE (X) == POST_DEC ? "-" : "", \
2701 GET_MODE_SIZE (output_memory_reference_mode)); \
2702 } \
2703 else if (GET_CODE (X) == PRE_MODIFY) \
2704 { \
2705 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2706 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2707 asm_fprintf (STREAM, "#%wd]!", \
2708 INTVAL (XEXP (XEXP (X, 1), 1))); \
2709 else \
2710 asm_fprintf (STREAM, "%r]!", \
2711 REGNO (XEXP (XEXP (X, 1), 1))); \
2712 } \
2713 else if (GET_CODE (X) == POST_MODIFY) \
2714 { \
2715 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2716 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2717 asm_fprintf (STREAM, "#%wd", \
2718 INTVAL (XEXP (XEXP (X, 1), 1))); \
2719 else \
2720 asm_fprintf (STREAM, "%r", \
2721 REGNO (XEXP (XEXP (X, 1), 1))); \
2722 } \
2723 else output_addr_const (STREAM, X); \
2724 }
2725
2726 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2727 { \
2728 if (GET_CODE (X) == REG) \
2729 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2730 else if (GET_CODE (X) == POST_INC) \
2731 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2732 else if (GET_CODE (X) == PLUS) \
2733 { \
2734 if (GET_CODE (XEXP (X, 0)) != REG) \
2735 abort (); \
2736 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2737 asm_fprintf (STREAM, "[%r, #%wd]", \
2738 REGNO (XEXP (X, 0)), \
2739 INTVAL (XEXP (X, 1))); \
2740 else \
2741 asm_fprintf (STREAM, "[%r, %r]", \
2742 REGNO (XEXP (X, 0)), \
2743 REGNO (XEXP (X, 1))); \
2744 } \
2745 else \
2746 output_addr_const (STREAM, X); \
2747 }
2748
2749 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2750 if (TARGET_ARM) \
2751 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2752 else \
2753 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2754
2755 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2756 if (GET_CODE (X) != CONST_VECTOR \
2757 || ! arm_emit_vector_const (FILE, X)) \
2758 goto FAIL;
2759
2760 /* A C expression whose value is RTL representing the value of the return
2761 address for the frame COUNT steps up from the current frame. */
2762
2763 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2764 arm_return_addr (COUNT, FRAME)
2765
2766 /* Mask of the bits in the PC that contain the real return address
2767 when running in 26-bit mode. */
2768 #define RETURN_ADDR_MASK26 (0x03fffffc)
2769
2770 /* Pick up the return address upon entry to a procedure. Used for
2771 dwarf2 unwind information. This also enables the table driven
2772 mechanism. */
2773 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2774 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2775
2776 /* Used to mask out junk bits from the return address, such as
2777 processor state, interrupt status, condition codes and the like. */
2778 #define MASK_RETURN_ADDR \
2779 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2780 in 26 bit mode, the condition codes must be masked out of the \
2781 return address. This does not apply to ARM6 and later processors \
2782 when running in 32 bit mode. */ \
2783 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2784 : (arm_arch4 || TARGET_THUMB) ? \
2785 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2786 : arm_gen_return_addr_mask ())
2787
2788 \f
2789 /* Define the codes that are matched by predicates in arm.c */
2790 #define PREDICATE_CODES \
2791 {"s_register_operand", {SUBREG, REG}}, \
2792 {"arm_general_register_operand", {SUBREG, REG}}, \
2793 {"arm_hard_register_operand", {REG}}, \
2794 {"f_register_operand", {SUBREG, REG}}, \
2795 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2796 {"arm_addimm_operand", {CONST_INT}}, \
2797 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2798 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2799 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2800 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2801 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2802 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2803 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2804 {"thumb_cmpneg_operand", {CONST_INT}}, \
2805 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2806 {"offsettable_memory_operand", {MEM}}, \
2807 {"alignable_memory_operand", {MEM}}, \
2808 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2809 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2810 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2811 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2812 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2813 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2814 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2815 {"load_multiple_operation", {PARALLEL}}, \
2816 {"store_multiple_operation", {PARALLEL}}, \
2817 {"equality_operator", {EQ, NE}}, \
2818 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2819 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2820 UNGE, UNGT}}, \
2821 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2822 {"const_shift_operand", {CONST_INT}}, \
2823 {"multi_register_push", {PARALLEL}}, \
2824 {"cc_register", {REG}}, \
2825 {"logical_binary_operator", {AND, IOR, XOR}}, \
2826 {"cirrus_register_operand", {REG}}, \
2827 {"cirrus_fp_register", {REG}}, \
2828 {"cirrus_shift_const", {CONST_INT}}, \
2829 {"dominant_cc_register", {REG}}, \
2830 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2831 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2832
2833 /* Define this if you have special predicates that know special things
2834 about modes. Genrecog will warn about certain forms of
2835 match_operand without a mode; if the operand predicate is listed in
2836 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2837 #define SPECIAL_MODE_PREDICATES \
2838 "cc_register", "dominant_cc_register",
2839
2840 enum arm_builtins
2841 {
2842 ARM_BUILTIN_GETWCX,
2843 ARM_BUILTIN_SETWCX,
2844
2845 ARM_BUILTIN_WZERO,
2846
2847 ARM_BUILTIN_WAVG2BR,
2848 ARM_BUILTIN_WAVG2HR,
2849 ARM_BUILTIN_WAVG2B,
2850 ARM_BUILTIN_WAVG2H,
2851
2852 ARM_BUILTIN_WACCB,
2853 ARM_BUILTIN_WACCH,
2854 ARM_BUILTIN_WACCW,
2855
2856 ARM_BUILTIN_WMACS,
2857 ARM_BUILTIN_WMACSZ,
2858 ARM_BUILTIN_WMACU,
2859 ARM_BUILTIN_WMACUZ,
2860
2861 ARM_BUILTIN_WSADB,
2862 ARM_BUILTIN_WSADBZ,
2863 ARM_BUILTIN_WSADH,
2864 ARM_BUILTIN_WSADHZ,
2865
2866 ARM_BUILTIN_WALIGN,
2867
2868 ARM_BUILTIN_TMIA,
2869 ARM_BUILTIN_TMIAPH,
2870 ARM_BUILTIN_TMIABB,
2871 ARM_BUILTIN_TMIABT,
2872 ARM_BUILTIN_TMIATB,
2873 ARM_BUILTIN_TMIATT,
2874
2875 ARM_BUILTIN_TMOVMSKB,
2876 ARM_BUILTIN_TMOVMSKH,
2877 ARM_BUILTIN_TMOVMSKW,
2878
2879 ARM_BUILTIN_TBCSTB,
2880 ARM_BUILTIN_TBCSTH,
2881 ARM_BUILTIN_TBCSTW,
2882
2883 ARM_BUILTIN_WMADDS,
2884 ARM_BUILTIN_WMADDU,
2885
2886 ARM_BUILTIN_WPACKHSS,
2887 ARM_BUILTIN_WPACKWSS,
2888 ARM_BUILTIN_WPACKDSS,
2889 ARM_BUILTIN_WPACKHUS,
2890 ARM_BUILTIN_WPACKWUS,
2891 ARM_BUILTIN_WPACKDUS,
2892
2893 ARM_BUILTIN_WADDB,
2894 ARM_BUILTIN_WADDH,
2895 ARM_BUILTIN_WADDW,
2896 ARM_BUILTIN_WADDSSB,
2897 ARM_BUILTIN_WADDSSH,
2898 ARM_BUILTIN_WADDSSW,
2899 ARM_BUILTIN_WADDUSB,
2900 ARM_BUILTIN_WADDUSH,
2901 ARM_BUILTIN_WADDUSW,
2902 ARM_BUILTIN_WSUBB,
2903 ARM_BUILTIN_WSUBH,
2904 ARM_BUILTIN_WSUBW,
2905 ARM_BUILTIN_WSUBSSB,
2906 ARM_BUILTIN_WSUBSSH,
2907 ARM_BUILTIN_WSUBSSW,
2908 ARM_BUILTIN_WSUBUSB,
2909 ARM_BUILTIN_WSUBUSH,
2910 ARM_BUILTIN_WSUBUSW,
2911
2912 ARM_BUILTIN_WAND,
2913 ARM_BUILTIN_WANDN,
2914 ARM_BUILTIN_WOR,
2915 ARM_BUILTIN_WXOR,
2916
2917 ARM_BUILTIN_WCMPEQB,
2918 ARM_BUILTIN_WCMPEQH,
2919 ARM_BUILTIN_WCMPEQW,
2920 ARM_BUILTIN_WCMPGTUB,
2921 ARM_BUILTIN_WCMPGTUH,
2922 ARM_BUILTIN_WCMPGTUW,
2923 ARM_BUILTIN_WCMPGTSB,
2924 ARM_BUILTIN_WCMPGTSH,
2925 ARM_BUILTIN_WCMPGTSW,
2926
2927 ARM_BUILTIN_TEXTRMSB,
2928 ARM_BUILTIN_TEXTRMSH,
2929 ARM_BUILTIN_TEXTRMSW,
2930 ARM_BUILTIN_TEXTRMUB,
2931 ARM_BUILTIN_TEXTRMUH,
2932 ARM_BUILTIN_TEXTRMUW,
2933 ARM_BUILTIN_TINSRB,
2934 ARM_BUILTIN_TINSRH,
2935 ARM_BUILTIN_TINSRW,
2936
2937 ARM_BUILTIN_WMAXSW,
2938 ARM_BUILTIN_WMAXSH,
2939 ARM_BUILTIN_WMAXSB,
2940 ARM_BUILTIN_WMAXUW,
2941 ARM_BUILTIN_WMAXUH,
2942 ARM_BUILTIN_WMAXUB,
2943 ARM_BUILTIN_WMINSW,
2944 ARM_BUILTIN_WMINSH,
2945 ARM_BUILTIN_WMINSB,
2946 ARM_BUILTIN_WMINUW,
2947 ARM_BUILTIN_WMINUH,
2948 ARM_BUILTIN_WMINUB,
2949
2950 ARM_BUILTIN_WMULUM,
2951 ARM_BUILTIN_WMULSM,
2952 ARM_BUILTIN_WMULUL,
2953
2954 ARM_BUILTIN_PSADBH,
2955 ARM_BUILTIN_WSHUFH,
2956
2957 ARM_BUILTIN_WSLLH,
2958 ARM_BUILTIN_WSLLW,
2959 ARM_BUILTIN_WSLLD,
2960 ARM_BUILTIN_WSRAH,
2961 ARM_BUILTIN_WSRAW,
2962 ARM_BUILTIN_WSRAD,
2963 ARM_BUILTIN_WSRLH,
2964 ARM_BUILTIN_WSRLW,
2965 ARM_BUILTIN_WSRLD,
2966 ARM_BUILTIN_WRORH,
2967 ARM_BUILTIN_WRORW,
2968 ARM_BUILTIN_WRORD,
2969 ARM_BUILTIN_WSLLHI,
2970 ARM_BUILTIN_WSLLWI,
2971 ARM_BUILTIN_WSLLDI,
2972 ARM_BUILTIN_WSRAHI,
2973 ARM_BUILTIN_WSRAWI,
2974 ARM_BUILTIN_WSRADI,
2975 ARM_BUILTIN_WSRLHI,
2976 ARM_BUILTIN_WSRLWI,
2977 ARM_BUILTIN_WSRLDI,
2978 ARM_BUILTIN_WRORHI,
2979 ARM_BUILTIN_WRORWI,
2980 ARM_BUILTIN_WRORDI,
2981
2982 ARM_BUILTIN_WUNPCKIHB,
2983 ARM_BUILTIN_WUNPCKIHH,
2984 ARM_BUILTIN_WUNPCKIHW,
2985 ARM_BUILTIN_WUNPCKILB,
2986 ARM_BUILTIN_WUNPCKILH,
2987 ARM_BUILTIN_WUNPCKILW,
2988
2989 ARM_BUILTIN_WUNPCKEHSB,
2990 ARM_BUILTIN_WUNPCKEHSH,
2991 ARM_BUILTIN_WUNPCKEHSW,
2992 ARM_BUILTIN_WUNPCKEHUB,
2993 ARM_BUILTIN_WUNPCKEHUH,
2994 ARM_BUILTIN_WUNPCKEHUW,
2995 ARM_BUILTIN_WUNPCKELSB,
2996 ARM_BUILTIN_WUNPCKELSH,
2997 ARM_BUILTIN_WUNPCKELSW,
2998 ARM_BUILTIN_WUNPCKELUB,
2999 ARM_BUILTIN_WUNPCKELUH,
3000 ARM_BUILTIN_WUNPCKELUW,
3001
3002 ARM_BUILTIN_MAX
3003 };
3004 #endif /* ! GCC_ARM_H */
Mirror of the offical gcc git repository hosted at gcc.gnu.org