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* arm.h (EXTRA_CONSTRAINT_STR_ARM): Update comment.
[official-gcc.git] / gcc / config / arm / arm.h
blob666ce7469073b0aa1bbeb1ea87010f511eeeb7a3
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 /* Define __arm__ even when in thumb mode, for \
34 consistency with armcc. */ \
35 builtin_define ("__arm__"); \
36 if (TARGET_THUMB) \
37 builtin_define ("__thumb__"); \
38 \
39 if (TARGET_BIG_END) \
40 { \
41 builtin_define ("__ARMEB__"); \
42 if (TARGET_THUMB) \
43 builtin_define ("__THUMBEB__"); \
44 if (TARGET_LITTLE_WORDS) \
45 builtin_define ("__ARMWEL__"); \
46 } \
47 else \
48 { \
49 builtin_define ("__ARMEL__"); \
50 if (TARGET_THUMB) \
51 builtin_define ("__THUMBEL__"); \
52 } \
53 \
54 if (TARGET_APCS_32) \
55 builtin_define ("__APCS_32__"); \
56 else \
57 builtin_define ("__APCS_26__"); \
58 \
59 if (TARGET_SOFT_FLOAT) \
60 builtin_define ("__SOFTFP__"); \
61 \
62 if (TARGET_VFP) \
63 builtin_define ("__VFP_FP__"); \
64 \
65 /* Add a define for interworking. \
66 Needed when building libgcc.a. */ \
67 if (TARGET_INTERWORK) \
68 builtin_define ("__THUMB_INTERWORK__"); \
69 \
70 builtin_assert ("cpu=arm"); \
71 builtin_assert ("machine=arm"); \
72 } while (0)
73
74 #define TARGET_CPU_arm2 0x0000
75 #define TARGET_CPU_arm250 0x0000
76 #define TARGET_CPU_arm3 0x0000
77 #define TARGET_CPU_arm6 0x0001
78 #define TARGET_CPU_arm600 0x0001
79 #define TARGET_CPU_arm610 0x0002
80 #define TARGET_CPU_arm7 0x0001
81 #define TARGET_CPU_arm7m 0x0004
82 #define TARGET_CPU_arm7dm 0x0004
83 #define TARGET_CPU_arm7dmi 0x0004
84 #define TARGET_CPU_arm700 0x0001
85 #define TARGET_CPU_arm710 0x0002
86 #define TARGET_CPU_arm7100 0x0002
87 #define TARGET_CPU_arm7500 0x0002
88 #define TARGET_CPU_arm7500fe 0x1001
89 #define TARGET_CPU_arm7tdmi 0x0008
90 #define TARGET_CPU_arm8 0x0010
91 #define TARGET_CPU_arm810 0x0020
92 #define TARGET_CPU_strongarm 0x0040
93 #define TARGET_CPU_strongarm110 0x0040
94 #define TARGET_CPU_strongarm1100 0x0040
95 #define TARGET_CPU_arm9 0x0080
96 #define TARGET_CPU_arm9tdmi 0x0080
97 #define TARGET_CPU_xscale 0x0100
98 #define TARGET_CPU_ep9312 0x0200
99 #define TARGET_CPU_iwmmxt 0x0400
100 #define TARGET_CPU_arm926ejs 0x0800
101 #define TARGET_CPU_arm1026ejs 0x1000
102 #define TARGET_CPU_arm1136js 0x2000
103 #define TARGET_CPU_arm1136jfs 0x4000
104 /* Configure didn't specify. */
105 #define TARGET_CPU_generic 0x8000
106
107 /* The various ARM cores. */
108 enum processor_type
109 {
110 #define ARM_CORE(NAME, FLAGS, COSTS) \
111 NAME,
112 #include "arm-cores.def"
113 #undef ARM_CORE
114 /* Used to indicate that no processor has been specified. */
115 arm_none
116 };
117
118 /* The processor for which instructions should be scheduled. */
119 extern enum processor_type arm_tune;
120
121 typedef enum arm_cond_code
122 {
123 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
124 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
125 }
126 arm_cc;
127
128 extern arm_cc arm_current_cc;
129
130 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
131
132 extern int arm_target_label;
133 extern int arm_ccfsm_state;
134 extern GTY(()) rtx arm_target_insn;
135 /* Run-time compilation parameters selecting different hardware subsets. */
136 extern int target_flags;
137 /* The floating point mode. */
138 extern const char *target_fpu_name;
139 /* For backwards compatibility. */
140 extern const char *target_fpe_name;
141 /* Whether to use floating point hardware. */
142 extern const char *target_float_abi_name;
143 /* Define the information needed to generate branch insns. This is
144 stored from the compare operation. */
145 extern GTY(()) rtx arm_compare_op0;
146 extern GTY(()) rtx arm_compare_op1;
147 /* The label of the current constant pool. */
148 extern rtx pool_vector_label;
149 /* Set to 1 when a return insn is output, this means that the epilogue
150 is not needed. */
151 extern int return_used_this_function;
152 /* Used to produce AOF syntax assembler. */
153 extern GTY(()) rtx aof_pic_label;
154 \f
155 /* Just in case configure has failed to define anything. */
156 #ifndef TARGET_CPU_DEFAULT
157 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
158 #endif
159
160 /* If the configuration file doesn't specify the cpu, the subtarget may
161 override it. If it doesn't, then default to an ARM6. */
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
163 #undef TARGET_CPU_DEFAULT
164
165 #ifdef SUBTARGET_CPU_DEFAULT
166 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
167 #else
168 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
169 #endif
170 #endif
171
172 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
173 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
174 #else
175 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
176 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
177 #else
178 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
179 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
180 #else
181 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
182 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
183 #else
184 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
185 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
186 #else
187 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
188 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
189 #else
190 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
191 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__"
192 /* Set TARGET_DEFAULT to the default, but without soft-float. */
193 #ifdef TARGET_DEFAULT
194 #undef TARGET_DEFAULT
195 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
196 #endif
197 #else
198 #if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
199 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__"
200 #else
201 #if (TARGET_CPU_DEFAULT == TARGET_CPU_arm926ejs || \
202 TARGET_CPU_DEFAULT == TARGET_CPU_arm1026ejs)
203 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TEJ__"
204 #else
205 #if (TARGET_CPU_DEFAULT == TARGET_CPU_arm1136js || \
206 TARGET_CPU_DEFAULT == TARGET_CPU_arm1136jfs)
207 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_6J__"
208 #else
209 #error Unrecognized value in TARGET_CPU_DEFAULT.
210 #endif
211 #endif
212 #endif
213 #endif
214 #endif
215 #endif
216 #endif
217 #endif
218 #endif
219 #endif
220
221 #undef CPP_SPEC
222 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
223 %{mapcs-32:%{mapcs-26: \
224 %e-mapcs-26 and -mapcs-32 may not be used together}} \
225 %{msoft-float:%{mhard-float: \
226 %e-msoft-float and -mhard_float may not be used together}} \
227 %{mbig-endian:%{mlittle-endian: \
228 %e-mbig-endian and -mlittle-endian may not be used together}}"
229
230 /* Set the architecture define -- if -march= is set, then it overrides
231 the -mcpu= setting. */
232 #define CPP_CPU_ARCH_SPEC "\
233 %{march=arm2:-D__ARM_ARCH_2__} \
234 %{march=arm250:-D__ARM_ARCH_2__} \
235 %{march=arm3:-D__ARM_ARCH_2__} \
236 %{march=arm6:-D__ARM_ARCH_3__} \
237 %{march=arm600:-D__ARM_ARCH_3__} \
238 %{march=arm610:-D__ARM_ARCH_3__} \
239 %{march=arm7:-D__ARM_ARCH_3__} \
240 %{march=arm700:-D__ARM_ARCH_3__} \
241 %{march=arm710:-D__ARM_ARCH_3__} \
242 %{march=arm720:-D__ARM_ARCH_3__} \
243 %{march=arm7100:-D__ARM_ARCH_3__} \
244 %{march=arm7500:-D__ARM_ARCH_3__} \
245 %{march=arm7500fe:-D__ARM_ARCH_3__} \
246 %{march=arm7m:-D__ARM_ARCH_3M__} \
247 %{march=arm7dm:-D__ARM_ARCH_3M__} \
248 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
249 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
250 %{march=arm8:-D__ARM_ARCH_4__} \
251 %{march=arm810:-D__ARM_ARCH_4__} \
252 %{march=arm9:-D__ARM_ARCH_4T__} \
253 %{march=arm920:-D__ARM_ARCH_4__} \
254 %{march=arm920t:-D__ARM_ARCH_4T__} \
255 %{march=arm926ejs:-D__ARM_ARCH_5TEJ__} \
256 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
257 %{march=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
258 %{march=arm1136js:-D__ARM_ARCH_6J__} \
259 %{march=arm1136jfs:-D__ARM_ARCH_6J__} \
260 %{march=strongarm:-D__ARM_ARCH_4__} \
261 %{march=strongarm110:-D__ARM_ARCH_4__} \
262 %{march=strongarm1100:-D__ARM_ARCH_4__} \
263 %{march=xscale:-D__ARM_ARCH_5TE__} \
264 %{march=xscale:-D__XSCALE__} \
265 %{march=ep9312:-D__ARM_ARCH_4T__} \
266 %{march=ep9312:-D__MAVERICK__} \
267 %{march=armv2:-D__ARM_ARCH_2__} \
268 %{march=armv2a:-D__ARM_ARCH_2__} \
269 %{march=armv3:-D__ARM_ARCH_3__} \
270 %{march=armv3m:-D__ARM_ARCH_3M__} \
271 %{march=armv4:-D__ARM_ARCH_4__} \
272 %{march=armv4t:-D__ARM_ARCH_4T__} \
273 %{march=armv5:-D__ARM_ARCH_5__} \
274 %{march=armv5t:-D__ARM_ARCH_5T__} \
275 %{march=armv5e:-D__ARM_ARCH_5E__} \
276 %{march=armv5te:-D__ARM_ARCH_5TE__} \
277 %{march=armv6:-D__ARM_ARCH6__} \
278 %{march=armv6j:-D__ARM_ARCH6J__} \
279 %{!march=*: \
280 %{mcpu=arm2:-D__ARM_ARCH_2__} \
281 %{mcpu=arm250:-D__ARM_ARCH_2__} \
282 %{mcpu=arm3:-D__ARM_ARCH_2__} \
283 %{mcpu=arm6:-D__ARM_ARCH_3__} \
284 %{mcpu=arm600:-D__ARM_ARCH_3__} \
285 %{mcpu=arm610:-D__ARM_ARCH_3__} \
286 %{mcpu=arm7:-D__ARM_ARCH_3__} \
287 %{mcpu=arm700:-D__ARM_ARCH_3__} \
288 %{mcpu=arm710:-D__ARM_ARCH_3__} \
289 %{mcpu=arm720:-D__ARM_ARCH_3__} \
290 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
291 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
292 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
293 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
294 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
295 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
296 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
297 %{mcpu=arm8:-D__ARM_ARCH_4__} \
298 %{mcpu=arm810:-D__ARM_ARCH_4__} \
299 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
300 %{mcpu=arm920:-D__ARM_ARCH_4__} \
301 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
302 %{mcpu=arm926ejs:-D__ARM_ARCH_5TEJ__} \
303 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
304 %{mcpu=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
305 %{mcpu=arm1136js:-D__ARM_ARCH_6J__} \
306 %{mcpu=arm1136jfs:-D__ARM_ARCH_6J__} \
307 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
308 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
309 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
310 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
311 %{mcpu=xscale:-D__XSCALE__} \
312 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
313 %{mcpu=ep9312:-D__MAVERICK__} \
314 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
315 %{mcpu=iwmmxt:-D__XSCALE__} \
316 %{mcpu=iwmmxt:-D__IWMMXT__} \
317 %{!mcpu*:%(cpp_cpu_arch_default)}} \
318 "
319
320 #ifndef CC1_SPEC
321 #define CC1_SPEC ""
322 #endif
323
324 /* This macro defines names of additional specifications to put in the specs
325 that can be used in various specifications like CC1_SPEC. Its definition
326 is an initializer with a subgrouping for each command option.
327
328 Each subgrouping contains a string constant, that defines the
329 specification name, and a string constant that used by the GCC driver
330 program.
331
332 Do not define this macro if it does not need to do anything. */
333 #define EXTRA_SPECS \
334 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
335 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
336 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
337 SUBTARGET_EXTRA_SPECS
338
339 #ifndef SUBTARGET_EXTRA_SPECS
340 #define SUBTARGET_EXTRA_SPECS
341 #endif
342
343 #ifndef SUBTARGET_CPP_SPEC
344 #define SUBTARGET_CPP_SPEC ""
345 #endif
346 \f
347 /* Run-time Target Specification. */
348 #ifndef TARGET_VERSION
349 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
350 #endif
351
352 /* Nonzero if the function prologue (and epilogue) should obey
353 the ARM Procedure Call Standard. */
354 #define ARM_FLAG_APCS_FRAME (1 << 0)
355
356 /* Nonzero if the function prologue should output the function name to enable
357 the post mortem debugger to print a backtrace (very useful on RISCOS,
358 unused on RISCiX). Specifying this flag also enables
359 -fno-omit-frame-pointer.
360 XXX Must still be implemented in the prologue. */
361 #define ARM_FLAG_POKE (1 << 1)
362
363 /* Nonzero if floating point instructions are emulated by the FPE, in which
364 case instruction scheduling becomes very uninteresting. */
365 #define ARM_FLAG_FPE (1 << 2)
366
367 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
368 that assume restoration of the condition flags when returning from a
369 branch and link (ie a function). */
370 #define ARM_FLAG_APCS_32 (1 << 3)
371
372 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
373
374 /* Nonzero if stack checking should be performed on entry to each function
375 which allocates temporary variables on the stack. */
376 #define ARM_FLAG_APCS_STACK (1 << 4)
377
378 /* Nonzero if floating point parameters should be passed to functions in
379 floating point registers. */
380 #define ARM_FLAG_APCS_FLOAT (1 << 5)
381
382 /* Nonzero if re-entrant, position independent code should be generated.
383 This is equivalent to -fpic. */
384 #define ARM_FLAG_APCS_REENT (1 << 6)
385
386 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
387 be loaded using either LDRH or LDRB instructions. */
388 #define ARM_FLAG_MMU_TRAPS (1 << 7)
389
390 /* Nonzero if all floating point instructions are missing (and there is no
391 emulator either). Generate function calls for all ops in this case. */
392 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
393
394 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
395 #define ARM_FLAG_BIG_END (1 << 9)
396
397 /* Nonzero if we should compile for Thumb interworking. */
398 #define ARM_FLAG_INTERWORK (1 << 10)
399
400 /* Nonzero if we should have little-endian words even when compiling for
401 big-endian (for backwards compatibility with older versions of GCC). */
402 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
403
404 /* Nonzero if we need to protect the prolog from scheduling */
405 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
406
407 /* Nonzero if a call to abort should be generated if a noreturn
408 function tries to return. */
409 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
410
411 /* Nonzero if function prologues should not load the PIC register. */
412 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
413
414 /* Nonzero if all call instructions should be indirect. */
415 #define ARM_FLAG_LONG_CALLS (1 << 15)
416
417 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
418 #define ARM_FLAG_THUMB (1 << 16)
419
420 /* Set if a TPCS style stack frame should be generated, for non-leaf
421 functions, even if they do not need one. */
422 #define THUMB_FLAG_BACKTRACE (1 << 17)
423
424 /* Set if a TPCS style stack frame should be generated, for leaf
425 functions, even if they do not need one. */
426 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
427
428 /* Set if externally visible functions should assume that they
429 might be called in ARM mode, from a non-thumb aware code. */
430 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
431
432 /* Set if calls via function pointers should assume that their
433 destination is non-Thumb aware. */
434 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
435
436 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
437 #define ARM_FLAG_ATPCS (1 << 21)
438
439 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
440 #define CIRRUS_FIX_INVALID_INSNS (1 << 22)
441
442 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
443 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
444 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
445 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
446 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
447 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
448 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
449 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
450 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
451 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
452 #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
453 #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
454 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
455 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
456 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
457 #define TARGET_IWMMXT (arm_arch_iwmmxt)
458 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
459 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
460 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
461 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
462 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
463 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
464 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
465 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
466 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
467 #define TARGET_ARM (! TARGET_THUMB)
468 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
469 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
470 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
471 #define TARGET_BACKTRACE (leaf_function_p () \
472 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
473 : (target_flags & THUMB_FLAG_BACKTRACE))
474 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
475
476 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
477 #ifndef SUBTARGET_SWITCHES
478 #define SUBTARGET_SWITCHES
479 #endif
480
481 #define TARGET_SWITCHES \
482 { \
483 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
484 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
485 N_("Generate APCS conformant stack frames") }, \
486 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
487 {"poke-function-name", ARM_FLAG_POKE, \
488 N_("Store function names in object code") }, \
489 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
490 {"fpe", ARM_FLAG_FPE, "" }, \
491 {"apcs-32", ARM_FLAG_APCS_32, \
492 N_("Use the 32-bit version of the APCS") }, \
493 {"apcs-26", -ARM_FLAG_APCS_32, \
494 N_("Use the 26-bit version of the APCS") }, \
495 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
496 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
497 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
498 N_("Pass FP arguments in FP registers") }, \
499 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
500 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
501 N_("Generate re-entrant, PIC code") }, \
502 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
503 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
504 N_("The MMU will trap on unaligned accesses") }, \
505 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
506 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
507 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
508 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
509 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
510 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
511 N_("Use library calls to perform FP operations") }, \
512 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
513 N_("Use hardware floating point instructions") }, \
514 {"big-endian", ARM_FLAG_BIG_END, \
515 N_("Assume target CPU is configured as big endian") }, \
516 {"little-endian", -ARM_FLAG_BIG_END, \
517 N_("Assume target CPU is configured as little endian") }, \
518 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
519 N_("Assume big endian bytes, little endian words") }, \
520 {"thumb-interwork", ARM_FLAG_INTERWORK, \
521 N_("Support calls between Thumb and ARM instruction sets") }, \
522 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
523 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
524 N_("Generate a call to abort if a noreturn function returns")}, \
525 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
526 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
527 N_("Do not move instructions into a function's prologue") }, \
528 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
529 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
530 N_("Do not load the PIC register in function prologues") }, \
531 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
532 {"long-calls", ARM_FLAG_LONG_CALLS, \
533 N_("Generate call insns as indirect calls, if necessary") }, \
534 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
535 {"thumb", ARM_FLAG_THUMB, \
536 N_("Compile for the Thumb not the ARM") }, \
537 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
538 {"arm", -ARM_FLAG_THUMB, "" }, \
539 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
540 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
541 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
542 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
543 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
544 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
545 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
546 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
547 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
548 "" }, \
549 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
550 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
551 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
552 "" }, \
553 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
554 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
555 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
556 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
557 SUBTARGET_SWITCHES \
558 {"", TARGET_DEFAULT, "" } \
559 }
560
561 #define TARGET_OPTIONS \
562 { \
563 {"cpu=", & arm_select[0].string, \
564 N_("Specify the name of the target CPU"), 0}, \
565 {"arch=", & arm_select[1].string, \
566 N_("Specify the name of the target architecture"), 0}, \
567 {"tune=", & arm_select[2].string, "", 0}, \
568 {"fpe=", & target_fpe_name, "", 0}, \
569 {"fp=", & target_fpe_name, "", 0}, \
570 {"fpu=", & target_fpu_name, \
571 N_("Specify the name of the target floating point hardware/format"), 0}, \
572 {"float-abi=", & target_float_abi_name, \
573 N_("Specify if floating point hardware should be used"), 0}, \
574 {"structure-size-boundary=", & structure_size_string, \
575 N_("Specify the minimum bit alignment of structures"), 0}, \
576 {"pic-register=", & arm_pic_register_string, \
577 N_("Specify the register to be used for PIC addressing"), 0} \
578 }
579
580 /* Support for a compile-time default CPU, et cetera. The rules are:
581 --with-arch is ignored if -march or -mcpu are specified.
582 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
583 by --with-arch.
584 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
585 by -march).
586 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
587 specified.
588 --with-fpu is ignored if -mfpu is specified. */
589 #define OPTION_DEFAULT_SPECS \
590 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
591 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
592 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
593 {"float", \
594 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
595 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"},
596
597 struct arm_cpu_select
598 {
599 const char * string;
600 const char * name;
601 const struct processors * processors;
602 };
603
604 /* This is a magic array. If the user specifies a command line switch
605 which matches one of the entries in TARGET_OPTIONS then the corresponding
606 string pointer will be set to the value specified by the user. */
607 extern struct arm_cpu_select arm_select[];
608
609 enum prog_mode_type
610 {
611 prog_mode26,
612 prog_mode32
613 };
614
615 /* Recast the program mode class to be the prog_mode attribute. */
616 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
617
618 extern enum prog_mode_type arm_prgmode;
619
620 /* Which floating point model to use. */
621 enum arm_fp_model
622 {
623 ARM_FP_MODEL_UNKNOWN,
624 /* FPA model (Hardware or software). */
625 ARM_FP_MODEL_FPA,
626 /* Cirrus Maverick floating point model. */
627 ARM_FP_MODEL_MAVERICK,
628 /* VFP floating point model. */
629 ARM_FP_MODEL_VFP
630 };
631
632 extern enum arm_fp_model arm_fp_model;
633
634 /* Which floating point hardware is available. Also update
635 fp_model_for_fpu in arm.c when adding entries to this list. */
636 enum fputype
637 {
638 /* No FP hardware. */
639 FPUTYPE_NONE,
640 /* Full FPA support. */
641 FPUTYPE_FPA,
642 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
643 FPUTYPE_FPA_EMU2,
644 /* Emulated FPA hardware, Issue 3 emulator. */
645 FPUTYPE_FPA_EMU3,
646 /* Cirrus Maverick floating point co-processor. */
647 FPUTYPE_MAVERICK,
648 /* VFP. */
649 FPUTYPE_VFP
650 };
651
652 /* Recast the floating point class to be the floating point attribute. */
653 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
654
655 /* What type of floating point to tune for */
656 extern enum fputype arm_fpu_tune;
657
658 /* What type of floating point instructions are available */
659 extern enum fputype arm_fpu_arch;
660
661 enum float_abi_type
662 {
663 ARM_FLOAT_ABI_SOFT,
664 ARM_FLOAT_ABI_SOFTFP,
665 ARM_FLOAT_ABI_HARD
666 };
667
668 extern enum float_abi_type arm_float_abi;
669
670 /* Default floating point architecture. Override in sub-target if
671 necessary.
672 FIXME: Is this still necessary/desirable? Do we want VFP chips to
673 default to VFP unless overridden by a subtarget? If so it would be best
674 to remove these definitions. It also assumes there is only one cpu model
675 with a Maverick fpu. */
676 #ifndef FPUTYPE_DEFAULT
677 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
678 #endif
679
680 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
681 #undef FPUTYPE_DEFAULT
682 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
683 #endif
684
685 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
686 extern int arm_arch3m;
687
688 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
689 extern int arm_arch4;
690
691 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
692 extern int arm_arch5;
693
694 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
695 extern int arm_arch5e;
696
697 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
698 extern int arm_arch6;
699
700 /* Nonzero if this chip can benefit from load scheduling. */
701 extern int arm_ld_sched;
702
703 /* Nonzero if generating thumb code. */
704 extern int thumb_code;
705
706 /* Nonzero if this chip is a StrongARM. */
707 extern int arm_is_strong;
708
709 /* Nonzero if this chip is a Cirrus variant. */
710 extern int arm_is_cirrus;
711
712 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
713 extern int arm_arch_iwmmxt;
714
715 /* Nonzero if this chip is an XScale. */
716 extern int arm_arch_xscale;
717
718 /* Nonzero if tuning for XScale */
719 extern int arm_tune_xscale;
720
721 /* Nonzero if this chip is an ARM6 or an ARM7. */
722 extern int arm_is_6_or_7;
723
724 #ifndef TARGET_DEFAULT
725 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
726 #endif
727
728 /* The frame pointer register used in gcc has nothing to do with debugging;
729 that is controlled by the APCS-FRAME option. */
730 #define CAN_DEBUG_WITHOUT_FP
731
732 #undef TARGET_MEM_FUNCTIONS
733 #define TARGET_MEM_FUNCTIONS 1
734
735 #define OVERRIDE_OPTIONS arm_override_options ()
736
737 /* Nonzero if PIC code requires explicit qualifiers to generate
738 PLT and GOT relocs rather than the assembler doing so implicitly.
739 Subtargets can override these if required. */
740 #ifndef NEED_GOT_RELOC
741 #define NEED_GOT_RELOC 0
742 #endif
743 #ifndef NEED_PLT_RELOC
744 #define NEED_PLT_RELOC 0
745 #endif
746
747 /* Nonzero if we need to refer to the GOT with a PC-relative
748 offset. In other words, generate
749
750 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
751
752 rather than
753
754 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
755
756 The default is true, which matches NetBSD. Subtargets can
757 override this if required. */
758 #ifndef GOT_PCREL
759 #define GOT_PCREL 1
760 #endif
761 \f
762 /* Target machine storage Layout. */
763
764
765 /* Define this macro if it is advisable to hold scalars in registers
766 in a wider mode than that declared by the program. In such cases,
767 the value is constrained to be within the bounds of the declared
768 type, but kept valid in the wider mode. The signedness of the
769 extension may differ from that of the type. */
770
771 /* It is far faster to zero extend chars than to sign extend them */
772
773 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
774 if (GET_MODE_CLASS (MODE) == MODE_INT \
775 && GET_MODE_SIZE (MODE) < 4) \
776 { \
777 if (MODE == QImode) \
778 UNSIGNEDP = 1; \
779 else if (MODE == HImode) \
780 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
781 (MODE) = SImode; \
782 }
783
784 /* Define this if most significant bit is lowest numbered
785 in instructions that operate on numbered bit-fields. */
786 #define BITS_BIG_ENDIAN 0
787
788 /* Define this if most significant byte of a word is the lowest numbered.
789 Most ARM processors are run in little endian mode, so that is the default.
790 If you want to have it run-time selectable, change the definition in a
791 cover file to be TARGET_BIG_ENDIAN. */
792 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
793
794 /* Define this if most significant word of a multiword number is the lowest
795 numbered.
796 This is always false, even when in big-endian mode. */
797 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
798
799 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
800 on processor pre-defineds when compiling libgcc2.c. */
801 #if defined(__ARMEB__) && !defined(__ARMWEL__)
802 #define LIBGCC2_WORDS_BIG_ENDIAN 1
803 #else
804 #define LIBGCC2_WORDS_BIG_ENDIAN 0
805 #endif
806
807 /* Define this if most significant word of doubles is the lowest numbered.
808 The rules are different based on whether or not we use FPA-format,
809 VFP-format or some other floating point co-processor's format doubles. */
810 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
811
812 #define UNITS_PER_WORD 4
813
814 #define PARM_BOUNDARY 32
815
816 #define IWMMXT_ALIGNMENT 64
817
818 #define STACK_BOUNDARY 32
819
820 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
821
822 #define FUNCTION_BOUNDARY 32
823
824 /* The lowest bit is used to indicate Thumb-mode functions, so the
825 vbit must go into the delta field of pointers to member
826 functions. */
827 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
828
829 #define EMPTY_FIELD_BOUNDARY 32
830
831 #define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32)
832
833 #define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \
834 (TARGET_REALLY_IWMMXT \
835 && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode)))
836
837 /* XXX Blah -- this macro is used directly by libobjc. Since it
838 supports no vector modes, cut out the complexity and fall back
839 on BIGGEST_FIELD_ALIGNMENT. */
840 #ifdef IN_TARGET_LIBS
841 #define BIGGEST_FIELD_ALIGNMENT 64
842 #else
843 /* An expression for the alignment of a structure field FIELD if the
844 alignment computed in the usual way is COMPUTED. GCC uses this
845 value instead of the value in `BIGGEST_ALIGNMENT' or
846 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
847 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
848 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \
849 ? IWMMXT_ALIGNMENT \
850 : (COMPUTED))
851 #endif
852
853 /* If defined, a C expression to compute the alignment for a static variable.
854 TYPE is the data type, and ALIGN is the alignment that the object
855 would ordinarily have. The value of this macro is used instead of that
856 alignment to align the object.
857
858 If this macro is not defined, then ALIGN is used. */
859 #define DATA_ALIGNMENT(TYPE, ALIGN) \
860 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
861
862 /* If defined, a C expression to compute the alignment for a
863 variables in the local store. TYPE is the data type, and
864 BASIC-ALIGN is the alignment that the object would ordinarily
865 have. The value of this macro is used instead of that alignment
866 to align the object.
867
868 If this macro is not defined, then BASIC-ALIGN is used. */
869 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
870 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
871
872 /* Make strings word-aligned so strcpy from constants will be faster. */
873 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
874
875 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
876 ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \
877 (TREE_CODE (EXP) == STRING_CST \
878 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
879 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
880
881 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
882 value set in previous versions of this toolchain was 8, which produces more
883 compact structures. The command line option -mstructure_size_boundary=<n>
884 can be used to change this value. For compatibility with the ARM SDK
885 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
886 0020D) page 2-20 says "Structures are aligned on word boundaries". */
887 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
888 extern int arm_structure_size_boundary;
889
890 /* This is the value used to initialize arm_structure_size_boundary. If a
891 particular arm target wants to change the default value it should change
892 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
893 for an example of this. */
894 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
895 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
896 #endif
897
898 /* Used when parsing command line option -mstructure_size_boundary. */
899 extern const char * structure_size_string;
900
901 /* Nonzero if move instructions will actually fail to work
902 when given unaligned data. */
903 #define STRICT_ALIGNMENT 1
904 \f
905 /* Standard register usage. */
906
907 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
908 (S - saved over call).
909
910 r0 * argument word/integer result
911 r1-r3 argument word
912
913 r4-r8 S register variable
914 r9 S (rfp) register variable (real frame pointer)
915
916 r10 F S (sl) stack limit (used by -mapcs-stack-check)
917 r11 F S (fp) argument pointer
918 r12 (ip) temp workspace
919 r13 F S (sp) lower end of current stack frame
920 r14 (lr) link address/workspace
921 r15 F (pc) program counter
922
923 f0 floating point result
924 f1-f3 floating point scratch
925
926 f4-f7 S floating point variable
927
928 cc This is NOT a real register, but is used internally
929 to represent things that use or set the condition
930 codes.
931 sfp This isn't either. It is used during rtl generation
932 since the offset between the frame pointer and the
933 auto's isn't known until after register allocation.
934 afp Nor this, we only need this because of non-local
935 goto. Without it fp appears to be used and the
936 elimination code won't get rid of sfp. It tracks
937 fp exactly at all times.
938
939 *: See CONDITIONAL_REGISTER_USAGE */
940
941 /*
942 mvf0 Cirrus floating point result
943 mvf1-mvf3 Cirrus floating point scratch
944 mvf4-mvf15 S Cirrus floating point variable. */
945
946 /* s0-s15 VFP scratch (aka d0-d7).
947 s16-s31 S VFP variable (aka d8-d15).
948 vfpcc Not a real register. Represents the VFP condition
949 code flags. */
950
951 /* The stack backtrace structure is as follows:
952 fp points to here: | save code pointer | [fp]
953 | return link value | [fp, #-4]
954 | return sp value | [fp, #-8]
955 | return fp value | [fp, #-12]
956 [| saved r10 value |]
957 [| saved r9 value |]
958 [| saved r8 value |]
959 [| saved r7 value |]
960 [| saved r6 value |]
961 [| saved r5 value |]
962 [| saved r4 value |]
963 [| saved r3 value |]
964 [| saved r2 value |]
965 [| saved r1 value |]
966 [| saved r0 value |]
967 [| saved f7 value |] three words
968 [| saved f6 value |] three words
969 [| saved f5 value |] three words
970 [| saved f4 value |] three words
971 r0-r3 are not normally saved in a C function. */
972
973 /* 1 for registers that have pervasive standard uses
974 and are not available for the register allocator. */
975 #define FIXED_REGISTERS \
976 { \
977 0,0,0,0,0,0,0,0, \
978 0,0,0,0,0,1,0,1, \
979 0,0,0,0,0,0,0,0, \
980 1,1,1, \
981 1,1,1,1,1,1,1,1, \
982 1,1,1,1,1,1,1,1, \
983 1,1,1,1,1,1,1,1, \
984 1,1,1,1,1,1,1,1, \
985 1,1,1,1, \
986 1,1,1,1,1,1,1,1, \
987 1,1,1,1,1,1,1,1, \
988 1,1,1,1,1,1,1,1, \
989 1,1,1,1,1,1,1,1, \
990 1 \
991 }
992
993 /* 1 for registers not available across function calls.
994 These must include the FIXED_REGISTERS and also any
995 registers that can be used without being saved.
996 The latter must include the registers where values are returned
997 and the register where structure-value addresses are passed.
998 Aside from that, you can include as many other registers as you like.
999 The CC is not preserved over function calls on the ARM 6, so it is
1000 easier to assume this for all. SFP is preserved, since FP is. */
1001 #define CALL_USED_REGISTERS \
1002 { \
1003 1,1,1,1,0,0,0,0, \
1004 0,0,0,0,1,1,1,1, \
1005 1,1,1,1,0,0,0,0, \
1006 1,1,1, \
1007 1,1,1,1,1,1,1,1, \
1008 1,1,1,1,1,1,1,1, \
1009 1,1,1,1,1,1,1,1, \
1010 1,1,1,1,1,1,1,1, \
1011 1,1,1,1, \
1012 1,1,1,1,1,1,1,1, \
1013 1,1,1,1,1,1,1,1, \
1014 1,1,1,1,1,1,1,1, \
1015 1,1,1,1,1,1,1,1, \
1016 1 \
1017 }
1018
1019 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
1020 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
1021 #endif
1022
1023 #define CONDITIONAL_REGISTER_USAGE \
1024 { \
1025 int regno; \
1026 \
1027 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
1028 { \
1029 for (regno = FIRST_FPA_REGNUM; \
1030 regno <= LAST_FPA_REGNUM; ++regno) \
1031 fixed_regs[regno] = call_used_regs[regno] = 1; \
1032 } \
1033 \
1034 if (TARGET_THUMB && optimize_size) \
1035 { \
1036 /* When optimizing for size, it's better not to use \
1037 the HI regs, because of the overhead of stacking \
1038 them. */ \
1039 for (regno = FIRST_HI_REGNUM; \
1040 regno <= LAST_HI_REGNUM; ++regno) \
1041 fixed_regs[regno] = call_used_regs[regno] = 1; \
1042 } \
1043 \
1044 /* The link register can be clobbered by any branch insn, \
1045 but we have no way to track that at present, so mark \
1046 it as unavailable. */ \
1047 if (TARGET_THUMB) \
1048 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
1049 \
1050 if (TARGET_ARM && TARGET_HARD_FLOAT) \
1051 { \
1052 if (TARGET_MAVERICK) \
1053 { \
1054 for (regno = FIRST_FPA_REGNUM; \
1055 regno <= LAST_FPA_REGNUM; ++ regno) \
1056 fixed_regs[regno] = call_used_regs[regno] = 1; \
1057 for (regno = FIRST_CIRRUS_FP_REGNUM; \
1058 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
1059 { \
1060 fixed_regs[regno] = 0; \
1061 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
1062 } \
1063 } \
1064 if (TARGET_VFP) \
1065 { \
1066 for (regno = FIRST_VFP_REGNUM; \
1067 regno <= LAST_VFP_REGNUM; ++ regno) \
1068 { \
1069 fixed_regs[regno] = 0; \
1070 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
1071 } \
1072 } \
1073 } \
1074 \
1075 if (TARGET_REALLY_IWMMXT) \
1076 { \
1077 regno = FIRST_IWMMXT_GR_REGNUM; \
1078 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
1079 and wCG1 as call-preserved registers. The 2002/11/21 \
1080 revision changed this so that all wCG registers are \
1081 scratch registers. */ \
1082 for (regno = FIRST_IWMMXT_GR_REGNUM; \
1083 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
1084 fixed_regs[regno] = call_used_regs[regno] = 0; \
1085 /* The XScale ABI has wR0 - wR9 as scratch registers, \
1086 the rest as call-preserved registers. */ \
1087 for (regno = FIRST_IWMMXT_REGNUM; \
1088 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
1089 { \
1090 fixed_regs[regno] = 0; \
1091 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
1092 } \
1093 } \
1094 \
1095 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1096 { \
1097 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1098 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1099 } \
1100 else if (TARGET_APCS_STACK) \
1101 { \
1102 fixed_regs[10] = 1; \
1103 call_used_regs[10] = 1; \
1104 } \
1105 if (TARGET_APCS_FRAME) \
1106 { \
1107 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1108 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1109 } \
1110 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
1111 }
1112
1113 /* These are a couple of extensions to the formats accepted
1114 by asm_fprintf:
1115 %@ prints out ASM_COMMENT_START
1116 %r prints out REGISTER_PREFIX reg_names[arg] */
1117 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
1118 case '@': \
1119 fputs (ASM_COMMENT_START, FILE); \
1120 break; \
1121 \
1122 case 'r': \
1123 fputs (REGISTER_PREFIX, FILE); \
1124 fputs (reg_names [va_arg (ARGS, int)], FILE); \
1125 break;
1126
1127 /* Round X up to the nearest word. */
1128 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
1129
1130 /* Convert fron bytes to ints. */
1131 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1132
1133 /* The number of (integer) registers required to hold a quantity of type MODE.
1134 Also used for VFP registers. */
1135 #define ARM_NUM_REGS(MODE) \
1136 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
1137
1138 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
1139 #define ARM_NUM_REGS2(MODE, TYPE) \
1140 ARM_NUM_INTS ((MODE) == BLKmode ? \
1141 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1142
1143 /* The number of (integer) argument register available. */
1144 #define NUM_ARG_REGS 4
1145
1146 /* Return the register number of the N'th (integer) argument. */
1147 #define ARG_REGISTER(N) (N - 1)
1148
1149 /* Specify the registers used for certain standard purposes.
1150 The values of these macros are register numbers. */
1151
1152 /* The number of the last argument register. */
1153 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
1154
1155 /* The numbers of the Thumb register ranges. */
1156 #define FIRST_LO_REGNUM 0
1157 #define LAST_LO_REGNUM 7
1158 #define FIRST_HI_REGNUM 8
1159 #define LAST_HI_REGNUM 11
1160
1161 /* The register that holds the return address in exception handlers. */
1162 #define EXCEPTION_LR_REGNUM 2
1163
1164 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1165 as an invisible last argument (possible since varargs don't exist in
1166 Pascal), so the following is not true. */
1167 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1168
1169 /* Define this to be where the real frame pointer is if it is not possible to
1170 work out the offset between the frame pointer and the automatic variables
1171 until after register allocation has taken place. FRAME_POINTER_REGNUM
1172 should point to a special register that we will make sure is eliminated.
1173
1174 For the Thumb we have another problem. The TPCS defines the frame pointer
1175 as r11, and GCC believes that it is always possible to use the frame pointer
1176 as base register for addressing purposes. (See comments in
1177 find_reloads_address()). But - the Thumb does not allow high registers,
1178 including r11, to be used as base address registers. Hence our problem.
1179
1180 The solution used here, and in the old thumb port is to use r7 instead of
1181 r11 as the hard frame pointer and to have special code to generate
1182 backtrace structures on the stack (if required to do so via a command line
1183 option) using r11. This is the only 'user visible' use of r11 as a frame
1184 pointer. */
1185 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1186 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1187
1188 #define HARD_FRAME_POINTER_REGNUM \
1189 (TARGET_ARM \
1190 ? ARM_HARD_FRAME_POINTER_REGNUM \
1191 : THUMB_HARD_FRAME_POINTER_REGNUM)
1192
1193 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1194
1195 /* Register to use for pushing function arguments. */
1196 #define STACK_POINTER_REGNUM SP_REGNUM
1197
1198 /* ARM floating pointer registers. */
1199 #define FIRST_FPA_REGNUM 16
1200 #define LAST_FPA_REGNUM 23
1201
1202 #define FIRST_IWMMXT_GR_REGNUM 43
1203 #define LAST_IWMMXT_GR_REGNUM 46
1204 #define FIRST_IWMMXT_REGNUM 47
1205 #define LAST_IWMMXT_REGNUM 62
1206 #define IS_IWMMXT_REGNUM(REGNUM) \
1207 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1208 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1209 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1210
1211 /* Base register for access to local variables of the function. */
1212 #define FRAME_POINTER_REGNUM 25
1213
1214 /* Base register for access to arguments of the function. */
1215 #define ARG_POINTER_REGNUM 26
1216
1217 #define FIRST_CIRRUS_FP_REGNUM 27
1218 #define LAST_CIRRUS_FP_REGNUM 42
1219 #define IS_CIRRUS_REGNUM(REGNUM) \
1220 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1221
1222 #define FIRST_VFP_REGNUM 63
1223 #define LAST_VFP_REGNUM 94
1224 #define IS_VFP_REGNUM(REGNUM) \
1225 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1226
1227 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1228 /* + 16 Cirrus registers take us up to 43. */
1229 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1230 /* VFP adds 32 + 1 more. */
1231 #define FIRST_PSEUDO_REGISTER 96
1232
1233 /* Value should be nonzero if functions must have frame pointers.
1234 Zero means the frame pointer need not be set up (and parms may be accessed
1235 via the stack pointer) in functions that seem suitable.
1236 If we have to have a frame pointer we might as well make use of it.
1237 APCS says that the frame pointer does not need to be pushed in leaf
1238 functions, or simple tail call functions. */
1239 #define FRAME_POINTER_REQUIRED \
1240 (current_function_has_nonlocal_label \
1241 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1242
1243 /* Return number of consecutive hard regs needed starting at reg REGNO
1244 to hold something of mode MODE.
1245 This is ordinarily the length in words of a value of mode MODE
1246 but can be less for certain modes in special long registers.
1247
1248 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1249 mode. */
1250 #define HARD_REGNO_NREGS(REGNO, MODE) \
1251 ((TARGET_ARM \
1252 && REGNO >= FIRST_FPA_REGNUM \
1253 && REGNO != FRAME_POINTER_REGNUM \
1254 && REGNO != ARG_POINTER_REGNUM) \
1255 && !IS_VFP_REGNUM (REGNO) \
1256 ? 1 : ARM_NUM_REGS (MODE))
1257
1258 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1259 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1260 arm_hard_regno_mode_ok ((REGNO), (MODE))
1261
1262 /* Value is 1 if it is a good idea to tie two pseudo registers
1263 when one has mode MODE1 and one has mode MODE2.
1264 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1265 for any hard reg, then this must be 0 for correct output. */
1266 #define MODES_TIEABLE_P(MODE1, MODE2) \
1267 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1268
1269 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1270 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1271
1272 #define VALID_IWMMXT_REG_MODE(MODE) \
1273 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1274
1275 /* The order in which register should be allocated. It is good to use ip
1276 since no saving is required (though calls clobber it) and it never contains
1277 function parameters. It is quite good to use lr since other calls may
1278 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1279 least likely to contain a function parameter; in addition results are
1280 returned in r0. */
1281
1282 #define REG_ALLOC_ORDER \
1283 { \
1284 3, 2, 1, 0, 12, 14, 4, 5, \
1285 6, 7, 8, 10, 9, 11, 13, 15, \
1286 16, 17, 18, 19, 20, 21, 22, 23, \
1287 27, 28, 29, 30, 31, 32, 33, 34, \
1288 35, 36, 37, 38, 39, 40, 41, 42, \
1289 43, 44, 45, 46, 47, 48, 49, 50, \
1290 51, 52, 53, 54, 55, 56, 57, 58, \
1291 59, 60, 61, 62, \
1292 24, 25, 26, \
1293 78, 77, 76, 75, 74, 73, 72, 71, \
1294 70, 69, 68, 67, 66, 65, 64, 63, \
1295 79, 80, 81, 82, 83, 84, 85, 86, \
1296 87, 88, 89, 90, 91, 92, 93, 94, \
1297 95 \
1298 }
1299
1300 /* Interrupt functions can only use registers that have already been
1301 saved by the prologue, even if they would normally be
1302 call-clobbered. */
1303 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1304 (! IS_INTERRUPT (cfun->machine->func_type) || \
1305 regs_ever_live[DST])
1306 \f
1307 /* Register and constant classes. */
1308
1309 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1310 Now that the Thumb is involved it has become more complicated. */
1311 enum reg_class
1312 {
1313 NO_REGS,
1314 FPA_REGS,
1315 CIRRUS_REGS,
1316 VFP_REGS,
1317 IWMMXT_GR_REGS,
1318 IWMMXT_REGS,
1319 LO_REGS,
1320 STACK_REG,
1321 BASE_REGS,
1322 HI_REGS,
1323 CC_REG,
1324 VFPCC_REG,
1325 GENERAL_REGS,
1326 ALL_REGS,
1327 LIM_REG_CLASSES
1328 };
1329
1330 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1331
1332 /* Give names of register classes as strings for dump file. */
1333 #define REG_CLASS_NAMES \
1334 { \
1335 "NO_REGS", \
1336 "FPA_REGS", \
1337 "CIRRUS_REGS", \
1338 "VFP_REGS", \
1339 "IWMMXT_GR_REGS", \
1340 "IWMMXT_REGS", \
1341 "LO_REGS", \
1342 "STACK_REG", \
1343 "BASE_REGS", \
1344 "HI_REGS", \
1345 "CC_REG", \
1346 "VFPCC_REG", \
1347 "GENERAL_REGS", \
1348 "ALL_REGS", \
1349 }
1350
1351 /* Define which registers fit in which classes.
1352 This is an initializer for a vector of HARD_REG_SET
1353 of length N_REG_CLASSES. */
1354 #define REG_CLASS_CONTENTS \
1355 { \
1356 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1357 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1358 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1359 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1360 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1361 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1362 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1363 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1364 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1365 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1366 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1367 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1368 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1369 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1370 }
1371
1372 /* The same information, inverted:
1373 Return the class number of the smallest class containing
1374 reg number REGNO. This could be a conditional expression
1375 or could index an array. */
1376 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1377
1378 /* FPA registers can't do subreg as all values are reformatted to internal
1379 precision. VFP registers may only be accessed in the mode they
1380 were set. */
1381 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1382 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1383 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1384 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1385 : 0)
1386
1387 /* The class value for index registers, and the one for base regs. */
1388 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1389 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1390
1391 /* For the Thumb the high registers cannot be used as base registers
1392 when addressing quantities in QI or HI mode; if we don't know the
1393 mode, then we must be conservative. After reload we must also be
1394 conservative, since we can't support SP+reg addressing, and we
1395 can't fix up any bad substitutions. */
1396 #define MODE_BASE_REG_CLASS(MODE) \
1397 (TARGET_ARM ? GENERAL_REGS : \
1398 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1399
1400 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1401 registers explicitly used in the rtl to be used as spill registers
1402 but prevents the compiler from extending the lifetime of these
1403 registers. */
1404 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1405
1406 /* Get reg_class from a letter such as appears in the machine description.
1407 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1408 ARM, but several more letters for the Thumb. */
1409 #define REG_CLASS_FROM_LETTER(C) \
1410 ( (C) == 'f' ? FPA_REGS \
1411 : (C) == 'v' ? CIRRUS_REGS \
1412 : (C) == 'w' ? VFP_REGS \
1413 : (C) == 'y' ? IWMMXT_REGS \
1414 : (C) == 'z' ? IWMMXT_GR_REGS \
1415 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1416 : TARGET_ARM ? NO_REGS \
1417 : (C) == 'h' ? HI_REGS \
1418 : (C) == 'b' ? BASE_REGS \
1419 : (C) == 'k' ? STACK_REG \
1420 : (C) == 'c' ? CC_REG \
1421 : NO_REGS)
1422
1423 /* The letters I, J, K, L and M in a register constraint string
1424 can be used to stand for particular ranges of immediate operands.
1425 This macro defines what the ranges are.
1426 C is the letter, and VALUE is a constant value.
1427 Return 1 if VALUE is in the range specified by C.
1428 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1429 J: valid indexing constants.
1430 K: ~value ok in rhs argument of data operand.
1431 L: -value ok in rhs argument of data operand.
1432 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1433 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1434 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1435 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1436 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1437 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1438 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1439 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1440 : 0)
1441
1442 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1443 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1444 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1445 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1446 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1447 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1448 && ((VAL) & 3) == 0) : \
1449 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1450 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1451 : 0)
1452
1453 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1454 (TARGET_ARM ? \
1455 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1456
1457 /* Constant letter 'G' for the FP immediate constants.
1458 'H' means the same constant negated. */
1459 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1460 ((C) == 'G' ? arm_const_double_rtx (X) : \
1461 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1462
1463 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1464 (TARGET_ARM ? \
1465 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1466
1467 /* For the ARM, `Q' means that this is a memory operand that is just
1468 an offset from a register.
1469 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1470 address. This means that the symbol is in the text segment and can be
1471 accessed without using a load.
1472 'U' Prefixes an extended memory constraint where:
1473 'Uv' is an address valid for VFP load/store insns.
1474 'Uq' is an address valid for ldrsb. */
1475
1476 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1477 (((C) == 'Q') ? (GET_CODE (OP) == MEM \
1478 && GET_CODE (XEXP (OP, 0)) == REG) : \
1479 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1480 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1481 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1482 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1483 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1484 ((C) == 'U' && (STR)[1] == 'v') ? vfp_mem_operand (OP) : \
1485 ((C) == 'U' && (STR)[1] == 'q') \
1486 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1487 : 0)
1488
1489 #define CONSTRAINT_LEN(C,STR) \
1490 ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1491
1492 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1493 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1494 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1495
1496 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1497 (TARGET_ARM \
1498 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1499 : EXTRA_CONSTRAINT_THUMB (X, C))
1500
1501 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1502
1503 /* Given an rtx X being reloaded into a reg required to be
1504 in class CLASS, return the class of reg to actually use.
1505 In general this is just CLASS, but for the Thumb we prefer
1506 a LO_REGS class or a subset. */
1507 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1508 (TARGET_ARM ? (CLASS) : \
1509 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1510
1511 /* Must leave BASE_REGS reloads alone */
1512 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1513 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1514 ? ((true_regnum (X) == -1 ? LO_REGS \
1515 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1516 : NO_REGS)) \
1517 : NO_REGS)
1518
1519 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1520 ((CLASS) != LO_REGS \
1521 ? ((true_regnum (X) == -1 ? LO_REGS \
1522 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1523 : NO_REGS)) \
1524 : NO_REGS)
1525
1526 /* Return the register class of a scratch register needed to copy IN into
1527 or out of a register in CLASS in MODE. If it can be done directly,
1528 NO_REGS is returned. */
1529 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1530 /* Restrict which direct reloads are allowed for VFP regs. */ \
1531 ((TARGET_VFP && TARGET_HARD_FLOAT \
1532 && (CLASS) == VFP_REGS) \
1533 ? vfp_secondary_reload_class (MODE, X) \
1534 : TARGET_ARM \
1535 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1536 ? GENERAL_REGS : NO_REGS) \
1537 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1538
1539 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1540 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1541 /* Restrict which direct reloads are allowed for VFP regs. */ \
1542 ((TARGET_VFP && TARGET_HARD_FLOAT \
1543 && (CLASS) == VFP_REGS) \
1544 ? vfp_secondary_reload_class (MODE, X) : \
1545 /* Cannot load constants into Cirrus registers. */ \
1546 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1547 && (CLASS) == CIRRUS_REGS \
1548 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1549 ? GENERAL_REGS : \
1550 (TARGET_ARM ? \
1551 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1552 && CONSTANT_P (X)) \
1553 ? GENERAL_REGS : \
1554 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1555 && (GET_CODE (X) == MEM \
1556 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1557 && true_regnum (X) == -1))) \
1558 ? GENERAL_REGS : NO_REGS) \
1559 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1560
1561 /* Try a machine-dependent way of reloading an illegitimate address
1562 operand. If we find one, push the reload and jump to WIN. This
1563 macro is used in only one place: `find_reloads_address' in reload.c.
1564
1565 For the ARM, we wish to handle large displacements off a base
1566 register by splitting the addend across a MOV and the mem insn.
1567 This can cut the number of reloads needed. */
1568 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1569 do \
1570 { \
1571 if (GET_CODE (X) == PLUS \
1572 && GET_CODE (XEXP (X, 0)) == REG \
1573 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1574 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1575 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1576 { \
1577 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1578 HOST_WIDE_INT low, high; \
1579 \
1580 if (MODE == DImode || (TARGET_SOFT_FLOAT && TARGET_FPA \
1581 && MODE == DFmode)) \
1582 low = ((val & 0xf) ^ 0x8) - 0x8; \
1583 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1584 /* Need to be careful, -256 is not a valid offset. */ \
1585 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1586 else if (MODE == SImode \
1587 || (MODE == SFmode && TARGET_SOFT_FLOAT && TARGET_FPA) \
1588 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1589 /* Need to be careful, -4096 is not a valid offset. */ \
1590 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1591 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1592 /* Need to be careful, -256 is not a valid offset. */ \
1593 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1594 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1595 && TARGET_HARD_FLOAT && TARGET_FPA) \
1596 /* Need to be careful, -1024 is not a valid offset. */ \
1597 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1598 else \
1599 break; \
1600 \
1601 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1602 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1603 - (unsigned HOST_WIDE_INT) 0x80000000); \
1604 /* Check for overflow or zero */ \
1605 if (low == 0 || high == 0 || (high + low != val)) \
1606 break; \
1607 \
1608 /* Reload the high part into a base reg; leave the low part \
1609 in the mem. */ \
1610 X = gen_rtx_PLUS (GET_MODE (X), \
1611 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1612 GEN_INT (high)), \
1613 GEN_INT (low)); \
1614 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1615 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1616 VOIDmode, 0, 0, OPNUM, TYPE); \
1617 goto WIN; \
1618 } \
1619 } \
1620 while (0)
1621
1622 /* XXX If an HImode FP+large_offset address is converted to an HImode
1623 SP+large_offset address, then reload won't know how to fix it. It sees
1624 only that SP isn't valid for HImode, and so reloads the SP into an index
1625 register, but the resulting address is still invalid because the offset
1626 is too big. We fix it here instead by reloading the entire address. */
1627 /* We could probably achieve better results by defining PROMOTE_MODE to help
1628 cope with the variances between the Thumb's signed and unsigned byte and
1629 halfword load instructions. */
1630 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1631 { \
1632 if (GET_CODE (X) == PLUS \
1633 && GET_MODE_SIZE (MODE) < 4 \
1634 && GET_CODE (XEXP (X, 0)) == REG \
1635 && XEXP (X, 0) == stack_pointer_rtx \
1636 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1637 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1638 { \
1639 rtx orig_X = X; \
1640 X = copy_rtx (X); \
1641 push_reload (orig_X, NULL_RTX, &X, NULL, \
1642 MODE_BASE_REG_CLASS (MODE), \
1643 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1644 goto WIN; \
1645 } \
1646 }
1647
1648 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1649 if (TARGET_ARM) \
1650 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1651 else \
1652 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1653
1654 /* Return the maximum number of consecutive registers
1655 needed to represent mode MODE in a register of class CLASS.
1656 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1657 #define CLASS_MAX_NREGS(CLASS, MODE) \
1658 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1659
1660 /* If defined, gives a class of registers that cannot be used as the
1661 operand of a SUBREG that changes the mode of the object illegally. */
1662
1663 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1664 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1665 (TARGET_ARM ? \
1666 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1667 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1668 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1669 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1670 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1671 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1672 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1673 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1674 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1675 2) \
1676 : \
1677 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1678 \f
1679 /* Stack layout; function entry, exit and calling. */
1680
1681 /* Define this if pushing a word on the stack
1682 makes the stack pointer a smaller address. */
1683 #define STACK_GROWS_DOWNWARD 1
1684
1685 /* Define this if the nominal address of the stack frame
1686 is at the high-address end of the local variables;
1687 that is, each additional local variable allocated
1688 goes at a more negative offset in the frame. */
1689 #define FRAME_GROWS_DOWNWARD 1
1690
1691 /* Offset within stack frame to start allocating local variables at.
1692 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1693 first local allocated. Otherwise, it is the offset to the BEGINNING
1694 of the first local allocated. */
1695 #define STARTING_FRAME_OFFSET 0
1696
1697 /* If we generate an insn to push BYTES bytes,
1698 this says how many the stack pointer really advances by. */
1699 /* The push insns do not do this rounding implicitly.
1700 So don't define this. */
1701 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1702
1703 /* Define this if the maximum size of all the outgoing args is to be
1704 accumulated and pushed during the prologue. The amount can be
1705 found in the variable current_function_outgoing_args_size. */
1706 #define ACCUMULATE_OUTGOING_ARGS 1
1707
1708 /* Offset of first parameter from the argument pointer register value. */
1709 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1710
1711 /* Value is the number of byte of arguments automatically
1712 popped when returning from a subroutine call.
1713 FUNDECL is the declaration node of the function (as a tree),
1714 FUNTYPE is the data type of the function (as a tree),
1715 or for a library call it is an identifier node for the subroutine name.
1716 SIZE is the number of bytes of arguments passed on the stack.
1717
1718 On the ARM, the caller does not pop any of its arguments that were passed
1719 on the stack. */
1720 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1721
1722 /* Define how to find the value returned by a library function
1723 assuming the value has mode MODE. */
1724 #define LIBCALL_VALUE(MODE) \
1725 (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
1726 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1727 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1728 : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
1729 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1730 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1731 : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \
1732 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1733 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1734
1735 /* Define how to find the value returned by a function.
1736 VALTYPE is the data type of the value (as a tree).
1737 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1738 otherwise, FUNC is 0. */
1739 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1740 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1741
1742 /* 1 if N is a possible register number for a function value.
1743 On the ARM, only r0 and f0 can return results. */
1744 /* On a Cirrus chip, mvf0 can return results. */
1745 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1746 ((REGNO) == ARG_REGISTER (1) \
1747 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1748 && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
1749 || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \
1750 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1751 && TARGET_HARD_FLOAT && TARGET_FPA))
1752
1753 /* How large values are returned */
1754 /* A C expression which can inhibit the returning of certain function values
1755 in registers, based on the type of value. */
1756 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1757
1758 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1759 values must be in memory. On the ARM, they need only do so if larger
1760 than a word, or if they contain elements offset from zero in the struct. */
1761 #define DEFAULT_PCC_STRUCT_RETURN 0
1762
1763 /* Flags for the call/call_value rtl operations set up by function_arg. */
1764 #define CALL_NORMAL 0x00000000 /* No special processing. */
1765 #define CALL_LONG 0x00000001 /* Always call indirect. */
1766 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1767
1768 /* These bits describe the different types of function supported
1769 by the ARM backend. They are exclusive. ie a function cannot be both a
1770 normal function and an interworked function, for example. Knowing the
1771 type of a function is important for determining its prologue and
1772 epilogue sequences.
1773 Note value 7 is currently unassigned. Also note that the interrupt
1774 function types all have bit 2 set, so that they can be tested for easily.
1775 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1776 machine_function structure is initialized (to zero) func_type will
1777 default to unknown. This will force the first use of arm_current_func_type
1778 to call arm_compute_func_type. */
1779 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1780 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1781 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1782 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1783 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1784 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1785 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1786
1787 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1788
1789 /* In addition functions can have several type modifiers,
1790 outlined by these bit masks: */
1791 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1792 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1793 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1794 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1795
1796 /* Some macros to test these flags. */
1797 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1798 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1799 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1800 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1801 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1802
1803 /* A C structure for machine-specific, per-function data.
1804 This is added to the cfun structure. */
1805 typedef struct machine_function GTY(())
1806 {
1807 /* Additional stack adjustment in __builtin_eh_throw. */
1808 rtx eh_epilogue_sp_ofs;
1809 /* Records if LR has to be saved for far jumps. */
1810 int far_jump_used;
1811 /* Records if ARG_POINTER was ever live. */
1812 int arg_pointer_live;
1813 /* Records if the save of LR has been eliminated. */
1814 int lr_save_eliminated;
1815 /* The size of the stack frame. Only valid after reload. */
1816 int frame_size;
1817 /* Records the type of the current function. */
1818 unsigned long func_type;
1819 /* Record if the function has a variable argument list. */
1820 int uses_anonymous_args;
1821 /* Records if sibcalls are blocked because an argument
1822 register is needed to preserve stack alignment. */
1823 int sibcall_blocked;
1824 }
1825 machine_function;
1826
1827 /* A C type for declaring a variable that is used as the first argument of
1828 `FUNCTION_ARG' and other related values. For some target machines, the
1829 type `int' suffices and can hold the number of bytes of argument so far. */
1830 typedef struct
1831 {
1832 /* This is the number of registers of arguments scanned so far. */
1833 int nregs;
1834 /* This is the number of iWMMXt register arguments scanned so far. */
1835 int iwmmxt_nregs;
1836 int named_count;
1837 int nargs;
1838 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1839 int call_cookie;
1840 } CUMULATIVE_ARGS;
1841
1842 /* Define where to put the arguments to a function.
1843 Value is zero to push the argument on the stack,
1844 or a hard register in which to store the argument.
1845
1846 MODE is the argument's machine mode.
1847 TYPE is the data type of the argument (as a tree).
1848 This is null for libcalls where that information may
1849 not be available.
1850 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1851 the preceding args and about the function being called.
1852 NAMED is nonzero if this argument is a named parameter
1853 (otherwise it is an extra parameter matching an ellipsis).
1854
1855 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1856 other arguments are passed on the stack. If (NAMED == 0) (which happens
1857 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1858 defined), say it is passed in the stack (function_prologue will
1859 indeed make it pass in the stack if necessary). */
1860 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1861 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1862
1863 /* For an arg passed partly in registers and partly in memory,
1864 this is the number of registers used.
1865 For args passed entirely in registers or entirely in memory, zero. */
1866 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1867 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1868 NUM_ARG_REGS > (CUM).nregs \
1869 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1870 ? NUM_ARG_REGS - (CUM).nregs : 0)
1871
1872 /* A C expression that indicates when an argument must be passed by
1873 reference. If nonzero for an argument, a copy of that argument is
1874 made in memory and a pointer to the argument is passed instead of
1875 the argument itself. The pointer is passed in whatever way is
1876 appropriate for passing a pointer to that type. */
1877 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1878 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1879
1880 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1881 for a call to a function whose data type is FNTYPE.
1882 For a library call, FNTYPE is 0.
1883 On the ARM, the offset starts at 0. */
1884 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1885 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1886
1887 /* Update the data in CUM to advance over an argument
1888 of mode MODE and data type TYPE.
1889 (TYPE is null for libcalls where that information may not be available.) */
1890 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1891 (CUM).nargs += 1; \
1892 if (VECTOR_MODE_SUPPORTED_P (MODE)) \
1893 if ((CUM).named_count <= (CUM).nargs) \
1894 (CUM).nregs += 2; \
1895 else \
1896 (CUM).iwmmxt_nregs += 1; \
1897 else \
1898 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1899
1900 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1901 argument with the specified mode and type. If it is not defined,
1902 `PARM_BOUNDARY' is used for all arguments. */
1903 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1904 (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \
1905 ? IWMMXT_ALIGNMENT : PARM_BOUNDARY)
1906
1907 /* 1 if N is a possible register number for function argument passing.
1908 On the ARM, r0-r3 are used to pass args. */
1909 #define FUNCTION_ARG_REGNO_P(REGNO) \
1910 (IN_RANGE ((REGNO), 0, 3) \
1911 || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1912
1913 /* Implement `va_arg'. */
1914 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1915 arm_va_arg (valist, type)
1916
1917 \f
1918 /* If your target environment doesn't prefix user functions with an
1919 underscore, you may wish to re-define this to prevent any conflicts.
1920 e.g. AOF may prefix mcount with an underscore. */
1921 #ifndef ARM_MCOUNT_NAME
1922 #define ARM_MCOUNT_NAME "*mcount"
1923 #endif
1924
1925 /* Call the function profiler with a given profile label. The Acorn
1926 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1927 On the ARM the full profile code will look like:
1928 .data
1929 LP1
1930 .word 0
1931 .text
1932 mov ip, lr
1933 bl mcount
1934 .word LP1
1935
1936 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1937 will output the .text section.
1938
1939 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1940 ``prof'' doesn't seem to mind about this!
1941
1942 Note - this version of the code is designed to work in both ARM and
1943 Thumb modes. */
1944 #ifndef ARM_FUNCTION_PROFILER
1945 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1946 { \
1947 char temp[20]; \
1948 rtx sym; \
1949 \
1950 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1951 IP_REGNUM, LR_REGNUM); \
1952 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1953 fputc ('\n', STREAM); \
1954 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1955 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1956 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1957 }
1958 #endif
1959
1960 #ifdef THUMB_FUNCTION_PROFILER
1961 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1962 if (TARGET_ARM) \
1963 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1964 else \
1965 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1966 #else
1967 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1968 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1969 #endif
1970
1971 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1972 the stack pointer does not matter. The value is tested only in
1973 functions that have frame pointers.
1974 No definition is equivalent to always zero.
1975
1976 On the ARM, the function epilogue recovers the stack pointer from the
1977 frame. */
1978 #define EXIT_IGNORE_STACK 1
1979
1980 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1981
1982 /* Determine if the epilogue should be output as RTL.
1983 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1984 #define USE_RETURN_INSN(ISCOND) \
1985 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1986
1987 /* Definitions for register eliminations.
1988
1989 This is an array of structures. Each structure initializes one pair
1990 of eliminable registers. The "from" register number is given first,
1991 followed by "to". Eliminations of the same "from" register are listed
1992 in order of preference.
1993
1994 We have two registers that can be eliminated on the ARM. First, the
1995 arg pointer register can often be eliminated in favor of the stack
1996 pointer register. Secondly, the pseudo frame pointer register can always
1997 be eliminated; it is replaced with either the stack or the real frame
1998 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1999 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
2000
2001 #define ELIMINABLE_REGS \
2002 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
2003 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
2004 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
2005 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
2006 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
2007 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
2008 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
2009
2010 /* Given FROM and TO register numbers, say whether this elimination is
2011 allowed. Frame pointer elimination is automatically handled.
2012
2013 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
2014 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
2015 pointer, we must eliminate FRAME_POINTER_REGNUM into
2016 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
2017 ARG_POINTER_REGNUM. */
2018 #define CAN_ELIMINATE(FROM, TO) \
2019 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
2020 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
2021 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
2022 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
2023 1)
2024
2025 #define THUMB_REG_PUSHED_P(reg) \
2026 (regs_ever_live [reg] \
2027 && (! call_used_regs [reg] \
2028 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
2029 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
2030
2031 /* Define the offset between two registers, one to be eliminated, and the
2032 other its replacement, at the start of a routine. */
2033 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2034 do \
2035 { \
2036 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
2037 } \
2038 while (0)
2039
2040 /* Note: This macro must match the code in thumb_function_prologue(). */
2041 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2042 { \
2043 (OFFSET) = 0; \
2044 if ((FROM) == ARG_POINTER_REGNUM) \
2045 { \
2046 int count_regs = 0; \
2047 int regno; \
2048 for (regno = 8; regno < 13; regno ++) \
2049 if (THUMB_REG_PUSHED_P (regno)) \
2050 count_regs ++; \
2051 if (count_regs) \
2052 (OFFSET) += 4 * count_regs; \
2053 count_regs = 0; \
2054 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
2055 if (THUMB_REG_PUSHED_P (regno)) \
2056 count_regs ++; \
2057 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
2058 (OFFSET) += 4 * (count_regs + 1); \
2059 if (TARGET_BACKTRACE) \
2060 { \
2061 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
2062 (OFFSET) += 20; \
2063 else \
2064 (OFFSET) += 16; \
2065 } \
2066 } \
2067 if ((TO) == STACK_POINTER_REGNUM) \
2068 { \
2069 (OFFSET) += current_function_outgoing_args_size; \
2070 (OFFSET) += thumb_get_frame_size (); \
2071 } \
2072 }
2073
2074 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2075 if (TARGET_ARM) \
2076 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
2077 else \
2078 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
2079
2080 /* Special case handling of the location of arguments passed on the stack. */
2081 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
2082
2083 /* Initialize data used by insn expanders. This is called from insn_emit,
2084 once for every function before code is generated. */
2085 #define INIT_EXPANDERS arm_init_expanders ()
2086
2087 /* Output assembler code for a block containing the constant parts
2088 of a trampoline, leaving space for the variable parts.
2089
2090 On the ARM, (if r8 is the static chain regnum, and remembering that
2091 referencing pc adds an offset of 8) the trampoline looks like:
2092 ldr r8, [pc, #0]
2093 ldr pc, [pc]
2094 .word static chain value
2095 .word function's address
2096 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
2097 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
2098 { \
2099 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
2100 STATIC_CHAIN_REGNUM, PC_REGNUM); \
2101 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
2102 PC_REGNUM, PC_REGNUM); \
2103 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
2104 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
2105 }
2106
2107 /* On the Thumb we always switch into ARM mode to execute the trampoline.
2108 Why - because it is easier. This code will always be branched to via
2109 a BX instruction and since the compiler magically generates the address
2110 of the function the linker has no opportunity to ensure that the
2111 bottom bit is set. Thus the processor will be in ARM mode when it
2112 reaches this code. So we duplicate the ARM trampoline code and add
2113 a switch into Thumb mode as well. */
2114 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
2115 { \
2116 fprintf (FILE, "\t.code 32\n"); \
2117 fprintf (FILE, ".Ltrampoline_start:\n"); \
2118 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2119 STATIC_CHAIN_REGNUM, PC_REGNUM); \
2120 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2121 IP_REGNUM, PC_REGNUM); \
2122 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
2123 IP_REGNUM, IP_REGNUM); \
2124 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
2125 fprintf (FILE, "\t.word\t0\n"); \
2126 fprintf (FILE, "\t.word\t0\n"); \
2127 fprintf (FILE, "\t.code 16\n"); \
2128 }
2129
2130 #define TRAMPOLINE_TEMPLATE(FILE) \
2131 if (TARGET_ARM) \
2132 ARM_TRAMPOLINE_TEMPLATE (FILE) \
2133 else \
2134 THUMB_TRAMPOLINE_TEMPLATE (FILE)
2135
2136 /* Length in units of the trampoline for entering a nested function. */
2137 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
2138
2139 /* Alignment required for a trampoline in bits. */
2140 #define TRAMPOLINE_ALIGNMENT 32
2141
2142 /* Emit RTL insns to initialize the variable parts of a trampoline.
2143 FNADDR is an RTX for the address of the function's pure code.
2144 CXT is an RTX for the static chain value for the function. */
2145 #ifndef INITIALIZE_TRAMPOLINE
2146 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2147 { \
2148 emit_move_insn (gen_rtx_MEM (SImode, \
2149 plus_constant (TRAMP, \
2150 TARGET_ARM ? 8 : 16)), \
2151 CXT); \
2152 emit_move_insn (gen_rtx_MEM (SImode, \
2153 plus_constant (TRAMP, \
2154 TARGET_ARM ? 12 : 20)), \
2155 FNADDR); \
2156 }
2157 #endif
2158
2159 \f
2160 /* Addressing modes, and classification of registers for them. */
2161 #define HAVE_POST_INCREMENT 1
2162 #define HAVE_PRE_INCREMENT TARGET_ARM
2163 #define HAVE_POST_DECREMENT TARGET_ARM
2164 #define HAVE_PRE_DECREMENT TARGET_ARM
2165 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2166 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2167 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2168 #define HAVE_POST_MODIFY_REG TARGET_ARM
2169
2170 /* Macros to check register numbers against specific register classes. */
2171
2172 /* These assume that REGNO is a hard or pseudo reg number.
2173 They give nonzero only if REGNO is a hard reg of the suitable class
2174 or a pseudo reg currently allocated to a suitable hard reg.
2175 Since they use reg_renumber, they are safe only once reg_renumber
2176 has been allocated, which happens in local-alloc.c. */
2177 #define TEST_REGNO(R, TEST, VALUE) \
2178 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2179
2180 /* On the ARM, don't allow the pc to be used. */
2181 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2182 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2183 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2184 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2185
2186 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2187 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2188 || (GET_MODE_SIZE (MODE) >= 4 \
2189 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2190
2191 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2192 (TARGET_THUMB \
2193 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2194 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2195
2196 /* For ARM code, we don't care about the mode, but for Thumb, the index
2197 must be suitable for use in a QImode load. */
2198 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2199 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2200
2201 /* Maximum number of registers that can appear in a valid memory address.
2202 Shifts in addresses can't be by a register. */
2203 #define MAX_REGS_PER_ADDRESS 2
2204
2205 /* Recognize any constant value that is a valid address. */
2206 /* XXX We can address any constant, eventually... */
2207
2208 #ifdef AOF_ASSEMBLER
2209
2210 #define CONSTANT_ADDRESS_P(X) \
2211 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2212
2213 #else
2214
2215 #define CONSTANT_ADDRESS_P(X) \
2216 (GET_CODE (X) == SYMBOL_REF \
2217 && (CONSTANT_POOL_ADDRESS_P (X) \
2218 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2219
2220 #endif /* AOF_ASSEMBLER */
2221
2222 /* Nonzero if the constant value X is a legitimate general operand.
2223 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2224
2225 On the ARM, allow any integer (invalid ones are removed later by insn
2226 patterns), nice doubles and symbol_refs which refer to the function's
2227 constant pool XXX.
2228
2229 When generating pic allow anything. */
2230 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2231
2232 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2233 ( GET_CODE (X) == CONST_INT \
2234 || GET_CODE (X) == CONST_DOUBLE \
2235 || GET_CODE (X) == CONSTANT_P_RTX \
2236 || CONSTANT_ADDRESS_P (X) \
2237 || flag_pic)
2238
2239 #define LEGITIMATE_CONSTANT_P(X) \
2240 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2241
2242 /* Special characters prefixed to function names
2243 in order to encode attribute like information.
2244 Note, '@' and '*' have already been taken. */
2245 #define SHORT_CALL_FLAG_CHAR '^'
2246 #define LONG_CALL_FLAG_CHAR '#'
2247
2248 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2249 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2250
2251 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2252 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2253
2254 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2255 #define SUBTARGET_NAME_ENCODING_LENGTHS
2256 #endif
2257
2258 /* This is a C fragment for the inside of a switch statement.
2259 Each case label should return the number of characters to
2260 be stripped from the start of a function's name, if that
2261 name starts with the indicated character. */
2262 #define ARM_NAME_ENCODING_LENGTHS \
2263 case SHORT_CALL_FLAG_CHAR: return 1; \
2264 case LONG_CALL_FLAG_CHAR: return 1; \
2265 case '*': return 1; \
2266 SUBTARGET_NAME_ENCODING_LENGTHS
2267
2268 /* This is how to output a reference to a user-level label named NAME.
2269 `assemble_name' uses this. */
2270 #undef ASM_OUTPUT_LABELREF
2271 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2272 arm_asm_output_labelref (FILE, NAME)
2273
2274 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2275 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2276
2277 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2278 and check its validity for a certain class.
2279 We have two alternate definitions for each of them.
2280 The usual definition accepts all pseudo regs; the other rejects
2281 them unless they have been allocated suitable hard regs.
2282 The symbol REG_OK_STRICT causes the latter definition to be used. */
2283 #ifndef REG_OK_STRICT
2284
2285 #define ARM_REG_OK_FOR_BASE_P(X) \
2286 (REGNO (X) <= LAST_ARM_REGNUM \
2287 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2288 || REGNO (X) == FRAME_POINTER_REGNUM \
2289 || REGNO (X) == ARG_POINTER_REGNUM)
2290
2291 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2292 (REGNO (X) <= LAST_LO_REGNUM \
2293 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2294 || (GET_MODE_SIZE (MODE) >= 4 \
2295 && (REGNO (X) == STACK_POINTER_REGNUM \
2296 || (X) == hard_frame_pointer_rtx \
2297 || (X) == arg_pointer_rtx)))
2298
2299 #define REG_STRICT_P 0
2300
2301 #else /* REG_OK_STRICT */
2302
2303 #define ARM_REG_OK_FOR_BASE_P(X) \
2304 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2305
2306 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2307 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2308
2309 #define REG_STRICT_P 1
2310
2311 #endif /* REG_OK_STRICT */
2312
2313 /* Now define some helpers in terms of the above. */
2314
2315 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2316 (TARGET_THUMB \
2317 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2318 : ARM_REG_OK_FOR_BASE_P (X))
2319
2320 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2321
2322 /* For Thumb, a valid index register is anything that can be used in
2323 a byte load instruction. */
2324 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2325
2326 /* Nonzero if X is a hard reg that can be used as an index
2327 or if it is a pseudo reg. On the Thumb, the stack pointer
2328 is not suitable. */
2329 #define REG_OK_FOR_INDEX_P(X) \
2330 (TARGET_THUMB \
2331 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2332 : ARM_REG_OK_FOR_INDEX_P (X))
2333
2334 \f
2335 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2336 that is a valid memory address for an instruction.
2337 The MODE argument is the machine mode for the MEM expression
2338 that wants to use this address. */
2339
2340 #define ARM_BASE_REGISTER_RTX_P(X) \
2341 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2342
2343 #define ARM_INDEX_REGISTER_RTX_P(X) \
2344 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2345
2346 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2347 { \
2348 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2349 goto WIN; \
2350 }
2351
2352 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2353 { \
2354 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2355 goto WIN; \
2356 }
2357
2358 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2359 if (TARGET_ARM) \
2360 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2361 else /* if (TARGET_THUMB) */ \
2362 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2363
2364 \f
2365 /* Try machine-dependent ways of modifying an illegitimate address
2366 to be legitimate. If we find one, return the new, valid address. */
2367 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2368 do { \
2369 X = arm_legitimize_address (X, OLDX, MODE); \
2370 } while (0)
2371
2372 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2373 do { \
2374 X = thumb_legitimize_address (X, OLDX, MODE); \
2375 } while (0)
2376
2377 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2378 do { \
2379 if (TARGET_ARM) \
2380 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2381 else \
2382 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2383 \
2384 if (memory_address_p (MODE, X)) \
2385 goto WIN; \
2386 } while (0)
2387
2388 /* Go to LABEL if ADDR (a legitimate address expression)
2389 has an effect that depends on the machine mode it is used for. */
2390 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2391 { \
2392 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2393 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2394 goto LABEL; \
2395 }
2396
2397 /* Nothing helpful to do for the Thumb */
2398 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2399 if (TARGET_ARM) \
2400 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2401 \f
2402
2403 /* Specify the machine mode that this machine uses
2404 for the index in the tablejump instruction. */
2405 #define CASE_VECTOR_MODE Pmode
2406
2407 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2408 unsigned is probably best, but may break some code. */
2409 #ifndef DEFAULT_SIGNED_CHAR
2410 #define DEFAULT_SIGNED_CHAR 0
2411 #endif
2412
2413 /* Don't cse the address of the function being compiled. */
2414 #define NO_RECURSIVE_FUNCTION_CSE 1
2415
2416 /* Max number of bytes we can move from memory to memory
2417 in one reasonably fast instruction. */
2418 #define MOVE_MAX 4
2419
2420 #undef MOVE_RATIO
2421 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2422
2423 /* Define if operations between registers always perform the operation
2424 on the full register even if a narrower mode is specified. */
2425 #define WORD_REGISTER_OPERATIONS
2426
2427 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2428 will either zero-extend or sign-extend. The value of this macro should
2429 be the code that says which one of the two operations is implicitly
2430 done, NIL if none. */
2431 #define LOAD_EXTEND_OP(MODE) \
2432 (TARGET_THUMB ? ZERO_EXTEND : \
2433 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2434 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2435
2436 /* Nonzero if access to memory by bytes is slow and undesirable. */
2437 #define SLOW_BYTE_ACCESS 0
2438
2439 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2440
2441 /* Immediate shift counts are truncated by the output routines (or was it
2442 the assembler?). Shift counts in a register are truncated by ARM. Note
2443 that the native compiler puts too large (> 32) immediate shift counts
2444 into a register and shifts by the register, letting the ARM decide what
2445 to do instead of doing that itself. */
2446 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2447 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2448 On the arm, Y in a register is used modulo 256 for the shift. Only for
2449 rotates is modulo 32 used. */
2450 /* #define SHIFT_COUNT_TRUNCATED 1 */
2451
2452 /* All integers have the same format so truncation is easy. */
2453 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2454
2455 /* Calling from registers is a massive pain. */
2456 #define NO_FUNCTION_CSE 1
2457
2458 /* The machine modes of pointers and functions */
2459 #define Pmode SImode
2460 #define FUNCTION_MODE Pmode
2461
2462 #define ARM_FRAME_RTX(X) \
2463 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2464 || (X) == arg_pointer_rtx)
2465
2466 /* Moves to and from memory are quite expensive */
2467 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2468 (TARGET_ARM ? 10 : \
2469 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2470 * (CLASS == LO_REGS ? 1 : 2)))
2471
2472 /* Try to generate sequences that don't involve branches, we can then use
2473 conditional instructions */
2474 #define BRANCH_COST \
2475 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2476 \f
2477 /* Position Independent Code. */
2478 /* We decide which register to use based on the compilation options and
2479 the assembler in use; this is more general than the APCS restriction of
2480 using sb (r9) all the time. */
2481 extern int arm_pic_register;
2482
2483 /* Used when parsing command line option -mpic-register=. */
2484 extern const char * arm_pic_register_string;
2485
2486 /* The register number of the register used to address a table of static
2487 data addresses in memory. */
2488 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2489
2490 #define FINALIZE_PIC arm_finalize_pic (1)
2491
2492 /* We can't directly access anything that contains a symbol,
2493 nor can we indirect via the constant pool. */
2494 #define LEGITIMATE_PIC_OPERAND_P(X) \
2495 (!(symbol_mentioned_p (X) \
2496 || label_mentioned_p (X) \
2497 || (GET_CODE (X) == SYMBOL_REF \
2498 && CONSTANT_POOL_ADDRESS_P (X) \
2499 && (symbol_mentioned_p (get_pool_constant (X)) \
2500 || label_mentioned_p (get_pool_constant (X))))))
2501
2502 /* We need to know when we are making a constant pool; this determines
2503 whether data needs to be in the GOT or can be referenced via a GOT
2504 offset. */
2505 extern int making_const_table;
2506 \f
2507 /* Handle pragmas for compatibility with Intel's compilers. */
2508 #define REGISTER_TARGET_PRAGMAS() do { \
2509 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2510 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2511 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2512 } while (0)
2513
2514 /* Condition code information. */
2515 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2516 return the mode to be used for the comparison. */
2517
2518 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2519
2520 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2521
2522 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2523 do \
2524 { \
2525 if (GET_CODE (OP1) == CONST_INT \
2526 && ! (const_ok_for_arm (INTVAL (OP1)) \
2527 || (const_ok_for_arm (- INTVAL (OP1))))) \
2528 { \
2529 rtx const_op = OP1; \
2530 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2531 OP1 = const_op; \
2532 } \
2533 } \
2534 while (0)
2535
2536 /* The arm5 clz instruction returns 32. */
2537 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2538 \f
2539 #undef ASM_APP_OFF
2540 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2541
2542 /* Output a push or a pop instruction (only used when profiling). */
2543 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2544 do \
2545 { \
2546 if (TARGET_ARM) \
2547 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2548 STACK_POINTER_REGNUM, REGNO); \
2549 else \
2550 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2551 } while (0)
2552
2553
2554 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2555 do \
2556 { \
2557 if (TARGET_ARM) \
2558 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2559 STACK_POINTER_REGNUM, REGNO); \
2560 else \
2561 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2562 } while (0)
2563
2564 /* This is how to output a label which precedes a jumptable. Since
2565 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2566 #undef ASM_OUTPUT_CASE_LABEL
2567 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2568 do \
2569 { \
2570 if (TARGET_THUMB) \
2571 ASM_OUTPUT_ALIGN (FILE, 2); \
2572 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2573 } \
2574 while (0)
2575
2576 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2577 do \
2578 { \
2579 if (TARGET_THUMB) \
2580 { \
2581 if (is_called_in_ARM_mode (DECL) \
2582 || current_function_is_thunk) \
2583 fprintf (STREAM, "\t.code 32\n") ; \
2584 else \
2585 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2586 } \
2587 if (TARGET_POKE_FUNCTION_NAME) \
2588 arm_poke_function_name (STREAM, (char *) NAME); \
2589 } \
2590 while (0)
2591
2592 /* For aliases of functions we use .thumb_set instead. */
2593 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2594 do \
2595 { \
2596 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2597 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2598 \
2599 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2600 { \
2601 fprintf (FILE, "\t.thumb_set "); \
2602 assemble_name (FILE, LABEL1); \
2603 fprintf (FILE, ","); \
2604 assemble_name (FILE, LABEL2); \
2605 fprintf (FILE, "\n"); \
2606 } \
2607 else \
2608 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2609 } \
2610 while (0)
2611
2612 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2613 /* To support -falign-* switches we need to use .p2align so
2614 that alignment directives in code sections will be padded
2615 with no-op instructions, rather than zeroes. */
2616 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2617 if ((LOG) != 0) \
2618 { \
2619 if ((MAX_SKIP) == 0) \
2620 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2621 else \
2622 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2623 (int) (LOG), (int) (MAX_SKIP)); \
2624 }
2625 #endif
2626 \f
2627 /* Only perform branch elimination (by making instructions conditional) if
2628 we're optimizing. Otherwise it's of no use anyway. */
2629 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2630 if (TARGET_ARM && optimize) \
2631 arm_final_prescan_insn (INSN); \
2632 else if (TARGET_THUMB) \
2633 thumb_final_prescan_insn (INSN)
2634
2635 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2636 (CODE == '@' || CODE == '|' \
2637 || (TARGET_ARM && (CODE == '?')) \
2638 || (TARGET_THUMB && (CODE == '_')))
2639
2640 /* Output an operand of an instruction. */
2641 #define PRINT_OPERAND(STREAM, X, CODE) \
2642 arm_print_operand (STREAM, X, CODE)
2643
2644 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2645 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2646 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2647 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2648 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2649 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2650 : 0))))
2651
2652 /* Output the address of an operand. */
2653 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2654 { \
2655 int is_minus = GET_CODE (X) == MINUS; \
2656 \
2657 if (GET_CODE (X) == REG) \
2658 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2659 else if (GET_CODE (X) == PLUS || is_minus) \
2660 { \
2661 rtx base = XEXP (X, 0); \
2662 rtx index = XEXP (X, 1); \
2663 HOST_WIDE_INT offset = 0; \
2664 if (GET_CODE (base) != REG) \
2665 { \
2666 /* Ensure that BASE is a register. */ \
2667 /* (one of them must be). */ \
2668 rtx temp = base; \
2669 base = index; \
2670 index = temp; \
2671 } \
2672 switch (GET_CODE (index)) \
2673 { \
2674 case CONST_INT: \
2675 offset = INTVAL (index); \
2676 if (is_minus) \
2677 offset = -offset; \
2678 asm_fprintf (STREAM, "[%r, #%wd]", \
2679 REGNO (base), offset); \
2680 break; \
2681 \
2682 case REG: \
2683 asm_fprintf (STREAM, "[%r, %s%r]", \
2684 REGNO (base), is_minus ? "-" : "", \
2685 REGNO (index)); \
2686 break; \
2687 \
2688 case MULT: \
2689 case ASHIFTRT: \
2690 case LSHIFTRT: \
2691 case ASHIFT: \
2692 case ROTATERT: \
2693 { \
2694 asm_fprintf (STREAM, "[%r, %s%r", \
2695 REGNO (base), is_minus ? "-" : "", \
2696 REGNO (XEXP (index, 0))); \
2697 arm_print_operand (STREAM, index, 'S'); \
2698 fputs ("]", STREAM); \
2699 break; \
2700 } \
2701 \
2702 default: \
2703 abort(); \
2704 } \
2705 } \
2706 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2707 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2708 { \
2709 extern enum machine_mode output_memory_reference_mode; \
2710 \
2711 if (GET_CODE (XEXP (X, 0)) != REG) \
2712 abort (); \
2713 \
2714 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2715 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2716 REGNO (XEXP (X, 0)), \
2717 GET_CODE (X) == PRE_DEC ? "-" : "", \
2718 GET_MODE_SIZE (output_memory_reference_mode)); \
2719 else \
2720 asm_fprintf (STREAM, "[%r], #%s%d", \
2721 REGNO (XEXP (X, 0)), \
2722 GET_CODE (X) == POST_DEC ? "-" : "", \
2723 GET_MODE_SIZE (output_memory_reference_mode)); \
2724 } \
2725 else if (GET_CODE (X) == PRE_MODIFY) \
2726 { \
2727 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2728 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2729 asm_fprintf (STREAM, "#%wd]!", \
2730 INTVAL (XEXP (XEXP (X, 1), 1))); \
2731 else \
2732 asm_fprintf (STREAM, "%r]!", \
2733 REGNO (XEXP (XEXP (X, 1), 1))); \
2734 } \
2735 else if (GET_CODE (X) == POST_MODIFY) \
2736 { \
2737 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2738 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2739 asm_fprintf (STREAM, "#%wd", \
2740 INTVAL (XEXP (XEXP (X, 1), 1))); \
2741 else \
2742 asm_fprintf (STREAM, "%r", \
2743 REGNO (XEXP (XEXP (X, 1), 1))); \
2744 } \
2745 else output_addr_const (STREAM, X); \
2746 }
2747
2748 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2749 { \
2750 if (GET_CODE (X) == REG) \
2751 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2752 else if (GET_CODE (X) == POST_INC) \
2753 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2754 else if (GET_CODE (X) == PLUS) \
2755 { \
2756 if (GET_CODE (XEXP (X, 0)) != REG) \
2757 abort (); \
2758 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2759 asm_fprintf (STREAM, "[%r, #%wd]", \
2760 REGNO (XEXP (X, 0)), \
2761 INTVAL (XEXP (X, 1))); \
2762 else \
2763 asm_fprintf (STREAM, "[%r, %r]", \
2764 REGNO (XEXP (X, 0)), \
2765 REGNO (XEXP (X, 1))); \
2766 } \
2767 else \
2768 output_addr_const (STREAM, X); \
2769 }
2770
2771 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2772 if (TARGET_ARM) \
2773 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2774 else \
2775 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2776
2777 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2778 if (GET_CODE (X) != CONST_VECTOR \
2779 || ! arm_emit_vector_const (FILE, X)) \
2780 goto FAIL;
2781
2782 /* A C expression whose value is RTL representing the value of the return
2783 address for the frame COUNT steps up from the current frame. */
2784
2785 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2786 arm_return_addr (COUNT, FRAME)
2787
2788 /* Mask of the bits in the PC that contain the real return address
2789 when running in 26-bit mode. */
2790 #define RETURN_ADDR_MASK26 (0x03fffffc)
2791
2792 /* Pick up the return address upon entry to a procedure. Used for
2793 dwarf2 unwind information. This also enables the table driven
2794 mechanism. */
2795 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2796 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2797
2798 /* Used to mask out junk bits from the return address, such as
2799 processor state, interrupt status, condition codes and the like. */
2800 #define MASK_RETURN_ADDR \
2801 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2802 in 26 bit mode, the condition codes must be masked out of the \
2803 return address. This does not apply to ARM6 and later processors \
2804 when running in 32 bit mode. */ \
2805 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2806 : (arm_arch4 || TARGET_THUMB) ? \
2807 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2808 : arm_gen_return_addr_mask ())
2809
2810 \f
2811 /* Define the codes that are matched by predicates in arm.c */
2812 #define PREDICATE_CODES \
2813 {"s_register_operand", {SUBREG, REG}}, \
2814 {"arm_general_register_operand", {SUBREG, REG}}, \
2815 {"arm_hard_register_operand", {REG}}, \
2816 {"f_register_operand", {SUBREG, REG}}, \
2817 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2818 {"arm_addimm_operand", {CONST_INT}}, \
2819 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2820 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2821 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2822 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2823 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2824 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2825 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2826 {"thumb_cmpneg_operand", {CONST_INT}}, \
2827 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2828 {"offsettable_memory_operand", {MEM}}, \
2829 {"alignable_memory_operand", {MEM}}, \
2830 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2831 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2832 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2833 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2834 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2835 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2836 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2837 {"load_multiple_operation", {PARALLEL}}, \
2838 {"store_multiple_operation", {PARALLEL}}, \
2839 {"equality_operator", {EQ, NE}}, \
2840 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2841 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2842 UNGE, UNGT}}, \
2843 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2844 {"const_shift_operand", {CONST_INT}}, \
2845 {"multi_register_push", {PARALLEL}}, \
2846 {"cc_register", {REG}}, \
2847 {"logical_binary_operator", {AND, IOR, XOR}}, \
2848 {"cirrus_register_operand", {REG}}, \
2849 {"cirrus_fp_register", {REG}}, \
2850 {"cirrus_shift_const", {CONST_INT}}, \
2851 {"dominant_cc_register", {REG}}, \
2852 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2853 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2854
2855 /* Define this if you have special predicates that know special things
2856 about modes. Genrecog will warn about certain forms of
2857 match_operand without a mode; if the operand predicate is listed in
2858 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2859 #define SPECIAL_MODE_PREDICATES \
2860 "cc_register", "dominant_cc_register",
2861
2862 enum arm_builtins
2863 {
2864 ARM_BUILTIN_GETWCX,
2865 ARM_BUILTIN_SETWCX,
2866
2867 ARM_BUILTIN_WZERO,
2868
2869 ARM_BUILTIN_WAVG2BR,
2870 ARM_BUILTIN_WAVG2HR,
2871 ARM_BUILTIN_WAVG2B,
2872 ARM_BUILTIN_WAVG2H,
2873
2874 ARM_BUILTIN_WACCB,
2875 ARM_BUILTIN_WACCH,
2876 ARM_BUILTIN_WACCW,
2877
2878 ARM_BUILTIN_WMACS,
2879 ARM_BUILTIN_WMACSZ,
2880 ARM_BUILTIN_WMACU,
2881 ARM_BUILTIN_WMACUZ,
2882
2883 ARM_BUILTIN_WSADB,
2884 ARM_BUILTIN_WSADBZ,
2885 ARM_BUILTIN_WSADH,
2886 ARM_BUILTIN_WSADHZ,
2887
2888 ARM_BUILTIN_WALIGN,
2889
2890 ARM_BUILTIN_TMIA,
2891 ARM_BUILTIN_TMIAPH,
2892 ARM_BUILTIN_TMIABB,
2893 ARM_BUILTIN_TMIABT,
2894 ARM_BUILTIN_TMIATB,
2895 ARM_BUILTIN_TMIATT,
2896
2897 ARM_BUILTIN_TMOVMSKB,
2898 ARM_BUILTIN_TMOVMSKH,
2899 ARM_BUILTIN_TMOVMSKW,
2900
2901 ARM_BUILTIN_TBCSTB,
2902 ARM_BUILTIN_TBCSTH,
2903 ARM_BUILTIN_TBCSTW,
2904
2905 ARM_BUILTIN_WMADDS,
2906 ARM_BUILTIN_WMADDU,
2907
2908 ARM_BUILTIN_WPACKHSS,
2909 ARM_BUILTIN_WPACKWSS,
2910 ARM_BUILTIN_WPACKDSS,
2911 ARM_BUILTIN_WPACKHUS,
2912 ARM_BUILTIN_WPACKWUS,
2913 ARM_BUILTIN_WPACKDUS,
2914
2915 ARM_BUILTIN_WADDB,
2916 ARM_BUILTIN_WADDH,
2917 ARM_BUILTIN_WADDW,
2918 ARM_BUILTIN_WADDSSB,
2919 ARM_BUILTIN_WADDSSH,
2920 ARM_BUILTIN_WADDSSW,
2921 ARM_BUILTIN_WADDUSB,
2922 ARM_BUILTIN_WADDUSH,
2923 ARM_BUILTIN_WADDUSW,
2924 ARM_BUILTIN_WSUBB,
2925 ARM_BUILTIN_WSUBH,
2926 ARM_BUILTIN_WSUBW,
2927 ARM_BUILTIN_WSUBSSB,
2928 ARM_BUILTIN_WSUBSSH,
2929 ARM_BUILTIN_WSUBSSW,
2930 ARM_BUILTIN_WSUBUSB,
2931 ARM_BUILTIN_WSUBUSH,
2932 ARM_BUILTIN_WSUBUSW,
2933
2934 ARM_BUILTIN_WAND,
2935 ARM_BUILTIN_WANDN,
2936 ARM_BUILTIN_WOR,
2937 ARM_BUILTIN_WXOR,
2938
2939 ARM_BUILTIN_WCMPEQB,
2940 ARM_BUILTIN_WCMPEQH,
2941 ARM_BUILTIN_WCMPEQW,
2942 ARM_BUILTIN_WCMPGTUB,
2943 ARM_BUILTIN_WCMPGTUH,
2944 ARM_BUILTIN_WCMPGTUW,
2945 ARM_BUILTIN_WCMPGTSB,
2946 ARM_BUILTIN_WCMPGTSH,
2947 ARM_BUILTIN_WCMPGTSW,
2948
2949 ARM_BUILTIN_TEXTRMSB,
2950 ARM_BUILTIN_TEXTRMSH,
2951 ARM_BUILTIN_TEXTRMSW,
2952 ARM_BUILTIN_TEXTRMUB,
2953 ARM_BUILTIN_TEXTRMUH,
2954 ARM_BUILTIN_TEXTRMUW,
2955 ARM_BUILTIN_TINSRB,
2956 ARM_BUILTIN_TINSRH,
2957 ARM_BUILTIN_TINSRW,
2958
2959 ARM_BUILTIN_WMAXSW,
2960 ARM_BUILTIN_WMAXSH,
2961 ARM_BUILTIN_WMAXSB,
2962 ARM_BUILTIN_WMAXUW,
2963 ARM_BUILTIN_WMAXUH,
2964 ARM_BUILTIN_WMAXUB,
2965 ARM_BUILTIN_WMINSW,
2966 ARM_BUILTIN_WMINSH,
2967 ARM_BUILTIN_WMINSB,
2968 ARM_BUILTIN_WMINUW,
2969 ARM_BUILTIN_WMINUH,
2970 ARM_BUILTIN_WMINUB,
2971
2972 ARM_BUILTIN_WMULUM,
2973 ARM_BUILTIN_WMULSM,
2974 ARM_BUILTIN_WMULUL,
2975
2976 ARM_BUILTIN_PSADBH,
2977 ARM_BUILTIN_WSHUFH,
2978
2979 ARM_BUILTIN_WSLLH,
2980 ARM_BUILTIN_WSLLW,
2981 ARM_BUILTIN_WSLLD,
2982 ARM_BUILTIN_WSRAH,
2983 ARM_BUILTIN_WSRAW,
2984 ARM_BUILTIN_WSRAD,
2985 ARM_BUILTIN_WSRLH,
2986 ARM_BUILTIN_WSRLW,
2987 ARM_BUILTIN_WSRLD,
2988 ARM_BUILTIN_WRORH,
2989 ARM_BUILTIN_WRORW,
2990 ARM_BUILTIN_WRORD,
2991 ARM_BUILTIN_WSLLHI,
2992 ARM_BUILTIN_WSLLWI,
2993 ARM_BUILTIN_WSLLDI,
2994 ARM_BUILTIN_WSRAHI,
2995 ARM_BUILTIN_WSRAWI,
2996 ARM_BUILTIN_WSRADI,
2997 ARM_BUILTIN_WSRLHI,
2998 ARM_BUILTIN_WSRLWI,
2999 ARM_BUILTIN_WSRLDI,
3000 ARM_BUILTIN_WRORHI,
3001 ARM_BUILTIN_WRORWI,
3002 ARM_BUILTIN_WRORDI,
3003
3004 ARM_BUILTIN_WUNPCKIHB,
3005 ARM_BUILTIN_WUNPCKIHH,
3006 ARM_BUILTIN_WUNPCKIHW,
3007 ARM_BUILTIN_WUNPCKILB,
3008 ARM_BUILTIN_WUNPCKILH,
3009 ARM_BUILTIN_WUNPCKILW,
3010
3011 ARM_BUILTIN_WUNPCKEHSB,
3012 ARM_BUILTIN_WUNPCKEHSH,
3013 ARM_BUILTIN_WUNPCKEHSW,
3014 ARM_BUILTIN_WUNPCKEHUB,
3015 ARM_BUILTIN_WUNPCKEHUH,
3016 ARM_BUILTIN_WUNPCKEHUW,
3017 ARM_BUILTIN_WUNPCKELSB,
3018 ARM_BUILTIN_WUNPCKELSH,
3019 ARM_BUILTIN_WUNPCKELSW,
3020 ARM_BUILTIN_WUNPCKELUB,
3021 ARM_BUILTIN_WUNPCKELUH,
3022 ARM_BUILTIN_WUNPCKELUW,
3023
3024 ARM_BUILTIN_MAX
3025 };
3026 #endif /* ! GCC_ARM_H */
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