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* rtl.def (NIL): Delete.
[official-gcc.git] / gcc / config / arm / arm.h
blob135a5743ac682ddfead50bb675921089892ffec4
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The archetecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
87 NAME,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##NAME,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Run-time compilation parameters selecting different hardware subsets. */
121 extern int target_flags;
122 /* The floating point mode. */
123 extern const char *target_fpu_name;
124 /* For backwards compatibility. */
125 extern const char *target_fpe_name;
126 /* Whether to use floating point hardware. */
127 extern const char *target_float_abi_name;
128 /* Which ABI to use. */
129 extern const char *target_abi_name;
130 /* Define the information needed to generate branch insns. This is
131 stored from the compare operation. */
132 extern GTY(()) rtx arm_compare_op0;
133 extern GTY(()) rtx arm_compare_op1;
134 /* The label of the current constant pool. */
135 extern rtx pool_vector_label;
136 /* Set to 1 when a return insn is output, this means that the epilogue
137 is not needed. */
138 extern int return_used_this_function;
139 /* Used to produce AOF syntax assembler. */
140 extern GTY(()) rtx aof_pic_label;
141 \f
142 /* Just in case configure has failed to define anything. */
143 #ifndef TARGET_CPU_DEFAULT
144 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
145 #endif
146
147
148 #undef CPP_SPEC
149 #define CPP_SPEC "%(subtarget_cpp_spec) \
150 %{msoft-float:%{mhard-float: \
151 %e-msoft-float and -mhard_float may not be used together}} \
152 %{mbig-endian:%{mlittle-endian: \
153 %e-mbig-endian and -mlittle-endian may not be used together}}"
154
155 #ifndef CC1_SPEC
156 #define CC1_SPEC ""
157 #endif
158
159 /* This macro defines names of additional specifications to put in the specs
160 that can be used in various specifications like CC1_SPEC. Its definition
161 is an initializer with a subgrouping for each command option.
162
163 Each subgrouping contains a string constant, that defines the
164 specification name, and a string constant that used by the GCC driver
165 program.
166
167 Do not define this macro if it does not need to do anything. */
168 #define EXTRA_SPECS \
169 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
170 SUBTARGET_EXTRA_SPECS
171
172 #ifndef SUBTARGET_EXTRA_SPECS
173 #define SUBTARGET_EXTRA_SPECS
174 #endif
175
176 #ifndef SUBTARGET_CPP_SPEC
177 #define SUBTARGET_CPP_SPEC ""
178 #endif
179 \f
180 /* Run-time Target Specification. */
181 #ifndef TARGET_VERSION
182 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
183 #endif
184
185 /* Nonzero if the function prologue (and epilogue) should obey
186 the ARM Procedure Call Standard. */
187 #define ARM_FLAG_APCS_FRAME (1 << 0)
188
189 /* Nonzero if the function prologue should output the function name to enable
190 the post mortem debugger to print a backtrace (very useful on RISCOS,
191 unused on RISCiX). Specifying this flag also enables
192 -fno-omit-frame-pointer.
193 XXX Must still be implemented in the prologue. */
194 #define ARM_FLAG_POKE (1 << 1)
195
196 /* Nonzero if floating point instructions are emulated by the FPE, in which
197 case instruction scheduling becomes very uninteresting. */
198 #define ARM_FLAG_FPE (1 << 2)
199
200 /* FLAG 0x0008 now spare (used to be apcs-32 selection). */
201
202 /* Nonzero if stack checking should be performed on entry to each function
203 which allocates temporary variables on the stack. */
204 #define ARM_FLAG_APCS_STACK (1 << 4)
205
206 /* Nonzero if floating point parameters should be passed to functions in
207 floating point registers. */
208 #define ARM_FLAG_APCS_FLOAT (1 << 5)
209
210 /* Nonzero if re-entrant, position independent code should be generated.
211 This is equivalent to -fpic. */
212 #define ARM_FLAG_APCS_REENT (1 << 6)
213
214 /* FLAG 0x0080 now spare (used to be alignment traps). */
215 /* Nonzero if all floating point instructions are missing (and there is no
216 emulator either). Generate function calls for all ops in this case. */
217 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
218
219 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
220 #define ARM_FLAG_BIG_END (1 << 9)
221
222 /* Nonzero if we should compile for Thumb interworking. */
223 #define ARM_FLAG_INTERWORK (1 << 10)
224
225 /* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
227 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
228
229 /* Nonzero if we need to protect the prolog from scheduling */
230 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
231
232 /* Nonzero if a call to abort should be generated if a noreturn
233 function tries to return. */
234 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
235
236 /* Nonzero if function prologues should not load the PIC register. */
237 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
238
239 /* Nonzero if all call instructions should be indirect. */
240 #define ARM_FLAG_LONG_CALLS (1 << 15)
241
242 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
243 #define ARM_FLAG_THUMB (1 << 16)
244
245 /* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247 #define THUMB_FLAG_BACKTRACE (1 << 17)
248
249 /* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
252
253 /* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
256
257 /* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
260
261 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
262 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
263
264 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
265 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
267 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
270 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
271 #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
272 #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
273 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
274 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
275 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
276 #define TARGET_IWMMXT (arm_arch_iwmmxt)
277 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
278 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
279 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
280 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
281 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
282 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
283 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
284 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
285 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
286 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
287 #define TARGET_ARM (! TARGET_THUMB)
288 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
289 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
290 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
291 #define TARGET_BACKTRACE (leaf_function_p () \
292 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
293 : (target_flags & THUMB_FLAG_BACKTRACE))
294 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
295 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
296 #define TARGET_AAPCS_BASED \
297 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
298
299 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
300 then TARGET_AAPCS_BASED must be true -- but the converse does not
301 hold. TARGET_BPABI implies the use of the BPABI runtime library,
302 etc., in addition to just the AAPCS calling conventions. */
303 #ifndef TARGET_BPABI
304 #define TARGET_BPABI false
305 #endif
306
307 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
308 #ifndef SUBTARGET_SWITCHES
309 #define SUBTARGET_SWITCHES
310 #endif
311
312 #define TARGET_SWITCHES \
313 { \
314 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
315 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
316 N_("Generate APCS conformant stack frames") }, \
317 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
318 {"poke-function-name", ARM_FLAG_POKE, \
319 N_("Store function names in object code") }, \
320 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
321 {"fpe", ARM_FLAG_FPE, "" }, \
322 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
323 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
324 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
325 N_("Pass FP arguments in FP registers") }, \
326 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
327 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
328 N_("Generate re-entrant, PIC code") }, \
329 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
330 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
331 N_("Use library calls to perform FP operations") }, \
332 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
333 N_("Use hardware floating point instructions") }, \
334 {"big-endian", ARM_FLAG_BIG_END, \
335 N_("Assume target CPU is configured as big endian") }, \
336 {"little-endian", -ARM_FLAG_BIG_END, \
337 N_("Assume target CPU is configured as little endian") }, \
338 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
339 N_("Assume big endian bytes, little endian words") }, \
340 {"thumb-interwork", ARM_FLAG_INTERWORK, \
341 N_("Support calls between Thumb and ARM instruction sets") }, \
342 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
343 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
344 N_("Generate a call to abort if a noreturn function returns")}, \
345 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
346 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
347 N_("Do not move instructions into a function's prologue") }, \
348 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
349 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
350 N_("Do not load the PIC register in function prologues") }, \
351 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
352 {"long-calls", ARM_FLAG_LONG_CALLS, \
353 N_("Generate call insns as indirect calls, if necessary") }, \
354 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
355 {"thumb", ARM_FLAG_THUMB, \
356 N_("Compile for the Thumb not the ARM") }, \
357 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
358 {"arm", -ARM_FLAG_THUMB, "" }, \
359 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
360 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
361 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
362 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
363 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
364 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
365 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
366 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
367 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
368 "" }, \
369 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
370 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
371 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
372 "" }, \
373 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
374 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
375 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
376 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
377 SUBTARGET_SWITCHES \
378 {"", TARGET_DEFAULT, "" } \
379 }
380
381 #define TARGET_OPTIONS \
382 { \
383 {"cpu=", & arm_select[0].string, \
384 N_("Specify the name of the target CPU"), 0}, \
385 {"arch=", & arm_select[1].string, \
386 N_("Specify the name of the target architecture"), 0}, \
387 {"tune=", & arm_select[2].string, "", 0}, \
388 {"fpe=", & target_fpe_name, "", 0}, \
389 {"fp=", & target_fpe_name, "", 0}, \
390 {"fpu=", & target_fpu_name, \
391 N_("Specify the name of the target floating point hardware/format"), 0}, \
392 {"float-abi=", & target_float_abi_name, \
393 N_("Specify if floating point hardware should be used"), 0}, \
394 {"structure-size-boundary=", & structure_size_string, \
395 N_("Specify the minimum bit alignment of structures"), 0}, \
396 {"pic-register=", & arm_pic_register_string, \
397 N_("Specify the register to be used for PIC addressing"), 0}, \
398 {"abi=", &target_abi_name, N_("Specify an ABI"), 0} \
399 }
400
401 /* Support for a compile-time default CPU, et cetera. The rules are:
402 --with-arch is ignored if -march or -mcpu are specified.
403 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
404 by --with-arch.
405 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
406 by -march).
407 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
408 specified.
409 --with-fpu is ignored if -mfpu is specified.
410 --with-abi is ignored is -mabi is specified. */
411 #define OPTION_DEFAULT_SPECS \
412 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
413 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
414 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
415 {"float", \
416 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
417 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
418 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
419
420 struct arm_cpu_select
421 {
422 const char * string;
423 const char * name;
424 const struct processors * processors;
425 };
426
427 /* This is a magic array. If the user specifies a command line switch
428 which matches one of the entries in TARGET_OPTIONS then the corresponding
429 string pointer will be set to the value specified by the user. */
430 extern struct arm_cpu_select arm_select[];
431
432 /* Which floating point model to use. */
433 enum arm_fp_model
434 {
435 ARM_FP_MODEL_UNKNOWN,
436 /* FPA model (Hardware or software). */
437 ARM_FP_MODEL_FPA,
438 /* Cirrus Maverick floating point model. */
439 ARM_FP_MODEL_MAVERICK,
440 /* VFP floating point model. */
441 ARM_FP_MODEL_VFP
442 };
443
444 extern enum arm_fp_model arm_fp_model;
445
446 /* Which floating point hardware is available. Also update
447 fp_model_for_fpu in arm.c when adding entries to this list. */
448 enum fputype
449 {
450 /* No FP hardware. */
451 FPUTYPE_NONE,
452 /* Full FPA support. */
453 FPUTYPE_FPA,
454 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
455 FPUTYPE_FPA_EMU2,
456 /* Emulated FPA hardware, Issue 3 emulator. */
457 FPUTYPE_FPA_EMU3,
458 /* Cirrus Maverick floating point co-processor. */
459 FPUTYPE_MAVERICK,
460 /* VFP. */
461 FPUTYPE_VFP
462 };
463
464 /* Recast the floating point class to be the floating point attribute. */
465 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
466
467 /* What type of floating point to tune for */
468 extern enum fputype arm_fpu_tune;
469
470 /* What type of floating point instructions are available */
471 extern enum fputype arm_fpu_arch;
472
473 enum float_abi_type
474 {
475 ARM_FLOAT_ABI_SOFT,
476 ARM_FLOAT_ABI_SOFTFP,
477 ARM_FLOAT_ABI_HARD
478 };
479
480 extern enum float_abi_type arm_float_abi;
481
482 /* Which ABI to use. */
483 enum arm_abi_type
484 {
485 ARM_ABI_APCS,
486 ARM_ABI_ATPCS,
487 ARM_ABI_AAPCS,
488 ARM_ABI_IWMMXT
489 };
490
491 extern enum arm_abi_type arm_abi;
492
493 #ifndef ARM_DEFAULT_ABI
494 #define ARM_DEFAULT_ABI ARM_ABI_APCS
495 #endif
496
497 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
498 extern int arm_arch3m;
499
500 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
501 extern int arm_arch4;
502
503 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
504 extern int arm_arch4t;
505
506 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
507 extern int arm_arch5;
508
509 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
510 extern int arm_arch5e;
511
512 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
513 extern int arm_arch6;
514
515 /* Nonzero if this chip can benefit from load scheduling. */
516 extern int arm_ld_sched;
517
518 /* Nonzero if generating thumb code. */
519 extern int thumb_code;
520
521 /* Nonzero if this chip is a StrongARM. */
522 extern int arm_is_strong;
523
524 /* Nonzero if this chip is a Cirrus variant. */
525 extern int arm_arch_cirrus;
526
527 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
528 extern int arm_arch_iwmmxt;
529
530 /* Nonzero if this chip is an XScale. */
531 extern int arm_arch_xscale;
532
533 /* Nonzero if tuning for XScale */
534 extern int arm_tune_xscale;
535
536 /* Nonzero if this chip is an ARM6 or an ARM7. */
537 extern int arm_is_6_or_7;
538
539 /* Nonzero if we should define __THUMB_INTERWORK__ in the
540 preprocessor.
541 XXX This is a bit of a hack, it's intended to help work around
542 problems in GLD which doesn't understand that armv5t code is
543 interworking clean. */
544 extern int arm_cpp_interwork;
545
546 #ifndef TARGET_DEFAULT
547 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
548 #endif
549
550 /* The frame pointer register used in gcc has nothing to do with debugging;
551 that is controlled by the APCS-FRAME option. */
552 #define CAN_DEBUG_WITHOUT_FP
553
554 #define OVERRIDE_OPTIONS arm_override_options ()
555
556 /* Nonzero if PIC code requires explicit qualifiers to generate
557 PLT and GOT relocs rather than the assembler doing so implicitly.
558 Subtargets can override these if required. */
559 #ifndef NEED_GOT_RELOC
560 #define NEED_GOT_RELOC 0
561 #endif
562 #ifndef NEED_PLT_RELOC
563 #define NEED_PLT_RELOC 0
564 #endif
565
566 /* Nonzero if we need to refer to the GOT with a PC-relative
567 offset. In other words, generate
568
569 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
570
571 rather than
572
573 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
574
575 The default is true, which matches NetBSD. Subtargets can
576 override this if required. */
577 #ifndef GOT_PCREL
578 #define GOT_PCREL 1
579 #endif
580 \f
581 /* Target machine storage Layout. */
582
583
584 /* Define this macro if it is advisable to hold scalars in registers
585 in a wider mode than that declared by the program. In such cases,
586 the value is constrained to be within the bounds of the declared
587 type, but kept valid in the wider mode. The signedness of the
588 extension may differ from that of the type. */
589
590 /* It is far faster to zero extend chars than to sign extend them */
591
592 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
593 if (GET_MODE_CLASS (MODE) == MODE_INT \
594 && GET_MODE_SIZE (MODE) < 4) \
595 { \
596 if (MODE == QImode) \
597 UNSIGNEDP = 1; \
598 else if (MODE == HImode) \
599 UNSIGNEDP = 1; \
600 (MODE) = SImode; \
601 }
602
603 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
604 if (GET_MODE_CLASS (MODE) == MODE_INT \
605 && GET_MODE_SIZE (MODE) < 4) \
606 (MODE) = SImode; \
607
608 /* Define this if most significant bit is lowest numbered
609 in instructions that operate on numbered bit-fields. */
610 #define BITS_BIG_ENDIAN 0
611
612 /* Define this if most significant byte of a word is the lowest numbered.
613 Most ARM processors are run in little endian mode, so that is the default.
614 If you want to have it run-time selectable, change the definition in a
615 cover file to be TARGET_BIG_ENDIAN. */
616 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
617
618 /* Define this if most significant word of a multiword number is the lowest
619 numbered.
620 This is always false, even when in big-endian mode. */
621 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
622
623 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
624 on processor pre-defineds when compiling libgcc2.c. */
625 #if defined(__ARMEB__) && !defined(__ARMWEL__)
626 #define LIBGCC2_WORDS_BIG_ENDIAN 1
627 #else
628 #define LIBGCC2_WORDS_BIG_ENDIAN 0
629 #endif
630
631 /* Define this if most significant word of doubles is the lowest numbered.
632 The rules are different based on whether or not we use FPA-format,
633 VFP-format or some other floating point co-processor's format doubles. */
634 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
635
636 #define UNITS_PER_WORD 4
637
638 /* True if natural alignment is used for doubleword types. */
639 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
640
641 #define DOUBLEWORD_ALIGNMENT 64
642
643 #define PARM_BOUNDARY 32
644
645 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
646
647 #define PREFERRED_STACK_BOUNDARY \
648 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
649
650 #define FUNCTION_BOUNDARY 32
651
652 /* The lowest bit is used to indicate Thumb-mode functions, so the
653 vbit must go into the delta field of pointers to member
654 functions. */
655 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
656
657 #define EMPTY_FIELD_BOUNDARY 32
658
659 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
660
661 /* XXX Blah -- this macro is used directly by libobjc. Since it
662 supports no vector modes, cut out the complexity and fall back
663 on BIGGEST_FIELD_ALIGNMENT. */
664 #ifdef IN_TARGET_LIBS
665 #define BIGGEST_FIELD_ALIGNMENT 64
666 #endif
667
668 /* Make strings word-aligned so strcpy from constants will be faster. */
669 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
670
671 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
672 ((TREE_CODE (EXP) == STRING_CST \
673 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
674 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
675
676 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
677 value set in previous versions of this toolchain was 8, which produces more
678 compact structures. The command line option -mstructure_size_boundary=<n>
679 can be used to change this value. For compatibility with the ARM SDK
680 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
681 0020D) page 2-20 says "Structures are aligned on word boundaries".
682 The AAPCS specifies a value of 8. */
683 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
684 extern int arm_structure_size_boundary;
685
686 /* This is the value used to initialize arm_structure_size_boundary. If a
687 particular arm target wants to change the default value it should change
688 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
689 for an example of this. */
690 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
691 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
692 #endif
693
694 /* Used when parsing command line option -mstructure_size_boundary. */
695 extern const char * structure_size_string;
696
697 /* Nonzero if move instructions will actually fail to work
698 when given unaligned data. */
699 #define STRICT_ALIGNMENT 1
700
701 /* wchar_t is unsigned under the AAPCS. */
702 #ifndef WCHAR_TYPE
703 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
704
705 #define WCHAR_TYPE_SIZE BITS_PER_WORD
706 #endif
707
708 #ifndef SIZE_TYPE
709 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
710 #endif
711
712 /* AAPCS requires that structure alignment is affected by bitfields. */
713 #ifndef PCC_BITFIELD_TYPE_MATTERS
714 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
715 #endif
716
717 \f
718 /* Standard register usage. */
719
720 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
721 (S - saved over call).
722
723 r0 * argument word/integer result
724 r1-r3 argument word
725
726 r4-r8 S register variable
727 r9 S (rfp) register variable (real frame pointer)
728
729 r10 F S (sl) stack limit (used by -mapcs-stack-check)
730 r11 F S (fp) argument pointer
731 r12 (ip) temp workspace
732 r13 F S (sp) lower end of current stack frame
733 r14 (lr) link address/workspace
734 r15 F (pc) program counter
735
736 f0 floating point result
737 f1-f3 floating point scratch
738
739 f4-f7 S floating point variable
740
741 cc This is NOT a real register, but is used internally
742 to represent things that use or set the condition
743 codes.
744 sfp This isn't either. It is used during rtl generation
745 since the offset between the frame pointer and the
746 auto's isn't known until after register allocation.
747 afp Nor this, we only need this because of non-local
748 goto. Without it fp appears to be used and the
749 elimination code won't get rid of sfp. It tracks
750 fp exactly at all times.
751
752 *: See CONDITIONAL_REGISTER_USAGE */
753
754 /*
755 mvf0 Cirrus floating point result
756 mvf1-mvf3 Cirrus floating point scratch
757 mvf4-mvf15 S Cirrus floating point variable. */
758
759 /* s0-s15 VFP scratch (aka d0-d7).
760 s16-s31 S VFP variable (aka d8-d15).
761 vfpcc Not a real register. Represents the VFP condition
762 code flags. */
763
764 /* The stack backtrace structure is as follows:
765 fp points to here: | save code pointer | [fp]
766 | return link value | [fp, #-4]
767 | return sp value | [fp, #-8]
768 | return fp value | [fp, #-12]
769 [| saved r10 value |]
770 [| saved r9 value |]
771 [| saved r8 value |]
772 [| saved r7 value |]
773 [| saved r6 value |]
774 [| saved r5 value |]
775 [| saved r4 value |]
776 [| saved r3 value |]
777 [| saved r2 value |]
778 [| saved r1 value |]
779 [| saved r0 value |]
780 [| saved f7 value |] three words
781 [| saved f6 value |] three words
782 [| saved f5 value |] three words
783 [| saved f4 value |] three words
784 r0-r3 are not normally saved in a C function. */
785
786 /* 1 for registers that have pervasive standard uses
787 and are not available for the register allocator. */
788 #define FIXED_REGISTERS \
789 { \
790 0,0,0,0,0,0,0,0, \
791 0,0,0,0,0,1,0,1, \
792 0,0,0,0,0,0,0,0, \
793 1,1,1, \
794 1,1,1,1,1,1,1,1, \
795 1,1,1,1,1,1,1,1, \
796 1,1,1,1,1,1,1,1, \
797 1,1,1,1,1,1,1,1, \
798 1,1,1,1, \
799 1,1,1,1,1,1,1,1, \
800 1,1,1,1,1,1,1,1, \
801 1,1,1,1,1,1,1,1, \
802 1,1,1,1,1,1,1,1, \
803 1 \
804 }
805
806 /* 1 for registers not available across function calls.
807 These must include the FIXED_REGISTERS and also any
808 registers that can be used without being saved.
809 The latter must include the registers where values are returned
810 and the register where structure-value addresses are passed.
811 Aside from that, you can include as many other registers as you like.
812 The CC is not preserved over function calls on the ARM 6, so it is
813 easier to assume this for all. SFP is preserved, since FP is. */
814 #define CALL_USED_REGISTERS \
815 { \
816 1,1,1,1,0,0,0,0, \
817 0,0,0,0,1,1,1,1, \
818 1,1,1,1,0,0,0,0, \
819 1,1,1, \
820 1,1,1,1,1,1,1,1, \
821 1,1,1,1,1,1,1,1, \
822 1,1,1,1,1,1,1,1, \
823 1,1,1,1,1,1,1,1, \
824 1,1,1,1, \
825 1,1,1,1,1,1,1,1, \
826 1,1,1,1,1,1,1,1, \
827 1,1,1,1,1,1,1,1, \
828 1,1,1,1,1,1,1,1, \
829 1 \
830 }
831
832 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
833 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
834 #endif
835
836 #define CONDITIONAL_REGISTER_USAGE \
837 { \
838 int regno; \
839 \
840 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
841 { \
842 for (regno = FIRST_FPA_REGNUM; \
843 regno <= LAST_FPA_REGNUM; ++regno) \
844 fixed_regs[regno] = call_used_regs[regno] = 1; \
845 } \
846 \
847 if (TARGET_THUMB && optimize_size) \
848 { \
849 /* When optimizing for size, it's better not to use \
850 the HI regs, because of the overhead of stacking \
851 them. */ \
852 for (regno = FIRST_HI_REGNUM; \
853 regno <= LAST_HI_REGNUM; ++regno) \
854 fixed_regs[regno] = call_used_regs[regno] = 1; \
855 } \
856 \
857 /* The link register can be clobbered by any branch insn, \
858 but we have no way to track that at present, so mark \
859 it as unavailable. */ \
860 if (TARGET_THUMB) \
861 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
862 \
863 if (TARGET_ARM && TARGET_HARD_FLOAT) \
864 { \
865 if (TARGET_MAVERICK) \
866 { \
867 for (regno = FIRST_FPA_REGNUM; \
868 regno <= LAST_FPA_REGNUM; ++ regno) \
869 fixed_regs[regno] = call_used_regs[regno] = 1; \
870 for (regno = FIRST_CIRRUS_FP_REGNUM; \
871 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
872 { \
873 fixed_regs[regno] = 0; \
874 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
875 } \
876 } \
877 if (TARGET_VFP) \
878 { \
879 for (regno = FIRST_VFP_REGNUM; \
880 regno <= LAST_VFP_REGNUM; ++ regno) \
881 { \
882 fixed_regs[regno] = 0; \
883 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
884 } \
885 } \
886 } \
887 \
888 if (TARGET_REALLY_IWMMXT) \
889 { \
890 regno = FIRST_IWMMXT_GR_REGNUM; \
891 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
892 and wCG1 as call-preserved registers. The 2002/11/21 \
893 revision changed this so that all wCG registers are \
894 scratch registers. */ \
895 for (regno = FIRST_IWMMXT_GR_REGNUM; \
896 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
897 fixed_regs[regno] = call_used_regs[regno] = 0; \
898 /* The XScale ABI has wR0 - wR9 as scratch registers, \
899 the rest as call-preserved registers. */ \
900 for (regno = FIRST_IWMMXT_REGNUM; \
901 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
902 { \
903 fixed_regs[regno] = 0; \
904 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
905 } \
906 } \
907 \
908 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
909 { \
910 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
911 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
912 } \
913 else if (TARGET_APCS_STACK) \
914 { \
915 fixed_regs[10] = 1; \
916 call_used_regs[10] = 1; \
917 } \
918 if (TARGET_APCS_FRAME) \
919 { \
920 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
921 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
922 } \
923 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
924 }
925
926 /* These are a couple of extensions to the formats accepted
927 by asm_fprintf:
928 %@ prints out ASM_COMMENT_START
929 %r prints out REGISTER_PREFIX reg_names[arg] */
930 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
931 case '@': \
932 fputs (ASM_COMMENT_START, FILE); \
933 break; \
934 \
935 case 'r': \
936 fputs (REGISTER_PREFIX, FILE); \
937 fputs (reg_names [va_arg (ARGS, int)], FILE); \
938 break;
939
940 /* Round X up to the nearest word. */
941 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
942
943 /* Convert fron bytes to ints. */
944 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
945
946 /* The number of (integer) registers required to hold a quantity of type MODE.
947 Also used for VFP registers. */
948 #define ARM_NUM_REGS(MODE) \
949 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
950
951 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
952 #define ARM_NUM_REGS2(MODE, TYPE) \
953 ARM_NUM_INTS ((MODE) == BLKmode ? \
954 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
955
956 /* The number of (integer) argument register available. */
957 #define NUM_ARG_REGS 4
958
959 /* Return the register number of the N'th (integer) argument. */
960 #define ARG_REGISTER(N) (N - 1)
961
962 /* Specify the registers used for certain standard purposes.
963 The values of these macros are register numbers. */
964
965 /* The number of the last argument register. */
966 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
967
968 /* The numbers of the Thumb register ranges. */
969 #define FIRST_LO_REGNUM 0
970 #define LAST_LO_REGNUM 7
971 #define FIRST_HI_REGNUM 8
972 #define LAST_HI_REGNUM 11
973
974 /* We use sjlj exceptions for backwards compatibility. */
975 #define MUST_USE_SJLJ_EXCEPTIONS 1
976 /* We can generate DWARF2 Unwind info, even though we don't use it. */
977 #define DWARF2_UNWIND_INFO 1
978
979 /* Use r0 and r1 to pass exception handling information. */
980 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
981
982 /* The register that holds the return address in exception handlers. */
983 #define ARM_EH_STACKADJ_REGNUM 2
984 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
985
986 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
987 as an invisible last argument (possible since varargs don't exist in
988 Pascal), so the following is not true. */
989 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
990
991 /* Define this to be where the real frame pointer is if it is not possible to
992 work out the offset between the frame pointer and the automatic variables
993 until after register allocation has taken place. FRAME_POINTER_REGNUM
994 should point to a special register that we will make sure is eliminated.
995
996 For the Thumb we have another problem. The TPCS defines the frame pointer
997 as r11, and GCC believes that it is always possible to use the frame pointer
998 as base register for addressing purposes. (See comments in
999 find_reloads_address()). But - the Thumb does not allow high registers,
1000 including r11, to be used as base address registers. Hence our problem.
1001
1002 The solution used here, and in the old thumb port is to use r7 instead of
1003 r11 as the hard frame pointer and to have special code to generate
1004 backtrace structures on the stack (if required to do so via a command line
1005 option) using r11. This is the only 'user visible' use of r11 as a frame
1006 pointer. */
1007 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1008 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1009
1010 #define HARD_FRAME_POINTER_REGNUM \
1011 (TARGET_ARM \
1012 ? ARM_HARD_FRAME_POINTER_REGNUM \
1013 : THUMB_HARD_FRAME_POINTER_REGNUM)
1014
1015 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1016
1017 /* Register to use for pushing function arguments. */
1018 #define STACK_POINTER_REGNUM SP_REGNUM
1019
1020 /* ARM floating pointer registers. */
1021 #define FIRST_FPA_REGNUM 16
1022 #define LAST_FPA_REGNUM 23
1023
1024 #define FIRST_IWMMXT_GR_REGNUM 43
1025 #define LAST_IWMMXT_GR_REGNUM 46
1026 #define FIRST_IWMMXT_REGNUM 47
1027 #define LAST_IWMMXT_REGNUM 62
1028 #define IS_IWMMXT_REGNUM(REGNUM) \
1029 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1030 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1031 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1032
1033 /* Base register for access to local variables of the function. */
1034 #define FRAME_POINTER_REGNUM 25
1035
1036 /* Base register for access to arguments of the function. */
1037 #define ARG_POINTER_REGNUM 26
1038
1039 #define FIRST_CIRRUS_FP_REGNUM 27
1040 #define LAST_CIRRUS_FP_REGNUM 42
1041 #define IS_CIRRUS_REGNUM(REGNUM) \
1042 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1043
1044 #define FIRST_VFP_REGNUM 63
1045 #define LAST_VFP_REGNUM 94
1046 #define IS_VFP_REGNUM(REGNUM) \
1047 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1048
1049 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1050 /* + 16 Cirrus registers take us up to 43. */
1051 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1052 /* VFP adds 32 + 1 more. */
1053 #define FIRST_PSEUDO_REGISTER 96
1054
1055 /* Value should be nonzero if functions must have frame pointers.
1056 Zero means the frame pointer need not be set up (and parms may be accessed
1057 via the stack pointer) in functions that seem suitable.
1058 If we have to have a frame pointer we might as well make use of it.
1059 APCS says that the frame pointer does not need to be pushed in leaf
1060 functions, or simple tail call functions. */
1061 #define FRAME_POINTER_REQUIRED \
1062 (current_function_has_nonlocal_label \
1063 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1064
1065 /* Return number of consecutive hard regs needed starting at reg REGNO
1066 to hold something of mode MODE.
1067 This is ordinarily the length in words of a value of mode MODE
1068 but can be less for certain modes in special long registers.
1069
1070 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1071 mode. */
1072 #define HARD_REGNO_NREGS(REGNO, MODE) \
1073 ((TARGET_ARM \
1074 && REGNO >= FIRST_FPA_REGNUM \
1075 && REGNO != FRAME_POINTER_REGNUM \
1076 && REGNO != ARG_POINTER_REGNUM) \
1077 && !IS_VFP_REGNUM (REGNO) \
1078 ? 1 : ARM_NUM_REGS (MODE))
1079
1080 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1081 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1082 arm_hard_regno_mode_ok ((REGNO), (MODE))
1083
1084 /* Value is 1 if it is a good idea to tie two pseudo registers
1085 when one has mode MODE1 and one has mode MODE2.
1086 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1087 for any hard reg, then this must be 0 for correct output. */
1088 #define MODES_TIEABLE_P(MODE1, MODE2) \
1089 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1090
1091 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1092 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1093
1094 #define VALID_IWMMXT_REG_MODE(MODE) \
1095 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1096
1097 /* The order in which register should be allocated. It is good to use ip
1098 since no saving is required (though calls clobber it) and it never contains
1099 function parameters. It is quite good to use lr since other calls may
1100 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1101 least likely to contain a function parameter; in addition results are
1102 returned in r0. */
1103
1104 #define REG_ALLOC_ORDER \
1105 { \
1106 3, 2, 1, 0, 12, 14, 4, 5, \
1107 6, 7, 8, 10, 9, 11, 13, 15, \
1108 16, 17, 18, 19, 20, 21, 22, 23, \
1109 27, 28, 29, 30, 31, 32, 33, 34, \
1110 35, 36, 37, 38, 39, 40, 41, 42, \
1111 43, 44, 45, 46, 47, 48, 49, 50, \
1112 51, 52, 53, 54, 55, 56, 57, 58, \
1113 59, 60, 61, 62, \
1114 24, 25, 26, \
1115 78, 77, 76, 75, 74, 73, 72, 71, \
1116 70, 69, 68, 67, 66, 65, 64, 63, \
1117 79, 80, 81, 82, 83, 84, 85, 86, \
1118 87, 88, 89, 90, 91, 92, 93, 94, \
1119 95 \
1120 }
1121
1122 /* Interrupt functions can only use registers that have already been
1123 saved by the prologue, even if they would normally be
1124 call-clobbered. */
1125 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1126 (! IS_INTERRUPT (cfun->machine->func_type) || \
1127 regs_ever_live[DST])
1128 \f
1129 /* Register and constant classes. */
1130
1131 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1132 Now that the Thumb is involved it has become more complicated. */
1133 enum reg_class
1134 {
1135 NO_REGS,
1136 FPA_REGS,
1137 CIRRUS_REGS,
1138 VFP_REGS,
1139 IWMMXT_GR_REGS,
1140 IWMMXT_REGS,
1141 LO_REGS,
1142 STACK_REG,
1143 BASE_REGS,
1144 HI_REGS,
1145 CC_REG,
1146 VFPCC_REG,
1147 GENERAL_REGS,
1148 ALL_REGS,
1149 LIM_REG_CLASSES
1150 };
1151
1152 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1153
1154 /* Give names of register classes as strings for dump file. */
1155 #define REG_CLASS_NAMES \
1156 { \
1157 "NO_REGS", \
1158 "FPA_REGS", \
1159 "CIRRUS_REGS", \
1160 "VFP_REGS", \
1161 "IWMMXT_GR_REGS", \
1162 "IWMMXT_REGS", \
1163 "LO_REGS", \
1164 "STACK_REG", \
1165 "BASE_REGS", \
1166 "HI_REGS", \
1167 "CC_REG", \
1168 "VFPCC_REG", \
1169 "GENERAL_REGS", \
1170 "ALL_REGS", \
1171 }
1172
1173 /* Define which registers fit in which classes.
1174 This is an initializer for a vector of HARD_REG_SET
1175 of length N_REG_CLASSES. */
1176 #define REG_CLASS_CONTENTS \
1177 { \
1178 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1179 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1180 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1181 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1182 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1183 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1184 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1185 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1186 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1187 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1188 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1189 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1190 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1191 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1192 }
1193
1194 /* The same information, inverted:
1195 Return the class number of the smallest class containing
1196 reg number REGNO. This could be a conditional expression
1197 or could index an array. */
1198 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1199
1200 /* FPA registers can't do subreg as all values are reformatted to internal
1201 precision. VFP registers may only be accessed in the mode they
1202 were set. */
1203 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1204 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1205 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1206 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1207 : 0)
1208
1209 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1210 using r0-r4 for function arguments, r7 for the stack frame and don't
1211 have enough left over to do doubleword arithmetic. */
1212 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1213 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1214 || (CLASS) == CC_REG)
1215
1216 /* The class value for index registers, and the one for base regs. */
1217 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1218 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1219
1220 /* For the Thumb the high registers cannot be used as base registers
1221 when addressing quantities in QI or HI mode; if we don't know the
1222 mode, then we must be conservative. After reload we must also be
1223 conservative, since we can't support SP+reg addressing, and we
1224 can't fix up any bad substitutions. */
1225 #define MODE_BASE_REG_CLASS(MODE) \
1226 (TARGET_ARM ? GENERAL_REGS : \
1227 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1228
1229 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1230 registers explicitly used in the rtl to be used as spill registers
1231 but prevents the compiler from extending the lifetime of these
1232 registers. */
1233 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1234
1235 /* Get reg_class from a letter such as appears in the machine description.
1236 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1237 ARM, but several more letters for the Thumb. */
1238 #define REG_CLASS_FROM_LETTER(C) \
1239 ( (C) == 'f' ? FPA_REGS \
1240 : (C) == 'v' ? CIRRUS_REGS \
1241 : (C) == 'w' ? VFP_REGS \
1242 : (C) == 'y' ? IWMMXT_REGS \
1243 : (C) == 'z' ? IWMMXT_GR_REGS \
1244 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1245 : TARGET_ARM ? NO_REGS \
1246 : (C) == 'h' ? HI_REGS \
1247 : (C) == 'b' ? BASE_REGS \
1248 : (C) == 'k' ? STACK_REG \
1249 : (C) == 'c' ? CC_REG \
1250 : NO_REGS)
1251
1252 /* The letters I, J, K, L and M in a register constraint string
1253 can be used to stand for particular ranges of immediate operands.
1254 This macro defines what the ranges are.
1255 C is the letter, and VALUE is a constant value.
1256 Return 1 if VALUE is in the range specified by C.
1257 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1258 J: valid indexing constants.
1259 K: ~value ok in rhs argument of data operand.
1260 L: -value ok in rhs argument of data operand.
1261 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1262 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1263 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1264 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1265 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1266 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1267 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1268 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1269 : 0)
1270
1271 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1272 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1273 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1274 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1275 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1276 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1277 && ((VAL) & 3) == 0) : \
1278 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1279 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1280 : 0)
1281
1282 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1283 (TARGET_ARM ? \
1284 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1285
1286 /* Constant letter 'G' for the FP immediate constants.
1287 'H' means the same constant negated. */
1288 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1289 ((C) == 'G' ? arm_const_double_rtx (X) : \
1290 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1291
1292 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1293 (TARGET_ARM ? \
1294 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1295
1296 /* For the ARM, `Q' means that this is a memory operand that is just
1297 an offset from a register.
1298 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1299 address. This means that the symbol is in the text segment and can be
1300 accessed without using a load.
1301 'U' Prefixes an extended memory constraint where:
1302 'Uv' is an address valid for VFP load/store insns.
1303 'Uy' is an address valid for iwmmxt load/store insns.
1304 'Uq' is an address valid for ldrsb. */
1305
1306 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1307 (((C) == 'Q') ? (GET_CODE (OP) == MEM \
1308 && GET_CODE (XEXP (OP, 0)) == REG) : \
1309 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1310 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1311 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1312 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1313 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1314 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1315 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1316 ((C) == 'U' && (STR)[1] == 'q') \
1317 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1318 : 0)
1319
1320 #define CONSTRAINT_LEN(C,STR) \
1321 ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1322
1323 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1324 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1325 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1326
1327 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1328 (TARGET_ARM \
1329 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1330 : EXTRA_CONSTRAINT_THUMB (X, C))
1331
1332 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1333
1334 /* Given an rtx X being reloaded into a reg required to be
1335 in class CLASS, return the class of reg to actually use.
1336 In general this is just CLASS, but for the Thumb we prefer
1337 a LO_REGS class or a subset. */
1338 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1339 (TARGET_ARM ? (CLASS) : \
1340 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1341
1342 /* Must leave BASE_REGS reloads alone */
1343 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1344 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1345 ? ((true_regnum (X) == -1 ? LO_REGS \
1346 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1347 : NO_REGS)) \
1348 : NO_REGS)
1349
1350 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1351 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1352 ? ((true_regnum (X) == -1 ? LO_REGS \
1353 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1354 : NO_REGS)) \
1355 : NO_REGS)
1356
1357 /* Return the register class of a scratch register needed to copy IN into
1358 or out of a register in CLASS in MODE. If it can be done directly,
1359 NO_REGS is returned. */
1360 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1361 /* Restrict which direct reloads are allowed for VFP regs. */ \
1362 ((TARGET_VFP && TARGET_HARD_FLOAT \
1363 && (CLASS) == VFP_REGS) \
1364 ? vfp_secondary_reload_class (MODE, X) \
1365 : TARGET_ARM \
1366 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1367 ? GENERAL_REGS : NO_REGS) \
1368 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1369
1370 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1371 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1372 /* Restrict which direct reloads are allowed for VFP regs. */ \
1373 ((TARGET_VFP && TARGET_HARD_FLOAT \
1374 && (CLASS) == VFP_REGS) \
1375 ? vfp_secondary_reload_class (MODE, X) : \
1376 /* Cannot load constants into Cirrus registers. */ \
1377 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1378 && (CLASS) == CIRRUS_REGS \
1379 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1380 ? GENERAL_REGS : \
1381 (TARGET_ARM ? \
1382 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1383 && CONSTANT_P (X)) \
1384 ? GENERAL_REGS : \
1385 (((MODE) == HImode && ! arm_arch4 \
1386 && (GET_CODE (X) == MEM \
1387 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1388 && true_regnum (X) == -1))) \
1389 ? GENERAL_REGS : NO_REGS) \
1390 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1391
1392 /* Try a machine-dependent way of reloading an illegitimate address
1393 operand. If we find one, push the reload and jump to WIN. This
1394 macro is used in only one place: `find_reloads_address' in reload.c.
1395
1396 For the ARM, we wish to handle large displacements off a base
1397 register by splitting the addend across a MOV and the mem insn.
1398 This can cut the number of reloads needed. */
1399 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1400 do \
1401 { \
1402 if (GET_CODE (X) == PLUS \
1403 && GET_CODE (XEXP (X, 0)) == REG \
1404 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1405 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1406 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1407 { \
1408 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1409 HOST_WIDE_INT low, high; \
1410 \
1411 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1412 low = ((val & 0xf) ^ 0x8) - 0x8; \
1413 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1414 /* Need to be careful, -256 is not a valid offset. */ \
1415 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1416 else if (MODE == SImode \
1417 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1418 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1419 /* Need to be careful, -4096 is not a valid offset. */ \
1420 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1421 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1422 /* Need to be careful, -256 is not a valid offset. */ \
1423 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1424 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1425 && TARGET_HARD_FLOAT && TARGET_FPA) \
1426 /* Need to be careful, -1024 is not a valid offset. */ \
1427 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1428 else \
1429 break; \
1430 \
1431 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1432 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1433 - (unsigned HOST_WIDE_INT) 0x80000000); \
1434 /* Check for overflow or zero */ \
1435 if (low == 0 || high == 0 || (high + low != val)) \
1436 break; \
1437 \
1438 /* Reload the high part into a base reg; leave the low part \
1439 in the mem. */ \
1440 X = gen_rtx_PLUS (GET_MODE (X), \
1441 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1442 GEN_INT (high)), \
1443 GEN_INT (low)); \
1444 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1445 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1446 VOIDmode, 0, 0, OPNUM, TYPE); \
1447 goto WIN; \
1448 } \
1449 } \
1450 while (0)
1451
1452 /* XXX If an HImode FP+large_offset address is converted to an HImode
1453 SP+large_offset address, then reload won't know how to fix it. It sees
1454 only that SP isn't valid for HImode, and so reloads the SP into an index
1455 register, but the resulting address is still invalid because the offset
1456 is too big. We fix it here instead by reloading the entire address. */
1457 /* We could probably achieve better results by defining PROMOTE_MODE to help
1458 cope with the variances between the Thumb's signed and unsigned byte and
1459 halfword load instructions. */
1460 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1461 { \
1462 if (GET_CODE (X) == PLUS \
1463 && GET_MODE_SIZE (MODE) < 4 \
1464 && GET_CODE (XEXP (X, 0)) == REG \
1465 && XEXP (X, 0) == stack_pointer_rtx \
1466 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1467 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1468 { \
1469 rtx orig_X = X; \
1470 X = copy_rtx (X); \
1471 push_reload (orig_X, NULL_RTX, &X, NULL, \
1472 MODE_BASE_REG_CLASS (MODE), \
1473 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1474 goto WIN; \
1475 } \
1476 }
1477
1478 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1479 if (TARGET_ARM) \
1480 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1481 else \
1482 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1483
1484 /* Return the maximum number of consecutive registers
1485 needed to represent mode MODE in a register of class CLASS.
1486 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1487 #define CLASS_MAX_NREGS(CLASS, MODE) \
1488 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1489
1490 /* If defined, gives a class of registers that cannot be used as the
1491 operand of a SUBREG that changes the mode of the object illegally. */
1492
1493 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1494 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1495 (TARGET_ARM ? \
1496 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1497 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1498 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1499 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1500 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1501 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1502 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1503 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1504 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1505 2) \
1506 : \
1507 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1508 \f
1509 /* Stack layout; function entry, exit and calling. */
1510
1511 /* Define this if pushing a word on the stack
1512 makes the stack pointer a smaller address. */
1513 #define STACK_GROWS_DOWNWARD 1
1514
1515 /* Define this if the nominal address of the stack frame
1516 is at the high-address end of the local variables;
1517 that is, each additional local variable allocated
1518 goes at a more negative offset in the frame. */
1519 #define FRAME_GROWS_DOWNWARD 1
1520
1521 /* Offset within stack frame to start allocating local variables at.
1522 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1523 first local allocated. Otherwise, it is the offset to the BEGINNING
1524 of the first local allocated. */
1525 #define STARTING_FRAME_OFFSET 0
1526
1527 /* If we generate an insn to push BYTES bytes,
1528 this says how many the stack pointer really advances by. */
1529 /* The push insns do not do this rounding implicitly.
1530 So don't define this. */
1531 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1532
1533 /* Define this if the maximum size of all the outgoing args is to be
1534 accumulated and pushed during the prologue. The amount can be
1535 found in the variable current_function_outgoing_args_size. */
1536 #define ACCUMULATE_OUTGOING_ARGS 1
1537
1538 /* Offset of first parameter from the argument pointer register value. */
1539 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1540
1541 /* Value is the number of byte of arguments automatically
1542 popped when returning from a subroutine call.
1543 FUNDECL is the declaration node of the function (as a tree),
1544 FUNTYPE is the data type of the function (as a tree),
1545 or for a library call it is an identifier node for the subroutine name.
1546 SIZE is the number of bytes of arguments passed on the stack.
1547
1548 On the ARM, the caller does not pop any of its arguments that were passed
1549 on the stack. */
1550 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1551
1552 /* Define how to find the value returned by a library function
1553 assuming the value has mode MODE. */
1554 #define LIBCALL_VALUE(MODE) \
1555 (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
1556 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1557 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1558 : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
1559 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1560 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1561 : TARGET_IWMMXT_ABI && VECTOR_MODE_SUPPORTED_P (MODE) \
1562 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1563 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1564
1565 /* Define how to find the value returned by a function.
1566 VALTYPE is the data type of the value (as a tree).
1567 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1568 otherwise, FUNC is 0. */
1569 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1570 arm_function_value (VALTYPE, FUNC);
1571
1572 /* 1 if N is a possible register number for a function value.
1573 On the ARM, only r0 and f0 can return results. */
1574 /* On a Cirrus chip, mvf0 can return results. */
1575 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1576 ((REGNO) == ARG_REGISTER (1) \
1577 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1578 && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
1579 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1580 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1581 && TARGET_HARD_FLOAT && TARGET_FPA))
1582
1583 /* How large values are returned */
1584 /* A C expression which can inhibit the returning of certain function values
1585 in registers, based on the type of value. */
1586 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1587
1588 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1589 values must be in memory. On the ARM, they need only do so if larger
1590 than a word, or if they contain elements offset from zero in the struct. */
1591 #define DEFAULT_PCC_STRUCT_RETURN 0
1592
1593 /* Flags for the call/call_value rtl operations set up by function_arg. */
1594 #define CALL_NORMAL 0x00000000 /* No special processing. */
1595 #define CALL_LONG 0x00000001 /* Always call indirect. */
1596 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1597
1598 /* These bits describe the different types of function supported
1599 by the ARM backend. They are exclusive. ie a function cannot be both a
1600 normal function and an interworked function, for example. Knowing the
1601 type of a function is important for determining its prologue and
1602 epilogue sequences.
1603 Note value 7 is currently unassigned. Also note that the interrupt
1604 function types all have bit 2 set, so that they can be tested for easily.
1605 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1606 machine_function structure is initialized (to zero) func_type will
1607 default to unknown. This will force the first use of arm_current_func_type
1608 to call arm_compute_func_type. */
1609 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1610 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1611 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1612 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1613 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1614 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1615
1616 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1617
1618 /* In addition functions can have several type modifiers,
1619 outlined by these bit masks: */
1620 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1621 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1622 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1623 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1624
1625 /* Some macros to test these flags. */
1626 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1627 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1628 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1629 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1630 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1631
1632
1633 /* Structure used to hold the function stack frame layout. Offsets are
1634 relative to the stack pointer on function entry. Positive offsets are
1635 in the direction of stack growth.
1636 Only soft_frame is used in thumb mode. */
1637
1638 typedef struct arm_stack_offsets GTY(())
1639 {
1640 int saved_args; /* ARG_POINTER_REGNUM. */
1641 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1642 int saved_regs;
1643 int soft_frame; /* FRAME_POINTER_REGNUM. */
1644 int outgoing_args; /* STACK_POINTER_REGNUM. */
1645 }
1646 arm_stack_offsets;
1647
1648 /* A C structure for machine-specific, per-function data.
1649 This is added to the cfun structure. */
1650 typedef struct machine_function GTY(())
1651 {
1652 /* Additional stack adjustment in __builtin_eh_throw. */
1653 rtx eh_epilogue_sp_ofs;
1654 /* Records if LR has to be saved for far jumps. */
1655 int far_jump_used;
1656 /* Records if ARG_POINTER was ever live. */
1657 int arg_pointer_live;
1658 /* Records if the save of LR has been eliminated. */
1659 int lr_save_eliminated;
1660 /* The size of the stack frame. Only valid after reload. */
1661 arm_stack_offsets stack_offsets;
1662 /* Records the type of the current function. */
1663 unsigned long func_type;
1664 /* Record if the function has a variable argument list. */
1665 int uses_anonymous_args;
1666 /* Records if sibcalls are blocked because an argument
1667 register is needed to preserve stack alignment. */
1668 int sibcall_blocked;
1669 }
1670 machine_function;
1671
1672 /* A C type for declaring a variable that is used as the first argument of
1673 `FUNCTION_ARG' and other related values. For some target machines, the
1674 type `int' suffices and can hold the number of bytes of argument so far. */
1675 typedef struct
1676 {
1677 /* This is the number of registers of arguments scanned so far. */
1678 int nregs;
1679 /* This is the number of iWMMXt register arguments scanned so far. */
1680 int iwmmxt_nregs;
1681 int named_count;
1682 int nargs;
1683 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1684 int call_cookie;
1685 int can_split;
1686 } CUMULATIVE_ARGS;
1687
1688 /* Define where to put the arguments to a function.
1689 Value is zero to push the argument on the stack,
1690 or a hard register in which to store the argument.
1691
1692 MODE is the argument's machine mode.
1693 TYPE is the data type of the argument (as a tree).
1694 This is null for libcalls where that information may
1695 not be available.
1696 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1697 the preceding args and about the function being called.
1698 NAMED is nonzero if this argument is a named parameter
1699 (otherwise it is an extra parameter matching an ellipsis).
1700
1701 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1702 other arguments are passed on the stack. If (NAMED == 0) (which happens
1703 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1704 defined), say it is passed in the stack (function_prologue will
1705 indeed make it pass in the stack if necessary). */
1706 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1707 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1708
1709 /* For an arg passed partly in registers and partly in memory,
1710 this is the number of registers used.
1711 For args passed entirely in registers or entirely in memory, zero. */
1712 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1713 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1714 NUM_ARG_REGS > (CUM).nregs \
1715 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE)) \
1716 && (CUM).can_split) \
1717 ? NUM_ARG_REGS - (CUM).nregs : 0)
1718
1719 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1720 for a call to a function whose data type is FNTYPE.
1721 For a library call, FNTYPE is 0.
1722 On the ARM, the offset starts at 0. */
1723 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1724 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1725
1726 /* Update the data in CUM to advance over an argument
1727 of mode MODE and data type TYPE.
1728 (TYPE is null for libcalls where that information may not be available.) */
1729 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1730 (CUM).nargs += 1; \
1731 if (VECTOR_MODE_SUPPORTED_P (MODE) \
1732 && (CUM).named_count > (CUM).nargs) \
1733 (CUM).iwmmxt_nregs += 1; \
1734 else \
1735 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1736
1737 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1738 argument with the specified mode and type. If it is not defined,
1739 `PARM_BOUNDARY' is used for all arguments. */
1740 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1741 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1742 ? DOUBLEWORD_ALIGNMENT \
1743 : PARM_BOUNDARY )
1744
1745 /* 1 if N is a possible register number for function argument passing.
1746 On the ARM, r0-r3 are used to pass args. */
1747 #define FUNCTION_ARG_REGNO_P(REGNO) \
1748 (IN_RANGE ((REGNO), 0, 3) \
1749 || (TARGET_IWMMXT_ABI \
1750 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1751
1752 \f
1753 /* If your target environment doesn't prefix user functions with an
1754 underscore, you may wish to re-define this to prevent any conflicts.
1755 e.g. AOF may prefix mcount with an underscore. */
1756 #ifndef ARM_MCOUNT_NAME
1757 #define ARM_MCOUNT_NAME "*mcount"
1758 #endif
1759
1760 /* Call the function profiler with a given profile label. The Acorn
1761 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1762 On the ARM the full profile code will look like:
1763 .data
1764 LP1
1765 .word 0
1766 .text
1767 mov ip, lr
1768 bl mcount
1769 .word LP1
1770
1771 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1772 will output the .text section.
1773
1774 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1775 ``prof'' doesn't seem to mind about this!
1776
1777 Note - this version of the code is designed to work in both ARM and
1778 Thumb modes. */
1779 #ifndef ARM_FUNCTION_PROFILER
1780 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1781 { \
1782 char temp[20]; \
1783 rtx sym; \
1784 \
1785 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1786 IP_REGNUM, LR_REGNUM); \
1787 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1788 fputc ('\n', STREAM); \
1789 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1790 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1791 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1792 }
1793 #endif
1794
1795 #ifdef THUMB_FUNCTION_PROFILER
1796 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1797 if (TARGET_ARM) \
1798 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1799 else \
1800 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1801 #else
1802 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1803 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1804 #endif
1805
1806 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1807 the stack pointer does not matter. The value is tested only in
1808 functions that have frame pointers.
1809 No definition is equivalent to always zero.
1810
1811 On the ARM, the function epilogue recovers the stack pointer from the
1812 frame. */
1813 #define EXIT_IGNORE_STACK 1
1814
1815 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1816
1817 /* Determine if the epilogue should be output as RTL.
1818 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1819 #define USE_RETURN_INSN(ISCOND) \
1820 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1821
1822 /* Definitions for register eliminations.
1823
1824 This is an array of structures. Each structure initializes one pair
1825 of eliminable registers. The "from" register number is given first,
1826 followed by "to". Eliminations of the same "from" register are listed
1827 in order of preference.
1828
1829 We have two registers that can be eliminated on the ARM. First, the
1830 arg pointer register can often be eliminated in favor of the stack
1831 pointer register. Secondly, the pseudo frame pointer register can always
1832 be eliminated; it is replaced with either the stack or the real frame
1833 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1834 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1835
1836 #define ELIMINABLE_REGS \
1837 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1838 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1839 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1840 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1841 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1842 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1843 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1844
1845 /* Given FROM and TO register numbers, say whether this elimination is
1846 allowed. Frame pointer elimination is automatically handled.
1847
1848 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1849 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1850 pointer, we must eliminate FRAME_POINTER_REGNUM into
1851 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1852 ARG_POINTER_REGNUM. */
1853 #define CAN_ELIMINATE(FROM, TO) \
1854 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1855 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1856 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1857 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1858 1)
1859
1860 /* Define the offset between two registers, one to be eliminated, and the
1861 other its replacement, at the start of a routine. */
1862 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1863 if (TARGET_ARM) \
1864 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1865 else \
1866 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1867
1868 /* Special case handling of the location of arguments passed on the stack. */
1869 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1870
1871 /* Initialize data used by insn expanders. This is called from insn_emit,
1872 once for every function before code is generated. */
1873 #define INIT_EXPANDERS arm_init_expanders ()
1874
1875 /* Output assembler code for a block containing the constant parts
1876 of a trampoline, leaving space for the variable parts.
1877
1878 On the ARM, (if r8 is the static chain regnum, and remembering that
1879 referencing pc adds an offset of 8) the trampoline looks like:
1880 ldr r8, [pc, #0]
1881 ldr pc, [pc]
1882 .word static chain value
1883 .word function's address
1884 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1885 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1886 { \
1887 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1888 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1889 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1890 PC_REGNUM, PC_REGNUM); \
1891 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1892 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1893 }
1894
1895 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1896 Why - because it is easier. This code will always be branched to via
1897 a BX instruction and since the compiler magically generates the address
1898 of the function the linker has no opportunity to ensure that the
1899 bottom bit is set. Thus the processor will be in ARM mode when it
1900 reaches this code. So we duplicate the ARM trampoline code and add
1901 a switch into Thumb mode as well. */
1902 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1903 { \
1904 fprintf (FILE, "\t.code 32\n"); \
1905 fprintf (FILE, ".Ltrampoline_start:\n"); \
1906 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1907 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1908 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1909 IP_REGNUM, PC_REGNUM); \
1910 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1911 IP_REGNUM, IP_REGNUM); \
1912 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1913 fprintf (FILE, "\t.word\t0\n"); \
1914 fprintf (FILE, "\t.word\t0\n"); \
1915 fprintf (FILE, "\t.code 16\n"); \
1916 }
1917
1918 #define TRAMPOLINE_TEMPLATE(FILE) \
1919 if (TARGET_ARM) \
1920 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1921 else \
1922 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1923
1924 /* Length in units of the trampoline for entering a nested function. */
1925 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1926
1927 /* Alignment required for a trampoline in bits. */
1928 #define TRAMPOLINE_ALIGNMENT 32
1929
1930 /* Emit RTL insns to initialize the variable parts of a trampoline.
1931 FNADDR is an RTX for the address of the function's pure code.
1932 CXT is an RTX for the static chain value for the function. */
1933 #ifndef INITIALIZE_TRAMPOLINE
1934 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1935 { \
1936 emit_move_insn (gen_rtx_MEM (SImode, \
1937 plus_constant (TRAMP, \
1938 TARGET_ARM ? 8 : 16)), \
1939 CXT); \
1940 emit_move_insn (gen_rtx_MEM (SImode, \
1941 plus_constant (TRAMP, \
1942 TARGET_ARM ? 12 : 20)), \
1943 FNADDR); \
1944 }
1945 #endif
1946
1947 \f
1948 /* Addressing modes, and classification of registers for them. */
1949 #define HAVE_POST_INCREMENT 1
1950 #define HAVE_PRE_INCREMENT TARGET_ARM
1951 #define HAVE_POST_DECREMENT TARGET_ARM
1952 #define HAVE_PRE_DECREMENT TARGET_ARM
1953 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1954 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1955 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1956 #define HAVE_POST_MODIFY_REG TARGET_ARM
1957
1958 /* Macros to check register numbers against specific register classes. */
1959
1960 /* These assume that REGNO is a hard or pseudo reg number.
1961 They give nonzero only if REGNO is a hard reg of the suitable class
1962 or a pseudo reg currently allocated to a suitable hard reg.
1963 Since they use reg_renumber, they are safe only once reg_renumber
1964 has been allocated, which happens in local-alloc.c. */
1965 #define TEST_REGNO(R, TEST, VALUE) \
1966 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1967
1968 /* On the ARM, don't allow the pc to be used. */
1969 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1970 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1971 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1972 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1973
1974 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1975 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1976 || (GET_MODE_SIZE (MODE) >= 4 \
1977 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1978
1979 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1980 (TARGET_THUMB \
1981 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1982 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1983
1984 /* For ARM code, we don't care about the mode, but for Thumb, the index
1985 must be suitable for use in a QImode load. */
1986 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1987 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1988
1989 /* Maximum number of registers that can appear in a valid memory address.
1990 Shifts in addresses can't be by a register. */
1991 #define MAX_REGS_PER_ADDRESS 2
1992
1993 /* Recognize any constant value that is a valid address. */
1994 /* XXX We can address any constant, eventually... */
1995
1996 #ifdef AOF_ASSEMBLER
1997
1998 #define CONSTANT_ADDRESS_P(X) \
1999 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2000
2001 #else
2002
2003 #define CONSTANT_ADDRESS_P(X) \
2004 (GET_CODE (X) == SYMBOL_REF \
2005 && (CONSTANT_POOL_ADDRESS_P (X) \
2006 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2007
2008 #endif /* AOF_ASSEMBLER */
2009
2010 /* Nonzero if the constant value X is a legitimate general operand.
2011 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2012
2013 On the ARM, allow any integer (invalid ones are removed later by insn
2014 patterns), nice doubles and symbol_refs which refer to the function's
2015 constant pool XXX.
2016
2017 When generating pic allow anything. */
2018 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2019
2020 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2021 ( GET_CODE (X) == CONST_INT \
2022 || GET_CODE (X) == CONST_DOUBLE \
2023 || CONSTANT_ADDRESS_P (X) \
2024 || flag_pic)
2025
2026 #define LEGITIMATE_CONSTANT_P(X) \
2027 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2028
2029 /* Special characters prefixed to function names
2030 in order to encode attribute like information.
2031 Note, '@' and '*' have already been taken. */
2032 #define SHORT_CALL_FLAG_CHAR '^'
2033 #define LONG_CALL_FLAG_CHAR '#'
2034
2035 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2036 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2037
2038 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2039 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2040
2041 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2042 #define SUBTARGET_NAME_ENCODING_LENGTHS
2043 #endif
2044
2045 /* This is a C fragment for the inside of a switch statement.
2046 Each case label should return the number of characters to
2047 be stripped from the start of a function's name, if that
2048 name starts with the indicated character. */
2049 #define ARM_NAME_ENCODING_LENGTHS \
2050 case SHORT_CALL_FLAG_CHAR: return 1; \
2051 case LONG_CALL_FLAG_CHAR: return 1; \
2052 case '*': return 1; \
2053 SUBTARGET_NAME_ENCODING_LENGTHS
2054
2055 /* This is how to output a reference to a user-level label named NAME.
2056 `assemble_name' uses this. */
2057 #undef ASM_OUTPUT_LABELREF
2058 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2059 arm_asm_output_labelref (FILE, NAME)
2060
2061 /* Set the short-call flag for any function compiled in the current
2062 compilation unit. We skip this for functions with the section
2063 attirubte when long-calls are in effect as this tells the compiler
2064 that the section might be placed a long way from the caller.
2065 See arm_is_longcall_p() for more information. */
2066 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2067 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
2068 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2069
2070 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2071 and check its validity for a certain class.
2072 We have two alternate definitions for each of them.
2073 The usual definition accepts all pseudo regs; the other rejects
2074 them unless they have been allocated suitable hard regs.
2075 The symbol REG_OK_STRICT causes the latter definition to be used. */
2076 #ifndef REG_OK_STRICT
2077
2078 #define ARM_REG_OK_FOR_BASE_P(X) \
2079 (REGNO (X) <= LAST_ARM_REGNUM \
2080 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2081 || REGNO (X) == FRAME_POINTER_REGNUM \
2082 || REGNO (X) == ARG_POINTER_REGNUM)
2083
2084 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2085 (REGNO (X) <= LAST_LO_REGNUM \
2086 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2087 || (GET_MODE_SIZE (MODE) >= 4 \
2088 && (REGNO (X) == STACK_POINTER_REGNUM \
2089 || (X) == hard_frame_pointer_rtx \
2090 || (X) == arg_pointer_rtx)))
2091
2092 #define REG_STRICT_P 0
2093
2094 #else /* REG_OK_STRICT */
2095
2096 #define ARM_REG_OK_FOR_BASE_P(X) \
2097 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2098
2099 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2100 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2101
2102 #define REG_STRICT_P 1
2103
2104 #endif /* REG_OK_STRICT */
2105
2106 /* Now define some helpers in terms of the above. */
2107
2108 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2109 (TARGET_THUMB \
2110 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2111 : ARM_REG_OK_FOR_BASE_P (X))
2112
2113 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2114
2115 /* For Thumb, a valid index register is anything that can be used in
2116 a byte load instruction. */
2117 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2118
2119 /* Nonzero if X is a hard reg that can be used as an index
2120 or if it is a pseudo reg. On the Thumb, the stack pointer
2121 is not suitable. */
2122 #define REG_OK_FOR_INDEX_P(X) \
2123 (TARGET_THUMB \
2124 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2125 : ARM_REG_OK_FOR_INDEX_P (X))
2126
2127 \f
2128 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2129 that is a valid memory address for an instruction.
2130 The MODE argument is the machine mode for the MEM expression
2131 that wants to use this address. */
2132
2133 #define ARM_BASE_REGISTER_RTX_P(X) \
2134 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2135
2136 #define ARM_INDEX_REGISTER_RTX_P(X) \
2137 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2138
2139 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2140 { \
2141 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2142 goto WIN; \
2143 }
2144
2145 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2146 { \
2147 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2148 goto WIN; \
2149 }
2150
2151 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2152 if (TARGET_ARM) \
2153 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2154 else /* if (TARGET_THUMB) */ \
2155 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2156
2157 \f
2158 /* Try machine-dependent ways of modifying an illegitimate address
2159 to be legitimate. If we find one, return the new, valid address. */
2160 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2161 do { \
2162 X = arm_legitimize_address (X, OLDX, MODE); \
2163 } while (0)
2164
2165 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2166 do { \
2167 X = thumb_legitimize_address (X, OLDX, MODE); \
2168 } while (0)
2169
2170 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2171 do { \
2172 if (TARGET_ARM) \
2173 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2174 else \
2175 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2176 \
2177 if (memory_address_p (MODE, X)) \
2178 goto WIN; \
2179 } while (0)
2180
2181 /* Go to LABEL if ADDR (a legitimate address expression)
2182 has an effect that depends on the machine mode it is used for. */
2183 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2184 { \
2185 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2186 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2187 goto LABEL; \
2188 }
2189
2190 /* Nothing helpful to do for the Thumb */
2191 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2192 if (TARGET_ARM) \
2193 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2194 \f
2195
2196 /* Specify the machine mode that this machine uses
2197 for the index in the tablejump instruction. */
2198 #define CASE_VECTOR_MODE Pmode
2199
2200 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2201 unsigned is probably best, but may break some code. */
2202 #ifndef DEFAULT_SIGNED_CHAR
2203 #define DEFAULT_SIGNED_CHAR 0
2204 #endif
2205
2206 /* Max number of bytes we can move from memory to memory
2207 in one reasonably fast instruction. */
2208 #define MOVE_MAX 4
2209
2210 #undef MOVE_RATIO
2211 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2212
2213 /* Define if operations between registers always perform the operation
2214 on the full register even if a narrower mode is specified. */
2215 #define WORD_REGISTER_OPERATIONS
2216
2217 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2218 will either zero-extend or sign-extend. The value of this macro should
2219 be the code that says which one of the two operations is implicitly
2220 done, UNKNOWN if none. */
2221 #define LOAD_EXTEND_OP(MODE) \
2222 (TARGET_THUMB ? ZERO_EXTEND : \
2223 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2224 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2225
2226 /* Nonzero if access to memory by bytes is slow and undesirable. */
2227 #define SLOW_BYTE_ACCESS 0
2228
2229 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2230
2231 /* Immediate shift counts are truncated by the output routines (or was it
2232 the assembler?). Shift counts in a register are truncated by ARM. Note
2233 that the native compiler puts too large (> 32) immediate shift counts
2234 into a register and shifts by the register, letting the ARM decide what
2235 to do instead of doing that itself. */
2236 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2237 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2238 On the arm, Y in a register is used modulo 256 for the shift. Only for
2239 rotates is modulo 32 used. */
2240 /* #define SHIFT_COUNT_TRUNCATED 1 */
2241
2242 /* All integers have the same format so truncation is easy. */
2243 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2244
2245 /* Calling from registers is a massive pain. */
2246 #define NO_FUNCTION_CSE 1
2247
2248 /* The machine modes of pointers and functions */
2249 #define Pmode SImode
2250 #define FUNCTION_MODE Pmode
2251
2252 #define ARM_FRAME_RTX(X) \
2253 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2254 || (X) == arg_pointer_rtx)
2255
2256 /* Moves to and from memory are quite expensive */
2257 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2258 (TARGET_ARM ? 10 : \
2259 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2260 * (CLASS == LO_REGS ? 1 : 2)))
2261
2262 /* Try to generate sequences that don't involve branches, we can then use
2263 conditional instructions */
2264 #define BRANCH_COST \
2265 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2266 \f
2267 /* Position Independent Code. */
2268 /* We decide which register to use based on the compilation options and
2269 the assembler in use; this is more general than the APCS restriction of
2270 using sb (r9) all the time. */
2271 extern int arm_pic_register;
2272
2273 /* Used when parsing command line option -mpic-register=. */
2274 extern const char * arm_pic_register_string;
2275
2276 /* The register number of the register used to address a table of static
2277 data addresses in memory. */
2278 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2279
2280 /* We can't directly access anything that contains a symbol,
2281 nor can we indirect via the constant pool. */
2282 #define LEGITIMATE_PIC_OPERAND_P(X) \
2283 (!(symbol_mentioned_p (X) \
2284 || label_mentioned_p (X) \
2285 || (GET_CODE (X) == SYMBOL_REF \
2286 && CONSTANT_POOL_ADDRESS_P (X) \
2287 && (symbol_mentioned_p (get_pool_constant (X)) \
2288 || label_mentioned_p (get_pool_constant (X))))))
2289
2290 /* We need to know when we are making a constant pool; this determines
2291 whether data needs to be in the GOT or can be referenced via a GOT
2292 offset. */
2293 extern int making_const_table;
2294 \f
2295 /* Handle pragmas for compatibility with Intel's compilers. */
2296 #define REGISTER_TARGET_PRAGMAS() do { \
2297 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2298 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2299 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2300 } while (0)
2301
2302 /* Condition code information. */
2303 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2304 return the mode to be used for the comparison. */
2305
2306 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2307
2308 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2309
2310 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2311 do \
2312 { \
2313 if (GET_CODE (OP1) == CONST_INT \
2314 && ! (const_ok_for_arm (INTVAL (OP1)) \
2315 || (const_ok_for_arm (- INTVAL (OP1))))) \
2316 { \
2317 rtx const_op = OP1; \
2318 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2319 OP1 = const_op; \
2320 } \
2321 } \
2322 while (0)
2323
2324 /* The arm5 clz instruction returns 32. */
2325 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2326 \f
2327 #undef ASM_APP_OFF
2328 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2329
2330 /* Output a push or a pop instruction (only used when profiling). */
2331 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2332 do \
2333 { \
2334 if (TARGET_ARM) \
2335 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2336 STACK_POINTER_REGNUM, REGNO); \
2337 else \
2338 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2339 } while (0)
2340
2341
2342 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2343 do \
2344 { \
2345 if (TARGET_ARM) \
2346 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2347 STACK_POINTER_REGNUM, REGNO); \
2348 else \
2349 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2350 } while (0)
2351
2352 /* This is how to output a label which precedes a jumptable. Since
2353 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2354 #undef ASM_OUTPUT_CASE_LABEL
2355 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2356 do \
2357 { \
2358 if (TARGET_THUMB) \
2359 ASM_OUTPUT_ALIGN (FILE, 2); \
2360 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2361 } \
2362 while (0)
2363
2364 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2365 do \
2366 { \
2367 if (TARGET_THUMB) \
2368 { \
2369 if (is_called_in_ARM_mode (DECL) \
2370 || current_function_is_thunk) \
2371 fprintf (STREAM, "\t.code 32\n") ; \
2372 else \
2373 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2374 } \
2375 if (TARGET_POKE_FUNCTION_NAME) \
2376 arm_poke_function_name (STREAM, (char *) NAME); \
2377 } \
2378 while (0)
2379
2380 /* For aliases of functions we use .thumb_set instead. */
2381 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2382 do \
2383 { \
2384 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2385 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2386 \
2387 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2388 { \
2389 fprintf (FILE, "\t.thumb_set "); \
2390 assemble_name (FILE, LABEL1); \
2391 fprintf (FILE, ","); \
2392 assemble_name (FILE, LABEL2); \
2393 fprintf (FILE, "\n"); \
2394 } \
2395 else \
2396 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2397 } \
2398 while (0)
2399
2400 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2401 /* To support -falign-* switches we need to use .p2align so
2402 that alignment directives in code sections will be padded
2403 with no-op instructions, rather than zeroes. */
2404 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2405 if ((LOG) != 0) \
2406 { \
2407 if ((MAX_SKIP) == 0) \
2408 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2409 else \
2410 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2411 (int) (LOG), (int) (MAX_SKIP)); \
2412 }
2413 #endif
2414 \f
2415 /* Only perform branch elimination (by making instructions conditional) if
2416 we're optimizing. Otherwise it's of no use anyway. */
2417 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2418 if (TARGET_ARM && optimize) \
2419 arm_final_prescan_insn (INSN); \
2420 else if (TARGET_THUMB) \
2421 thumb_final_prescan_insn (INSN)
2422
2423 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2424 (CODE == '@' || CODE == '|' \
2425 || (TARGET_ARM && (CODE == '?')) \
2426 || (TARGET_THUMB && (CODE == '_')))
2427
2428 /* Output an operand of an instruction. */
2429 #define PRINT_OPERAND(STREAM, X, CODE) \
2430 arm_print_operand (STREAM, X, CODE)
2431
2432 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2433 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2434 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2435 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2436 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2437 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2438 : 0))))
2439
2440 /* Output the address of an operand. */
2441 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2442 { \
2443 int is_minus = GET_CODE (X) == MINUS; \
2444 \
2445 if (GET_CODE (X) == REG) \
2446 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2447 else if (GET_CODE (X) == PLUS || is_minus) \
2448 { \
2449 rtx base = XEXP (X, 0); \
2450 rtx index = XEXP (X, 1); \
2451 HOST_WIDE_INT offset = 0; \
2452 if (GET_CODE (base) != REG) \
2453 { \
2454 /* Ensure that BASE is a register. */ \
2455 /* (one of them must be). */ \
2456 rtx temp = base; \
2457 base = index; \
2458 index = temp; \
2459 } \
2460 switch (GET_CODE (index)) \
2461 { \
2462 case CONST_INT: \
2463 offset = INTVAL (index); \
2464 if (is_minus) \
2465 offset = -offset; \
2466 asm_fprintf (STREAM, "[%r, #%wd]", \
2467 REGNO (base), offset); \
2468 break; \
2469 \
2470 case REG: \
2471 asm_fprintf (STREAM, "[%r, %s%r]", \
2472 REGNO (base), is_minus ? "-" : "", \
2473 REGNO (index)); \
2474 break; \
2475 \
2476 case MULT: \
2477 case ASHIFTRT: \
2478 case LSHIFTRT: \
2479 case ASHIFT: \
2480 case ROTATERT: \
2481 { \
2482 asm_fprintf (STREAM, "[%r, %s%r", \
2483 REGNO (base), is_minus ? "-" : "", \
2484 REGNO (XEXP (index, 0))); \
2485 arm_print_operand (STREAM, index, 'S'); \
2486 fputs ("]", STREAM); \
2487 break; \
2488 } \
2489 \
2490 default: \
2491 abort(); \
2492 } \
2493 } \
2494 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2495 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2496 { \
2497 extern enum machine_mode output_memory_reference_mode; \
2498 \
2499 if (GET_CODE (XEXP (X, 0)) != REG) \
2500 abort (); \
2501 \
2502 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2503 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2504 REGNO (XEXP (X, 0)), \
2505 GET_CODE (X) == PRE_DEC ? "-" : "", \
2506 GET_MODE_SIZE (output_memory_reference_mode)); \
2507 else \
2508 asm_fprintf (STREAM, "[%r], #%s%d", \
2509 REGNO (XEXP (X, 0)), \
2510 GET_CODE (X) == POST_DEC ? "-" : "", \
2511 GET_MODE_SIZE (output_memory_reference_mode)); \
2512 } \
2513 else if (GET_CODE (X) == PRE_MODIFY) \
2514 { \
2515 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2516 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2517 asm_fprintf (STREAM, "#%wd]!", \
2518 INTVAL (XEXP (XEXP (X, 1), 1))); \
2519 else \
2520 asm_fprintf (STREAM, "%r]!", \
2521 REGNO (XEXP (XEXP (X, 1), 1))); \
2522 } \
2523 else if (GET_CODE (X) == POST_MODIFY) \
2524 { \
2525 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2526 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2527 asm_fprintf (STREAM, "#%wd", \
2528 INTVAL (XEXP (XEXP (X, 1), 1))); \
2529 else \
2530 asm_fprintf (STREAM, "%r", \
2531 REGNO (XEXP (XEXP (X, 1), 1))); \
2532 } \
2533 else output_addr_const (STREAM, X); \
2534 }
2535
2536 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2537 { \
2538 if (GET_CODE (X) == REG) \
2539 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2540 else if (GET_CODE (X) == POST_INC) \
2541 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2542 else if (GET_CODE (X) == PLUS) \
2543 { \
2544 if (GET_CODE (XEXP (X, 0)) != REG) \
2545 abort (); \
2546 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2547 asm_fprintf (STREAM, "[%r, #%wd]", \
2548 REGNO (XEXP (X, 0)), \
2549 INTVAL (XEXP (X, 1))); \
2550 else \
2551 asm_fprintf (STREAM, "[%r, %r]", \
2552 REGNO (XEXP (X, 0)), \
2553 REGNO (XEXP (X, 1))); \
2554 } \
2555 else \
2556 output_addr_const (STREAM, X); \
2557 }
2558
2559 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2560 if (TARGET_ARM) \
2561 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2562 else \
2563 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2564
2565 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2566 if (GET_CODE (X) != CONST_VECTOR \
2567 || ! arm_emit_vector_const (FILE, X)) \
2568 goto FAIL;
2569
2570 /* A C expression whose value is RTL representing the value of the return
2571 address for the frame COUNT steps up from the current frame. */
2572
2573 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2574 arm_return_addr (COUNT, FRAME)
2575
2576 /* Mask of the bits in the PC that contain the real return address
2577 when running in 26-bit mode. */
2578 #define RETURN_ADDR_MASK26 (0x03fffffc)
2579
2580 /* Pick up the return address upon entry to a procedure. Used for
2581 dwarf2 unwind information. This also enables the table driven
2582 mechanism. */
2583 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2584 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2585
2586 /* Used to mask out junk bits from the return address, such as
2587 processor state, interrupt status, condition codes and the like. */
2588 #define MASK_RETURN_ADDR \
2589 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2590 in 26 bit mode, the condition codes must be masked out of the \
2591 return address. This does not apply to ARM6 and later processors \
2592 when running in 32 bit mode. */ \
2593 ((arm_arch4 || TARGET_THUMB) \
2594 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2595 : arm_gen_return_addr_mask ())
2596
2597 \f
2598 /* Define the codes that are matched by predicates in arm.c */
2599 #define PREDICATE_CODES \
2600 {"s_register_operand", {SUBREG, REG}}, \
2601 {"arm_general_register_operand", {SUBREG, REG}}, \
2602 {"arm_hard_register_operand", {REG}}, \
2603 {"f_register_operand", {SUBREG, REG}}, \
2604 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2605 {"arm_addimm_operand", {CONST_INT}}, \
2606 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2607 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2608 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2609 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2610 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2611 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2612 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2613 {"thumb_cmpneg_operand", {CONST_INT}}, \
2614 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2615 {"offsettable_memory_operand", {MEM}}, \
2616 {"alignable_memory_operand", {MEM}}, \
2617 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2618 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2619 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2620 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2621 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2622 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2623 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2624 {"load_multiple_operation", {PARALLEL}}, \
2625 {"store_multiple_operation", {PARALLEL}}, \
2626 {"equality_operator", {EQ, NE}}, \
2627 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2628 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2629 UNGE, UNGT}}, \
2630 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2631 {"const_shift_operand", {CONST_INT}}, \
2632 {"multi_register_push", {PARALLEL}}, \
2633 {"cc_register", {REG}}, \
2634 {"logical_binary_operator", {AND, IOR, XOR}}, \
2635 {"cirrus_register_operand", {REG}}, \
2636 {"cirrus_fp_register", {REG}}, \
2637 {"cirrus_shift_const", {CONST_INT}}, \
2638 {"dominant_cc_register", {REG}}, \
2639 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2640 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2641
2642 /* Define this if you have special predicates that know special things
2643 about modes. Genrecog will warn about certain forms of
2644 match_operand without a mode; if the operand predicate is listed in
2645 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2646 #define SPECIAL_MODE_PREDICATES \
2647 "cc_register", "dominant_cc_register",
2648
2649 enum arm_builtins
2650 {
2651 ARM_BUILTIN_GETWCX,
2652 ARM_BUILTIN_SETWCX,
2653
2654 ARM_BUILTIN_WZERO,
2655
2656 ARM_BUILTIN_WAVG2BR,
2657 ARM_BUILTIN_WAVG2HR,
2658 ARM_BUILTIN_WAVG2B,
2659 ARM_BUILTIN_WAVG2H,
2660
2661 ARM_BUILTIN_WACCB,
2662 ARM_BUILTIN_WACCH,
2663 ARM_BUILTIN_WACCW,
2664
2665 ARM_BUILTIN_WMACS,
2666 ARM_BUILTIN_WMACSZ,
2667 ARM_BUILTIN_WMACU,
2668 ARM_BUILTIN_WMACUZ,
2669
2670 ARM_BUILTIN_WSADB,
2671 ARM_BUILTIN_WSADBZ,
2672 ARM_BUILTIN_WSADH,
2673 ARM_BUILTIN_WSADHZ,
2674
2675 ARM_BUILTIN_WALIGN,
2676
2677 ARM_BUILTIN_TMIA,
2678 ARM_BUILTIN_TMIAPH,
2679 ARM_BUILTIN_TMIABB,
2680 ARM_BUILTIN_TMIABT,
2681 ARM_BUILTIN_TMIATB,
2682 ARM_BUILTIN_TMIATT,
2683
2684 ARM_BUILTIN_TMOVMSKB,
2685 ARM_BUILTIN_TMOVMSKH,
2686 ARM_BUILTIN_TMOVMSKW,
2687
2688 ARM_BUILTIN_TBCSTB,
2689 ARM_BUILTIN_TBCSTH,
2690 ARM_BUILTIN_TBCSTW,
2691
2692 ARM_BUILTIN_WMADDS,
2693 ARM_BUILTIN_WMADDU,
2694
2695 ARM_BUILTIN_WPACKHSS,
2696 ARM_BUILTIN_WPACKWSS,
2697 ARM_BUILTIN_WPACKDSS,
2698 ARM_BUILTIN_WPACKHUS,
2699 ARM_BUILTIN_WPACKWUS,
2700 ARM_BUILTIN_WPACKDUS,
2701
2702 ARM_BUILTIN_WADDB,
2703 ARM_BUILTIN_WADDH,
2704 ARM_BUILTIN_WADDW,
2705 ARM_BUILTIN_WADDSSB,
2706 ARM_BUILTIN_WADDSSH,
2707 ARM_BUILTIN_WADDSSW,
2708 ARM_BUILTIN_WADDUSB,
2709 ARM_BUILTIN_WADDUSH,
2710 ARM_BUILTIN_WADDUSW,
2711 ARM_BUILTIN_WSUBB,
2712 ARM_BUILTIN_WSUBH,
2713 ARM_BUILTIN_WSUBW,
2714 ARM_BUILTIN_WSUBSSB,
2715 ARM_BUILTIN_WSUBSSH,
2716 ARM_BUILTIN_WSUBSSW,
2717 ARM_BUILTIN_WSUBUSB,
2718 ARM_BUILTIN_WSUBUSH,
2719 ARM_BUILTIN_WSUBUSW,
2720
2721 ARM_BUILTIN_WAND,
2722 ARM_BUILTIN_WANDN,
2723 ARM_BUILTIN_WOR,
2724 ARM_BUILTIN_WXOR,
2725
2726 ARM_BUILTIN_WCMPEQB,
2727 ARM_BUILTIN_WCMPEQH,
2728 ARM_BUILTIN_WCMPEQW,
2729 ARM_BUILTIN_WCMPGTUB,
2730 ARM_BUILTIN_WCMPGTUH,
2731 ARM_BUILTIN_WCMPGTUW,
2732 ARM_BUILTIN_WCMPGTSB,
2733 ARM_BUILTIN_WCMPGTSH,
2734 ARM_BUILTIN_WCMPGTSW,
2735
2736 ARM_BUILTIN_TEXTRMSB,
2737 ARM_BUILTIN_TEXTRMSH,
2738 ARM_BUILTIN_TEXTRMSW,
2739 ARM_BUILTIN_TEXTRMUB,
2740 ARM_BUILTIN_TEXTRMUH,
2741 ARM_BUILTIN_TEXTRMUW,
2742 ARM_BUILTIN_TINSRB,
2743 ARM_BUILTIN_TINSRH,
2744 ARM_BUILTIN_TINSRW,
2745
2746 ARM_BUILTIN_WMAXSW,
2747 ARM_BUILTIN_WMAXSH,
2748 ARM_BUILTIN_WMAXSB,
2749 ARM_BUILTIN_WMAXUW,
2750 ARM_BUILTIN_WMAXUH,
2751 ARM_BUILTIN_WMAXUB,
2752 ARM_BUILTIN_WMINSW,
2753 ARM_BUILTIN_WMINSH,
2754 ARM_BUILTIN_WMINSB,
2755 ARM_BUILTIN_WMINUW,
2756 ARM_BUILTIN_WMINUH,
2757 ARM_BUILTIN_WMINUB,
2758
2759 ARM_BUILTIN_WMULUM,
2760 ARM_BUILTIN_WMULSM,
2761 ARM_BUILTIN_WMULUL,
2762
2763 ARM_BUILTIN_PSADBH,
2764 ARM_BUILTIN_WSHUFH,
2765
2766 ARM_BUILTIN_WSLLH,
2767 ARM_BUILTIN_WSLLW,
2768 ARM_BUILTIN_WSLLD,
2769 ARM_BUILTIN_WSRAH,
2770 ARM_BUILTIN_WSRAW,
2771 ARM_BUILTIN_WSRAD,
2772 ARM_BUILTIN_WSRLH,
2773 ARM_BUILTIN_WSRLW,
2774 ARM_BUILTIN_WSRLD,
2775 ARM_BUILTIN_WRORH,
2776 ARM_BUILTIN_WRORW,
2777 ARM_BUILTIN_WRORD,
2778 ARM_BUILTIN_WSLLHI,
2779 ARM_BUILTIN_WSLLWI,
2780 ARM_BUILTIN_WSLLDI,
2781 ARM_BUILTIN_WSRAHI,
2782 ARM_BUILTIN_WSRAWI,
2783 ARM_BUILTIN_WSRADI,
2784 ARM_BUILTIN_WSRLHI,
2785 ARM_BUILTIN_WSRLWI,
2786 ARM_BUILTIN_WSRLDI,
2787 ARM_BUILTIN_WRORHI,
2788 ARM_BUILTIN_WRORWI,
2789 ARM_BUILTIN_WRORDI,
2790
2791 ARM_BUILTIN_WUNPCKIHB,
2792 ARM_BUILTIN_WUNPCKIHH,
2793 ARM_BUILTIN_WUNPCKIHW,
2794 ARM_BUILTIN_WUNPCKILB,
2795 ARM_BUILTIN_WUNPCKILH,
2796 ARM_BUILTIN_WUNPCKILW,
2797
2798 ARM_BUILTIN_WUNPCKEHSB,
2799 ARM_BUILTIN_WUNPCKEHSH,
2800 ARM_BUILTIN_WUNPCKEHSW,
2801 ARM_BUILTIN_WUNPCKEHUB,
2802 ARM_BUILTIN_WUNPCKEHUH,
2803 ARM_BUILTIN_WUNPCKEHUW,
2804 ARM_BUILTIN_WUNPCKELSB,
2805 ARM_BUILTIN_WUNPCKELSH,
2806 ARM_BUILTIN_WUNPCKELSW,
2807 ARM_BUILTIN_WUNPCKELUB,
2808 ARM_BUILTIN_WUNPCKELUH,
2809 ARM_BUILTIN_WUNPCKELUW,
2810
2811 ARM_BUILTIN_MAX
2812 };
2813 #endif /* ! GCC_ARM_H */
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