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2006-03-17 Paul Brook <paul@codesourcery.com>
[official-gcc.git] / gcc / config / arm / arm.h
blob6cc612b0d9ff6322229e1c84a2e09081c864368e
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* The architecture define. */
30 extern char arm_arch_name[];
31
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
40 if (TARGET_THUMB) \
41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 if (TARGET_VFP) \
62 builtin_define ("__VFP_FP__"); \
63 \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
81 } while (0)
82
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
88 #include "arm-cores.def"
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
93
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
98 #include "arm-cores.def"
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
102
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
105
106 typedef enum arm_cond_code
107 {
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
110 }
111 arm_cc;
112
113 extern arm_cc arm_current_cc;
114
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
116
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 extern GTY(()) rtx arm_compare_op0;
123 extern GTY(()) rtx arm_compare_op1;
124 /* The label of the current constant pool. */
125 extern rtx pool_vector_label;
126 /* Set to 1 when a return insn is output, this means that the epilogue
127 is not needed. */
128 extern int return_used_this_function;
129 /* Used to produce AOF syntax assembler. */
130 extern GTY(()) rtx aof_pic_label;
131 \f
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
135 #endif
136
137
138 #undef CPP_SPEC
139 #define CPP_SPEC "%(subtarget_cpp_spec) \
140 %{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142 %{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
144
145 #ifndef CC1_SPEC
146 #define CC1_SPEC ""
147 #endif
148
149 /* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
152
153 Each subgrouping contains a string constant, that defines the
154 specification name, and a string constant that used by the GCC driver
155 program.
156
157 Do not define this macro if it does not need to do anything. */
158 #define EXTRA_SPECS \
159 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
160 SUBTARGET_EXTRA_SPECS
161
162 #ifndef SUBTARGET_EXTRA_SPECS
163 #define SUBTARGET_EXTRA_SPECS
164 #endif
165
166 #ifndef SUBTARGET_CPP_SPEC
167 #define SUBTARGET_CPP_SPEC ""
168 #endif
169 \f
170 /* Run-time Target Specification. */
171 #ifndef TARGET_VERSION
172 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
173 #endif
174
175 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
176 /* Use hardware floating point instructions. */
177 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point calling convention. */
179 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
180 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
183 #define TARGET_IWMMXT (arm_arch_iwmmxt)
184 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
185 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
186 #define TARGET_ARM (! TARGET_THUMB)
187 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
188 #define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
190 : TARGET_TPCS_FRAME)
191 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
192 #define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
194
195 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
196 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
197
198 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
199 then TARGET_AAPCS_BASED must be true -- but the converse does not
200 hold. TARGET_BPABI implies the use of the BPABI runtime library,
201 etc., in addition to just the AAPCS calling conventions. */
202 #ifndef TARGET_BPABI
203 #define TARGET_BPABI false
204 #endif
205
206 /* Support for a compile-time default CPU, et cetera. The rules are:
207 --with-arch is ignored if -march or -mcpu are specified.
208 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
209 by --with-arch.
210 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
211 by -march).
212 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
213 specified.
214 --with-fpu is ignored if -mfpu is specified.
215 --with-abi is ignored is -mabi is specified. */
216 #define OPTION_DEFAULT_SPECS \
217 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
218 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
219 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
220 {"float", \
221 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
222 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
223 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
224 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
225
226 /* Which floating point model to use. */
227 enum arm_fp_model
228 {
229 ARM_FP_MODEL_UNKNOWN,
230 /* FPA model (Hardware or software). */
231 ARM_FP_MODEL_FPA,
232 /* Cirrus Maverick floating point model. */
233 ARM_FP_MODEL_MAVERICK,
234 /* VFP floating point model. */
235 ARM_FP_MODEL_VFP
236 };
237
238 extern enum arm_fp_model arm_fp_model;
239
240 /* Which floating point hardware is available. Also update
241 fp_model_for_fpu in arm.c when adding entries to this list. */
242 enum fputype
243 {
244 /* No FP hardware. */
245 FPUTYPE_NONE,
246 /* Full FPA support. */
247 FPUTYPE_FPA,
248 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
249 FPUTYPE_FPA_EMU2,
250 /* Emulated FPA hardware, Issue 3 emulator. */
251 FPUTYPE_FPA_EMU3,
252 /* Cirrus Maverick floating point co-processor. */
253 FPUTYPE_MAVERICK,
254 /* VFP. */
255 FPUTYPE_VFP
256 };
257
258 /* Recast the floating point class to be the floating point attribute. */
259 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
260
261 /* What type of floating point to tune for */
262 extern enum fputype arm_fpu_tune;
263
264 /* What type of floating point instructions are available */
265 extern enum fputype arm_fpu_arch;
266
267 enum float_abi_type
268 {
269 ARM_FLOAT_ABI_SOFT,
270 ARM_FLOAT_ABI_SOFTFP,
271 ARM_FLOAT_ABI_HARD
272 };
273
274 extern enum float_abi_type arm_float_abi;
275
276 #ifndef TARGET_DEFAULT_FLOAT_ABI
277 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
278 #endif
279
280 /* Which ABI to use. */
281 enum arm_abi_type
282 {
283 ARM_ABI_APCS,
284 ARM_ABI_ATPCS,
285 ARM_ABI_AAPCS,
286 ARM_ABI_IWMMXT,
287 ARM_ABI_AAPCS_LINUX
288 };
289
290 extern enum arm_abi_type arm_abi;
291
292 #ifndef ARM_DEFAULT_ABI
293 #define ARM_DEFAULT_ABI ARM_ABI_APCS
294 #endif
295
296 /* Which thread pointer access sequence to use. */
297 enum arm_tp_type {
298 TP_AUTO,
299 TP_SOFT,
300 TP_CP15
301 };
302
303 extern enum arm_tp_type target_thread_pointer;
304
305 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
306 extern int arm_arch3m;
307
308 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
309 extern int arm_arch4;
310
311 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
312 extern int arm_arch4t;
313
314 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
315 extern int arm_arch5;
316
317 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
318 extern int arm_arch5e;
319
320 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
321 extern int arm_arch6;
322
323 /* Nonzero if this chip can benefit from load scheduling. */
324 extern int arm_ld_sched;
325
326 /* Nonzero if generating thumb code. */
327 extern int thumb_code;
328
329 /* Nonzero if this chip is a StrongARM. */
330 extern int arm_tune_strongarm;
331
332 /* Nonzero if this chip is a Cirrus variant. */
333 extern int arm_arch_cirrus;
334
335 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
336 extern int arm_arch_iwmmxt;
337
338 /* Nonzero if this chip is an XScale. */
339 extern int arm_arch_xscale;
340
341 /* Nonzero if tuning for XScale. */
342 extern int arm_tune_xscale;
343
344 /* Nonzero if tuning for stores via the write buffer. */
345 extern int arm_tune_wbuf;
346
347 /* Nonzero if we should define __THUMB_INTERWORK__ in the
348 preprocessor.
349 XXX This is a bit of a hack, it's intended to help work around
350 problems in GLD which doesn't understand that armv5t code is
351 interworking clean. */
352 extern int arm_cpp_interwork;
353
354 #ifndef TARGET_DEFAULT
355 #define TARGET_DEFAULT (MASK_APCS_FRAME)
356 #endif
357
358 /* The frame pointer register used in gcc has nothing to do with debugging;
359 that is controlled by the APCS-FRAME option. */
360 #define CAN_DEBUG_WITHOUT_FP
361
362 #define OVERRIDE_OPTIONS arm_override_options ()
363
364 /* Nonzero if PIC code requires explicit qualifiers to generate
365 PLT and GOT relocs rather than the assembler doing so implicitly.
366 Subtargets can override these if required. */
367 #ifndef NEED_GOT_RELOC
368 #define NEED_GOT_RELOC 0
369 #endif
370 #ifndef NEED_PLT_RELOC
371 #define NEED_PLT_RELOC 0
372 #endif
373
374 /* Nonzero if we need to refer to the GOT with a PC-relative
375 offset. In other words, generate
376
377 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
378
379 rather than
380
381 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
382
383 The default is true, which matches NetBSD. Subtargets can
384 override this if required. */
385 #ifndef GOT_PCREL
386 #define GOT_PCREL 1
387 #endif
388 \f
389 /* Target machine storage Layout. */
390
391
392 /* Define this macro if it is advisable to hold scalars in registers
393 in a wider mode than that declared by the program. In such cases,
394 the value is constrained to be within the bounds of the declared
395 type, but kept valid in the wider mode. The signedness of the
396 extension may differ from that of the type. */
397
398 /* It is far faster to zero extend chars than to sign extend them */
399
400 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
401 if (GET_MODE_CLASS (MODE) == MODE_INT \
402 && GET_MODE_SIZE (MODE) < 4) \
403 { \
404 if (MODE == QImode) \
405 UNSIGNEDP = 1; \
406 else if (MODE == HImode) \
407 UNSIGNEDP = 1; \
408 (MODE) = SImode; \
409 }
410
411 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
412 if ((GET_MODE_CLASS (MODE) == MODE_INT \
413 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
414 && GET_MODE_SIZE (MODE) < 4) \
415 (MODE) = SImode; \
416
417 /* Define this if most significant bit is lowest numbered
418 in instructions that operate on numbered bit-fields. */
419 #define BITS_BIG_ENDIAN 0
420
421 /* Define this if most significant byte of a word is the lowest numbered.
422 Most ARM processors are run in little endian mode, so that is the default.
423 If you want to have it run-time selectable, change the definition in a
424 cover file to be TARGET_BIG_ENDIAN. */
425 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
426
427 /* Define this if most significant word of a multiword number is the lowest
428 numbered.
429 This is always false, even when in big-endian mode. */
430 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
431
432 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
433 on processor pre-defineds when compiling libgcc2.c. */
434 #if defined(__ARMEB__) && !defined(__ARMWEL__)
435 #define LIBGCC2_WORDS_BIG_ENDIAN 1
436 #else
437 #define LIBGCC2_WORDS_BIG_ENDIAN 0
438 #endif
439
440 /* Define this if most significant word of doubles is the lowest numbered.
441 The rules are different based on whether or not we use FPA-format,
442 VFP-format or some other floating point co-processor's format doubles. */
443 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
444
445 #define UNITS_PER_WORD 4
446
447 /* True if natural alignment is used for doubleword types. */
448 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
449
450 #define DOUBLEWORD_ALIGNMENT 64
451
452 #define PARM_BOUNDARY 32
453
454 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
455
456 #define PREFERRED_STACK_BOUNDARY \
457 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
458
459 #define FUNCTION_BOUNDARY 32
460
461 /* The lowest bit is used to indicate Thumb-mode functions, so the
462 vbit must go into the delta field of pointers to member
463 functions. */
464 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
465
466 #define EMPTY_FIELD_BOUNDARY 32
467
468 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
469
470 /* XXX Blah -- this macro is used directly by libobjc. Since it
471 supports no vector modes, cut out the complexity and fall back
472 on BIGGEST_FIELD_ALIGNMENT. */
473 #ifdef IN_TARGET_LIBS
474 #define BIGGEST_FIELD_ALIGNMENT 64
475 #endif
476
477 /* Make strings word-aligned so strcpy from constants will be faster. */
478 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
479
480 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
481 ((TREE_CODE (EXP) == STRING_CST \
482 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
483 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
484
485 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
486 value set in previous versions of this toolchain was 8, which produces more
487 compact structures. The command line option -mstructure_size_boundary=<n>
488 can be used to change this value. For compatibility with the ARM SDK
489 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
490 0020D) page 2-20 says "Structures are aligned on word boundaries".
491 The AAPCS specifies a value of 8. */
492 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
493 extern int arm_structure_size_boundary;
494
495 /* This is the value used to initialize arm_structure_size_boundary. If a
496 particular arm target wants to change the default value it should change
497 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
498 for an example of this. */
499 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
500 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
501 #endif
502
503 /* Nonzero if move instructions will actually fail to work
504 when given unaligned data. */
505 #define STRICT_ALIGNMENT 1
506
507 /* wchar_t is unsigned under the AAPCS. */
508 #ifndef WCHAR_TYPE
509 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
510
511 #define WCHAR_TYPE_SIZE BITS_PER_WORD
512 #endif
513
514 #ifndef SIZE_TYPE
515 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
516 #endif
517
518 #ifndef PTRDIFF_TYPE
519 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
520 #endif
521
522 /* AAPCS requires that structure alignment is affected by bitfields. */
523 #ifndef PCC_BITFIELD_TYPE_MATTERS
524 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
525 #endif
526
527 \f
528 /* Standard register usage. */
529
530 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
531 (S - saved over call).
532
533 r0 * argument word/integer result
534 r1-r3 argument word
535
536 r4-r8 S register variable
537 r9 S (rfp) register variable (real frame pointer)
538
539 r10 F S (sl) stack limit (used by -mapcs-stack-check)
540 r11 F S (fp) argument pointer
541 r12 (ip) temp workspace
542 r13 F S (sp) lower end of current stack frame
543 r14 (lr) link address/workspace
544 r15 F (pc) program counter
545
546 f0 floating point result
547 f1-f3 floating point scratch
548
549 f4-f7 S floating point variable
550
551 cc This is NOT a real register, but is used internally
552 to represent things that use or set the condition
553 codes.
554 sfp This isn't either. It is used during rtl generation
555 since the offset between the frame pointer and the
556 auto's isn't known until after register allocation.
557 afp Nor this, we only need this because of non-local
558 goto. Without it fp appears to be used and the
559 elimination code won't get rid of sfp. It tracks
560 fp exactly at all times.
561
562 *: See CONDITIONAL_REGISTER_USAGE */
563
564 /*
565 mvf0 Cirrus floating point result
566 mvf1-mvf3 Cirrus floating point scratch
567 mvf4-mvf15 S Cirrus floating point variable. */
568
569 /* s0-s15 VFP scratch (aka d0-d7).
570 s16-s31 S VFP variable (aka d8-d15).
571 vfpcc Not a real register. Represents the VFP condition
572 code flags. */
573
574 /* The stack backtrace structure is as follows:
575 fp points to here: | save code pointer | [fp]
576 | return link value | [fp, #-4]
577 | return sp value | [fp, #-8]
578 | return fp value | [fp, #-12]
579 [| saved r10 value |]
580 [| saved r9 value |]
581 [| saved r8 value |]
582 [| saved r7 value |]
583 [| saved r6 value |]
584 [| saved r5 value |]
585 [| saved r4 value |]
586 [| saved r3 value |]
587 [| saved r2 value |]
588 [| saved r1 value |]
589 [| saved r0 value |]
590 [| saved f7 value |] three words
591 [| saved f6 value |] three words
592 [| saved f5 value |] three words
593 [| saved f4 value |] three words
594 r0-r3 are not normally saved in a C function. */
595
596 /* 1 for registers that have pervasive standard uses
597 and are not available for the register allocator. */
598 #define FIXED_REGISTERS \
599 { \
600 0,0,0,0,0,0,0,0, \
601 0,0,0,0,0,1,0,1, \
602 0,0,0,0,0,0,0,0, \
603 1,1,1, \
604 1,1,1,1,1,1,1,1, \
605 1,1,1,1,1,1,1,1, \
606 1,1,1,1,1,1,1,1, \
607 1,1,1,1,1,1,1,1, \
608 1,1,1,1, \
609 1,1,1,1,1,1,1,1, \
610 1,1,1,1,1,1,1,1, \
611 1,1,1,1,1,1,1,1, \
612 1,1,1,1,1,1,1,1, \
613 1 \
614 }
615
616 /* 1 for registers not available across function calls.
617 These must include the FIXED_REGISTERS and also any
618 registers that can be used without being saved.
619 The latter must include the registers where values are returned
620 and the register where structure-value addresses are passed.
621 Aside from that, you can include as many other registers as you like.
622 The CC is not preserved over function calls on the ARM 6, so it is
623 easier to assume this for all. SFP is preserved, since FP is. */
624 #define CALL_USED_REGISTERS \
625 { \
626 1,1,1,1,0,0,0,0, \
627 0,0,0,0,1,1,1,1, \
628 1,1,1,1,0,0,0,0, \
629 1,1,1, \
630 1,1,1,1,1,1,1,1, \
631 1,1,1,1,1,1,1,1, \
632 1,1,1,1,1,1,1,1, \
633 1,1,1,1,1,1,1,1, \
634 1,1,1,1, \
635 1,1,1,1,1,1,1,1, \
636 1,1,1,1,1,1,1,1, \
637 1,1,1,1,1,1,1,1, \
638 1,1,1,1,1,1,1,1, \
639 1 \
640 }
641
642 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
643 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
644 #endif
645
646 #define CONDITIONAL_REGISTER_USAGE \
647 { \
648 int regno; \
649 \
650 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
651 { \
652 for (regno = FIRST_FPA_REGNUM; \
653 regno <= LAST_FPA_REGNUM; ++regno) \
654 fixed_regs[regno] = call_used_regs[regno] = 1; \
655 } \
656 \
657 if (TARGET_THUMB && optimize_size) \
658 { \
659 /* When optimizing for size, it's better not to use \
660 the HI regs, because of the overhead of stacking \
661 them. */ \
662 for (regno = FIRST_HI_REGNUM; \
663 regno <= LAST_HI_REGNUM; ++regno) \
664 fixed_regs[regno] = call_used_regs[regno] = 1; \
665 } \
666 \
667 /* The link register can be clobbered by any branch insn, \
668 but we have no way to track that at present, so mark \
669 it as unavailable. */ \
670 if (TARGET_THUMB) \
671 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
672 \
673 if (TARGET_ARM && TARGET_HARD_FLOAT) \
674 { \
675 if (TARGET_MAVERICK) \
676 { \
677 for (regno = FIRST_FPA_REGNUM; \
678 regno <= LAST_FPA_REGNUM; ++ regno) \
679 fixed_regs[regno] = call_used_regs[regno] = 1; \
680 for (regno = FIRST_CIRRUS_FP_REGNUM; \
681 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
682 { \
683 fixed_regs[regno] = 0; \
684 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
685 } \
686 } \
687 if (TARGET_VFP) \
688 { \
689 for (regno = FIRST_VFP_REGNUM; \
690 regno <= LAST_VFP_REGNUM; ++ regno) \
691 { \
692 fixed_regs[regno] = 0; \
693 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
694 } \
695 } \
696 } \
697 \
698 if (TARGET_REALLY_IWMMXT) \
699 { \
700 regno = FIRST_IWMMXT_GR_REGNUM; \
701 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
702 and wCG1 as call-preserved registers. The 2002/11/21 \
703 revision changed this so that all wCG registers are \
704 scratch registers. */ \
705 for (regno = FIRST_IWMMXT_GR_REGNUM; \
706 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
707 fixed_regs[regno] = 0; \
708 /* The XScale ABI has wR0 - wR9 as scratch registers, \
709 the rest as call-preserved registers. */ \
710 for (regno = FIRST_IWMMXT_REGNUM; \
711 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
712 { \
713 fixed_regs[regno] = 0; \
714 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
715 } \
716 } \
717 \
718 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
719 { \
720 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
721 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
722 } \
723 else if (TARGET_APCS_STACK) \
724 { \
725 fixed_regs[10] = 1; \
726 call_used_regs[10] = 1; \
727 } \
728 /* -mcaller-super-interworking reserves r11 for calls to \
729 _interwork_r11_call_via_rN(). Making the register global \
730 is an easy way of ensuring that it remains valid for all \
731 calls. */ \
732 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
733 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
734 { \
735 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
736 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
737 if (TARGET_CALLER_INTERWORKING) \
738 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
739 } \
740 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
741 }
742
743 /* These are a couple of extensions to the formats accepted
744 by asm_fprintf:
745 %@ prints out ASM_COMMENT_START
746 %r prints out REGISTER_PREFIX reg_names[arg] */
747 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
748 case '@': \
749 fputs (ASM_COMMENT_START, FILE); \
750 break; \
751 \
752 case 'r': \
753 fputs (REGISTER_PREFIX, FILE); \
754 fputs (reg_names [va_arg (ARGS, int)], FILE); \
755 break;
756
757 /* Round X up to the nearest word. */
758 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
759
760 /* Convert fron bytes to ints. */
761 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
762
763 /* The number of (integer) registers required to hold a quantity of type MODE.
764 Also used for VFP registers. */
765 #define ARM_NUM_REGS(MODE) \
766 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
767
768 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
769 #define ARM_NUM_REGS2(MODE, TYPE) \
770 ARM_NUM_INTS ((MODE) == BLKmode ? \
771 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
772
773 /* The number of (integer) argument register available. */
774 #define NUM_ARG_REGS 4
775
776 /* Return the register number of the N'th (integer) argument. */
777 #define ARG_REGISTER(N) (N - 1)
778
779 /* Specify the registers used for certain standard purposes.
780 The values of these macros are register numbers. */
781
782 /* The number of the last argument register. */
783 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
784
785 /* The numbers of the Thumb register ranges. */
786 #define FIRST_LO_REGNUM 0
787 #define LAST_LO_REGNUM 7
788 #define FIRST_HI_REGNUM 8
789 #define LAST_HI_REGNUM 11
790
791 #ifndef TARGET_UNWIND_INFO
792 /* We use sjlj exceptions for backwards compatibility. */
793 #define MUST_USE_SJLJ_EXCEPTIONS 1
794 #endif
795
796 /* We can generate DWARF2 Unwind info, even though we don't use it. */
797 #define DWARF2_UNWIND_INFO 1
798
799 /* Use r0 and r1 to pass exception handling information. */
800 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
801
802 /* The register that holds the return address in exception handlers. */
803 #define ARM_EH_STACKADJ_REGNUM 2
804 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
805
806 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
807 as an invisible last argument (possible since varargs don't exist in
808 Pascal), so the following is not true. */
809 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
810
811 /* Define this to be where the real frame pointer is if it is not possible to
812 work out the offset between the frame pointer and the automatic variables
813 until after register allocation has taken place. FRAME_POINTER_REGNUM
814 should point to a special register that we will make sure is eliminated.
815
816 For the Thumb we have another problem. The TPCS defines the frame pointer
817 as r11, and GCC believes that it is always possible to use the frame pointer
818 as base register for addressing purposes. (See comments in
819 find_reloads_address()). But - the Thumb does not allow high registers,
820 including r11, to be used as base address registers. Hence our problem.
821
822 The solution used here, and in the old thumb port is to use r7 instead of
823 r11 as the hard frame pointer and to have special code to generate
824 backtrace structures on the stack (if required to do so via a command line
825 option) using r11. This is the only 'user visible' use of r11 as a frame
826 pointer. */
827 #define ARM_HARD_FRAME_POINTER_REGNUM 11
828 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
829
830 #define HARD_FRAME_POINTER_REGNUM \
831 (TARGET_ARM \
832 ? ARM_HARD_FRAME_POINTER_REGNUM \
833 : THUMB_HARD_FRAME_POINTER_REGNUM)
834
835 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
836
837 /* Register to use for pushing function arguments. */
838 #define STACK_POINTER_REGNUM SP_REGNUM
839
840 /* ARM floating pointer registers. */
841 #define FIRST_FPA_REGNUM 16
842 #define LAST_FPA_REGNUM 23
843 #define IS_FPA_REGNUM(REGNUM) \
844 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
845
846 #define FIRST_IWMMXT_GR_REGNUM 43
847 #define LAST_IWMMXT_GR_REGNUM 46
848 #define FIRST_IWMMXT_REGNUM 47
849 #define LAST_IWMMXT_REGNUM 62
850 #define IS_IWMMXT_REGNUM(REGNUM) \
851 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
852 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
853 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
854
855 /* Base register for access to local variables of the function. */
856 #define FRAME_POINTER_REGNUM 25
857
858 /* Base register for access to arguments of the function. */
859 #define ARG_POINTER_REGNUM 26
860
861 #define FIRST_CIRRUS_FP_REGNUM 27
862 #define LAST_CIRRUS_FP_REGNUM 42
863 #define IS_CIRRUS_REGNUM(REGNUM) \
864 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
865
866 #define FIRST_VFP_REGNUM 63
867 #define LAST_VFP_REGNUM 94
868 #define IS_VFP_REGNUM(REGNUM) \
869 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
870
871 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
872 /* + 16 Cirrus registers take us up to 43. */
873 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
874 /* VFP adds 32 + 1 more. */
875 #define FIRST_PSEUDO_REGISTER 96
876
877 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
878
879 /* Value should be nonzero if functions must have frame pointers.
880 Zero means the frame pointer need not be set up (and parms may be accessed
881 via the stack pointer) in functions that seem suitable.
882 If we have to have a frame pointer we might as well make use of it.
883 APCS says that the frame pointer does not need to be pushed in leaf
884 functions, or simple tail call functions. */
885
886 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
887 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
888 #endif
889
890 #define FRAME_POINTER_REQUIRED \
891 (current_function_has_nonlocal_label \
892 || SUBTARGET_FRAME_POINTER_REQUIRED \
893 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
894
895 /* Return number of consecutive hard regs needed starting at reg REGNO
896 to hold something of mode MODE.
897 This is ordinarily the length in words of a value of mode MODE
898 but can be less for certain modes in special long registers.
899
900 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
901 mode. */
902 #define HARD_REGNO_NREGS(REGNO, MODE) \
903 ((TARGET_ARM \
904 && REGNO >= FIRST_FPA_REGNUM \
905 && REGNO != FRAME_POINTER_REGNUM \
906 && REGNO != ARG_POINTER_REGNUM) \
907 && !IS_VFP_REGNUM (REGNO) \
908 ? 1 : ARM_NUM_REGS (MODE))
909
910 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
911 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
912 arm_hard_regno_mode_ok ((REGNO), (MODE))
913
914 /* Value is 1 if it is a good idea to tie two pseudo registers
915 when one has mode MODE1 and one has mode MODE2.
916 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
917 for any hard reg, then this must be 0 for correct output. */
918 #define MODES_TIEABLE_P(MODE1, MODE2) \
919 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
920
921 #define VALID_IWMMXT_REG_MODE(MODE) \
922 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
923
924 /* The order in which register should be allocated. It is good to use ip
925 since no saving is required (though calls clobber it) and it never contains
926 function parameters. It is quite good to use lr since other calls may
927 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
928 least likely to contain a function parameter; in addition results are
929 returned in r0. */
930
931 #define REG_ALLOC_ORDER \
932 { \
933 3, 2, 1, 0, 12, 14, 4, 5, \
934 6, 7, 8, 10, 9, 11, 13, 15, \
935 16, 17, 18, 19, 20, 21, 22, 23, \
936 27, 28, 29, 30, 31, 32, 33, 34, \
937 35, 36, 37, 38, 39, 40, 41, 42, \
938 43, 44, 45, 46, 47, 48, 49, 50, \
939 51, 52, 53, 54, 55, 56, 57, 58, \
940 59, 60, 61, 62, \
941 24, 25, 26, \
942 78, 77, 76, 75, 74, 73, 72, 71, \
943 70, 69, 68, 67, 66, 65, 64, 63, \
944 79, 80, 81, 82, 83, 84, 85, 86, \
945 87, 88, 89, 90, 91, 92, 93, 94, \
946 95 \
947 }
948
949 /* Interrupt functions can only use registers that have already been
950 saved by the prologue, even if they would normally be
951 call-clobbered. */
952 #define HARD_REGNO_RENAME_OK(SRC, DST) \
953 (! IS_INTERRUPT (cfun->machine->func_type) || \
954 regs_ever_live[DST])
955 \f
956 /* Register and constant classes. */
957
958 /* Register classes: used to be simple, just all ARM regs or all FPA regs
959 Now that the Thumb is involved it has become more complicated. */
960 enum reg_class
961 {
962 NO_REGS,
963 FPA_REGS,
964 CIRRUS_REGS,
965 VFP_REGS,
966 IWMMXT_GR_REGS,
967 IWMMXT_REGS,
968 LO_REGS,
969 STACK_REG,
970 BASE_REGS,
971 HI_REGS,
972 CC_REG,
973 VFPCC_REG,
974 GENERAL_REGS,
975 ALL_REGS,
976 LIM_REG_CLASSES
977 };
978
979 #define N_REG_CLASSES (int) LIM_REG_CLASSES
980
981 /* Give names of register classes as strings for dump file. */
982 #define REG_CLASS_NAMES \
983 { \
984 "NO_REGS", \
985 "FPA_REGS", \
986 "CIRRUS_REGS", \
987 "VFP_REGS", \
988 "IWMMXT_GR_REGS", \
989 "IWMMXT_REGS", \
990 "LO_REGS", \
991 "STACK_REG", \
992 "BASE_REGS", \
993 "HI_REGS", \
994 "CC_REG", \
995 "VFPCC_REG", \
996 "GENERAL_REGS", \
997 "ALL_REGS", \
998 }
999
1000 /* Define which registers fit in which classes.
1001 This is an initializer for a vector of HARD_REG_SET
1002 of length N_REG_CLASSES. */
1003 #define REG_CLASS_CONTENTS \
1004 { \
1005 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1006 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1007 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1008 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1009 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1010 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1011 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1012 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1013 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1014 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1015 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1016 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1017 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1018 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1019 }
1020
1021 /* The same information, inverted:
1022 Return the class number of the smallest class containing
1023 reg number REGNO. This could be a conditional expression
1024 or could index an array. */
1025 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1026
1027 /* FPA registers can't do subreg as all values are reformatted to internal
1028 precision. VFP registers may only be accessed in the mode they
1029 were set. */
1030 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1031 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1032 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1033 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1034 : 0)
1035
1036 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1037 using r0-r4 for function arguments, r7 for the stack frame and don't
1038 have enough left over to do doubleword arithmetic. */
1039 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1040 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1041 || (CLASS) == CC_REG)
1042
1043 /* The class value for index registers, and the one for base regs. */
1044 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1045 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1046
1047 /* For the Thumb the high registers cannot be used as base registers
1048 when addressing quantities in QI or HI mode; if we don't know the
1049 mode, then we must be conservative. */
1050 #define MODE_BASE_REG_CLASS(MODE) \
1051 (TARGET_ARM ? GENERAL_REGS : \
1052 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1053
1054 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1055 instead of BASE_REGS. */
1056 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1057
1058 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1059 registers explicitly used in the rtl to be used as spill registers
1060 but prevents the compiler from extending the lifetime of these
1061 registers. */
1062 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1063
1064 /* Get reg_class from a letter such as appears in the machine description.
1065 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1066 ARM, but several more letters for the Thumb. */
1067 #define REG_CLASS_FROM_LETTER(C) \
1068 ( (C) == 'f' ? FPA_REGS \
1069 : (C) == 'v' ? CIRRUS_REGS \
1070 : (C) == 'w' ? VFP_REGS \
1071 : (C) == 'y' ? IWMMXT_REGS \
1072 : (C) == 'z' ? IWMMXT_GR_REGS \
1073 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1074 : TARGET_ARM ? NO_REGS \
1075 : (C) == 'h' ? HI_REGS \
1076 : (C) == 'b' ? BASE_REGS \
1077 : (C) == 'k' ? STACK_REG \
1078 : (C) == 'c' ? CC_REG \
1079 : NO_REGS)
1080
1081 /* The letters I, J, K, L and M in a register constraint string
1082 can be used to stand for particular ranges of immediate operands.
1083 This macro defines what the ranges are.
1084 C is the letter, and VALUE is a constant value.
1085 Return 1 if VALUE is in the range specified by C.
1086 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1087 J: valid indexing constants.
1088 K: ~value ok in rhs argument of data operand.
1089 L: -value ok in rhs argument of data operand.
1090 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1091 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1092 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1093 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1094 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1095 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1096 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1097 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1098 : 0)
1099
1100 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1101 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1102 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1103 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1104 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1105 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1106 && ((VAL) & 3) == 0) : \
1107 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1108 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1109 : 0)
1110
1111 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1112 (TARGET_ARM ? \
1113 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1114
1115 /* Constant letter 'G' for the FP immediate constants.
1116 'H' means the same constant negated. */
1117 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1118 ((C) == 'G' ? arm_const_double_rtx (X) : \
1119 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1120
1121 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1122 (TARGET_ARM ? \
1123 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1124
1125 /* For the ARM, `Q' means that this is a memory operand that is just
1126 an offset from a register.
1127 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1128 address. This means that the symbol is in the text segment and can be
1129 accessed without using a load.
1130 'D' Prefixes a number of const_double operands where:
1131 'Da' is a constant that takes two ARM insns to load.
1132 'Db' takes three ARM insns.
1133 'Dc' takes four ARM insns, if we allow that in this compilation.
1134 'U' Prefixes an extended memory constraint where:
1135 'Uv' is an address valid for VFP load/store insns.
1136 'Uy' is an address valid for iwmmxt load/store insns.
1137 'Uq' is an address valid for ldrsb. */
1138
1139 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1140 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1141 || GET_CODE (OP) == CONST_INT \
1142 || GET_CODE (OP) == CONST_VECTOR) \
1143 && (((STR)[1] == 'a' \
1144 && arm_const_double_inline_cost (OP) == 2) \
1145 || ((STR)[1] == 'b' \
1146 && arm_const_double_inline_cost (OP) == 3) \
1147 || ((STR)[1] == 'c' \
1148 && arm_const_double_inline_cost (OP) == 4 \
1149 && !(optimize_size || arm_ld_sched)))) : \
1150 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1151 && GET_CODE (XEXP (OP, 0)) == REG) : \
1152 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1153 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1154 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1155 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1156 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1157 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1158 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1159 ((C) == 'U' && (STR)[1] == 'q') \
1160 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1161 : 0)
1162
1163 #define CONSTRAINT_LEN(C,STR) \
1164 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1165
1166 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1167 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1168 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1169
1170 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1171 (TARGET_ARM \
1172 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1173 : EXTRA_CONSTRAINT_THUMB (X, C))
1174
1175 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1176
1177 /* Given an rtx X being reloaded into a reg required to be
1178 in class CLASS, return the class of reg to actually use.
1179 In general this is just CLASS, but for the Thumb we prefer
1180 a LO_REGS class or a subset. */
1181 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1182 (TARGET_ARM ? (CLASS) : \
1183 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1184
1185 /* Must leave BASE_REGS reloads alone */
1186 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1187 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1188 ? ((true_regnum (X) == -1 ? LO_REGS \
1189 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1190 : NO_REGS)) \
1191 : NO_REGS)
1192
1193 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1194 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1195 ? ((true_regnum (X) == -1 ? LO_REGS \
1196 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1197 : NO_REGS)) \
1198 : NO_REGS)
1199
1200 /* Return the register class of a scratch register needed to copy IN into
1201 or out of a register in CLASS in MODE. If it can be done directly,
1202 NO_REGS is returned. */
1203 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1204 /* Restrict which direct reloads are allowed for VFP regs. */ \
1205 ((TARGET_VFP && TARGET_HARD_FLOAT \
1206 && (CLASS) == VFP_REGS) \
1207 ? vfp_secondary_reload_class (MODE, X) \
1208 : TARGET_ARM \
1209 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1210 ? GENERAL_REGS : NO_REGS) \
1211 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1212
1213 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1214 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1215 /* Restrict which direct reloads are allowed for VFP regs. */ \
1216 ((TARGET_VFP && TARGET_HARD_FLOAT \
1217 && (CLASS) == VFP_REGS) \
1218 ? vfp_secondary_reload_class (MODE, X) : \
1219 /* Cannot load constants into Cirrus registers. */ \
1220 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1221 && (CLASS) == CIRRUS_REGS \
1222 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1223 ? GENERAL_REGS : \
1224 (TARGET_ARM ? \
1225 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1226 && CONSTANT_P (X)) \
1227 ? GENERAL_REGS : \
1228 (((MODE) == HImode && ! arm_arch4 \
1229 && (GET_CODE (X) == MEM \
1230 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1231 && true_regnum (X) == -1))) \
1232 ? GENERAL_REGS : NO_REGS) \
1233 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1234
1235 /* Try a machine-dependent way of reloading an illegitimate address
1236 operand. If we find one, push the reload and jump to WIN. This
1237 macro is used in only one place: `find_reloads_address' in reload.c.
1238
1239 For the ARM, we wish to handle large displacements off a base
1240 register by splitting the addend across a MOV and the mem insn.
1241 This can cut the number of reloads needed. */
1242 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1243 do \
1244 { \
1245 if (GET_CODE (X) == PLUS \
1246 && GET_CODE (XEXP (X, 0)) == REG \
1247 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1248 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1249 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1250 { \
1251 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1252 HOST_WIDE_INT low, high; \
1253 \
1254 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1255 low = ((val & 0xf) ^ 0x8) - 0x8; \
1256 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1257 /* Need to be careful, -256 is not a valid offset. */ \
1258 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1259 else if (MODE == SImode \
1260 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1261 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1262 /* Need to be careful, -4096 is not a valid offset. */ \
1263 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1264 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1265 /* Need to be careful, -256 is not a valid offset. */ \
1266 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1267 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1268 && TARGET_HARD_FLOAT && TARGET_FPA) \
1269 /* Need to be careful, -1024 is not a valid offset. */ \
1270 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1271 else \
1272 break; \
1273 \
1274 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1275 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1276 - (unsigned HOST_WIDE_INT) 0x80000000); \
1277 /* Check for overflow or zero */ \
1278 if (low == 0 || high == 0 || (high + low != val)) \
1279 break; \
1280 \
1281 /* Reload the high part into a base reg; leave the low part \
1282 in the mem. */ \
1283 X = gen_rtx_PLUS (GET_MODE (X), \
1284 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1285 GEN_INT (high)), \
1286 GEN_INT (low)); \
1287 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1288 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1289 VOIDmode, 0, 0, OPNUM, TYPE); \
1290 goto WIN; \
1291 } \
1292 } \
1293 while (0)
1294
1295 /* XXX If an HImode FP+large_offset address is converted to an HImode
1296 SP+large_offset address, then reload won't know how to fix it. It sees
1297 only that SP isn't valid for HImode, and so reloads the SP into an index
1298 register, but the resulting address is still invalid because the offset
1299 is too big. We fix it here instead by reloading the entire address. */
1300 /* We could probably achieve better results by defining PROMOTE_MODE to help
1301 cope with the variances between the Thumb's signed and unsigned byte and
1302 halfword load instructions. */
1303 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1304 do { \
1305 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1306 if (new_x) \
1307 { \
1308 X = new_x; \
1309 goto WIN; \
1310 } \
1311 } while (0)
1312
1313 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1314 if (TARGET_ARM) \
1315 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1316 else \
1317 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1318
1319 /* Return the maximum number of consecutive registers
1320 needed to represent mode MODE in a register of class CLASS.
1321 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1322 #define CLASS_MAX_NREGS(CLASS, MODE) \
1323 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1324
1325 /* If defined, gives a class of registers that cannot be used as the
1326 operand of a SUBREG that changes the mode of the object illegally. */
1327
1328 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1329 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1330 (TARGET_ARM ? \
1331 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1332 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1333 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1334 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1335 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1336 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1337 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1338 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1339 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1340 2) \
1341 : \
1342 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1343 \f
1344 /* Stack layout; function entry, exit and calling. */
1345
1346 /* Define this if pushing a word on the stack
1347 makes the stack pointer a smaller address. */
1348 #define STACK_GROWS_DOWNWARD 1
1349
1350 /* Define this to nonzero if the nominal address of the stack frame
1351 is at the high-address end of the local variables;
1352 that is, each additional local variable allocated
1353 goes at a more negative offset in the frame. */
1354 #define FRAME_GROWS_DOWNWARD 1
1355
1356 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1357 When present, it is one word in size, and sits at the top of the frame,
1358 between the soft frame pointer and either r7 or r11.
1359
1360 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1361 and only then if some outgoing arguments are passed on the stack. It would
1362 be tempting to also check whether the stack arguments are passed by indirect
1363 calls, but there seems to be no reason in principle why a post-reload pass
1364 couldn't convert a direct call into an indirect one. */
1365 #define CALLER_INTERWORKING_SLOT_SIZE \
1366 (TARGET_CALLER_INTERWORKING \
1367 && current_function_outgoing_args_size != 0 \
1368 ? UNITS_PER_WORD : 0)
1369
1370 /* Offset within stack frame to start allocating local variables at.
1371 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1372 first local allocated. Otherwise, it is the offset to the BEGINNING
1373 of the first local allocated. */
1374 #define STARTING_FRAME_OFFSET 0
1375
1376 /* If we generate an insn to push BYTES bytes,
1377 this says how many the stack pointer really advances by. */
1378 /* The push insns do not do this rounding implicitly.
1379 So don't define this. */
1380 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1381
1382 /* Define this if the maximum size of all the outgoing args is to be
1383 accumulated and pushed during the prologue. The amount can be
1384 found in the variable current_function_outgoing_args_size. */
1385 #define ACCUMULATE_OUTGOING_ARGS 1
1386
1387 /* Offset of first parameter from the argument pointer register value. */
1388 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1389
1390 /* Value is the number of byte of arguments automatically
1391 popped when returning from a subroutine call.
1392 FUNDECL is the declaration node of the function (as a tree),
1393 FUNTYPE is the data type of the function (as a tree),
1394 or for a library call it is an identifier node for the subroutine name.
1395 SIZE is the number of bytes of arguments passed on the stack.
1396
1397 On the ARM, the caller does not pop any of its arguments that were passed
1398 on the stack. */
1399 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1400
1401 /* Define how to find the value returned by a library function
1402 assuming the value has mode MODE. */
1403 #define LIBCALL_VALUE(MODE) \
1404 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1405 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1406 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1407 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1408 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1409 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1410 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1411 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1412 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1413
1414 /* Define how to find the value returned by a function.
1415 VALTYPE is the data type of the value (as a tree).
1416 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1417 otherwise, FUNC is 0. */
1418 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1419 arm_function_value (VALTYPE, FUNC);
1420
1421 /* 1 if N is a possible register number for a function value.
1422 On the ARM, only r0 and f0 can return results. */
1423 /* On a Cirrus chip, mvf0 can return results. */
1424 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1425 ((REGNO) == ARG_REGISTER (1) \
1426 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1427 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1428 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1429 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1430 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1431
1432 /* Amount of memory needed for an untyped call to save all possible return
1433 registers. */
1434 #define APPLY_RESULT_SIZE arm_apply_result_size()
1435
1436 /* How large values are returned */
1437 /* A C expression which can inhibit the returning of certain function values
1438 in registers, based on the type of value. */
1439 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1440
1441 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1442 values must be in memory. On the ARM, they need only do so if larger
1443 than a word, or if they contain elements offset from zero in the struct. */
1444 #define DEFAULT_PCC_STRUCT_RETURN 0
1445
1446 /* Flags for the call/call_value rtl operations set up by function_arg. */
1447 #define CALL_NORMAL 0x00000000 /* No special processing. */
1448 #define CALL_LONG 0x00000001 /* Always call indirect. */
1449 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1450
1451 /* These bits describe the different types of function supported
1452 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1453 normal function and an interworked function, for example. Knowing the
1454 type of a function is important for determining its prologue and
1455 epilogue sequences.
1456 Note value 7 is currently unassigned. Also note that the interrupt
1457 function types all have bit 2 set, so that they can be tested for easily.
1458 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1459 machine_function structure is initialized (to zero) func_type will
1460 default to unknown. This will force the first use of arm_current_func_type
1461 to call arm_compute_func_type. */
1462 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1463 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1464 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1465 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1466 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1467 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1468
1469 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1470
1471 /* In addition functions can have several type modifiers,
1472 outlined by these bit masks: */
1473 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1474 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1475 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1476 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1477
1478 /* Some macros to test these flags. */
1479 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1480 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1481 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1482 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1483 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1484
1485
1486 /* Structure used to hold the function stack frame layout. Offsets are
1487 relative to the stack pointer on function entry. Positive offsets are
1488 in the direction of stack growth.
1489 Only soft_frame is used in thumb mode. */
1490
1491 typedef struct arm_stack_offsets GTY(())
1492 {
1493 int saved_args; /* ARG_POINTER_REGNUM. */
1494 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1495 int saved_regs;
1496 int soft_frame; /* FRAME_POINTER_REGNUM. */
1497 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1498 int outgoing_args; /* STACK_POINTER_REGNUM. */
1499 }
1500 arm_stack_offsets;
1501
1502 /* A C structure for machine-specific, per-function data.
1503 This is added to the cfun structure. */
1504 typedef struct machine_function GTY(())
1505 {
1506 /* Additional stack adjustment in __builtin_eh_throw. */
1507 rtx eh_epilogue_sp_ofs;
1508 /* Records if LR has to be saved for far jumps. */
1509 int far_jump_used;
1510 /* Records if ARG_POINTER was ever live. */
1511 int arg_pointer_live;
1512 /* Records if the save of LR has been eliminated. */
1513 int lr_save_eliminated;
1514 /* The size of the stack frame. Only valid after reload. */
1515 arm_stack_offsets stack_offsets;
1516 /* Records the type of the current function. */
1517 unsigned long func_type;
1518 /* Record if the function has a variable argument list. */
1519 int uses_anonymous_args;
1520 /* Records if sibcalls are blocked because an argument
1521 register is needed to preserve stack alignment. */
1522 int sibcall_blocked;
1523 /* The PIC register for this function. This might be a pseudo. */
1524 rtx pic_reg;
1525 /* Labels for per-function Thumb call-via stubs. One per potential calling
1526 register. We can never call via LR or PC. We can call via SP if a
1527 trampoline happens to be on the top of the stack. */
1528 rtx call_via[14];
1529 }
1530 machine_function;
1531
1532 /* As in the machine_function, a global set of call-via labels, for code
1533 that is in text_section. */
1534 extern GTY(()) rtx thumb_call_via_label[14];
1535
1536 /* A C type for declaring a variable that is used as the first argument of
1537 `FUNCTION_ARG' and other related values. For some target machines, the
1538 type `int' suffices and can hold the number of bytes of argument so far. */
1539 typedef struct
1540 {
1541 /* This is the number of registers of arguments scanned so far. */
1542 int nregs;
1543 /* This is the number of iWMMXt register arguments scanned so far. */
1544 int iwmmxt_nregs;
1545 int named_count;
1546 int nargs;
1547 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1548 int call_cookie;
1549 int can_split;
1550 } CUMULATIVE_ARGS;
1551
1552 /* Define where to put the arguments to a function.
1553 Value is zero to push the argument on the stack,
1554 or a hard register in which to store the argument.
1555
1556 MODE is the argument's machine mode.
1557 TYPE is the data type of the argument (as a tree).
1558 This is null for libcalls where that information may
1559 not be available.
1560 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1561 the preceding args and about the function being called.
1562 NAMED is nonzero if this argument is a named parameter
1563 (otherwise it is an extra parameter matching an ellipsis).
1564
1565 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1566 other arguments are passed on the stack. If (NAMED == 0) (which happens
1567 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1568 defined), say it is passed in the stack (function_prologue will
1569 indeed make it pass in the stack if necessary). */
1570 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1571 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1572
1573 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1574 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1575
1576 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1577 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1578
1579 /* For AAPCS, padding should never be below the argument. For other ABIs,
1580 * mimic the default. */
1581 #define PAD_VARARGS_DOWN \
1582 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1583
1584 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1585 for a call to a function whose data type is FNTYPE.
1586 For a library call, FNTYPE is 0.
1587 On the ARM, the offset starts at 0. */
1588 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1589 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1590
1591 /* Update the data in CUM to advance over an argument
1592 of mode MODE and data type TYPE.
1593 (TYPE is null for libcalls where that information may not be available.) */
1594 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1595 (CUM).nargs += 1; \
1596 if (arm_vector_mode_supported_p (MODE) \
1597 && (CUM).named_count > (CUM).nargs) \
1598 (CUM).iwmmxt_nregs += 1; \
1599 else \
1600 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1601
1602 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1603 argument with the specified mode and type. If it is not defined,
1604 `PARM_BOUNDARY' is used for all arguments. */
1605 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1606 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1607 ? DOUBLEWORD_ALIGNMENT \
1608 : PARM_BOUNDARY )
1609
1610 /* 1 if N is a possible register number for function argument passing.
1611 On the ARM, r0-r3 are used to pass args. */
1612 #define FUNCTION_ARG_REGNO_P(REGNO) \
1613 (IN_RANGE ((REGNO), 0, 3) \
1614 || (TARGET_IWMMXT_ABI \
1615 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1616
1617 \f
1618 /* If your target environment doesn't prefix user functions with an
1619 underscore, you may wish to re-define this to prevent any conflicts.
1620 e.g. AOF may prefix mcount with an underscore. */
1621 #ifndef ARM_MCOUNT_NAME
1622 #define ARM_MCOUNT_NAME "*mcount"
1623 #endif
1624
1625 /* Call the function profiler with a given profile label. The Acorn
1626 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1627 On the ARM the full profile code will look like:
1628 .data
1629 LP1
1630 .word 0
1631 .text
1632 mov ip, lr
1633 bl mcount
1634 .word LP1
1635
1636 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1637 will output the .text section.
1638
1639 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1640 ``prof'' doesn't seem to mind about this!
1641
1642 Note - this version of the code is designed to work in both ARM and
1643 Thumb modes. */
1644 #ifndef ARM_FUNCTION_PROFILER
1645 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1646 { \
1647 char temp[20]; \
1648 rtx sym; \
1649 \
1650 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1651 IP_REGNUM, LR_REGNUM); \
1652 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1653 fputc ('\n', STREAM); \
1654 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1655 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1656 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1657 }
1658 #endif
1659
1660 #ifdef THUMB_FUNCTION_PROFILER
1661 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1662 if (TARGET_ARM) \
1663 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1664 else \
1665 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1666 #else
1667 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1668 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1669 #endif
1670
1671 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1672 the stack pointer does not matter. The value is tested only in
1673 functions that have frame pointers.
1674 No definition is equivalent to always zero.
1675
1676 On the ARM, the function epilogue recovers the stack pointer from the
1677 frame. */
1678 #define EXIT_IGNORE_STACK 1
1679
1680 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1681
1682 /* Determine if the epilogue should be output as RTL.
1683 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1684 #define USE_RETURN_INSN(ISCOND) \
1685 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1686
1687 /* Definitions for register eliminations.
1688
1689 This is an array of structures. Each structure initializes one pair
1690 of eliminable registers. The "from" register number is given first,
1691 followed by "to". Eliminations of the same "from" register are listed
1692 in order of preference.
1693
1694 We have two registers that can be eliminated on the ARM. First, the
1695 arg pointer register can often be eliminated in favor of the stack
1696 pointer register. Secondly, the pseudo frame pointer register can always
1697 be eliminated; it is replaced with either the stack or the real frame
1698 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1699 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1700
1701 #define ELIMINABLE_REGS \
1702 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1703 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1704 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1705 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1706 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1707 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1708 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1709
1710 /* Given FROM and TO register numbers, say whether this elimination is
1711 allowed. Frame pointer elimination is automatically handled.
1712
1713 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1714 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1715 pointer, we must eliminate FRAME_POINTER_REGNUM into
1716 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1717 ARG_POINTER_REGNUM. */
1718 #define CAN_ELIMINATE(FROM, TO) \
1719 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1720 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1721 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1722 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1723 1)
1724
1725 /* Define the offset between two registers, one to be eliminated, and the
1726 other its replacement, at the start of a routine. */
1727 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1728 if (TARGET_ARM) \
1729 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1730 else \
1731 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1732
1733 /* Special case handling of the location of arguments passed on the stack. */
1734 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1735
1736 /* Initialize data used by insn expanders. This is called from insn_emit,
1737 once for every function before code is generated. */
1738 #define INIT_EXPANDERS arm_init_expanders ()
1739
1740 /* Output assembler code for a block containing the constant parts
1741 of a trampoline, leaving space for the variable parts.
1742
1743 On the ARM, (if r8 is the static chain regnum, and remembering that
1744 referencing pc adds an offset of 8) the trampoline looks like:
1745 ldr r8, [pc, #0]
1746 ldr pc, [pc]
1747 .word static chain value
1748 .word function's address
1749 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1750 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1751 { \
1752 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1753 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1754 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1755 PC_REGNUM, PC_REGNUM); \
1756 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1757 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1758 }
1759
1760 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1761 Why - because it is easier. This code will always be branched to via
1762 a BX instruction and since the compiler magically generates the address
1763 of the function the linker has no opportunity to ensure that the
1764 bottom bit is set. Thus the processor will be in ARM mode when it
1765 reaches this code. So we duplicate the ARM trampoline code and add
1766 a switch into Thumb mode as well. */
1767 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1768 { \
1769 fprintf (FILE, "\t.code 32\n"); \
1770 fprintf (FILE, ".Ltrampoline_start:\n"); \
1771 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1772 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1773 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1774 IP_REGNUM, PC_REGNUM); \
1775 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1776 IP_REGNUM, IP_REGNUM); \
1777 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1778 fprintf (FILE, "\t.word\t0\n"); \
1779 fprintf (FILE, "\t.word\t0\n"); \
1780 fprintf (FILE, "\t.code 16\n"); \
1781 }
1782
1783 #define TRAMPOLINE_TEMPLATE(FILE) \
1784 if (TARGET_ARM) \
1785 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1786 else \
1787 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1788
1789 /* Length in units of the trampoline for entering a nested function. */
1790 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1791
1792 /* Alignment required for a trampoline in bits. */
1793 #define TRAMPOLINE_ALIGNMENT 32
1794
1795
1796 /* Emit RTL insns to initialize the variable parts of a trampoline.
1797 FNADDR is an RTX for the address of the function's pure code.
1798 CXT is an RTX for the static chain value for the function. */
1799 #ifndef INITIALIZE_TRAMPOLINE
1800 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1801 { \
1802 emit_move_insn (gen_rtx_MEM (SImode, \
1803 plus_constant (TRAMP, \
1804 TARGET_ARM ? 8 : 16)), \
1805 CXT); \
1806 emit_move_insn (gen_rtx_MEM (SImode, \
1807 plus_constant (TRAMP, \
1808 TARGET_ARM ? 12 : 20)), \
1809 FNADDR); \
1810 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1811 0, VOIDmode, 2, TRAMP, Pmode, \
1812 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1813 }
1814 #endif
1815
1816 \f
1817 /* Addressing modes, and classification of registers for them. */
1818 #define HAVE_POST_INCREMENT 1
1819 #define HAVE_PRE_INCREMENT TARGET_ARM
1820 #define HAVE_POST_DECREMENT TARGET_ARM
1821 #define HAVE_PRE_DECREMENT TARGET_ARM
1822 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1823 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1824 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1825 #define HAVE_POST_MODIFY_REG TARGET_ARM
1826
1827 /* Macros to check register numbers against specific register classes. */
1828
1829 /* These assume that REGNO is a hard or pseudo reg number.
1830 They give nonzero only if REGNO is a hard reg of the suitable class
1831 or a pseudo reg currently allocated to a suitable hard reg.
1832 Since they use reg_renumber, they are safe only once reg_renumber
1833 has been allocated, which happens in local-alloc.c. */
1834 #define TEST_REGNO(R, TEST, VALUE) \
1835 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1836
1837 /* On the ARM, don't allow the pc to be used. */
1838 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1839 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1840 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1841 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1842
1843 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1844 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1845 || (GET_MODE_SIZE (MODE) >= 4 \
1846 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1847
1848 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1849 (TARGET_THUMB \
1850 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1851 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1852
1853 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1854 For Thumb, we can not use SP + reg, so reject SP. */
1855 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1856 REGNO_OK_FOR_INDEX_P (X)
1857
1858 /* For ARM code, we don't care about the mode, but for Thumb, the index
1859 must be suitable for use in a QImode load. */
1860 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1861 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1862
1863 /* Maximum number of registers that can appear in a valid memory address.
1864 Shifts in addresses can't be by a register. */
1865 #define MAX_REGS_PER_ADDRESS 2
1866
1867 /* Recognize any constant value that is a valid address. */
1868 /* XXX We can address any constant, eventually... */
1869
1870 #ifdef AOF_ASSEMBLER
1871
1872 #define CONSTANT_ADDRESS_P(X) \
1873 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1874
1875 #else
1876
1877 #define CONSTANT_ADDRESS_P(X) \
1878 (GET_CODE (X) == SYMBOL_REF \
1879 && (CONSTANT_POOL_ADDRESS_P (X) \
1880 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1881
1882 #endif /* AOF_ASSEMBLER */
1883
1884 /* Nonzero if the constant value X is a legitimate general operand.
1885 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1886
1887 On the ARM, allow any integer (invalid ones are removed later by insn
1888 patterns), nice doubles and symbol_refs which refer to the function's
1889 constant pool XXX.
1890
1891 When generating pic allow anything. */
1892 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1893
1894 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1895 ( GET_CODE (X) == CONST_INT \
1896 || GET_CODE (X) == CONST_DOUBLE \
1897 || CONSTANT_ADDRESS_P (X) \
1898 || flag_pic)
1899
1900 #define LEGITIMATE_CONSTANT_P(X) \
1901 (!arm_tls_referenced_p (X) \
1902 && (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) \
1903 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1904
1905 /* Special characters prefixed to function names
1906 in order to encode attribute like information.
1907 Note, '@' and '*' have already been taken. */
1908 #define SHORT_CALL_FLAG_CHAR '^'
1909 #define LONG_CALL_FLAG_CHAR '#'
1910
1911 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1912 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1913
1914 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1915 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1916
1917 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1918 #define SUBTARGET_NAME_ENCODING_LENGTHS
1919 #endif
1920
1921 /* This is a C fragment for the inside of a switch statement.
1922 Each case label should return the number of characters to
1923 be stripped from the start of a function's name, if that
1924 name starts with the indicated character. */
1925 #define ARM_NAME_ENCODING_LENGTHS \
1926 case SHORT_CALL_FLAG_CHAR: return 1; \
1927 case LONG_CALL_FLAG_CHAR: return 1; \
1928 case '*': return 1; \
1929 SUBTARGET_NAME_ENCODING_LENGTHS
1930
1931 /* This is how to output a reference to a user-level label named NAME.
1932 `assemble_name' uses this. */
1933 #undef ASM_OUTPUT_LABELREF
1934 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1935 arm_asm_output_labelref (FILE, NAME)
1936
1937 /* The EABI specifies that constructors should go in .init_array.
1938 Other targets use .ctors for compatibility. */
1939 #ifndef ARM_EABI_CTORS_SECTION_OP
1940 #define ARM_EABI_CTORS_SECTION_OP \
1941 "\t.section\t.init_array,\"aw\",%init_array"
1942 #endif
1943 #ifndef ARM_EABI_DTORS_SECTION_OP
1944 #define ARM_EABI_DTORS_SECTION_OP \
1945 "\t.section\t.fini_array,\"aw\",%fini_array"
1946 #endif
1947 #define ARM_CTORS_SECTION_OP \
1948 "\t.section\t.ctors,\"aw\",%progbits"
1949 #define ARM_DTORS_SECTION_OP \
1950 "\t.section\t.dtors,\"aw\",%progbits"
1951
1952 /* Define CTORS_SECTION_ASM_OP. */
1953 #undef CTORS_SECTION_ASM_OP
1954 #undef DTORS_SECTION_ASM_OP
1955 #ifndef IN_LIBGCC2
1956 # define CTORS_SECTION_ASM_OP \
1957 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1958 # define DTORS_SECTION_ASM_OP \
1959 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1960 #else /* !defined (IN_LIBGCC2) */
1961 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1962 so we cannot use the definition above. */
1963 # ifdef __ARM_EABI__
1964 /* The .ctors section is not part of the EABI, so we do not define
1965 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1966 from trying to use it. We do define it when doing normal
1967 compilation, as .init_array can be used instead of .ctors. */
1968 /* There is no need to emit begin or end markers when using
1969 init_array; the dynamic linker will compute the size of the
1970 array itself based on special symbols created by the static
1971 linker. However, we do need to arrange to set up
1972 exception-handling here. */
1973 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1974 # define CTOR_LIST_END /* empty */
1975 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1976 # define DTOR_LIST_END /* empty */
1977 # else /* !defined (__ARM_EABI__) */
1978 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1979 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1980 # endif /* !defined (__ARM_EABI__) */
1981 #endif /* !defined (IN_LIBCC2) */
1982
1983 /* True if the operating system can merge entities with vague linkage
1984 (e.g., symbols in COMDAT group) during dynamic linking. */
1985 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1986 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1987 #endif
1988
1989 /* Set the short-call flag for any function compiled in the current
1990 compilation unit. We skip this for functions with the section
1991 attribute when long-calls are in effect as this tells the compiler
1992 that the section might be placed a long way from the caller.
1993 See arm_is_longcall_p() for more information. */
1994 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1995 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1996 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1997
1998 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1999
2000 #ifdef TARGET_UNWIND_INFO
2001 #define ARM_EABI_UNWIND_TABLES \
2002 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2003 #else
2004 #define ARM_EABI_UNWIND_TABLES 0
2005 #endif
2006
2007 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2008 and check its validity for a certain class.
2009 We have two alternate definitions for each of them.
2010 The usual definition accepts all pseudo regs; the other rejects
2011 them unless they have been allocated suitable hard regs.
2012 The symbol REG_OK_STRICT causes the latter definition to be used. */
2013 #ifndef REG_OK_STRICT
2014
2015 #define ARM_REG_OK_FOR_BASE_P(X) \
2016 (REGNO (X) <= LAST_ARM_REGNUM \
2017 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2018 || REGNO (X) == FRAME_POINTER_REGNUM \
2019 || REGNO (X) == ARG_POINTER_REGNUM)
2020
2021 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2022 (REGNO (X) <= LAST_LO_REGNUM \
2023 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2024 || (GET_MODE_SIZE (MODE) >= 4 \
2025 && (REGNO (X) == STACK_POINTER_REGNUM \
2026 || (X) == hard_frame_pointer_rtx \
2027 || (X) == arg_pointer_rtx)))
2028
2029 #define REG_STRICT_P 0
2030
2031 #else /* REG_OK_STRICT */
2032
2033 #define ARM_REG_OK_FOR_BASE_P(X) \
2034 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2035
2036 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2037 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2038
2039 #define REG_STRICT_P 1
2040
2041 #endif /* REG_OK_STRICT */
2042
2043 /* Now define some helpers in terms of the above. */
2044
2045 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2046 (TARGET_THUMB \
2047 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2048 : ARM_REG_OK_FOR_BASE_P (X))
2049
2050 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2051
2052 /* For Thumb, a valid index register is anything that can be used in
2053 a byte load instruction. */
2054 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2055
2056 /* Nonzero if X is a hard reg that can be used as an index
2057 or if it is a pseudo reg. On the Thumb, the stack pointer
2058 is not suitable. */
2059 #define REG_OK_FOR_INDEX_P(X) \
2060 (TARGET_THUMB \
2061 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2062 : ARM_REG_OK_FOR_INDEX_P (X))
2063
2064 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2065 For Thumb, we can not use SP + reg, so reject SP. */
2066 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2067 REG_OK_FOR_INDEX_P (X)
2068 \f
2069 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2070 that is a valid memory address for an instruction.
2071 The MODE argument is the machine mode for the MEM expression
2072 that wants to use this address. */
2073
2074 #define ARM_BASE_REGISTER_RTX_P(X) \
2075 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2076
2077 #define ARM_INDEX_REGISTER_RTX_P(X) \
2078 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2079
2080 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2081 { \
2082 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2083 goto WIN; \
2084 }
2085
2086 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2087 { \
2088 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2089 goto WIN; \
2090 }
2091
2092 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2093 if (TARGET_ARM) \
2094 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2095 else /* if (TARGET_THUMB) */ \
2096 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2097
2098 \f
2099 /* Try machine-dependent ways of modifying an illegitimate address
2100 to be legitimate. If we find one, return the new, valid address. */
2101 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2102 do { \
2103 X = arm_legitimize_address (X, OLDX, MODE); \
2104 } while (0)
2105
2106 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2107 do { \
2108 X = thumb_legitimize_address (X, OLDX, MODE); \
2109 } while (0)
2110
2111 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2112 do { \
2113 if (TARGET_ARM) \
2114 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2115 else \
2116 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2117 \
2118 if (memory_address_p (MODE, X)) \
2119 goto WIN; \
2120 } while (0)
2121
2122 /* Go to LABEL if ADDR (a legitimate address expression)
2123 has an effect that depends on the machine mode it is used for. */
2124 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2125 { \
2126 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2127 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2128 goto LABEL; \
2129 }
2130
2131 /* Nothing helpful to do for the Thumb */
2132 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2133 if (TARGET_ARM) \
2134 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2135 \f
2136
2137 /* Specify the machine mode that this machine uses
2138 for the index in the tablejump instruction. */
2139 #define CASE_VECTOR_MODE Pmode
2140
2141 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2142 unsigned is probably best, but may break some code. */
2143 #ifndef DEFAULT_SIGNED_CHAR
2144 #define DEFAULT_SIGNED_CHAR 0
2145 #endif
2146
2147 /* Max number of bytes we can move from memory to memory
2148 in one reasonably fast instruction. */
2149 #define MOVE_MAX 4
2150
2151 #undef MOVE_RATIO
2152 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2153
2154 /* Define if operations between registers always perform the operation
2155 on the full register even if a narrower mode is specified. */
2156 #define WORD_REGISTER_OPERATIONS
2157
2158 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2159 will either zero-extend or sign-extend. The value of this macro should
2160 be the code that says which one of the two operations is implicitly
2161 done, UNKNOWN if none. */
2162 #define LOAD_EXTEND_OP(MODE) \
2163 (TARGET_THUMB ? ZERO_EXTEND : \
2164 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2165 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2166
2167 /* Nonzero if access to memory by bytes is slow and undesirable. */
2168 #define SLOW_BYTE_ACCESS 0
2169
2170 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2171
2172 /* Immediate shift counts are truncated by the output routines (or was it
2173 the assembler?). Shift counts in a register are truncated by ARM. Note
2174 that the native compiler puts too large (> 32) immediate shift counts
2175 into a register and shifts by the register, letting the ARM decide what
2176 to do instead of doing that itself. */
2177 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2178 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2179 On the arm, Y in a register is used modulo 256 for the shift. Only for
2180 rotates is modulo 32 used. */
2181 /* #define SHIFT_COUNT_TRUNCATED 1 */
2182
2183 /* All integers have the same format so truncation is easy. */
2184 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2185
2186 /* Calling from registers is a massive pain. */
2187 #define NO_FUNCTION_CSE 1
2188
2189 /* The machine modes of pointers and functions */
2190 #define Pmode SImode
2191 #define FUNCTION_MODE Pmode
2192
2193 #define ARM_FRAME_RTX(X) \
2194 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2195 || (X) == arg_pointer_rtx)
2196
2197 /* Moves to and from memory are quite expensive */
2198 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2199 (TARGET_ARM ? 10 : \
2200 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2201 * (CLASS == LO_REGS ? 1 : 2)))
2202
2203 /* Try to generate sequences that don't involve branches, we can then use
2204 conditional instructions */
2205 #define BRANCH_COST \
2206 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2207 \f
2208 /* Position Independent Code. */
2209 /* We decide which register to use based on the compilation options and
2210 the assembler in use; this is more general than the APCS restriction of
2211 using sb (r9) all the time. */
2212 extern unsigned arm_pic_register;
2213
2214 /* The register number of the register used to address a table of static
2215 data addresses in memory. */
2216 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2217
2218 /* We can't directly access anything that contains a symbol,
2219 nor can we indirect via the constant pool. One exception is
2220 UNSPEC_TLS, which is always PIC. */
2221 #define LEGITIMATE_PIC_OPERAND_P(X) \
2222 (!(symbol_mentioned_p (X) \
2223 || label_mentioned_p (X) \
2224 || (GET_CODE (X) == SYMBOL_REF \
2225 && CONSTANT_POOL_ADDRESS_P (X) \
2226 && (symbol_mentioned_p (get_pool_constant (X)) \
2227 || label_mentioned_p (get_pool_constant (X))))) \
2228 || tls_mentioned_p (X))
2229
2230 /* We need to know when we are making a constant pool; this determines
2231 whether data needs to be in the GOT or can be referenced via a GOT
2232 offset. */
2233 extern int making_const_table;
2234 \f
2235 /* Handle pragmas for compatibility with Intel's compilers. */
2236 #define REGISTER_TARGET_PRAGMAS() do { \
2237 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2238 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2239 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2240 } while (0)
2241
2242 /* Condition code information. */
2243 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2244 return the mode to be used for the comparison. */
2245
2246 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2247
2248 #define REVERSIBLE_CC_MODE(MODE) 1
2249
2250 #define REVERSE_CONDITION(CODE,MODE) \
2251 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2252 ? reverse_condition_maybe_unordered (code) \
2253 : reverse_condition (code))
2254
2255 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2256 do \
2257 { \
2258 if (GET_CODE (OP1) == CONST_INT \
2259 && ! (const_ok_for_arm (INTVAL (OP1)) \
2260 || (const_ok_for_arm (- INTVAL (OP1))))) \
2261 { \
2262 rtx const_op = OP1; \
2263 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2264 &const_op); \
2265 OP1 = const_op; \
2266 } \
2267 } \
2268 while (0)
2269
2270 /* The arm5 clz instruction returns 32. */
2271 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2272 \f
2273 #undef ASM_APP_OFF
2274 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2275
2276 /* Output a push or a pop instruction (only used when profiling). */
2277 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2278 do \
2279 { \
2280 if (TARGET_ARM) \
2281 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2282 STACK_POINTER_REGNUM, REGNO); \
2283 else \
2284 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2285 } while (0)
2286
2287
2288 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2289 do \
2290 { \
2291 if (TARGET_ARM) \
2292 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2293 STACK_POINTER_REGNUM, REGNO); \
2294 else \
2295 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2296 } while (0)
2297
2298 /* This is how to output a label which precedes a jumptable. Since
2299 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2300 #undef ASM_OUTPUT_CASE_LABEL
2301 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2302 do \
2303 { \
2304 if (TARGET_THUMB) \
2305 ASM_OUTPUT_ALIGN (FILE, 2); \
2306 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2307 } \
2308 while (0)
2309
2310 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2311 do \
2312 { \
2313 if (TARGET_THUMB) \
2314 { \
2315 if (is_called_in_ARM_mode (DECL) \
2316 || current_function_is_thunk) \
2317 fprintf (STREAM, "\t.code 32\n") ; \
2318 else \
2319 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2320 } \
2321 if (TARGET_POKE_FUNCTION_NAME) \
2322 arm_poke_function_name (STREAM, (char *) NAME); \
2323 } \
2324 while (0)
2325
2326 /* For aliases of functions we use .thumb_set instead. */
2327 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2328 do \
2329 { \
2330 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2331 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2332 \
2333 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2334 { \
2335 fprintf (FILE, "\t.thumb_set "); \
2336 assemble_name (FILE, LABEL1); \
2337 fprintf (FILE, ","); \
2338 assemble_name (FILE, LABEL2); \
2339 fprintf (FILE, "\n"); \
2340 } \
2341 else \
2342 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2343 } \
2344 while (0)
2345
2346 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2347 /* To support -falign-* switches we need to use .p2align so
2348 that alignment directives in code sections will be padded
2349 with no-op instructions, rather than zeroes. */
2350 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2351 if ((LOG) != 0) \
2352 { \
2353 if ((MAX_SKIP) == 0) \
2354 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2355 else \
2356 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2357 (int) (LOG), (int) (MAX_SKIP)); \
2358 }
2359 #endif
2360 \f
2361 /* Only perform branch elimination (by making instructions conditional) if
2362 we're optimizing. Otherwise it's of no use anyway. */
2363 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2364 if (TARGET_ARM && optimize) \
2365 arm_final_prescan_insn (INSN); \
2366 else if (TARGET_THUMB) \
2367 thumb_final_prescan_insn (INSN)
2368
2369 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2370 (CODE == '@' || CODE == '|' \
2371 || (TARGET_ARM && (CODE == '?')) \
2372 || (TARGET_THUMB && (CODE == '_')))
2373
2374 /* Output an operand of an instruction. */
2375 #define PRINT_OPERAND(STREAM, X, CODE) \
2376 arm_print_operand (STREAM, X, CODE)
2377
2378 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2379 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2380 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2381 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2382 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2383 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2384 : 0))))
2385
2386 /* Output the address of an operand. */
2387 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2388 { \
2389 int is_minus = GET_CODE (X) == MINUS; \
2390 \
2391 if (GET_CODE (X) == REG) \
2392 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2393 else if (GET_CODE (X) == PLUS || is_minus) \
2394 { \
2395 rtx base = XEXP (X, 0); \
2396 rtx index = XEXP (X, 1); \
2397 HOST_WIDE_INT offset = 0; \
2398 if (GET_CODE (base) != REG) \
2399 { \
2400 /* Ensure that BASE is a register. */ \
2401 /* (one of them must be). */ \
2402 rtx temp = base; \
2403 base = index; \
2404 index = temp; \
2405 } \
2406 switch (GET_CODE (index)) \
2407 { \
2408 case CONST_INT: \
2409 offset = INTVAL (index); \
2410 if (is_minus) \
2411 offset = -offset; \
2412 asm_fprintf (STREAM, "[%r, #%wd]", \
2413 REGNO (base), offset); \
2414 break; \
2415 \
2416 case REG: \
2417 asm_fprintf (STREAM, "[%r, %s%r]", \
2418 REGNO (base), is_minus ? "-" : "", \
2419 REGNO (index)); \
2420 break; \
2421 \
2422 case MULT: \
2423 case ASHIFTRT: \
2424 case LSHIFTRT: \
2425 case ASHIFT: \
2426 case ROTATERT: \
2427 { \
2428 asm_fprintf (STREAM, "[%r, %s%r", \
2429 REGNO (base), is_minus ? "-" : "", \
2430 REGNO (XEXP (index, 0))); \
2431 arm_print_operand (STREAM, index, 'S'); \
2432 fputs ("]", STREAM); \
2433 break; \
2434 } \
2435 \
2436 default: \
2437 gcc_unreachable (); \
2438 } \
2439 } \
2440 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2441 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2442 { \
2443 extern enum machine_mode output_memory_reference_mode; \
2444 \
2445 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2446 \
2447 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2448 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2449 REGNO (XEXP (X, 0)), \
2450 GET_CODE (X) == PRE_DEC ? "-" : "", \
2451 GET_MODE_SIZE (output_memory_reference_mode)); \
2452 else \
2453 asm_fprintf (STREAM, "[%r], #%s%d", \
2454 REGNO (XEXP (X, 0)), \
2455 GET_CODE (X) == POST_DEC ? "-" : "", \
2456 GET_MODE_SIZE (output_memory_reference_mode)); \
2457 } \
2458 else if (GET_CODE (X) == PRE_MODIFY) \
2459 { \
2460 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2461 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2462 asm_fprintf (STREAM, "#%wd]!", \
2463 INTVAL (XEXP (XEXP (X, 1), 1))); \
2464 else \
2465 asm_fprintf (STREAM, "%r]!", \
2466 REGNO (XEXP (XEXP (X, 1), 1))); \
2467 } \
2468 else if (GET_CODE (X) == POST_MODIFY) \
2469 { \
2470 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2471 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2472 asm_fprintf (STREAM, "#%wd", \
2473 INTVAL (XEXP (XEXP (X, 1), 1))); \
2474 else \
2475 asm_fprintf (STREAM, "%r", \
2476 REGNO (XEXP (XEXP (X, 1), 1))); \
2477 } \
2478 else output_addr_const (STREAM, X); \
2479 }
2480
2481 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2482 { \
2483 if (GET_CODE (X) == REG) \
2484 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2485 else if (GET_CODE (X) == POST_INC) \
2486 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2487 else if (GET_CODE (X) == PLUS) \
2488 { \
2489 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2490 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2491 asm_fprintf (STREAM, "[%r, #%wd]", \
2492 REGNO (XEXP (X, 0)), \
2493 INTVAL (XEXP (X, 1))); \
2494 else \
2495 asm_fprintf (STREAM, "[%r, %r]", \
2496 REGNO (XEXP (X, 0)), \
2497 REGNO (XEXP (X, 1))); \
2498 } \
2499 else \
2500 output_addr_const (STREAM, X); \
2501 }
2502
2503 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2504 if (TARGET_ARM) \
2505 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2506 else \
2507 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2508
2509 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2510 if (arm_output_addr_const_extra (file, x) == FALSE) \
2511 goto fail
2512
2513 /* A C expression whose value is RTL representing the value of the return
2514 address for the frame COUNT steps up from the current frame. */
2515
2516 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2517 arm_return_addr (COUNT, FRAME)
2518
2519 /* Mask of the bits in the PC that contain the real return address
2520 when running in 26-bit mode. */
2521 #define RETURN_ADDR_MASK26 (0x03fffffc)
2522
2523 /* Pick up the return address upon entry to a procedure. Used for
2524 dwarf2 unwind information. This also enables the table driven
2525 mechanism. */
2526 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2527 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2528
2529 /* Used to mask out junk bits from the return address, such as
2530 processor state, interrupt status, condition codes and the like. */
2531 #define MASK_RETURN_ADDR \
2532 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2533 in 26 bit mode, the condition codes must be masked out of the \
2534 return address. This does not apply to ARM6 and later processors \
2535 when running in 32 bit mode. */ \
2536 ((arm_arch4 || TARGET_THUMB) \
2537 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2538 : arm_gen_return_addr_mask ())
2539
2540 \f
2541 enum arm_builtins
2542 {
2543 ARM_BUILTIN_GETWCX,
2544 ARM_BUILTIN_SETWCX,
2545
2546 ARM_BUILTIN_WZERO,
2547
2548 ARM_BUILTIN_WAVG2BR,
2549 ARM_BUILTIN_WAVG2HR,
2550 ARM_BUILTIN_WAVG2B,
2551 ARM_BUILTIN_WAVG2H,
2552
2553 ARM_BUILTIN_WACCB,
2554 ARM_BUILTIN_WACCH,
2555 ARM_BUILTIN_WACCW,
2556
2557 ARM_BUILTIN_WMACS,
2558 ARM_BUILTIN_WMACSZ,
2559 ARM_BUILTIN_WMACU,
2560 ARM_BUILTIN_WMACUZ,
2561
2562 ARM_BUILTIN_WSADB,
2563 ARM_BUILTIN_WSADBZ,
2564 ARM_BUILTIN_WSADH,
2565 ARM_BUILTIN_WSADHZ,
2566
2567 ARM_BUILTIN_WALIGN,
2568
2569 ARM_BUILTIN_TMIA,
2570 ARM_BUILTIN_TMIAPH,
2571 ARM_BUILTIN_TMIABB,
2572 ARM_BUILTIN_TMIABT,
2573 ARM_BUILTIN_TMIATB,
2574 ARM_BUILTIN_TMIATT,
2575
2576 ARM_BUILTIN_TMOVMSKB,
2577 ARM_BUILTIN_TMOVMSKH,
2578 ARM_BUILTIN_TMOVMSKW,
2579
2580 ARM_BUILTIN_TBCSTB,
2581 ARM_BUILTIN_TBCSTH,
2582 ARM_BUILTIN_TBCSTW,
2583
2584 ARM_BUILTIN_WMADDS,
2585 ARM_BUILTIN_WMADDU,
2586
2587 ARM_BUILTIN_WPACKHSS,
2588 ARM_BUILTIN_WPACKWSS,
2589 ARM_BUILTIN_WPACKDSS,
2590 ARM_BUILTIN_WPACKHUS,
2591 ARM_BUILTIN_WPACKWUS,
2592 ARM_BUILTIN_WPACKDUS,
2593
2594 ARM_BUILTIN_WADDB,
2595 ARM_BUILTIN_WADDH,
2596 ARM_BUILTIN_WADDW,
2597 ARM_BUILTIN_WADDSSB,
2598 ARM_BUILTIN_WADDSSH,
2599 ARM_BUILTIN_WADDSSW,
2600 ARM_BUILTIN_WADDUSB,
2601 ARM_BUILTIN_WADDUSH,
2602 ARM_BUILTIN_WADDUSW,
2603 ARM_BUILTIN_WSUBB,
2604 ARM_BUILTIN_WSUBH,
2605 ARM_BUILTIN_WSUBW,
2606 ARM_BUILTIN_WSUBSSB,
2607 ARM_BUILTIN_WSUBSSH,
2608 ARM_BUILTIN_WSUBSSW,
2609 ARM_BUILTIN_WSUBUSB,
2610 ARM_BUILTIN_WSUBUSH,
2611 ARM_BUILTIN_WSUBUSW,
2612
2613 ARM_BUILTIN_WAND,
2614 ARM_BUILTIN_WANDN,
2615 ARM_BUILTIN_WOR,
2616 ARM_BUILTIN_WXOR,
2617
2618 ARM_BUILTIN_WCMPEQB,
2619 ARM_BUILTIN_WCMPEQH,
2620 ARM_BUILTIN_WCMPEQW,
2621 ARM_BUILTIN_WCMPGTUB,
2622 ARM_BUILTIN_WCMPGTUH,
2623 ARM_BUILTIN_WCMPGTUW,
2624 ARM_BUILTIN_WCMPGTSB,
2625 ARM_BUILTIN_WCMPGTSH,
2626 ARM_BUILTIN_WCMPGTSW,
2627
2628 ARM_BUILTIN_TEXTRMSB,
2629 ARM_BUILTIN_TEXTRMSH,
2630 ARM_BUILTIN_TEXTRMSW,
2631 ARM_BUILTIN_TEXTRMUB,
2632 ARM_BUILTIN_TEXTRMUH,
2633 ARM_BUILTIN_TEXTRMUW,
2634 ARM_BUILTIN_TINSRB,
2635 ARM_BUILTIN_TINSRH,
2636 ARM_BUILTIN_TINSRW,
2637
2638 ARM_BUILTIN_WMAXSW,
2639 ARM_BUILTIN_WMAXSH,
2640 ARM_BUILTIN_WMAXSB,
2641 ARM_BUILTIN_WMAXUW,
2642 ARM_BUILTIN_WMAXUH,
2643 ARM_BUILTIN_WMAXUB,
2644 ARM_BUILTIN_WMINSW,
2645 ARM_BUILTIN_WMINSH,
2646 ARM_BUILTIN_WMINSB,
2647 ARM_BUILTIN_WMINUW,
2648 ARM_BUILTIN_WMINUH,
2649 ARM_BUILTIN_WMINUB,
2650
2651 ARM_BUILTIN_WMULUM,
2652 ARM_BUILTIN_WMULSM,
2653 ARM_BUILTIN_WMULUL,
2654
2655 ARM_BUILTIN_PSADBH,
2656 ARM_BUILTIN_WSHUFH,
2657
2658 ARM_BUILTIN_WSLLH,
2659 ARM_BUILTIN_WSLLW,
2660 ARM_BUILTIN_WSLLD,
2661 ARM_BUILTIN_WSRAH,
2662 ARM_BUILTIN_WSRAW,
2663 ARM_BUILTIN_WSRAD,
2664 ARM_BUILTIN_WSRLH,
2665 ARM_BUILTIN_WSRLW,
2666 ARM_BUILTIN_WSRLD,
2667 ARM_BUILTIN_WRORH,
2668 ARM_BUILTIN_WRORW,
2669 ARM_BUILTIN_WRORD,
2670 ARM_BUILTIN_WSLLHI,
2671 ARM_BUILTIN_WSLLWI,
2672 ARM_BUILTIN_WSLLDI,
2673 ARM_BUILTIN_WSRAHI,
2674 ARM_BUILTIN_WSRAWI,
2675 ARM_BUILTIN_WSRADI,
2676 ARM_BUILTIN_WSRLHI,
2677 ARM_BUILTIN_WSRLWI,
2678 ARM_BUILTIN_WSRLDI,
2679 ARM_BUILTIN_WRORHI,
2680 ARM_BUILTIN_WRORWI,
2681 ARM_BUILTIN_WRORDI,
2682
2683 ARM_BUILTIN_WUNPCKIHB,
2684 ARM_BUILTIN_WUNPCKIHH,
2685 ARM_BUILTIN_WUNPCKIHW,
2686 ARM_BUILTIN_WUNPCKILB,
2687 ARM_BUILTIN_WUNPCKILH,
2688 ARM_BUILTIN_WUNPCKILW,
2689
2690 ARM_BUILTIN_WUNPCKEHSB,
2691 ARM_BUILTIN_WUNPCKEHSH,
2692 ARM_BUILTIN_WUNPCKEHSW,
2693 ARM_BUILTIN_WUNPCKEHUB,
2694 ARM_BUILTIN_WUNPCKEHUH,
2695 ARM_BUILTIN_WUNPCKEHUW,
2696 ARM_BUILTIN_WUNPCKELSB,
2697 ARM_BUILTIN_WUNPCKELSH,
2698 ARM_BUILTIN_WUNPCKELSW,
2699 ARM_BUILTIN_WUNPCKELUB,
2700 ARM_BUILTIN_WUNPCKELUH,
2701 ARM_BUILTIN_WUNPCKELUW,
2702
2703 ARM_BUILTIN_THREAD_POINTER,
2704
2705 ARM_BUILTIN_MAX
2706 };
2707 #endif /* ! GCC_ARM_H */
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