1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
75 static rtx
emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx
, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
81 static arm_cc
get_arm_condition_code (rtx
);
82 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
83 static rtx
is_jump_table (rtx
);
84 static const char *output_multi_immediate (rtx
*, const char *, const char *,
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_size_rtx_costs (rtx
, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
133 static int arm_address_cost (rtx
);
134 static bool arm_memory_load_p (rtx
);
135 static bool arm_cirrus_insn_p (rtx
);
136 static void cirrus_reorg (rtx
);
137 static void arm_init_builtins (void);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
141 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
142 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
143 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
144 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 static rtx
emit_set_insn (rtx
, rtx
);
146 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
149 #ifdef OBJECT_FORMAT_ELF
150 static void arm_elf_asm_constructor (rtx
, int);
153 static void arm_encode_section_info (tree
, rtx
, int);
156 static void arm_file_end (void);
159 static void aof_globalize_label (FILE *, const char *);
160 static void aof_dump_imports (FILE *);
161 static void aof_dump_pic_table (FILE *);
162 static void aof_file_start (void);
163 static void aof_file_end (void);
165 static rtx
arm_struct_value_rtx (tree
, int);
166 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
168 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
169 enum machine_mode
, tree
, bool);
170 static bool arm_promote_prototypes (tree
);
171 static bool arm_default_short_enums (void);
172 static bool arm_align_anon_bitfield (void);
173 static bool arm_return_in_msb (tree
);
174 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
175 #ifdef TARGET_UNWIND_INFO
176 static void arm_unwind_emit (FILE *, rtx
);
177 static bool arm_output_ttype (rtx
);
180 static tree
arm_cxx_guard_type (void);
181 static bool arm_cxx_guard_mask_bit (void);
182 static tree
arm_get_cookie_size (tree
);
183 static bool arm_cookie_has_size (void);
184 static bool arm_cxx_cdtor_returns_this (void);
185 static bool arm_cxx_key_method_may_be_inline (void);
186 static void arm_cxx_determine_class_data_visibility (tree
);
187 static bool arm_cxx_class_data_always_comdat (void);
188 static bool arm_cxx_use_aeabi_atexit (void);
189 static void arm_init_libfuncs (void);
190 static bool arm_handle_option (size_t, const char *, int);
191 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
192 static bool arm_cannot_copy_insn_p (rtx
);
193 static bool arm_tls_symbol_p (rtx x
);
196 /* Initialize the GCC target structure. */
197 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
198 #undef TARGET_MERGE_DECL_ATTRIBUTES
199 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
202 #undef TARGET_ATTRIBUTE_TABLE
203 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
205 #undef TARGET_ASM_FILE_END
206 #define TARGET_ASM_FILE_END arm_file_end
209 #undef TARGET_ASM_BYTE_OP
210 #define TARGET_ASM_BYTE_OP "\tDCB\t"
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
213 #undef TARGET_ASM_ALIGNED_SI_OP
214 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
215 #undef TARGET_ASM_GLOBALIZE_LABEL
216 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
217 #undef TARGET_ASM_FILE_START
218 #define TARGET_ASM_FILE_START aof_file_start
219 #undef TARGET_ASM_FILE_END
220 #define TARGET_ASM_FILE_END aof_file_end
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP NULL
224 #undef TARGET_ASM_INTEGER
225 #define TARGET_ASM_INTEGER arm_assemble_integer
228 #undef TARGET_ASM_FUNCTION_PROLOGUE
229 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
231 #undef TARGET_ASM_FUNCTION_EPILOGUE
232 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
234 #undef TARGET_DEFAULT_TARGET_FLAGS
235 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
236 #undef TARGET_HANDLE_OPTION
237 #define TARGET_HANDLE_OPTION arm_handle_option
239 #undef TARGET_COMP_TYPE_ATTRIBUTES
240 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
242 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
243 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
245 #undef TARGET_SCHED_ADJUST_COST
246 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
248 #undef TARGET_ENCODE_SECTION_INFO
250 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
252 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
255 #undef TARGET_STRIP_NAME_ENCODING
256 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
258 #undef TARGET_ASM_INTERNAL_LABEL
259 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
261 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
262 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
264 #undef TARGET_ASM_OUTPUT_MI_THUNK
265 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
266 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
267 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
269 /* This will be overridden in arm_override_options. */
270 #undef TARGET_RTX_COSTS
271 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
272 #undef TARGET_ADDRESS_COST
273 #define TARGET_ADDRESS_COST arm_address_cost
275 #undef TARGET_SHIFT_TRUNCATION_MASK
276 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
277 #undef TARGET_VECTOR_MODE_SUPPORTED_P
278 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
280 #undef TARGET_MACHINE_DEPENDENT_REORG
281 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
283 #undef TARGET_INIT_BUILTINS
284 #define TARGET_INIT_BUILTINS arm_init_builtins
285 #undef TARGET_EXPAND_BUILTIN
286 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
288 #undef TARGET_INIT_LIBFUNCS
289 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
291 #undef TARGET_PROMOTE_FUNCTION_ARGS
292 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
293 #undef TARGET_PROMOTE_FUNCTION_RETURN
294 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
295 #undef TARGET_PROMOTE_PROTOTYPES
296 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
297 #undef TARGET_PASS_BY_REFERENCE
298 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
299 #undef TARGET_ARG_PARTIAL_BYTES
300 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
302 #undef TARGET_STRUCT_VALUE_RTX
303 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
305 #undef TARGET_SETUP_INCOMING_VARARGS
306 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
308 #undef TARGET_DEFAULT_SHORT_ENUMS
309 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
311 #undef TARGET_ALIGN_ANON_BITFIELD
312 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
314 #undef TARGET_CXX_GUARD_TYPE
315 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
317 #undef TARGET_CXX_GUARD_MASK_BIT
318 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
320 #undef TARGET_CXX_GET_COOKIE_SIZE
321 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
323 #undef TARGET_CXX_COOKIE_HAS_SIZE
324 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
326 #undef TARGET_CXX_CDTOR_RETURNS_THIS
327 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
329 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
330 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
332 #undef TARGET_CXX_USE_AEABI_ATEXIT
333 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
335 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
336 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
337 arm_cxx_determine_class_data_visibility
339 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
340 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
342 #undef TARGET_RETURN_IN_MSB
343 #define TARGET_RETURN_IN_MSB arm_return_in_msb
345 #undef TARGET_MUST_PASS_IN_STACK
346 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
348 #ifdef TARGET_UNWIND_INFO
349 #undef TARGET_UNWIND_EMIT
350 #define TARGET_UNWIND_EMIT arm_unwind_emit
352 /* EABI unwinding tables use a different format for the typeinfo tables. */
353 #undef TARGET_ASM_TTYPE
354 #define TARGET_ASM_TTYPE arm_output_ttype
356 #undef TARGET_ARM_EABI_UNWINDER
357 #define TARGET_ARM_EABI_UNWINDER true
358 #endif /* TARGET_UNWIND_INFO */
360 #undef TARGET_CANNOT_COPY_INSN_P
361 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
364 #undef TARGET_HAVE_TLS
365 #define TARGET_HAVE_TLS true
368 #undef TARGET_CANNOT_FORCE_CONST_MEM
369 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
371 struct gcc_target targetm
= TARGET_INITIALIZER
;
373 /* Obstack for minipool constant handling. */
374 static struct obstack minipool_obstack
;
375 static char * minipool_startobj
;
377 /* The maximum number of insns skipped which
378 will be conditionalised if possible. */
379 static int max_insns_skipped
= 5;
381 extern FILE * asm_out_file
;
383 /* True if we are currently building a constant table. */
384 int making_const_table
;
386 /* Define the information needed to generate branch insns. This is
387 stored from the compare operation. */
388 rtx arm_compare_op0
, arm_compare_op1
;
390 /* The processor for which instructions should be scheduled. */
391 enum processor_type arm_tune
= arm_none
;
393 /* Which floating point model to use. */
394 enum arm_fp_model arm_fp_model
;
396 /* Which floating point hardware is available. */
397 enum fputype arm_fpu_arch
;
399 /* Which floating point hardware to schedule for. */
400 enum fputype arm_fpu_tune
;
402 /* Whether to use floating point hardware. */
403 enum float_abi_type arm_float_abi
;
405 /* Which ABI to use. */
406 enum arm_abi_type arm_abi
;
408 /* Which thread pointer model to use. */
409 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
411 /* Used to parse -mstructure_size_boundary command line option. */
412 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
414 /* Used for Thumb call_via trampolines. */
415 rtx thumb_call_via_label
[14];
416 static int thumb_call_reg_needed
;
418 /* Bit values used to identify processor capabilities. */
419 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
420 #define FL_ARCH3M (1 << 1) /* Extended multiply */
421 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
422 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
423 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
424 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
425 #define FL_THUMB (1 << 6) /* Thumb aware */
426 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
427 #define FL_STRONG (1 << 8) /* StrongARM */
428 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
429 #define FL_XSCALE (1 << 10) /* XScale */
430 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
431 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
432 media instructions. */
433 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
434 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
435 Note: ARM6 & 7 derivatives only. */
436 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
438 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
440 #define FL_FOR_ARCH2 0
441 #define FL_FOR_ARCH3 FL_MODE32
442 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
443 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
444 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
445 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
446 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
447 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
448 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
449 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
450 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
451 #define FL_FOR_ARCH6J FL_FOR_ARCH6
452 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
453 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
454 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
456 /* The bits in this mask specify which
457 instructions we are allowed to generate. */
458 static unsigned long insn_flags
= 0;
460 /* The bits in this mask specify which instruction scheduling options should
462 static unsigned long tune_flags
= 0;
464 /* The following are used in the arm.md file as equivalents to bits
465 in the above two flag variables. */
467 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
470 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
473 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
476 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
479 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
482 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
485 /* Nonzero if this chip supports the ARM 6K extensions. */
488 /* Nonzero if this chip can benefit from load scheduling. */
489 int arm_ld_sched
= 0;
491 /* Nonzero if this chip is a StrongARM. */
492 int arm_tune_strongarm
= 0;
494 /* Nonzero if this chip is a Cirrus variant. */
495 int arm_arch_cirrus
= 0;
497 /* Nonzero if this chip supports Intel Wireless MMX technology. */
498 int arm_arch_iwmmxt
= 0;
500 /* Nonzero if this chip is an XScale. */
501 int arm_arch_xscale
= 0;
503 /* Nonzero if tuning for XScale */
504 int arm_tune_xscale
= 0;
506 /* Nonzero if we want to tune for stores that access the write-buffer.
507 This typically means an ARM6 or ARM7 with MMU or MPU. */
508 int arm_tune_wbuf
= 0;
510 /* Nonzero if generating Thumb instructions. */
513 /* Nonzero if we should define __THUMB_INTERWORK__ in the
515 XXX This is a bit of a hack, it's intended to help work around
516 problems in GLD which doesn't understand that armv5t code is
517 interworking clean. */
518 int arm_cpp_interwork
= 0;
520 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
521 must report the mode of the memory reference from PRINT_OPERAND to
522 PRINT_OPERAND_ADDRESS. */
523 enum machine_mode output_memory_reference_mode
;
525 /* The register number to be used for the PIC offset register. */
526 int arm_pic_register
= INVALID_REGNUM
;
528 /* Set to 1 when a return insn is output, this means that the epilogue
530 int return_used_this_function
;
532 /* Set to 1 after arm_reorg has started. Reset to start at the start of
533 the next function. */
534 static int after_arm_reorg
= 0;
536 /* The maximum number of insns to be used when loading a constant. */
537 static int arm_constant_limit
= 3;
539 /* For an explanation of these variables, see final_prescan_insn below. */
541 enum arm_cond_code arm_current_cc
;
543 int arm_target_label
;
545 /* The condition codes of the ARM, and the inverse function. */
546 static const char * const arm_condition_codes
[] =
548 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
549 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
552 #define streq(string1, string2) (strcmp (string1, string2) == 0)
554 /* Initialization code. */
558 const char *const name
;
559 enum processor_type core
;
561 const unsigned long flags
;
562 bool (* rtx_costs
) (rtx
, int, int, int *);
565 /* Not all of these give usefully different compilation alternatives,
566 but there is no simple way of generalizing them. */
567 static const struct processors all_cores
[] =
570 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
571 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
572 #include "arm-cores.def"
574 {NULL
, arm_none
, NULL
, 0, NULL
}
577 static const struct processors all_architectures
[] =
579 /* ARM Architectures */
580 /* We don't specify rtx_costs here as it will be figured out
583 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
584 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
585 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
586 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
587 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
588 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
589 implementations that support it, so we will leave it out for now. */
590 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
591 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
592 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
593 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
594 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
595 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
596 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
597 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
598 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
599 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
600 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
601 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
602 {NULL
, arm_none
, NULL
, 0 , NULL
}
605 struct arm_cpu_select
609 const struct processors
* processors
;
612 /* This is a magic structure. The 'string' field is magically filled in
613 with a pointer to the value specified by the user on the command line
614 assuming that the user has specified such a value. */
616 static struct arm_cpu_select arm_select
[] =
618 /* string name processors */
619 { NULL
, "-mcpu=", all_cores
},
620 { NULL
, "-march=", all_architectures
},
621 { NULL
, "-mtune=", all_cores
}
624 /* Defines representing the indexes into the above table. */
625 #define ARM_OPT_SET_CPU 0
626 #define ARM_OPT_SET_ARCH 1
627 #define ARM_OPT_SET_TUNE 2
629 /* The name of the proprocessor macro to define for this architecture. */
631 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
640 /* Available values for for -mfpu=. */
642 static const struct fpu_desc all_fpus
[] =
644 {"fpa", FPUTYPE_FPA
},
645 {"fpe2", FPUTYPE_FPA_EMU2
},
646 {"fpe3", FPUTYPE_FPA_EMU2
},
647 {"maverick", FPUTYPE_MAVERICK
},
652 /* Floating point models used by the different hardware.
653 See fputype in arm.h. */
655 static const enum fputype fp_model_for_fpu
[] =
657 /* No FP hardware. */
658 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
659 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
660 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
661 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
662 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
663 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
670 enum float_abi_type abi_type
;
674 /* Available values for -mfloat-abi=. */
676 static const struct float_abi all_float_abis
[] =
678 {"soft", ARM_FLOAT_ABI_SOFT
},
679 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
680 {"hard", ARM_FLOAT_ABI_HARD
}
687 enum arm_abi_type abi_type
;
691 /* Available values for -mabi=. */
693 static const struct abi_name arm_all_abis
[] =
695 {"apcs-gnu", ARM_ABI_APCS
},
696 {"atpcs", ARM_ABI_ATPCS
},
697 {"aapcs", ARM_ABI_AAPCS
},
698 {"iwmmxt", ARM_ABI_IWMMXT
},
699 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
702 /* Supported TLS relocations. */
712 /* Emit an insn that's a simple single-set. Both the operands must be known
715 emit_set_insn (rtx x
, rtx y
)
717 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
720 /* Return the number of bits set in VALUE. */
722 bit_count (unsigned long value
)
724 unsigned long count
= 0;
729 value
&= value
- 1; /* Clear the least-significant set bit. */
735 /* Set up library functions unique to ARM. */
738 arm_init_libfuncs (void)
740 /* There are no special library functions unless we are using the
745 /* The functions below are described in Section 4 of the "Run-Time
746 ABI for the ARM architecture", Version 1.0. */
748 /* Double-precision floating-point arithmetic. Table 2. */
749 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
750 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
751 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
752 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
753 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
755 /* Double-precision comparisons. Table 3. */
756 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
757 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
758 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
759 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
760 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
761 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
762 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
764 /* Single-precision floating-point arithmetic. Table 4. */
765 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
766 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
767 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
768 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
769 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
771 /* Single-precision comparisons. Table 5. */
772 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
773 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
774 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
775 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
776 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
777 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
778 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
780 /* Floating-point to integer conversions. Table 6. */
781 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
782 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
783 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
784 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
785 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
786 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
787 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
788 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
790 /* Conversions between floating types. Table 7. */
791 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
792 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
794 /* Integer to floating-point conversions. Table 8. */
795 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
796 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
797 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
798 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
799 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
800 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
801 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
802 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
804 /* Long long. Table 9. */
805 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
806 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
807 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
808 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
809 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
810 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
811 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
812 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
814 /* Integer (32/32->32) division. \S 4.3.1. */
815 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
816 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
818 /* The divmod functions are designed so that they can be used for
819 plain division, even though they return both the quotient and the
820 remainder. The quotient is returned in the usual location (i.e.,
821 r0 for SImode, {r0, r1} for DImode), just as would be expected
822 for an ordinary division routine. Because the AAPCS calling
823 conventions specify that all of { r0, r1, r2, r3 } are
824 callee-saved registers, there is no need to tell the compiler
825 explicitly that those registers are clobbered by these
827 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
828 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
830 /* For SImode division the ABI provides div-without-mod routines,
832 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
833 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
835 /* We don't have mod libcalls. Fortunately gcc knows how to use the
836 divmod libcalls instead. */
837 set_optab_libfunc (smod_optab
, DImode
, NULL
);
838 set_optab_libfunc (umod_optab
, DImode
, NULL
);
839 set_optab_libfunc (smod_optab
, SImode
, NULL
);
840 set_optab_libfunc (umod_optab
, SImode
, NULL
);
843 /* Implement TARGET_HANDLE_OPTION. */
846 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
851 arm_select
[1].string
= arg
;
855 arm_select
[0].string
= arg
;
858 case OPT_mhard_float
:
859 target_float_abi_name
= "hard";
862 case OPT_msoft_float
:
863 target_float_abi_name
= "soft";
867 arm_select
[2].string
= arg
;
875 /* Fix up any incompatible options that the user has specified.
876 This has now turned into a maze. */
878 arm_override_options (void)
881 enum processor_type target_arch_cpu
= arm_none
;
883 /* Set up the flags based on the cpu/architecture selected by the user. */
884 for (i
= ARRAY_SIZE (arm_select
); i
--;)
886 struct arm_cpu_select
* ptr
= arm_select
+ i
;
888 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
890 const struct processors
* sel
;
892 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
893 if (streq (ptr
->string
, sel
->name
))
895 /* Set the architecture define. */
896 if (i
!= ARM_OPT_SET_TUNE
)
897 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
899 /* Determine the processor core for which we should
900 tune code-generation. */
901 if (/* -mcpu= is a sensible default. */
903 /* -mtune= overrides -mcpu= and -march=. */
904 || i
== ARM_OPT_SET_TUNE
)
905 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
907 /* Remember the CPU associated with this architecture.
908 If no other option is used to set the CPU type,
909 we'll use this to guess the most suitable tuning
911 if (i
== ARM_OPT_SET_ARCH
)
912 target_arch_cpu
= sel
->core
;
914 if (i
!= ARM_OPT_SET_TUNE
)
916 /* If we have been given an architecture and a processor
917 make sure that they are compatible. We only generate
918 a warning though, and we prefer the CPU over the
920 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
921 warning (0, "switch -mcpu=%s conflicts with -march= switch",
924 insn_flags
= sel
->flags
;
930 if (sel
->name
== NULL
)
931 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
935 /* Guess the tuning options from the architecture if necessary. */
936 if (arm_tune
== arm_none
)
937 arm_tune
= target_arch_cpu
;
939 /* If the user did not specify a processor, choose one for them. */
942 const struct processors
* sel
;
944 enum processor_type cpu
;
946 cpu
= TARGET_CPU_DEFAULT
;
949 #ifdef SUBTARGET_CPU_DEFAULT
950 /* Use the subtarget default CPU if none was specified by
952 cpu
= SUBTARGET_CPU_DEFAULT
;
954 /* Default to ARM6. */
958 sel
= &all_cores
[cpu
];
960 insn_flags
= sel
->flags
;
962 /* Now check to see if the user has specified some command line
963 switch that require certain abilities from the cpu. */
966 if (TARGET_INTERWORK
|| TARGET_THUMB
)
968 sought
|= (FL_THUMB
| FL_MODE32
);
970 /* There are no ARM processors that support both APCS-26 and
971 interworking. Therefore we force FL_MODE26 to be removed
972 from insn_flags here (if it was set), so that the search
973 below will always be able to find a compatible processor. */
974 insn_flags
&= ~FL_MODE26
;
977 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
979 /* Try to locate a CPU type that supports all of the abilities
980 of the default CPU, plus the extra abilities requested by
982 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
983 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
986 if (sel
->name
== NULL
)
988 unsigned current_bit_count
= 0;
989 const struct processors
* best_fit
= NULL
;
991 /* Ideally we would like to issue an error message here
992 saying that it was not possible to find a CPU compatible
993 with the default CPU, but which also supports the command
994 line options specified by the programmer, and so they
995 ought to use the -mcpu=<name> command line option to
996 override the default CPU type.
998 If we cannot find a cpu that has both the
999 characteristics of the default cpu and the given
1000 command line options we scan the array again looking
1001 for a best match. */
1002 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1003 if ((sel
->flags
& sought
) == sought
)
1007 count
= bit_count (sel
->flags
& insn_flags
);
1009 if (count
>= current_bit_count
)
1012 current_bit_count
= count
;
1016 gcc_assert (best_fit
);
1020 insn_flags
= sel
->flags
;
1022 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1023 if (arm_tune
== arm_none
)
1024 arm_tune
= (enum processor_type
) (sel
- all_cores
);
1027 /* The processor for which we should tune should now have been
1029 gcc_assert (arm_tune
!= arm_none
);
1031 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1033 targetm
.rtx_costs
= arm_size_rtx_costs
;
1035 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1037 /* Make sure that the processor choice does not conflict with any of the
1038 other command line choices. */
1039 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1041 warning (0, "target CPU does not support interworking" );
1042 target_flags
&= ~MASK_INTERWORK
;
1045 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1047 warning (0, "target CPU does not support THUMB instructions");
1048 target_flags
&= ~MASK_THUMB
;
1051 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1053 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1054 target_flags
&= ~MASK_APCS_FRAME
;
1057 /* Callee super interworking implies thumb interworking. Adding
1058 this to the flags here simplifies the logic elsewhere. */
1059 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1060 target_flags
|= MASK_INTERWORK
;
1062 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1063 from here where no function is being compiled currently. */
1064 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1065 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1067 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1068 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1070 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1071 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1073 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1075 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1076 target_flags
|= MASK_APCS_FRAME
;
1079 if (TARGET_POKE_FUNCTION_NAME
)
1080 target_flags
|= MASK_APCS_FRAME
;
1082 if (TARGET_APCS_REENT
&& flag_pic
)
1083 error ("-fpic and -mapcs-reent are incompatible");
1085 if (TARGET_APCS_REENT
)
1086 warning (0, "APCS reentrant code not supported. Ignored");
1088 /* If this target is normally configured to use APCS frames, warn if they
1089 are turned off and debugging is turned on. */
1091 && write_symbols
!= NO_DEBUG
1092 && !TARGET_APCS_FRAME
1093 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1094 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1096 /* If stack checking is disabled, we can use r10 as the PIC register,
1097 which keeps r9 available. */
1099 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
1101 if (TARGET_APCS_FLOAT
)
1102 warning (0, "passing floating point arguments in fp regs not yet supported");
1104 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1105 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1106 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1107 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1108 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1109 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1110 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1111 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1112 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1113 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1115 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1116 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1117 thumb_code
= (TARGET_ARM
== 0);
1118 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1119 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1120 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1122 /* V5 code we generate is completely interworking capable, so we turn off
1123 TARGET_INTERWORK here to avoid many tests later on. */
1125 /* XXX However, we must pass the right pre-processor defines to CPP
1126 or GLD can get confused. This is a hack. */
1127 if (TARGET_INTERWORK
)
1128 arm_cpp_interwork
= 1;
1131 target_flags
&= ~MASK_INTERWORK
;
1133 if (target_abi_name
)
1135 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1137 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1139 arm_abi
= arm_all_abis
[i
].abi_type
;
1143 if (i
== ARRAY_SIZE (arm_all_abis
))
1144 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1147 arm_abi
= ARM_DEFAULT_ABI
;
1149 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1150 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1152 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1153 error ("iwmmxt abi requires an iwmmxt capable cpu");
1155 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1156 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1158 if (streq (target_fpe_name
, "2"))
1159 target_fpu_name
= "fpe2";
1160 else if (streq (target_fpe_name
, "3"))
1161 target_fpu_name
= "fpe3";
1163 error ("invalid floating point emulation option: -mfpe=%s",
1166 if (target_fpu_name
!= NULL
)
1168 /* The user specified a FPU. */
1169 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1171 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1173 arm_fpu_arch
= all_fpus
[i
].fpu
;
1174 arm_fpu_tune
= arm_fpu_arch
;
1175 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1179 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1180 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1184 #ifdef FPUTYPE_DEFAULT
1185 /* Use the default if it is specified for this platform. */
1186 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1187 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1189 /* Pick one based on CPU type. */
1190 /* ??? Some targets assume FPA is the default.
1191 if ((insn_flags & FL_VFP) != 0)
1192 arm_fpu_arch = FPUTYPE_VFP;
1195 if (arm_arch_cirrus
)
1196 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1198 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1200 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1201 arm_fpu_tune
= FPUTYPE_FPA
;
1203 arm_fpu_tune
= arm_fpu_arch
;
1204 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1205 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1208 if (target_float_abi_name
!= NULL
)
1210 /* The user specified a FP ABI. */
1211 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1213 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1215 arm_float_abi
= all_float_abis
[i
].abi_type
;
1219 if (i
== ARRAY_SIZE (all_float_abis
))
1220 error ("invalid floating point abi: -mfloat-abi=%s",
1221 target_float_abi_name
);
1224 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1226 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1227 sorry ("-mfloat-abi=hard and VFP");
1229 /* If soft-float is specified then don't use FPU. */
1230 if (TARGET_SOFT_FLOAT
)
1231 arm_fpu_arch
= FPUTYPE_NONE
;
1233 /* For arm2/3 there is no need to do any scheduling if there is only
1234 a floating point emulator, or we are doing software floating-point. */
1235 if ((TARGET_SOFT_FLOAT
1236 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1237 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1238 && (tune_flags
& FL_MODE32
) == 0)
1239 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1241 if (target_thread_switch
)
1243 if (strcmp (target_thread_switch
, "soft") == 0)
1244 target_thread_pointer
= TP_SOFT
;
1245 else if (strcmp (target_thread_switch
, "auto") == 0)
1246 target_thread_pointer
= TP_AUTO
;
1247 else if (strcmp (target_thread_switch
, "cp15") == 0)
1248 target_thread_pointer
= TP_CP15
;
1250 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1253 /* Use the cp15 method if it is available. */
1254 if (target_thread_pointer
== TP_AUTO
)
1256 if (arm_arch6k
&& !TARGET_THUMB
)
1257 target_thread_pointer
= TP_CP15
;
1259 target_thread_pointer
= TP_SOFT
;
1262 if (TARGET_HARD_TP
&& TARGET_THUMB
)
1263 error ("can not use -mtp=cp15 with -mthumb");
1265 /* Override the default structure alignment for AAPCS ABI. */
1266 if (TARGET_AAPCS_BASED
)
1267 arm_structure_size_boundary
= 8;
1269 if (structure_size_string
!= NULL
)
1271 int size
= strtol (structure_size_string
, NULL
, 0);
1273 if (size
== 8 || size
== 32
1274 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1275 arm_structure_size_boundary
= size
;
1277 warning (0, "structure size boundary can only be set to %s",
1278 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1281 if (arm_pic_register_string
!= NULL
)
1283 int pic_register
= decode_reg_name (arm_pic_register_string
);
1286 warning (0, "-mpic-register= is useless without -fpic");
1288 /* Prevent the user from choosing an obviously stupid PIC register. */
1289 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1290 || pic_register
== HARD_FRAME_POINTER_REGNUM
1291 || pic_register
== STACK_POINTER_REGNUM
1292 || pic_register
>= PC_REGNUM
)
1293 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1295 arm_pic_register
= pic_register
;
1298 if (TARGET_THUMB
&& flag_schedule_insns
)
1300 /* Don't warn since it's on by default in -O2. */
1301 flag_schedule_insns
= 0;
1306 arm_constant_limit
= 1;
1308 /* If optimizing for size, bump the number of instructions that we
1309 are prepared to conditionally execute (even on a StrongARM). */
1310 max_insns_skipped
= 6;
1314 /* For processors with load scheduling, it never costs more than
1315 2 cycles to load a constant, and the load scheduler may well
1316 reduce that to 1. */
1318 arm_constant_limit
= 1;
1320 /* On XScale the longer latency of a load makes it more difficult
1321 to achieve a good schedule, so it's faster to synthesize
1322 constants that can be done in two insns. */
1323 if (arm_tune_xscale
)
1324 arm_constant_limit
= 2;
1326 /* StrongARM has early execution of branches, so a sequence
1327 that is worth skipping is shorter. */
1328 if (arm_tune_strongarm
)
1329 max_insns_skipped
= 3;
1332 /* Register global variables with the garbage collector. */
1333 arm_add_gc_roots ();
1337 arm_add_gc_roots (void)
1339 gcc_obstack_init(&minipool_obstack
);
1340 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1343 /* A table of known ARM exception types.
1344 For use with the interrupt function attribute. */
1348 const char *const arg
;
1349 const unsigned long return_value
;
1353 static const isr_attribute_arg isr_attribute_args
[] =
1355 { "IRQ", ARM_FT_ISR
},
1356 { "irq", ARM_FT_ISR
},
1357 { "FIQ", ARM_FT_FIQ
},
1358 { "fiq", ARM_FT_FIQ
},
1359 { "ABORT", ARM_FT_ISR
},
1360 { "abort", ARM_FT_ISR
},
1361 { "ABORT", ARM_FT_ISR
},
1362 { "abort", ARM_FT_ISR
},
1363 { "UNDEF", ARM_FT_EXCEPTION
},
1364 { "undef", ARM_FT_EXCEPTION
},
1365 { "SWI", ARM_FT_EXCEPTION
},
1366 { "swi", ARM_FT_EXCEPTION
},
1367 { NULL
, ARM_FT_NORMAL
}
1370 /* Returns the (interrupt) function type of the current
1371 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1373 static unsigned long
1374 arm_isr_value (tree argument
)
1376 const isr_attribute_arg
* ptr
;
1379 /* No argument - default to IRQ. */
1380 if (argument
== NULL_TREE
)
1383 /* Get the value of the argument. */
1384 if (TREE_VALUE (argument
) == NULL_TREE
1385 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1386 return ARM_FT_UNKNOWN
;
1388 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1390 /* Check it against the list of known arguments. */
1391 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1392 if (streq (arg
, ptr
->arg
))
1393 return ptr
->return_value
;
1395 /* An unrecognized interrupt type. */
1396 return ARM_FT_UNKNOWN
;
1399 /* Computes the type of the current function. */
1401 static unsigned long
1402 arm_compute_func_type (void)
1404 unsigned long type
= ARM_FT_UNKNOWN
;
1408 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1410 /* Decide if the current function is volatile. Such functions
1411 never return, and many memory cycles can be saved by not storing
1412 register values that will never be needed again. This optimization
1413 was added to speed up context switching in a kernel application. */
1415 && TREE_NOTHROW (current_function_decl
)
1416 && TREE_THIS_VOLATILE (current_function_decl
))
1417 type
|= ARM_FT_VOLATILE
;
1419 if (cfun
->static_chain_decl
!= NULL
)
1420 type
|= ARM_FT_NESTED
;
1422 attr
= DECL_ATTRIBUTES (current_function_decl
);
1424 a
= lookup_attribute ("naked", attr
);
1426 type
|= ARM_FT_NAKED
;
1428 a
= lookup_attribute ("isr", attr
);
1430 a
= lookup_attribute ("interrupt", attr
);
1433 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1435 type
|= arm_isr_value (TREE_VALUE (a
));
1440 /* Returns the type of the current function. */
1443 arm_current_func_type (void)
1445 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1446 cfun
->machine
->func_type
= arm_compute_func_type ();
1448 return cfun
->machine
->func_type
;
1451 /* Return 1 if it is possible to return using a single instruction.
1452 If SIBLING is non-null, this is a test for a return before a sibling
1453 call. SIBLING is the call insn, so we can examine its register usage. */
1456 use_return_insn (int iscond
, rtx sibling
)
1459 unsigned int func_type
;
1460 unsigned long saved_int_regs
;
1461 unsigned HOST_WIDE_INT stack_adjust
;
1462 arm_stack_offsets
*offsets
;
1464 /* Never use a return instruction before reload has run. */
1465 if (!reload_completed
)
1468 func_type
= arm_current_func_type ();
1470 /* Naked functions and volatile functions need special
1472 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1475 /* So do interrupt functions that use the frame pointer. */
1476 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1479 offsets
= arm_get_frame_offsets ();
1480 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1482 /* As do variadic functions. */
1483 if (current_function_pretend_args_size
1484 || cfun
->machine
->uses_anonymous_args
1485 /* Or if the function calls __builtin_eh_return () */
1486 || current_function_calls_eh_return
1487 /* Or if the function calls alloca */
1488 || current_function_calls_alloca
1489 /* Or if there is a stack adjustment. However, if the stack pointer
1490 is saved on the stack, we can use a pre-incrementing stack load. */
1491 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1494 saved_int_regs
= arm_compute_save_reg_mask ();
1496 /* Unfortunately, the insn
1498 ldmib sp, {..., sp, ...}
1500 triggers a bug on most SA-110 based devices, such that the stack
1501 pointer won't be correctly restored if the instruction takes a
1502 page fault. We work around this problem by popping r3 along with
1503 the other registers, since that is never slower than executing
1504 another instruction.
1506 We test for !arm_arch5 here, because code for any architecture
1507 less than this could potentially be run on one of the buggy
1509 if (stack_adjust
== 4 && !arm_arch5
)
1511 /* Validate that r3 is a call-clobbered register (always true in
1512 the default abi) ... */
1513 if (!call_used_regs
[3])
1516 /* ... that it isn't being used for a return value ... */
1517 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1520 /* ... or for a tail-call argument ... */
1523 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1525 if (find_regno_fusage (sibling
, USE
, 3))
1529 /* ... and that there are no call-saved registers in r0-r2
1530 (always true in the default ABI). */
1531 if (saved_int_regs
& 0x7)
1535 /* Can't be done if interworking with Thumb, and any registers have been
1537 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1540 /* On StrongARM, conditional returns are expensive if they aren't
1541 taken and multiple registers have been stacked. */
1542 if (iscond
&& arm_tune_strongarm
)
1544 /* Conditional return when just the LR is stored is a simple
1545 conditional-load instruction, that's not expensive. */
1546 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1549 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1553 /* If there are saved registers but the LR isn't saved, then we need
1554 two instructions for the return. */
1555 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1558 /* Can't be done if any of the FPA regs are pushed,
1559 since this also requires an insn. */
1560 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1561 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1562 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1565 /* Likewise VFP regs. */
1566 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1567 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1568 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1571 if (TARGET_REALLY_IWMMXT
)
1572 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1573 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1579 /* Return TRUE if int I is a valid immediate ARM constant. */
1582 const_ok_for_arm (HOST_WIDE_INT i
)
1586 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1587 be all zero, or all one. */
1588 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1589 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1590 != ((~(unsigned HOST_WIDE_INT
) 0)
1591 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1594 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1596 /* Fast return for 0 and small values. We must do this for zero, since
1597 the code below can't handle that one case. */
1598 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1601 /* Get the number of trailing zeros, rounded down to the nearest even
1603 lowbit
= (ffs ((int) i
) - 1) & ~1;
1605 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1607 else if (lowbit
<= 4
1608 && ((i
& ~0xc000003f) == 0
1609 || (i
& ~0xf000000f) == 0
1610 || (i
& ~0xfc000003) == 0))
1616 /* Return true if I is a valid constant for the operation CODE. */
1618 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1620 if (const_ok_for_arm (i
))
1626 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1628 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1634 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1641 /* Emit a sequence of insns to handle a large constant.
1642 CODE is the code of the operation required, it can be any of SET, PLUS,
1643 IOR, AND, XOR, MINUS;
1644 MODE is the mode in which the operation is being performed;
1645 VAL is the integer to operate on;
1646 SOURCE is the other operand (a register, or a null-pointer for SET);
1647 SUBTARGETS means it is safe to create scratch registers if that will
1648 either produce a simpler sequence, or we will want to cse the values.
1649 Return value is the number of insns emitted. */
1652 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1653 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1657 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1658 cond
= COND_EXEC_TEST (PATTERN (insn
));
1662 if (subtargets
|| code
== SET
1663 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1664 && REGNO (target
) != REGNO (source
)))
1666 /* After arm_reorg has been called, we can't fix up expensive
1667 constants by pushing them into memory so we must synthesize
1668 them in-line, regardless of the cost. This is only likely to
1669 be more costly on chips that have load delay slots and we are
1670 compiling without running the scheduler (so no splitting
1671 occurred before the final instruction emission).
1673 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1675 if (!after_arm_reorg
1677 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1679 > arm_constant_limit
+ (code
!= SET
)))
1683 /* Currently SET is the only monadic value for CODE, all
1684 the rest are diadic. */
1685 emit_set_insn (target
, GEN_INT (val
));
1690 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1692 emit_set_insn (temp
, GEN_INT (val
));
1693 /* For MINUS, the value is subtracted from, since we never
1694 have subtraction of a constant. */
1696 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
1698 emit_set_insn (target
,
1699 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
1705 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1710 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1712 HOST_WIDE_INT temp1
;
1720 if (remainder
& (3 << (i
- 2)))
1725 temp1
= remainder
& ((0x0ff << end
)
1726 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1727 remainder
&= ~temp1
;
1732 } while (remainder
);
1736 /* Emit an instruction with the indicated PATTERN. If COND is
1737 non-NULL, conditionalize the execution of the instruction on COND
1741 emit_constant_insn (rtx cond
, rtx pattern
)
1744 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1745 emit_insn (pattern
);
1748 /* As above, but extra parameter GENERATE which, if clear, suppresses
1752 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1753 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1758 int can_negate_initial
= 0;
1761 int num_bits_set
= 0;
1762 int set_sign_bit_copies
= 0;
1763 int clear_sign_bit_copies
= 0;
1764 int clear_zero_bit_copies
= 0;
1765 int set_zero_bit_copies
= 0;
1767 unsigned HOST_WIDE_INT temp1
, temp2
;
1768 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1770 /* Find out which operations are safe for a given CODE. Also do a quick
1771 check for degenerate cases; these can occur when DImode operations
1783 can_negate_initial
= 1;
1787 if (remainder
== 0xffffffff)
1790 emit_constant_insn (cond
,
1791 gen_rtx_SET (VOIDmode
, target
,
1792 GEN_INT (ARM_SIGN_EXTEND (val
))));
1797 if (reload_completed
&& rtx_equal_p (target
, source
))
1800 emit_constant_insn (cond
,
1801 gen_rtx_SET (VOIDmode
, target
, source
));
1810 emit_constant_insn (cond
,
1811 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1814 if (remainder
== 0xffffffff)
1816 if (reload_completed
&& rtx_equal_p (target
, source
))
1819 emit_constant_insn (cond
,
1820 gen_rtx_SET (VOIDmode
, target
, source
));
1829 if (reload_completed
&& rtx_equal_p (target
, source
))
1832 emit_constant_insn (cond
,
1833 gen_rtx_SET (VOIDmode
, target
, source
));
1837 /* We don't know how to handle other cases yet. */
1838 gcc_assert (remainder
== 0xffffffff);
1841 emit_constant_insn (cond
,
1842 gen_rtx_SET (VOIDmode
, target
,
1843 gen_rtx_NOT (mode
, source
)));
1847 /* We treat MINUS as (val - source), since (source - val) is always
1848 passed as (source + (-val)). */
1852 emit_constant_insn (cond
,
1853 gen_rtx_SET (VOIDmode
, target
,
1854 gen_rtx_NEG (mode
, source
)));
1857 if (const_ok_for_arm (val
))
1860 emit_constant_insn (cond
,
1861 gen_rtx_SET (VOIDmode
, target
,
1862 gen_rtx_MINUS (mode
, GEN_INT (val
),
1874 /* If we can do it in one insn get out quickly. */
1875 if (const_ok_for_arm (val
)
1876 || (can_negate_initial
&& const_ok_for_arm (-val
))
1877 || (can_invert
&& const_ok_for_arm (~val
)))
1880 emit_constant_insn (cond
,
1881 gen_rtx_SET (VOIDmode
, target
,
1883 ? gen_rtx_fmt_ee (code
, mode
, source
,
1889 /* Calculate a few attributes that may be useful for specific
1891 for (i
= 31; i
>= 0; i
--)
1893 if ((remainder
& (1 << i
)) == 0)
1894 clear_sign_bit_copies
++;
1899 for (i
= 31; i
>= 0; i
--)
1901 if ((remainder
& (1 << i
)) != 0)
1902 set_sign_bit_copies
++;
1907 for (i
= 0; i
<= 31; i
++)
1909 if ((remainder
& (1 << i
)) == 0)
1910 clear_zero_bit_copies
++;
1915 for (i
= 0; i
<= 31; i
++)
1917 if ((remainder
& (1 << i
)) != 0)
1918 set_zero_bit_copies
++;
1926 /* See if we can do this by sign_extending a constant that is known
1927 to be negative. This is a good, way of doing it, since the shift
1928 may well merge into a subsequent insn. */
1929 if (set_sign_bit_copies
> 1)
1931 if (const_ok_for_arm
1932 (temp1
= ARM_SIGN_EXTEND (remainder
1933 << (set_sign_bit_copies
- 1))))
1937 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1938 emit_constant_insn (cond
,
1939 gen_rtx_SET (VOIDmode
, new_src
,
1941 emit_constant_insn (cond
,
1942 gen_ashrsi3 (target
, new_src
,
1943 GEN_INT (set_sign_bit_copies
- 1)));
1947 /* For an inverted constant, we will need to set the low bits,
1948 these will be shifted out of harm's way. */
1949 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1950 if (const_ok_for_arm (~temp1
))
1954 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1955 emit_constant_insn (cond
,
1956 gen_rtx_SET (VOIDmode
, new_src
,
1958 emit_constant_insn (cond
,
1959 gen_ashrsi3 (target
, new_src
,
1960 GEN_INT (set_sign_bit_copies
- 1)));
1966 /* See if we can calculate the value as the difference between two
1967 valid immediates. */
1968 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
1970 int topshift
= clear_sign_bit_copies
& ~1;
1972 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
1973 & (0xff000000 >> topshift
));
1975 /* If temp1 is zero, then that means the 9 most significant
1976 bits of remainder were 1 and we've caused it to overflow.
1977 When topshift is 0 we don't need to do anything since we
1978 can borrow from 'bit 32'. */
1979 if (temp1
== 0 && topshift
!= 0)
1980 temp1
= 0x80000000 >> (topshift
- 1);
1982 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
1984 if (const_ok_for_arm (temp2
))
1988 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1989 emit_constant_insn (cond
,
1990 gen_rtx_SET (VOIDmode
, new_src
,
1992 emit_constant_insn (cond
,
1993 gen_addsi3 (target
, new_src
,
2001 /* See if we can generate this by setting the bottom (or the top)
2002 16 bits, and then shifting these into the other half of the
2003 word. We only look for the simplest cases, to do more would cost
2004 too much. Be careful, however, not to generate this when the
2005 alternative would take fewer insns. */
2006 if (val
& 0xffff0000)
2008 temp1
= remainder
& 0xffff0000;
2009 temp2
= remainder
& 0x0000ffff;
2011 /* Overlaps outside this range are best done using other methods. */
2012 for (i
= 9; i
< 24; i
++)
2014 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2015 && !const_ok_for_arm (temp2
))
2017 rtx new_src
= (subtargets
2018 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2020 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2021 source
, subtargets
, generate
);
2029 gen_rtx_ASHIFT (mode
, source
,
2036 /* Don't duplicate cases already considered. */
2037 for (i
= 17; i
< 24; i
++)
2039 if (((temp1
| (temp1
>> i
)) == remainder
)
2040 && !const_ok_for_arm (temp1
))
2042 rtx new_src
= (subtargets
2043 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2045 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2046 source
, subtargets
, generate
);
2051 gen_rtx_SET (VOIDmode
, target
,
2054 gen_rtx_LSHIFTRT (mode
, source
,
2065 /* If we have IOR or XOR, and the constant can be loaded in a
2066 single instruction, and we can find a temporary to put it in,
2067 then this can be done in two instructions instead of 3-4. */
2069 /* TARGET can't be NULL if SUBTARGETS is 0 */
2070 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2072 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2076 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2078 emit_constant_insn (cond
,
2079 gen_rtx_SET (VOIDmode
, sub
,
2081 emit_constant_insn (cond
,
2082 gen_rtx_SET (VOIDmode
, target
,
2083 gen_rtx_fmt_ee (code
, mode
,
2093 if (set_sign_bit_copies
> 8
2094 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2098 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2099 rtx shift
= GEN_INT (set_sign_bit_copies
);
2103 gen_rtx_SET (VOIDmode
, sub
,
2105 gen_rtx_ASHIFT (mode
,
2110 gen_rtx_SET (VOIDmode
, target
,
2112 gen_rtx_LSHIFTRT (mode
, sub
,
2118 if (set_zero_bit_copies
> 8
2119 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2123 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2124 rtx shift
= GEN_INT (set_zero_bit_copies
);
2128 gen_rtx_SET (VOIDmode
, sub
,
2130 gen_rtx_LSHIFTRT (mode
,
2135 gen_rtx_SET (VOIDmode
, target
,
2137 gen_rtx_ASHIFT (mode
, sub
,
2143 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2147 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2148 emit_constant_insn (cond
,
2149 gen_rtx_SET (VOIDmode
, sub
,
2150 gen_rtx_NOT (mode
, source
)));
2153 sub
= gen_reg_rtx (mode
);
2154 emit_constant_insn (cond
,
2155 gen_rtx_SET (VOIDmode
, sub
,
2156 gen_rtx_AND (mode
, source
,
2158 emit_constant_insn (cond
,
2159 gen_rtx_SET (VOIDmode
, target
,
2160 gen_rtx_NOT (mode
, sub
)));
2167 /* See if two shifts will do 2 or more insn's worth of work. */
2168 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2170 HOST_WIDE_INT shift_mask
= ((0xffffffff
2171 << (32 - clear_sign_bit_copies
))
2174 if ((remainder
| shift_mask
) != 0xffffffff)
2178 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2179 insns
= arm_gen_constant (AND
, mode
, cond
,
2180 remainder
| shift_mask
,
2181 new_src
, source
, subtargets
, 1);
2186 rtx targ
= subtargets
? NULL_RTX
: target
;
2187 insns
= arm_gen_constant (AND
, mode
, cond
,
2188 remainder
| shift_mask
,
2189 targ
, source
, subtargets
, 0);
2195 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2196 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2198 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2199 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2205 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2207 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2209 if ((remainder
| shift_mask
) != 0xffffffff)
2213 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2215 insns
= arm_gen_constant (AND
, mode
, cond
,
2216 remainder
| shift_mask
,
2217 new_src
, source
, subtargets
, 1);
2222 rtx targ
= subtargets
? NULL_RTX
: target
;
2224 insns
= arm_gen_constant (AND
, mode
, cond
,
2225 remainder
| shift_mask
,
2226 targ
, source
, subtargets
, 0);
2232 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2233 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2235 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2236 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2248 for (i
= 0; i
< 32; i
++)
2249 if (remainder
& (1 << i
))
2252 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2253 remainder
= (~remainder
) & 0xffffffff;
2254 else if (code
== PLUS
&& num_bits_set
> 16)
2255 remainder
= (-remainder
) & 0xffffffff;
2262 /* Now try and find a way of doing the job in either two or three
2264 We start by looking for the largest block of zeros that are aligned on
2265 a 2-bit boundary, we then fill up the temps, wrapping around to the
2266 top of the word when we drop off the bottom.
2267 In the worst case this code should produce no more than four insns. */
2270 int best_consecutive_zeros
= 0;
2272 for (i
= 0; i
< 32; i
+= 2)
2274 int consecutive_zeros
= 0;
2276 if (!(remainder
& (3 << i
)))
2278 while ((i
< 32) && !(remainder
& (3 << i
)))
2280 consecutive_zeros
+= 2;
2283 if (consecutive_zeros
> best_consecutive_zeros
)
2285 best_consecutive_zeros
= consecutive_zeros
;
2286 best_start
= i
- consecutive_zeros
;
2292 /* So long as it won't require any more insns to do so, it's
2293 desirable to emit a small constant (in bits 0...9) in the last
2294 insn. This way there is more chance that it can be combined with
2295 a later addressing insn to form a pre-indexed load or store
2296 operation. Consider:
2298 *((volatile int *)0xe0000100) = 1;
2299 *((volatile int *)0xe0000110) = 2;
2301 We want this to wind up as:
2305 str rB, [rA, #0x100]
2307 str rB, [rA, #0x110]
2309 rather than having to synthesize both large constants from scratch.
2311 Therefore, we calculate how many insns would be required to emit
2312 the constant starting from `best_start', and also starting from
2313 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2314 yield a shorter sequence, we may as well use zero. */
2316 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2317 && (count_insns_for_constant (remainder
, 0) <=
2318 count_insns_for_constant (remainder
, best_start
)))
2321 /* Now start emitting the insns. */
2329 if (remainder
& (3 << (i
- 2)))
2334 temp1
= remainder
& ((0x0ff << end
)
2335 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2336 remainder
&= ~temp1
;
2340 rtx new_src
, temp1_rtx
;
2342 if (code
== SET
|| code
== MINUS
)
2344 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2345 if (can_invert
&& code
!= MINUS
)
2350 if (remainder
&& subtargets
)
2351 new_src
= gen_reg_rtx (mode
);
2356 else if (can_negate
)
2360 temp1
= trunc_int_for_mode (temp1
, mode
);
2361 temp1_rtx
= GEN_INT (temp1
);
2365 else if (code
== MINUS
)
2366 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2368 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2370 emit_constant_insn (cond
,
2371 gen_rtx_SET (VOIDmode
, new_src
,
2381 else if (code
== MINUS
)
2395 /* Canonicalize a comparison so that we are more likely to recognize it.
2396 This can be done for a few constant compares, where we can make the
2397 immediate value easier to load. */
2400 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2403 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2404 unsigned HOST_WIDE_INT maxval
;
2405 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2416 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2418 *op1
= GEN_INT (i
+ 1);
2419 return code
== GT
? GE
: LT
;
2426 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2428 *op1
= GEN_INT (i
- 1);
2429 return code
== GE
? GT
: LE
;
2435 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2436 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2438 *op1
= GEN_INT (i
+ 1);
2439 return code
== GTU
? GEU
: LTU
;
2446 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2448 *op1
= GEN_INT (i
- 1);
2449 return code
== GEU
? GTU
: LEU
;
2461 /* Define how to find the value returned by a function. */
2464 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2466 enum machine_mode mode
;
2467 int unsignedp ATTRIBUTE_UNUSED
;
2468 rtx r ATTRIBUTE_UNUSED
;
2470 mode
= TYPE_MODE (type
);
2471 /* Promote integer types. */
2472 if (INTEGRAL_TYPE_P (type
))
2473 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2475 /* Promotes small structs returned in a register to full-word size
2476 for big-endian AAPCS. */
2477 if (arm_return_in_msb (type
))
2479 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2480 if (size
% UNITS_PER_WORD
!= 0)
2482 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2483 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2487 return LIBCALL_VALUE(mode
);
2490 /* Determine the amount of memory needed to store the possible return
2491 registers of an untyped call. */
2493 arm_apply_result_size (void)
2499 if (TARGET_HARD_FLOAT_ABI
)
2503 if (TARGET_MAVERICK
)
2506 if (TARGET_IWMMXT_ABI
)
2513 /* Decide whether a type should be returned in memory (true)
2514 or in a register (false). This is called by the macro
2515 RETURN_IN_MEMORY. */
2517 arm_return_in_memory (tree type
)
2521 if (!AGGREGATE_TYPE_P (type
) &&
2522 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2523 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2524 /* All simple types are returned in registers.
2525 For AAPCS, complex types are treated the same as aggregates. */
2528 size
= int_size_in_bytes (type
);
2530 if (arm_abi
!= ARM_ABI_APCS
)
2532 /* ATPCS and later return aggregate types in memory only if they are
2533 larger than a word (or are variable size). */
2534 return (size
< 0 || size
> UNITS_PER_WORD
);
2537 /* To maximize backwards compatibility with previous versions of gcc,
2538 return vectors up to 4 words in registers. */
2539 if (TREE_CODE (type
) == VECTOR_TYPE
)
2540 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2542 /* For the arm-wince targets we choose to be compatible with Microsoft's
2543 ARM and Thumb compilers, which always return aggregates in memory. */
2545 /* All structures/unions bigger than one word are returned in memory.
2546 Also catch the case where int_size_in_bytes returns -1. In this case
2547 the aggregate is either huge or of variable size, and in either case
2548 we will want to return it via memory and not in a register. */
2549 if (size
< 0 || size
> UNITS_PER_WORD
)
2552 if (TREE_CODE (type
) == RECORD_TYPE
)
2556 /* For a struct the APCS says that we only return in a register
2557 if the type is 'integer like' and every addressable element
2558 has an offset of zero. For practical purposes this means
2559 that the structure can have at most one non bit-field element
2560 and that this element must be the first one in the structure. */
2562 /* Find the first field, ignoring non FIELD_DECL things which will
2563 have been created by C++. */
2564 for (field
= TYPE_FIELDS (type
);
2565 field
&& TREE_CODE (field
) != FIELD_DECL
;
2566 field
= TREE_CHAIN (field
))
2570 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2572 /* Check that the first field is valid for returning in a register. */
2574 /* ... Floats are not allowed */
2575 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2578 /* ... Aggregates that are not themselves valid for returning in
2579 a register are not allowed. */
2580 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2583 /* Now check the remaining fields, if any. Only bitfields are allowed,
2584 since they are not addressable. */
2585 for (field
= TREE_CHAIN (field
);
2587 field
= TREE_CHAIN (field
))
2589 if (TREE_CODE (field
) != FIELD_DECL
)
2592 if (!DECL_BIT_FIELD_TYPE (field
))
2599 if (TREE_CODE (type
) == UNION_TYPE
)
2603 /* Unions can be returned in registers if every element is
2604 integral, or can be returned in an integer register. */
2605 for (field
= TYPE_FIELDS (type
);
2607 field
= TREE_CHAIN (field
))
2609 if (TREE_CODE (field
) != FIELD_DECL
)
2612 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2615 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2621 #endif /* not ARM_WINCE */
2623 /* Return all other types in memory. */
2627 /* Indicate whether or not words of a double are in big-endian order. */
2630 arm_float_words_big_endian (void)
2632 if (TARGET_MAVERICK
)
2635 /* For FPA, float words are always big-endian. For VFP, floats words
2636 follow the memory system mode. */
2644 return (TARGET_BIG_END
? 1 : 0);
2649 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2650 for a call to a function whose data type is FNTYPE.
2651 For a library call, FNTYPE is NULL. */
2653 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2654 rtx libname ATTRIBUTE_UNUSED
,
2655 tree fndecl ATTRIBUTE_UNUSED
)
2657 /* On the ARM, the offset starts at 0. */
2658 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2659 pcum
->iwmmxt_nregs
= 0;
2660 pcum
->can_split
= true;
2662 pcum
->call_cookie
= CALL_NORMAL
;
2664 if (TARGET_LONG_CALLS
)
2665 pcum
->call_cookie
= CALL_LONG
;
2667 /* Check for long call/short call attributes. The attributes
2668 override any command line option. */
2671 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2672 pcum
->call_cookie
= CALL_SHORT
;
2673 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2674 pcum
->call_cookie
= CALL_LONG
;
2677 /* Varargs vectors are treated the same as long long.
2678 named_count avoids having to change the way arm handles 'named' */
2679 pcum
->named_count
= 0;
2682 if (TARGET_REALLY_IWMMXT
&& fntype
)
2686 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2688 fn_arg
= TREE_CHAIN (fn_arg
))
2689 pcum
->named_count
+= 1;
2691 if (! pcum
->named_count
)
2692 pcum
->named_count
= INT_MAX
;
2697 /* Return true if mode/type need doubleword alignment. */
2699 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2701 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2702 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2706 /* Determine where to put an argument to a function.
2707 Value is zero to push the argument on the stack,
2708 or a hard register in which to store the argument.
2710 MODE is the argument's machine mode.
2711 TYPE is the data type of the argument (as a tree).
2712 This is null for libcalls where that information may
2714 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2715 the preceding args and about the function being called.
2716 NAMED is nonzero if this argument is a named parameter
2717 (otherwise it is an extra parameter matching an ellipsis). */
2720 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2721 tree type
, int named
)
2725 /* Varargs vectors are treated the same as long long.
2726 named_count avoids having to change the way arm handles 'named' */
2727 if (TARGET_IWMMXT_ABI
2728 && arm_vector_mode_supported_p (mode
)
2729 && pcum
->named_count
> pcum
->nargs
+ 1)
2731 if (pcum
->iwmmxt_nregs
<= 9)
2732 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2735 pcum
->can_split
= false;
2740 /* Put doubleword aligned quantities in even register pairs. */
2742 && ARM_DOUBLEWORD_ALIGN
2743 && arm_needs_doubleword_align (mode
, type
))
2746 if (mode
== VOIDmode
)
2747 /* Compute operand 2 of the call insn. */
2748 return GEN_INT (pcum
->call_cookie
);
2750 /* Only allow splitting an arg between regs and memory if all preceding
2751 args were allocated to regs. For args passed by reference we only count
2752 the reference pointer. */
2753 if (pcum
->can_split
)
2756 nregs
= ARM_NUM_REGS2 (mode
, type
);
2758 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2761 return gen_rtx_REG (mode
, pcum
->nregs
);
2765 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2766 tree type
, bool named ATTRIBUTE_UNUSED
)
2768 int nregs
= pcum
->nregs
;
2770 if (arm_vector_mode_supported_p (mode
))
2773 if (NUM_ARG_REGS
> nregs
2774 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2776 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2781 /* Variable sized types are passed by reference. This is a GCC
2782 extension to the ARM ABI. */
2785 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2786 enum machine_mode mode ATTRIBUTE_UNUSED
,
2787 tree type
, bool named ATTRIBUTE_UNUSED
)
2789 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2792 /* Encode the current state of the #pragma [no_]long_calls. */
2795 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2796 LONG
, /* #pragma long_calls is in effect. */
2797 SHORT
/* #pragma no_long_calls is in effect. */
2800 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2803 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2805 arm_pragma_long_calls
= LONG
;
2809 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2811 arm_pragma_long_calls
= SHORT
;
2815 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2817 arm_pragma_long_calls
= OFF
;
2820 /* Table of machine attributes. */
2821 const struct attribute_spec arm_attribute_table
[] =
2823 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2824 /* Function calls made to this symbol must be done indirectly, because
2825 it may lie outside of the 26 bit addressing range of a normal function
2827 { "long_call", 0, 0, false, true, true, NULL
},
2828 /* Whereas these functions are always known to reside within the 26 bit
2829 addressing range. */
2830 { "short_call", 0, 0, false, true, true, NULL
},
2831 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2832 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2833 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2834 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2836 /* ARM/PE has three new attributes:
2838 dllexport - for exporting a function/variable that will live in a dll
2839 dllimport - for importing a function/variable from a dll
2841 Microsoft allows multiple declspecs in one __declspec, separating
2842 them with spaces. We do NOT support this. Instead, use __declspec
2845 { "dllimport", 0, 0, true, false, false, NULL
},
2846 { "dllexport", 0, 0, true, false, false, NULL
},
2847 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2848 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2849 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2850 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2851 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2853 { NULL
, 0, 0, false, false, false, NULL
}
2856 /* Handle an attribute requiring a FUNCTION_DECL;
2857 arguments as in struct attribute_spec.handler. */
2859 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2860 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2862 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2864 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2865 IDENTIFIER_POINTER (name
));
2866 *no_add_attrs
= true;
2872 /* Handle an "interrupt" or "isr" attribute;
2873 arguments as in struct attribute_spec.handler. */
2875 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2880 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2882 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2883 IDENTIFIER_POINTER (name
));
2884 *no_add_attrs
= true;
2886 /* FIXME: the argument if any is checked for type attributes;
2887 should it be checked for decl ones? */
2891 if (TREE_CODE (*node
) == FUNCTION_TYPE
2892 || TREE_CODE (*node
) == METHOD_TYPE
)
2894 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2896 warning (OPT_Wattributes
, "%qs attribute ignored",
2897 IDENTIFIER_POINTER (name
));
2898 *no_add_attrs
= true;
2901 else if (TREE_CODE (*node
) == POINTER_TYPE
2902 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2903 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2904 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2906 *node
= build_variant_type_copy (*node
);
2907 TREE_TYPE (*node
) = build_type_attribute_variant
2909 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2910 *no_add_attrs
= true;
2914 /* Possibly pass this attribute on from the type to a decl. */
2915 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2916 | (int) ATTR_FLAG_FUNCTION_NEXT
2917 | (int) ATTR_FLAG_ARRAY_NEXT
))
2919 *no_add_attrs
= true;
2920 return tree_cons (name
, args
, NULL_TREE
);
2924 warning (OPT_Wattributes
, "%qs attribute ignored",
2925 IDENTIFIER_POINTER (name
));
2933 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2934 /* Handle the "notshared" attribute. This attribute is another way of
2935 requesting hidden visibility. ARM's compiler supports
2936 "__declspec(notshared)"; we support the same thing via an
2940 arm_handle_notshared_attribute (tree
*node
,
2941 tree name ATTRIBUTE_UNUSED
,
2942 tree args ATTRIBUTE_UNUSED
,
2943 int flags ATTRIBUTE_UNUSED
,
2946 tree decl
= TYPE_NAME (*node
);
2950 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
2951 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
2952 *no_add_attrs
= false;
2958 /* Return 0 if the attributes for two types are incompatible, 1 if they
2959 are compatible, and 2 if they are nearly compatible (which causes a
2960 warning to be generated). */
2962 arm_comp_type_attributes (tree type1
, tree type2
)
2966 /* Check for mismatch of non-default calling convention. */
2967 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2970 /* Check for mismatched call attributes. */
2971 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2972 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2973 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2974 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2976 /* Only bother to check if an attribute is defined. */
2977 if (l1
| l2
| s1
| s2
)
2979 /* If one type has an attribute, the other must have the same attribute. */
2980 if ((l1
!= l2
) || (s1
!= s2
))
2983 /* Disallow mixed attributes. */
2984 if ((l1
& s2
) || (l2
& s1
))
2988 /* Check for mismatched ISR attribute. */
2989 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2991 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2992 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2994 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
3001 /* Encode long_call or short_call attribute by prefixing
3002 symbol name in DECL with a special character FLAG. */
3004 arm_encode_call_attribute (tree decl
, int flag
)
3006 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
3007 int len
= strlen (str
);
3010 /* Do not allow weak functions to be treated as short call. */
3011 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3014 newstr
= alloca (len
+ 2);
3016 strcpy (newstr
+ 1, str
);
3018 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3019 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3022 /* Assigns default attributes to newly defined type. This is used to
3023 set short_call/long_call attributes for function types of
3024 functions defined inside corresponding #pragma scopes. */
3026 arm_set_default_type_attributes (tree type
)
3028 /* Add __attribute__ ((long_call)) to all functions, when
3029 inside #pragma long_calls or __attribute__ ((short_call)),
3030 when inside #pragma no_long_calls. */
3031 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3033 tree type_attr_list
, attr_name
;
3034 type_attr_list
= TYPE_ATTRIBUTES (type
);
3036 if (arm_pragma_long_calls
== LONG
)
3037 attr_name
= get_identifier ("long_call");
3038 else if (arm_pragma_long_calls
== SHORT
)
3039 attr_name
= get_identifier ("short_call");
3043 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3044 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3048 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3049 defined within the current compilation unit. If this cannot be
3050 determined, then 0 is returned. */
3052 current_file_function_operand (rtx sym_ref
)
3054 /* This is a bit of a fib. A function will have a short call flag
3055 applied to its name if it has the short call attribute, or it has
3056 already been defined within the current compilation unit. */
3057 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3060 /* The current function is always defined within the current compilation
3061 unit. If it s a weak definition however, then this may not be the real
3062 definition of the function, and so we have to say no. */
3063 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3064 && !DECL_WEAK (current_function_decl
))
3067 /* We cannot make the determination - default to returning 0. */
3071 /* Return nonzero if a 32 bit "long_call" should be generated for
3072 this call. We generate a long_call if the function:
3074 a. has an __attribute__((long call))
3075 or b. is within the scope of a #pragma long_calls
3076 or c. the -mlong-calls command line switch has been specified
3078 1. -ffunction-sections is in effect
3079 or 2. the current function has __attribute__ ((section))
3080 or 3. the target function has __attribute__ ((section))
3082 However we do not generate a long call if the function:
3084 d. has an __attribute__ ((short_call))
3085 or e. is inside the scope of a #pragma no_long_calls
3086 or f. is defined within the current compilation unit.
3088 This function will be called by C fragments contained in the machine
3089 description file. SYM_REF and CALL_COOKIE correspond to the matched
3090 rtl operands. CALL_SYMBOL is used to distinguish between
3091 two different callers of the function. It is set to 1 in the
3092 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3093 and "call_value" patterns. This is because of the difference in the
3094 SYM_REFs passed by these patterns. */
3096 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3100 if (GET_CODE (sym_ref
) != MEM
)
3103 sym_ref
= XEXP (sym_ref
, 0);
3106 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3109 if (call_cookie
& CALL_SHORT
)
3112 if (TARGET_LONG_CALLS
)
3114 if (flag_function_sections
3115 || DECL_SECTION_NAME (current_function_decl
))
3116 /* c.3 is handled by the definition of the
3117 ARM_DECLARE_FUNCTION_SIZE macro. */
3121 if (current_file_function_operand (sym_ref
))
3124 return (call_cookie
& CALL_LONG
)
3125 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3126 || TARGET_LONG_CALLS
;
3129 /* Return nonzero if it is ok to make a tail-call to DECL. */
3131 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3133 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3135 if (cfun
->machine
->sibcall_blocked
)
3138 /* Never tailcall something for which we have no decl, or if we
3139 are in Thumb mode. */
3140 if (decl
== NULL
|| TARGET_THUMB
)
3143 /* Get the calling method. */
3144 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3145 call_type
= CALL_SHORT
;
3146 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3147 call_type
= CALL_LONG
;
3149 /* Cannot tail-call to long calls, since these are out of range of
3150 a branch instruction. However, if not compiling PIC, we know
3151 we can reach the symbol if it is in this compilation unit. */
3152 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3155 /* If we are interworking and the function is not declared static
3156 then we can't tail-call it unless we know that it exists in this
3157 compilation unit (since it might be a Thumb routine). */
3158 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3161 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3162 if (IS_INTERRUPT (arm_current_func_type ()))
3165 /* Everything else is ok. */
3170 /* Addressing mode support functions. */
3172 /* Return nonzero if X is a legitimate immediate operand when compiling
3175 legitimate_pic_operand_p (rtx x
)
3179 && (GET_CODE (x
) == SYMBOL_REF
3180 || (GET_CODE (x
) == CONST
3181 && GET_CODE (XEXP (x
, 0)) == PLUS
3182 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
3189 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3191 if (GET_CODE (orig
) == SYMBOL_REF
3192 || GET_CODE (orig
) == LABEL_REF
)
3194 #ifndef AOF_ASSEMBLER
3195 rtx pic_ref
, address
;
3202 gcc_assert (!no_new_pseudos
);
3203 reg
= gen_reg_rtx (Pmode
);
3208 #ifdef AOF_ASSEMBLER
3209 /* The AOF assembler can generate relocations for these directly, and
3210 understands that the PIC register has to be added into the offset. */
3211 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3214 address
= gen_reg_rtx (Pmode
);
3219 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3221 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
3223 if ((GET_CODE (orig
) == LABEL_REF
3224 || (GET_CODE (orig
) == SYMBOL_REF
&&
3225 SYMBOL_REF_LOCAL_P (orig
)))
3227 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
3230 pic_ref
= gen_const_mem (Pmode
,
3231 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3235 insn
= emit_move_insn (reg
, pic_ref
);
3237 current_function_uses_pic_offset_table
= 1;
3238 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3240 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3244 else if (GET_CODE (orig
) == CONST
)
3248 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3249 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3252 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3253 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3258 gcc_assert (!no_new_pseudos
);
3259 reg
= gen_reg_rtx (Pmode
);
3262 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3264 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3265 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3266 base
== reg
? 0 : reg
);
3268 if (GET_CODE (offset
) == CONST_INT
)
3270 /* The base register doesn't really matter, we only want to
3271 test the index for the appropriate mode. */
3272 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3274 gcc_assert (!no_new_pseudos
);
3275 offset
= force_reg (Pmode
, offset
);
3278 if (GET_CODE (offset
) == CONST_INT
)
3279 return plus_constant (base
, INTVAL (offset
));
3282 if (GET_MODE_SIZE (mode
) > 4
3283 && (GET_MODE_CLASS (mode
) == MODE_INT
3284 || TARGET_SOFT_FLOAT
))
3286 emit_insn (gen_addsi3 (reg
, base
, offset
));
3290 return gen_rtx_PLUS (Pmode
, base
, offset
);
3297 /* Find a spare low register to use during the prolog of a function. */
3300 thumb_find_work_register (unsigned long pushed_regs_mask
)
3304 /* Check the argument registers first as these are call-used. The
3305 register allocation order means that sometimes r3 might be used
3306 but earlier argument registers might not, so check them all. */
3307 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3308 if (!regs_ever_live
[reg
])
3311 /* Before going on to check the call-saved registers we can try a couple
3312 more ways of deducing that r3 is available. The first is when we are
3313 pushing anonymous arguments onto the stack and we have less than 4
3314 registers worth of fixed arguments(*). In this case r3 will be part of
3315 the variable argument list and so we can be sure that it will be
3316 pushed right at the start of the function. Hence it will be available
3317 for the rest of the prologue.
3318 (*): ie current_function_pretend_args_size is greater than 0. */
3319 if (cfun
->machine
->uses_anonymous_args
3320 && current_function_pretend_args_size
> 0)
3321 return LAST_ARG_REGNUM
;
3323 /* The other case is when we have fixed arguments but less than 4 registers
3324 worth. In this case r3 might be used in the body of the function, but
3325 it is not being used to convey an argument into the function. In theory
3326 we could just check current_function_args_size to see how many bytes are
3327 being passed in argument registers, but it seems that it is unreliable.
3328 Sometimes it will have the value 0 when in fact arguments are being
3329 passed. (See testcase execute/20021111-1.c for an example). So we also
3330 check the args_info.nregs field as well. The problem with this field is
3331 that it makes no allowances for arguments that are passed to the
3332 function but which are not used. Hence we could miss an opportunity
3333 when a function has an unused argument in r3. But it is better to be
3334 safe than to be sorry. */
3335 if (! cfun
->machine
->uses_anonymous_args
3336 && current_function_args_size
>= 0
3337 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3338 && cfun
->args_info
.nregs
< 4)
3339 return LAST_ARG_REGNUM
;
3341 /* Otherwise look for a call-saved register that is going to be pushed. */
3342 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3343 if (pushed_regs_mask
& (1 << reg
))
3346 /* Something went wrong - thumb_compute_save_reg_mask()
3347 should have arranged for a suitable register to be pushed. */
3351 static GTY(()) int pic_labelno
;
3353 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3357 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3359 #ifndef AOF_ASSEMBLER
3360 rtx l1
, labelno
, pic_tmp
, pic_tmp2
, pic_rtx
;
3361 rtx global_offset_table
;
3363 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3366 gcc_assert (flag_pic
);
3368 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3369 in the code stream. */
3371 labelno
= GEN_INT (pic_labelno
++);
3372 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3373 l1
= gen_rtx_CONST (VOIDmode
, l1
);
3375 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3376 /* On the ARM the PC register contains 'dot + 8' at the time of the
3377 addition, on the Thumb it is 'dot + 4'. */
3378 pic_tmp
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
3380 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3381 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3383 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3385 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3389 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3390 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
,
3391 pic_offset_table_rtx
, labelno
));
3395 if (REGNO (pic_offset_table_rtx
) > LAST_LO_REGNUM
)
3397 /* We will have pushed the pic register, so we should always be
3398 able to find a work register. */
3399 pic_tmp
= gen_rtx_REG (SImode
,
3400 thumb_find_work_register (saved_regs
));
3401 emit_insn (gen_pic_load_addr_thumb (pic_tmp
, pic_rtx
));
3402 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3405 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3406 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
,
3407 pic_offset_table_rtx
, labelno
));
3410 /* Need to emit this whether or not we obey regdecls,
3411 since setjmp/longjmp can cause life info to screw up. */
3412 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3413 #endif /* AOF_ASSEMBLER */
3417 /* Return nonzero if X is valid as an ARM state addressing register. */
3419 arm_address_register_rtx_p (rtx x
, int strict_p
)
3423 if (GET_CODE (x
) != REG
)
3429 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3431 return (regno
<= LAST_ARM_REGNUM
3432 || regno
>= FIRST_PSEUDO_REGISTER
3433 || regno
== FRAME_POINTER_REGNUM
3434 || regno
== ARG_POINTER_REGNUM
);
3437 /* Return TRUE if this rtx is the difference of a symbol and a label,
3438 and will reduce to a PC-relative relocation in the object file.
3439 Expressions like this can be left alone when generating PIC, rather
3440 than forced through the GOT. */
3442 pcrel_constant_p (rtx x
)
3444 if (GET_CODE (x
) == MINUS
)
3445 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3450 /* Return nonzero if X is a valid ARM state address operand. */
3452 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3456 enum rtx_code code
= GET_CODE (x
);
3458 if (arm_address_register_rtx_p (x
, strict_p
))
3461 use_ldrd
= (TARGET_LDRD
3463 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3465 if (code
== POST_INC
|| code
== PRE_DEC
3466 || ((code
== PRE_INC
|| code
== POST_DEC
)
3467 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3468 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3470 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3471 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3472 && GET_CODE (XEXP (x
, 1)) == PLUS
3473 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3475 rtx addend
= XEXP (XEXP (x
, 1), 1);
3477 /* Don't allow ldrd post increment by register because it's hard
3478 to fixup invalid register choices. */
3480 && GET_CODE (x
) == POST_MODIFY
3481 && GET_CODE (addend
) == REG
)
3484 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3485 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3488 /* After reload constants split into minipools will have addresses
3489 from a LABEL_REF. */
3490 else if (reload_completed
3491 && (code
== LABEL_REF
3493 && GET_CODE (XEXP (x
, 0)) == PLUS
3494 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3495 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3498 else if (mode
== TImode
)
3501 else if (code
== PLUS
)
3503 rtx xop0
= XEXP (x
, 0);
3504 rtx xop1
= XEXP (x
, 1);
3506 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3507 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3508 || (arm_address_register_rtx_p (xop1
, strict_p
)
3509 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3513 /* Reload currently can't handle MINUS, so disable this for now */
3514 else if (GET_CODE (x
) == MINUS
)
3516 rtx xop0
= XEXP (x
, 0);
3517 rtx xop1
= XEXP (x
, 1);
3519 return (arm_address_register_rtx_p (xop0
, strict_p
)
3520 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3524 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3525 && code
== SYMBOL_REF
3526 && CONSTANT_POOL_ADDRESS_P (x
)
3528 && symbol_mentioned_p (get_pool_constant (x
))
3529 && ! pcrel_constant_p (get_pool_constant (x
))))
3535 /* Return nonzero if INDEX is valid for an address index operand in
3538 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3541 HOST_WIDE_INT range
;
3542 enum rtx_code code
= GET_CODE (index
);
3544 /* Standard coprocessor addressing modes. */
3545 if (TARGET_HARD_FLOAT
3546 && (TARGET_FPA
|| TARGET_MAVERICK
)
3547 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3548 || (TARGET_MAVERICK
&& mode
== DImode
)))
3549 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3550 && INTVAL (index
) > -1024
3551 && (INTVAL (index
) & 3) == 0);
3553 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3554 return (code
== CONST_INT
3555 && INTVAL (index
) < 1024
3556 && INTVAL (index
) > -1024
3557 && (INTVAL (index
) & 3) == 0);
3559 if (arm_address_register_rtx_p (index
, strict_p
)
3560 && (GET_MODE_SIZE (mode
) <= 4))
3563 if (mode
== DImode
|| mode
== DFmode
)
3565 if (code
== CONST_INT
)
3567 HOST_WIDE_INT val
= INTVAL (index
);
3570 return val
> -256 && val
< 256;
3572 return val
> -4096 && val
< 4092;
3575 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3578 if (GET_MODE_SIZE (mode
) <= 4
3581 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3585 rtx xiop0
= XEXP (index
, 0);
3586 rtx xiop1
= XEXP (index
, 1);
3588 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3589 && power_of_two_operand (xiop1
, SImode
))
3590 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3591 && power_of_two_operand (xiop0
, SImode
)));
3593 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3594 || code
== ASHIFT
|| code
== ROTATERT
)
3596 rtx op
= XEXP (index
, 1);
3598 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3599 && GET_CODE (op
) == CONST_INT
3601 && INTVAL (op
) <= 31);
3605 /* For ARM v4 we may be doing a sign-extend operation during the
3609 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3615 range
= (mode
== HImode
) ? 4095 : 4096;
3617 return (code
== CONST_INT
3618 && INTVAL (index
) < range
3619 && INTVAL (index
) > -range
);
3622 /* Return nonzero if X is valid as a Thumb state base register. */
3624 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3628 if (GET_CODE (x
) != REG
)
3634 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3636 return (regno
<= LAST_LO_REGNUM
3637 || regno
> LAST_VIRTUAL_REGISTER
3638 || regno
== FRAME_POINTER_REGNUM
3639 || (GET_MODE_SIZE (mode
) >= 4
3640 && (regno
== STACK_POINTER_REGNUM
3641 || regno
>= FIRST_PSEUDO_REGISTER
3642 || x
== hard_frame_pointer_rtx
3643 || x
== arg_pointer_rtx
)));
3646 /* Return nonzero if x is a legitimate index register. This is the case
3647 for any base register that can access a QImode object. */
3649 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3651 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3654 /* Return nonzero if x is a legitimate Thumb-state address.
3656 The AP may be eliminated to either the SP or the FP, so we use the
3657 least common denominator, e.g. SImode, and offsets from 0 to 64.
3659 ??? Verify whether the above is the right approach.
3661 ??? Also, the FP may be eliminated to the SP, so perhaps that
3662 needs special handling also.
3664 ??? Look at how the mips16 port solves this problem. It probably uses
3665 better ways to solve some of these problems.
3667 Although it is not incorrect, we don't accept QImode and HImode
3668 addresses based on the frame pointer or arg pointer until the
3669 reload pass starts. This is so that eliminating such addresses
3670 into stack based ones won't produce impossible code. */
3672 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3674 /* ??? Not clear if this is right. Experiment. */
3675 if (GET_MODE_SIZE (mode
) < 4
3676 && !(reload_in_progress
|| reload_completed
)
3677 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3678 || reg_mentioned_p (arg_pointer_rtx
, x
)
3679 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3680 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3681 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3682 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3685 /* Accept any base register. SP only in SImode or larger. */
3686 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3689 /* This is PC relative data before arm_reorg runs. */
3690 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3691 && GET_CODE (x
) == SYMBOL_REF
3692 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3695 /* This is PC relative data after arm_reorg runs. */
3696 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3697 && (GET_CODE (x
) == LABEL_REF
3698 || (GET_CODE (x
) == CONST
3699 && GET_CODE (XEXP (x
, 0)) == PLUS
3700 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3701 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3704 /* Post-inc indexing only supported for SImode and larger. */
3705 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3706 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3709 else if (GET_CODE (x
) == PLUS
)
3711 /* REG+REG address can be any two index registers. */
3712 /* We disallow FRAME+REG addressing since we know that FRAME
3713 will be replaced with STACK, and SP relative addressing only
3714 permits SP+OFFSET. */
3715 if (GET_MODE_SIZE (mode
) <= 4
3716 && XEXP (x
, 0) != frame_pointer_rtx
3717 && XEXP (x
, 1) != frame_pointer_rtx
3718 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3719 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3722 /* REG+const has 5-7 bit offset for non-SP registers. */
3723 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3724 || XEXP (x
, 0) == arg_pointer_rtx
)
3725 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3726 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3729 /* REG+const has 10 bit offset for SP, but only SImode and
3730 larger is supported. */
3731 /* ??? Should probably check for DI/DFmode overflow here
3732 just like GO_IF_LEGITIMATE_OFFSET does. */
3733 else if (GET_CODE (XEXP (x
, 0)) == REG
3734 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3735 && GET_MODE_SIZE (mode
) >= 4
3736 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3737 && INTVAL (XEXP (x
, 1)) >= 0
3738 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3739 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3742 else if (GET_CODE (XEXP (x
, 0)) == REG
3743 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3744 && GET_MODE_SIZE (mode
) >= 4
3745 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3746 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3750 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3751 && GET_MODE_SIZE (mode
) == 4
3752 && GET_CODE (x
) == SYMBOL_REF
3753 && CONSTANT_POOL_ADDRESS_P (x
)
3755 && symbol_mentioned_p (get_pool_constant (x
))
3756 && ! pcrel_constant_p (get_pool_constant (x
))))
3762 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3763 instruction of mode MODE. */
3765 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3767 switch (GET_MODE_SIZE (mode
))
3770 return val
>= 0 && val
< 32;
3773 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3777 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3782 /* Build the SYMBOL_REF for __tls_get_addr. */
3784 static GTY(()) rtx tls_get_addr_libfunc
;
3787 get_tls_get_addr (void)
3789 if (!tls_get_addr_libfunc
)
3790 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
3791 return tls_get_addr_libfunc
;
3795 arm_load_tp (rtx target
)
3798 target
= gen_reg_rtx (SImode
);
3802 /* Can return in any reg. */
3803 emit_insn (gen_load_tp_hard (target
));
3807 /* Always returned in r0. Immediately copy the result into a pseudo,
3808 otherwise other uses of r0 (e.g. setting up function arguments) may
3809 clobber the value. */
3813 emit_insn (gen_load_tp_soft ());
3815 tmp
= gen_rtx_REG (SImode
, 0);
3816 emit_move_insn (target
, tmp
);
3822 load_tls_operand (rtx x
, rtx reg
)
3826 if (reg
== NULL_RTX
)
3827 reg
= gen_reg_rtx (SImode
);
3829 tmp
= gen_rtx_CONST (SImode
, x
);
3831 emit_move_insn (reg
, tmp
);
3837 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
3839 rtx insns
, label
, labelno
, sum
;
3843 labelno
= GEN_INT (pic_labelno
++);
3844 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3845 label
= gen_rtx_CONST (VOIDmode
, label
);
3847 sum
= gen_rtx_UNSPEC (Pmode
,
3848 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
3849 GEN_INT (TARGET_ARM
? 8 : 4)),
3851 reg
= load_tls_operand (sum
, reg
);
3854 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
3856 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3858 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
3859 Pmode
, 1, reg
, Pmode
);
3861 insns
= get_insns ();
3868 legitimize_tls_address (rtx x
, rtx reg
)
3870 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
3871 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
3875 case TLS_MODEL_GLOBAL_DYNAMIC
:
3876 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
3877 dest
= gen_reg_rtx (Pmode
);
3878 emit_libcall_block (insns
, dest
, ret
, x
);
3881 case TLS_MODEL_LOCAL_DYNAMIC
:
3882 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
3884 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3885 share the LDM result with other LD model accesses. */
3886 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
3888 dest
= gen_reg_rtx (Pmode
);
3889 emit_libcall_block (insns
, dest
, ret
, eqv
);
3891 /* Load the addend. */
3892 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
3894 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
3895 return gen_rtx_PLUS (Pmode
, dest
, addend
);
3897 case TLS_MODEL_INITIAL_EXEC
:
3898 labelno
= GEN_INT (pic_labelno
++);
3899 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3900 label
= gen_rtx_CONST (VOIDmode
, label
);
3901 sum
= gen_rtx_UNSPEC (Pmode
,
3902 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
3903 GEN_INT (TARGET_ARM
? 8 : 4)),
3905 reg
= load_tls_operand (sum
, reg
);
3908 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
3911 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
3912 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
3915 tp
= arm_load_tp (NULL_RTX
);
3917 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3919 case TLS_MODEL_LOCAL_EXEC
:
3920 tp
= arm_load_tp (NULL_RTX
);
3922 reg
= gen_rtx_UNSPEC (Pmode
,
3923 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
3925 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
3927 return gen_rtx_PLUS (Pmode
, tp
, reg
);
3934 /* Try machine-dependent ways of modifying an illegitimate address
3935 to be legitimate. If we find one, return the new, valid address. */
3937 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3939 if (arm_tls_symbol_p (x
))
3940 return legitimize_tls_address (x
, NULL_RTX
);
3942 if (GET_CODE (x
) == PLUS
)
3944 rtx xop0
= XEXP (x
, 0);
3945 rtx xop1
= XEXP (x
, 1);
3947 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3948 xop0
= force_reg (SImode
, xop0
);
3950 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3951 xop1
= force_reg (SImode
, xop1
);
3953 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3954 && GET_CODE (xop1
) == CONST_INT
)
3956 HOST_WIDE_INT n
, low_n
;
3960 /* VFP addressing modes actually allow greater offsets, but for
3961 now we just stick with the lowest common denominator. */
3963 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3975 low_n
= ((mode
) == TImode
? 0
3976 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3980 base_reg
= gen_reg_rtx (SImode
);
3981 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
3982 emit_move_insn (base_reg
, val
);
3983 x
= plus_constant (base_reg
, low_n
);
3985 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3986 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3989 /* XXX We don't allow MINUS any more -- see comment in
3990 arm_legitimate_address_p (). */
3991 else if (GET_CODE (x
) == MINUS
)
3993 rtx xop0
= XEXP (x
, 0);
3994 rtx xop1
= XEXP (x
, 1);
3996 if (CONSTANT_P (xop0
))
3997 xop0
= force_reg (SImode
, xop0
);
3999 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
4000 xop1
= force_reg (SImode
, xop1
);
4002 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4003 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
4006 /* Make sure to take full advantage of the pre-indexed addressing mode
4007 with absolute addresses which often allows for the base register to
4008 be factorized for multiple adjacent memory references, and it might
4009 even allows for the mini pool to be avoided entirely. */
4010 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
4013 HOST_WIDE_INT mask
, base
, index
;
4016 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4017 use a 8 bit index. So let's use a 12 bit index for SImode only and
4018 hope that arm_gen_constant will enable ldrb to use more bits. */
4019 bits
= (mode
== SImode
) ? 12 : 8;
4020 mask
= (1 << bits
) - 1;
4021 base
= INTVAL (x
) & ~mask
;
4022 index
= INTVAL (x
) & mask
;
4023 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4025 /* It'll most probably be more efficient to generate the base
4026 with more bits set and use a negative index instead. */
4030 base_reg
= force_reg (SImode
, GEN_INT (base
));
4031 x
= plus_constant (base_reg
, index
);
4036 /* We need to find and carefully transform any SYMBOL and LABEL
4037 references; so go back to the original address expression. */
4038 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4040 if (new_x
!= orig_x
)
4048 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4049 to be legitimate. If we find one, return the new, valid address. */
4051 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4053 if (arm_tls_symbol_p (x
))
4054 return legitimize_tls_address (x
, NULL_RTX
);
4056 if (GET_CODE (x
) == PLUS
4057 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4058 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4059 || INTVAL (XEXP (x
, 1)) < 0))
4061 rtx xop0
= XEXP (x
, 0);
4062 rtx xop1
= XEXP (x
, 1);
4063 HOST_WIDE_INT offset
= INTVAL (xop1
);
4065 /* Try and fold the offset into a biasing of the base register and
4066 then offsetting that. Don't do this when optimizing for space
4067 since it can cause too many CSEs. */
4068 if (optimize_size
&& offset
>= 0
4069 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4071 HOST_WIDE_INT delta
;
4074 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4075 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4076 delta
= 31 * GET_MODE_SIZE (mode
);
4078 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4080 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4082 x
= plus_constant (xop0
, delta
);
4084 else if (offset
< 0 && offset
> -256)
4085 /* Small negative offsets are best done with a subtract before the
4086 dereference, forcing these into a register normally takes two
4088 x
= force_operand (x
, NULL_RTX
);
4091 /* For the remaining cases, force the constant into a register. */
4092 xop1
= force_reg (SImode
, xop1
);
4093 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4096 else if (GET_CODE (x
) == PLUS
4097 && s_register_operand (XEXP (x
, 1), SImode
)
4098 && !s_register_operand (XEXP (x
, 0), SImode
))
4100 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4102 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4107 /* We need to find and carefully transform any SYMBOL and LABEL
4108 references; so go back to the original address expression. */
4109 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4111 if (new_x
!= orig_x
)
4119 thumb_legitimize_reload_address (rtx
*x_p
,
4120 enum machine_mode mode
,
4121 int opnum
, int type
,
4122 int ind_levels ATTRIBUTE_UNUSED
)
4126 if (GET_CODE (x
) == PLUS
4127 && GET_MODE_SIZE (mode
) < 4
4128 && REG_P (XEXP (x
, 0))
4129 && XEXP (x
, 0) == stack_pointer_rtx
4130 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4131 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4136 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4137 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4141 /* If both registers are hi-regs, then it's better to reload the
4142 entire expression rather than each register individually. That
4143 only requires one reload register rather than two. */
4144 if (GET_CODE (x
) == PLUS
4145 && REG_P (XEXP (x
, 0))
4146 && REG_P (XEXP (x
, 1))
4147 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4148 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4153 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4154 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4161 /* Test for various thread-local symbols. */
4163 /* Return TRUE if X is a thread-local symbol. */
4166 arm_tls_symbol_p (rtx x
)
4168 if (! TARGET_HAVE_TLS
)
4171 if (GET_CODE (x
) != SYMBOL_REF
)
4174 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4177 /* Helper for arm_tls_referenced_p. */
4180 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4182 if (GET_CODE (*x
) == SYMBOL_REF
)
4183 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4185 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4186 TLS offsets, not real symbol references. */
4187 if (GET_CODE (*x
) == UNSPEC
4188 && XINT (*x
, 1) == UNSPEC_TLS
)
4194 /* Return TRUE if X contains any TLS symbol references. */
4197 arm_tls_referenced_p (rtx x
)
4199 if (! TARGET_HAVE_TLS
)
4202 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4205 #define REG_OR_SUBREG_REG(X) \
4206 (GET_CODE (X) == REG \
4207 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4209 #define REG_OR_SUBREG_RTX(X) \
4210 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4212 #ifndef COSTS_N_INSNS
4213 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4216 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4218 enum machine_mode mode
= GET_MODE (x
);
4231 return COSTS_N_INSNS (1);
4234 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4237 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4244 return COSTS_N_INSNS (2) + cycles
;
4246 return COSTS_N_INSNS (1) + 16;
4249 return (COSTS_N_INSNS (1)
4250 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4251 + GET_CODE (SET_DEST (x
)) == MEM
));
4256 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4258 if (thumb_shiftable_const (INTVAL (x
)))
4259 return COSTS_N_INSNS (2);
4260 return COSTS_N_INSNS (3);
4262 else if ((outer
== PLUS
|| outer
== COMPARE
)
4263 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4265 else if (outer
== AND
4266 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4267 return COSTS_N_INSNS (1);
4268 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4269 || outer
== LSHIFTRT
)
4271 return COSTS_N_INSNS (2);
4277 return COSTS_N_INSNS (3);
4295 /* XXX another guess. */
4296 /* Memory costs quite a lot for the first word, but subsequent words
4297 load at the equivalent of a single insn each. */
4298 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4299 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4304 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4309 /* XXX still guessing. */
4310 switch (GET_MODE (XEXP (x
, 0)))
4313 return (1 + (mode
== DImode
? 4 : 0)
4314 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4317 return (4 + (mode
== DImode
? 4 : 0)
4318 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4321 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4333 /* Worker routine for arm_rtx_costs. */
4335 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4337 enum machine_mode mode
= GET_MODE (x
);
4338 enum rtx_code subcode
;
4344 /* Memory costs quite a lot for the first word, but subsequent words
4345 load at the equivalent of a single insn each. */
4346 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4347 + (GET_CODE (x
) == SYMBOL_REF
4348 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4354 return optimize_size
? COSTS_N_INSNS (2) : 100;
4357 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4364 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4366 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4367 + ((GET_CODE (XEXP (x
, 0)) == REG
4368 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4369 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4371 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4372 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4373 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4375 + ((GET_CODE (XEXP (x
, 1)) == REG
4376 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4377 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4378 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4383 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4384 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4385 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4386 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4389 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4390 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4391 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4392 && arm_const_double_rtx (XEXP (x
, 1))))
4394 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4395 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4396 && arm_const_double_rtx (XEXP (x
, 0))))
4399 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4400 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4401 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4402 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4403 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4404 || subcode
== ROTATE
|| subcode
== ROTATERT
4406 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4407 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4408 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4409 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4410 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4411 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4412 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4417 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4418 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4419 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4420 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4421 && arm_const_double_rtx (XEXP (x
, 1))))
4425 case AND
: case XOR
: case IOR
:
4428 /* Normally the frame registers will be spilt into reg+const during
4429 reload, so it is a bad idea to combine them with other instructions,
4430 since then they might not be moved outside of loops. As a compromise
4431 we allow integration with ops that have a constant as their second
4433 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4434 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4435 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4436 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4437 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4441 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4442 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4443 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4444 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4447 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4448 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4449 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4450 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4451 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4454 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4455 return (1 + extra_cost
4456 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4457 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4458 || subcode
== ROTATE
|| subcode
== ROTATERT
4460 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4461 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4462 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4463 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4464 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4465 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4471 /* This should have been handled by the CPU specific routines. */
4475 if (arm_arch3m
&& mode
== SImode
4476 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4477 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4478 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4479 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4480 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4481 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4486 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4487 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4491 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4493 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4496 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4504 return 4 + (mode
== DImode
? 4 : 0);
4507 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4508 return (4 + (mode
== DImode
? 4 : 0)
4509 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4512 switch (GET_MODE (XEXP (x
, 0)))
4515 return (1 + (mode
== DImode
? 4 : 0)
4516 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4519 return (4 + (mode
== DImode
? 4 : 0)
4520 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4523 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4538 if (const_ok_for_arm (INTVAL (x
)))
4539 return outer
== SET
? 2 : -1;
4540 else if (outer
== AND
4541 && const_ok_for_arm (~INTVAL (x
)))
4543 else if ((outer
== COMPARE
4544 || outer
== PLUS
|| outer
== MINUS
)
4545 && const_ok_for_arm (-INTVAL (x
)))
4556 if (arm_const_double_rtx (x
))
4557 return outer
== SET
? 2 : -1;
4558 else if ((outer
== COMPARE
|| outer
== PLUS
)
4559 && neg_const_double_rtx_ok_for_fpa (x
))
4568 /* RTX costs when optimizing for size. */
4570 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4572 enum machine_mode mode
= GET_MODE (x
);
4576 /* XXX TBD. For now, use the standard costs. */
4577 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4584 /* A memory access costs 1 insn if the mode is small, or the address is
4585 a single register, otherwise it costs one insn per word. */
4586 if (REG_P (XEXP (x
, 0)))
4587 *total
= COSTS_N_INSNS (1);
4589 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4596 /* Needs a libcall, so it costs about this. */
4597 *total
= COSTS_N_INSNS (2);
4601 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4603 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
4611 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4613 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
4616 else if (mode
== SImode
)
4618 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
4619 /* Slightly disparage register shifts, but not by much. */
4620 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4621 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
4625 /* Needs a libcall. */
4626 *total
= COSTS_N_INSNS (2);
4630 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4632 *total
= COSTS_N_INSNS (1);
4638 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
4639 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
4641 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
4642 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
4643 || subcode1
== ROTATE
|| subcode1
== ROTATERT
4644 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
4645 || subcode1
== ASHIFTRT
)
4647 /* It's just the cost of the two operands. */
4652 *total
= COSTS_N_INSNS (1);
4656 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4660 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4662 *total
= COSTS_N_INSNS (1);
4667 case AND
: case XOR
: case IOR
:
4670 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
4672 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
4673 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4674 || (code
== AND
&& subcode
== NOT
))
4676 /* It's just the cost of the two operands. */
4682 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4686 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4690 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4691 *total
= COSTS_N_INSNS (1);
4694 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4703 if (cc_register (XEXP (x
, 0), VOIDmode
))
4706 *total
= COSTS_N_INSNS (1);
4710 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4711 *total
= COSTS_N_INSNS (1);
4713 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
4718 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
4720 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4721 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4724 *total
+= COSTS_N_INSNS (1);
4729 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
4731 switch (GET_MODE (XEXP (x
, 0)))
4734 *total
+= COSTS_N_INSNS (1);
4738 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
4744 *total
+= COSTS_N_INSNS (2);
4749 *total
+= COSTS_N_INSNS (1);
4754 if (const_ok_for_arm (INTVAL (x
)))
4755 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
4756 else if (const_ok_for_arm (~INTVAL (x
)))
4757 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
4758 else if (const_ok_for_arm (-INTVAL (x
)))
4760 if (outer_code
== COMPARE
|| outer_code
== PLUS
4761 || outer_code
== MINUS
)
4764 *total
= COSTS_N_INSNS (1);
4767 *total
= COSTS_N_INSNS (2);
4773 *total
= COSTS_N_INSNS (2);
4777 *total
= COSTS_N_INSNS (4);
4781 if (mode
!= VOIDmode
)
4782 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4784 *total
= COSTS_N_INSNS (4); /* How knows? */
4789 /* RTX costs for cores with a slow MUL implementation. */
4792 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4794 enum machine_mode mode
= GET_MODE (x
);
4798 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4805 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4812 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4814 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4815 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4816 int cost
, const_ok
= const_ok_for_arm (i
);
4817 int j
, booth_unit_size
;
4819 /* Tune as appropriate. */
4820 cost
= const_ok
? 4 : 8;
4821 booth_unit_size
= 2;
4822 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4824 i
>>= booth_unit_size
;
4832 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4833 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4837 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4843 /* RTX cost for cores with a fast multiply unit (M variants). */
4846 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4848 enum machine_mode mode
= GET_MODE (x
);
4852 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4859 /* There is no point basing this on the tuning, since it is always the
4860 fast variant if it exists at all. */
4862 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4863 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4864 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4871 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4878 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4880 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4881 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4882 int cost
, const_ok
= const_ok_for_arm (i
);
4883 int j
, booth_unit_size
;
4885 /* Tune as appropriate. */
4886 cost
= const_ok
? 4 : 8;
4887 booth_unit_size
= 8;
4888 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4890 i
>>= booth_unit_size
;
4898 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4899 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4903 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4909 /* RTX cost for XScale CPUs. */
4912 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4914 enum machine_mode mode
= GET_MODE (x
);
4918 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4925 /* There is no point basing this on the tuning, since it is always the
4926 fast variant if it exists at all. */
4928 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4929 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4930 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4937 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4944 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4946 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4947 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4948 int cost
, const_ok
= const_ok_for_arm (i
);
4949 unsigned HOST_WIDE_INT masked_const
;
4951 /* The cost will be related to two insns.
4952 First a load of the constant (MOV or LDR), then a multiply. */
4955 cost
+= 1; /* LDR is probably more expensive because
4956 of longer result latency. */
4957 masked_const
= i
& 0xffff8000;
4958 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4960 masked_const
= i
& 0xf8000000;
4961 if (masked_const
== 0 || masked_const
== 0xf8000000)
4970 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4971 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4975 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4976 will stall until the multiplication is complete. */
4977 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4978 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
4980 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4984 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4990 /* RTX costs for 9e (and later) cores. */
4993 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4995 enum machine_mode mode
= GET_MODE (x
);
5004 *total
= COSTS_N_INSNS (3);
5008 *total
= thumb_rtx_costs (x
, code
, outer_code
);
5016 /* There is no point basing this on the tuning, since it is always the
5017 fast variant if it exists at all. */
5019 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5020 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5021 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5028 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5045 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5046 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5050 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5054 /* All address computations that can be done are free, but rtx cost returns
5055 the same for practically all of them. So we weight the different types
5056 of address here in the order (most pref first):
5057 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5059 arm_arm_address_cost (rtx x
)
5061 enum rtx_code c
= GET_CODE (x
);
5063 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5065 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5068 if (c
== PLUS
|| c
== MINUS
)
5070 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5073 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5083 arm_thumb_address_cost (rtx x
)
5085 enum rtx_code c
= GET_CODE (x
);
5090 && GET_CODE (XEXP (x
, 0)) == REG
5091 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5098 arm_address_cost (rtx x
)
5100 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5104 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5108 /* Some true dependencies can have a higher cost depending
5109 on precisely how certain input operands are used. */
5111 && REG_NOTE_KIND (link
) == 0
5112 && recog_memoized (insn
) >= 0
5113 && recog_memoized (dep
) >= 0)
5115 int shift_opnum
= get_attr_shift (insn
);
5116 enum attr_type attr_type
= get_attr_type (dep
);
5118 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5119 operand for INSN. If we have a shifted input operand and the
5120 instruction we depend on is another ALU instruction, then we may
5121 have to account for an additional stall. */
5122 if (shift_opnum
!= 0
5123 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5125 rtx shifted_operand
;
5128 /* Get the shifted operand. */
5129 extract_insn (insn
);
5130 shifted_operand
= recog_data
.operand
[shift_opnum
];
5132 /* Iterate over all the operands in DEP. If we write an operand
5133 that overlaps with SHIFTED_OPERAND, then we have increase the
5134 cost of this dependency. */
5136 preprocess_constraints ();
5137 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5139 /* We can ignore strict inputs. */
5140 if (recog_data
.operand_type
[opno
] == OP_IN
)
5143 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5150 /* XXX This is not strictly true for the FPA. */
5151 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5152 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5155 /* Call insns don't incur a stall, even if they follow a load. */
5156 if (REG_NOTE_KIND (link
) == 0
5157 && GET_CODE (insn
) == CALL_INSN
)
5160 if ((i_pat
= single_set (insn
)) != NULL
5161 && GET_CODE (SET_SRC (i_pat
)) == MEM
5162 && (d_pat
= single_set (dep
)) != NULL
5163 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5165 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5166 /* This is a load after a store, there is no conflict if the load reads
5167 from a cached area. Assume that loads from the stack, and from the
5168 constant pool are cached, and that others will miss. This is a
5171 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5172 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5173 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5174 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5181 static int fp_consts_inited
= 0;
5183 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5184 static const char * const strings_fp
[8] =
5187 "4", "5", "0.5", "10"
5190 static REAL_VALUE_TYPE values_fp
[8];
5193 init_fp_table (void)
5199 fp_consts_inited
= 1;
5201 fp_consts_inited
= 8;
5203 for (i
= 0; i
< fp_consts_inited
; i
++)
5205 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5210 /* Return TRUE if rtx X is a valid immediate FP constant. */
5212 arm_const_double_rtx (rtx x
)
5217 if (!fp_consts_inited
)
5220 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5221 if (REAL_VALUE_MINUS_ZERO (r
))
5224 for (i
= 0; i
< fp_consts_inited
; i
++)
5225 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5231 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5233 neg_const_double_rtx_ok_for_fpa (rtx x
)
5238 if (!fp_consts_inited
)
5241 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5242 r
= REAL_VALUE_NEGATE (r
);
5243 if (REAL_VALUE_MINUS_ZERO (r
))
5246 for (i
= 0; i
< 8; i
++)
5247 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5253 /* Predicates for `match_operand' and `match_operator'. */
5255 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5257 cirrus_memory_offset (rtx op
)
5259 /* Reject eliminable registers. */
5260 if (! (reload_in_progress
|| reload_completed
)
5261 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5262 || reg_mentioned_p (arg_pointer_rtx
, op
)
5263 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5264 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5265 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5266 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5269 if (GET_CODE (op
) == MEM
)
5275 /* Match: (mem (reg)). */
5276 if (GET_CODE (ind
) == REG
)
5282 if (GET_CODE (ind
) == PLUS
5283 && GET_CODE (XEXP (ind
, 0)) == REG
5284 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5285 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5292 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5293 WB if true if writeback address modes are allowed. */
5296 arm_coproc_mem_operand (rtx op
, bool wb
)
5300 /* Reject eliminable registers. */
5301 if (! (reload_in_progress
|| reload_completed
)
5302 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5303 || reg_mentioned_p (arg_pointer_rtx
, op
)
5304 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5305 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5306 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5307 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5310 /* Constants are converted into offsets from labels. */
5311 if (GET_CODE (op
) != MEM
)
5316 if (reload_completed
5317 && (GET_CODE (ind
) == LABEL_REF
5318 || (GET_CODE (ind
) == CONST
5319 && GET_CODE (XEXP (ind
, 0)) == PLUS
5320 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5321 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5324 /* Match: (mem (reg)). */
5325 if (GET_CODE (ind
) == REG
)
5326 return arm_address_register_rtx_p (ind
, 0);
5328 /* Autoincremment addressing modes. */
5330 && (GET_CODE (ind
) == PRE_INC
5331 || GET_CODE (ind
) == POST_INC
5332 || GET_CODE (ind
) == PRE_DEC
5333 || GET_CODE (ind
) == POST_DEC
))
5334 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5337 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5338 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5339 && GET_CODE (XEXP (ind
, 1)) == PLUS
5340 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5341 ind
= XEXP (ind
, 1);
5346 if (GET_CODE (ind
) == PLUS
5347 && GET_CODE (XEXP (ind
, 0)) == REG
5348 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5349 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5350 && INTVAL (XEXP (ind
, 1)) > -1024
5351 && INTVAL (XEXP (ind
, 1)) < 1024
5352 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5358 /* Return true if X is a register that will be eliminated later on. */
5360 arm_eliminable_register (rtx x
)
5362 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5363 || REGNO (x
) == ARG_POINTER_REGNUM
5364 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5365 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5368 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5369 VFP registers. Otherwise return NO_REGS. */
5372 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
5374 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
5377 return GENERAL_REGS
;
5380 /* Values which must be returned in the most-significant end of the return
5384 arm_return_in_msb (tree valtype
)
5386 return (TARGET_AAPCS_BASED
5388 && (AGGREGATE_TYPE_P (valtype
)
5389 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5392 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5393 Use by the Cirrus Maverick code which has to workaround
5394 a hardware bug triggered by such instructions. */
5396 arm_memory_load_p (rtx insn
)
5398 rtx body
, lhs
, rhs
;;
5400 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5403 body
= PATTERN (insn
);
5405 if (GET_CODE (body
) != SET
)
5408 lhs
= XEXP (body
, 0);
5409 rhs
= XEXP (body
, 1);
5411 lhs
= REG_OR_SUBREG_RTX (lhs
);
5413 /* If the destination is not a general purpose
5414 register we do not have to worry. */
5415 if (GET_CODE (lhs
) != REG
5416 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5419 /* As well as loads from memory we also have to react
5420 to loads of invalid constants which will be turned
5421 into loads from the minipool. */
5422 return (GET_CODE (rhs
) == MEM
5423 || GET_CODE (rhs
) == SYMBOL_REF
5424 || note_invalid_constants (insn
, -1, false));
5427 /* Return TRUE if INSN is a Cirrus instruction. */
5429 arm_cirrus_insn_p (rtx insn
)
5431 enum attr_cirrus attr
;
5433 /* get_attr cannot accept USE or CLOBBER. */
5435 || GET_CODE (insn
) != INSN
5436 || GET_CODE (PATTERN (insn
)) == USE
5437 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5440 attr
= get_attr_cirrus (insn
);
5442 return attr
!= CIRRUS_NOT
;
5445 /* Cirrus reorg for invalid instruction combinations. */
5447 cirrus_reorg (rtx first
)
5449 enum attr_cirrus attr
;
5450 rtx body
= PATTERN (first
);
5454 /* Any branch must be followed by 2 non Cirrus instructions. */
5455 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5458 t
= next_nonnote_insn (first
);
5460 if (arm_cirrus_insn_p (t
))
5463 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5467 emit_insn_after (gen_nop (), first
);
5472 /* (float (blah)) is in parallel with a clobber. */
5473 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5474 body
= XVECEXP (body
, 0, 0);
5476 if (GET_CODE (body
) == SET
)
5478 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5480 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5481 be followed by a non Cirrus insn. */
5482 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5484 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5485 emit_insn_after (gen_nop (), first
);
5489 else if (arm_memory_load_p (first
))
5491 unsigned int arm_regno
;
5493 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5494 ldr/cfmv64hr combination where the Rd field is the same
5495 in both instructions must be split with a non Cirrus
5502 /* Get Arm register number for ldr insn. */
5503 if (GET_CODE (lhs
) == REG
)
5504 arm_regno
= REGNO (lhs
);
5507 gcc_assert (GET_CODE (rhs
) == REG
);
5508 arm_regno
= REGNO (rhs
);
5512 first
= next_nonnote_insn (first
);
5514 if (! arm_cirrus_insn_p (first
))
5517 body
= PATTERN (first
);
5519 /* (float (blah)) is in parallel with a clobber. */
5520 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5521 body
= XVECEXP (body
, 0, 0);
5523 if (GET_CODE (body
) == FLOAT
)
5524 body
= XEXP (body
, 0);
5526 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5527 && GET_CODE (XEXP (body
, 1)) == REG
5528 && arm_regno
== REGNO (XEXP (body
, 1)))
5529 emit_insn_after (gen_nop (), first
);
5535 /* get_attr cannot accept USE or CLOBBER. */
5537 || GET_CODE (first
) != INSN
5538 || GET_CODE (PATTERN (first
)) == USE
5539 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5542 attr
= get_attr_cirrus (first
);
5544 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5545 must be followed by a non-coprocessor instruction. */
5546 if (attr
== CIRRUS_COMPARE
)
5550 t
= next_nonnote_insn (first
);
5552 if (arm_cirrus_insn_p (t
))
5555 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5559 emit_insn_after (gen_nop (), first
);
5565 /* Return TRUE if X references a SYMBOL_REF. */
5567 symbol_mentioned_p (rtx x
)
5572 if (GET_CODE (x
) == SYMBOL_REF
)
5575 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5576 are constant offsets, not symbols. */
5577 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5580 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5582 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5588 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5589 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5592 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5599 /* Return TRUE if X references a LABEL_REF. */
5601 label_mentioned_p (rtx x
)
5606 if (GET_CODE (x
) == LABEL_REF
)
5609 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5610 instruction, but they are constant offsets, not symbols. */
5611 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5614 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5615 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5622 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5625 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5633 tls_mentioned_p (rtx x
)
5635 switch (GET_CODE (x
))
5638 return tls_mentioned_p (XEXP (x
, 0));
5641 if (XINT (x
, 1) == UNSPEC_TLS
)
5649 /* Must not copy a SET whose source operand is PC-relative. */
5652 arm_cannot_copy_insn_p (rtx insn
)
5654 rtx pat
= PATTERN (insn
);
5656 if (GET_CODE (pat
) == PARALLEL
5657 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
5659 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
5661 if (GET_CODE (rhs
) == UNSPEC
5662 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
5665 if (GET_CODE (rhs
) == MEM
5666 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
5667 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
5677 enum rtx_code code
= GET_CODE (x
);
5694 /* Return 1 if memory locations are adjacent. */
5696 adjacent_mem_locations (rtx a
, rtx b
)
5698 /* We don't guarantee to preserve the order of these memory refs. */
5699 if (volatile_refs_p (a
) || volatile_refs_p (b
))
5702 if ((GET_CODE (XEXP (a
, 0)) == REG
5703 || (GET_CODE (XEXP (a
, 0)) == PLUS
5704 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5705 && (GET_CODE (XEXP (b
, 0)) == REG
5706 || (GET_CODE (XEXP (b
, 0)) == PLUS
5707 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5709 HOST_WIDE_INT val0
= 0, val1
= 0;
5713 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5715 reg0
= XEXP (XEXP (a
, 0), 0);
5716 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5721 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5723 reg1
= XEXP (XEXP (b
, 0), 0);
5724 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5729 /* Don't accept any offset that will require multiple
5730 instructions to handle, since this would cause the
5731 arith_adjacentmem pattern to output an overlong sequence. */
5732 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5735 /* Don't allow an eliminable register: register elimination can make
5736 the offset too large. */
5737 if (arm_eliminable_register (reg0
))
5740 val_diff
= val1
- val0
;
5744 /* If the target has load delay slots, then there's no benefit
5745 to using an ldm instruction unless the offset is zero and
5746 we are optimizing for size. */
5747 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
5748 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
5749 && (val_diff
== 4 || val_diff
== -4));
5752 return ((REGNO (reg0
) == REGNO (reg1
))
5753 && (val_diff
== 4 || val_diff
== -4));
5760 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5761 HOST_WIDE_INT
*load_offset
)
5763 int unsorted_regs
[4];
5764 HOST_WIDE_INT unsorted_offsets
[4];
5769 /* Can only handle 2, 3, or 4 insns at present,
5770 though could be easily extended if required. */
5771 gcc_assert (nops
>= 2 && nops
<= 4);
5773 /* Loop over the operands and check that the memory references are
5774 suitable (i.e. immediate offsets from the same base register). At
5775 the same time, extract the target register, and the memory
5777 for (i
= 0; i
< nops
; i
++)
5782 /* Convert a subreg of a mem into the mem itself. */
5783 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5784 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5786 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
5788 /* Don't reorder volatile memory references; it doesn't seem worth
5789 looking for the case where the order is ok anyway. */
5790 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5793 offset
= const0_rtx
;
5795 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5796 || (GET_CODE (reg
) == SUBREG
5797 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5798 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5799 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5801 || (GET_CODE (reg
) == SUBREG
5802 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5803 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5808 base_reg
= REGNO (reg
);
5809 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5810 ? REGNO (operands
[i
])
5811 : REGNO (SUBREG_REG (operands
[i
])));
5816 if (base_reg
!= (int) REGNO (reg
))
5817 /* Not addressed from the same base register. */
5820 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5821 ? REGNO (operands
[i
])
5822 : REGNO (SUBREG_REG (operands
[i
])));
5823 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5827 /* If it isn't an integer register, or if it overwrites the
5828 base register but isn't the last insn in the list, then
5829 we can't do this. */
5830 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5831 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5834 unsorted_offsets
[i
] = INTVAL (offset
);
5837 /* Not a suitable memory address. */
5841 /* All the useful information has now been extracted from the
5842 operands into unsorted_regs and unsorted_offsets; additionally,
5843 order[0] has been set to the lowest numbered register in the
5844 list. Sort the registers into order, and check that the memory
5845 offsets are ascending and adjacent. */
5847 for (i
= 1; i
< nops
; i
++)
5851 order
[i
] = order
[i
- 1];
5852 for (j
= 0; j
< nops
; j
++)
5853 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5854 && (order
[i
] == order
[i
- 1]
5855 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5858 /* Have we found a suitable register? if not, one must be used more
5860 if (order
[i
] == order
[i
- 1])
5863 /* Is the memory address adjacent and ascending? */
5864 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5872 for (i
= 0; i
< nops
; i
++)
5873 regs
[i
] = unsorted_regs
[order
[i
]];
5875 *load_offset
= unsorted_offsets
[order
[0]];
5878 if (unsorted_offsets
[order
[0]] == 0)
5879 return 1; /* ldmia */
5881 if (unsorted_offsets
[order
[0]] == 4)
5882 return 2; /* ldmib */
5884 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5885 return 3; /* ldmda */
5887 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5888 return 4; /* ldmdb */
5890 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5891 if the offset isn't small enough. The reason 2 ldrs are faster
5892 is because these ARMs are able to do more than one cache access
5893 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5894 whilst the ARM8 has a double bandwidth cache. This means that
5895 these cores can do both an instruction fetch and a data fetch in
5896 a single cycle, so the trick of calculating the address into a
5897 scratch register (one of the result regs) and then doing a load
5898 multiple actually becomes slower (and no smaller in code size).
5899 That is the transformation
5901 ldr rd1, [rbase + offset]
5902 ldr rd2, [rbase + offset + 4]
5906 add rd1, rbase, offset
5907 ldmia rd1, {rd1, rd2}
5909 produces worse code -- '3 cycles + any stalls on rd2' instead of
5910 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5911 access per cycle, the first sequence could never complete in less
5912 than 6 cycles, whereas the ldm sequence would only take 5 and
5913 would make better use of sequential accesses if not hitting the
5916 We cheat here and test 'arm_ld_sched' which we currently know to
5917 only be true for the ARM8, ARM9 and StrongARM. If this ever
5918 changes, then the test below needs to be reworked. */
5919 if (nops
== 2 && arm_ld_sched
)
5922 /* Can't do it without setting up the offset, only do this if it takes
5923 no more than one insn. */
5924 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5925 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5929 emit_ldm_seq (rtx
*operands
, int nops
)
5933 HOST_WIDE_INT offset
;
5937 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5940 strcpy (buf
, "ldm%?ia\t");
5944 strcpy (buf
, "ldm%?ib\t");
5948 strcpy (buf
, "ldm%?da\t");
5952 strcpy (buf
, "ldm%?db\t");
5957 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5958 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5961 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5962 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5964 output_asm_insn (buf
, operands
);
5966 strcpy (buf
, "ldm%?ia\t");
5973 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5974 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5976 for (i
= 1; i
< nops
; i
++)
5977 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5978 reg_names
[regs
[i
]]);
5980 strcat (buf
, "}\t%@ phole ldm");
5982 output_asm_insn (buf
, operands
);
5987 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5988 HOST_WIDE_INT
* load_offset
)
5990 int unsorted_regs
[4];
5991 HOST_WIDE_INT unsorted_offsets
[4];
5996 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5997 extended if required. */
5998 gcc_assert (nops
>= 2 && nops
<= 4);
6000 /* Loop over the operands and check that the memory references are
6001 suitable (i.e. immediate offsets from the same base register). At
6002 the same time, extract the target register, and the memory
6004 for (i
= 0; i
< nops
; i
++)
6009 /* Convert a subreg of a mem into the mem itself. */
6010 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6011 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6013 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6015 /* Don't reorder volatile memory references; it doesn't seem worth
6016 looking for the case where the order is ok anyway. */
6017 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6020 offset
= const0_rtx
;
6022 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6023 || (GET_CODE (reg
) == SUBREG
6024 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6025 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6026 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6028 || (GET_CODE (reg
) == SUBREG
6029 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6030 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6035 base_reg
= REGNO (reg
);
6036 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6037 ? REGNO (operands
[i
])
6038 : REGNO (SUBREG_REG (operands
[i
])));
6043 if (base_reg
!= (int) REGNO (reg
))
6044 /* Not addressed from the same base register. */
6047 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6048 ? REGNO (operands
[i
])
6049 : REGNO (SUBREG_REG (operands
[i
])));
6050 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6054 /* If it isn't an integer register, then we can't do this. */
6055 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6058 unsorted_offsets
[i
] = INTVAL (offset
);
6061 /* Not a suitable memory address. */
6065 /* All the useful information has now been extracted from the
6066 operands into unsorted_regs and unsorted_offsets; additionally,
6067 order[0] has been set to the lowest numbered register in the
6068 list. Sort the registers into order, and check that the memory
6069 offsets are ascending and adjacent. */
6071 for (i
= 1; i
< nops
; i
++)
6075 order
[i
] = order
[i
- 1];
6076 for (j
= 0; j
< nops
; j
++)
6077 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6078 && (order
[i
] == order
[i
- 1]
6079 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6082 /* Have we found a suitable register? if not, one must be used more
6084 if (order
[i
] == order
[i
- 1])
6087 /* Is the memory address adjacent and ascending? */
6088 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6096 for (i
= 0; i
< nops
; i
++)
6097 regs
[i
] = unsorted_regs
[order
[i
]];
6099 *load_offset
= unsorted_offsets
[order
[0]];
6102 if (unsorted_offsets
[order
[0]] == 0)
6103 return 1; /* stmia */
6105 if (unsorted_offsets
[order
[0]] == 4)
6106 return 2; /* stmib */
6108 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6109 return 3; /* stmda */
6111 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6112 return 4; /* stmdb */
6118 emit_stm_seq (rtx
*operands
, int nops
)
6122 HOST_WIDE_INT offset
;
6126 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6129 strcpy (buf
, "stm%?ia\t");
6133 strcpy (buf
, "stm%?ib\t");
6137 strcpy (buf
, "stm%?da\t");
6141 strcpy (buf
, "stm%?db\t");
6148 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6149 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6151 for (i
= 1; i
< nops
; i
++)
6152 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6153 reg_names
[regs
[i
]]);
6155 strcat (buf
, "}\t%@ phole stm");
6157 output_asm_insn (buf
, operands
);
6161 /* Routines for use in generating RTL. */
6164 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6165 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6167 HOST_WIDE_INT offset
= *offsetp
;
6170 int sign
= up
? 1 : -1;
6173 /* XScale has load-store double instructions, but they have stricter
6174 alignment requirements than load-store multiple, so we cannot
6177 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6178 the pipeline until completion.
6186 An ldr instruction takes 1-3 cycles, but does not block the
6195 Best case ldr will always win. However, the more ldr instructions
6196 we issue, the less likely we are to be able to schedule them well.
6197 Using ldr instructions also increases code size.
6199 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6200 for counts of 3 or 4 regs. */
6201 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6207 for (i
= 0; i
< count
; i
++)
6209 addr
= plus_constant (from
, i
* 4 * sign
);
6210 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6211 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6217 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6227 result
= gen_rtx_PARALLEL (VOIDmode
,
6228 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6231 XVECEXP (result
, 0, 0)
6232 = gen_rtx_SET (VOIDmode
, from
, plus_constant (from
, count
* 4 * sign
));
6237 for (j
= 0; i
< count
; i
++, j
++)
6239 addr
= plus_constant (from
, j
* 4 * sign
);
6240 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6241 XVECEXP (result
, 0, i
)
6242 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6253 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6254 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6256 HOST_WIDE_INT offset
= *offsetp
;
6259 int sign
= up
? 1 : -1;
6262 /* See arm_gen_load_multiple for discussion of
6263 the pros/cons of ldm/stm usage for XScale. */
6264 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6270 for (i
= 0; i
< count
; i
++)
6272 addr
= plus_constant (to
, i
* 4 * sign
);
6273 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6274 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6280 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6290 result
= gen_rtx_PARALLEL (VOIDmode
,
6291 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6294 XVECEXP (result
, 0, 0)
6295 = gen_rtx_SET (VOIDmode
, to
,
6296 plus_constant (to
, count
* 4 * sign
));
6301 for (j
= 0; i
< count
; i
++, j
++)
6303 addr
= plus_constant (to
, j
* 4 * sign
);
6304 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6305 XVECEXP (result
, 0, i
)
6306 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6317 arm_gen_movmemqi (rtx
*operands
)
6319 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6320 HOST_WIDE_INT srcoffset
, dstoffset
;
6322 rtx src
, dst
, srcbase
, dstbase
;
6323 rtx part_bytes_reg
= NULL
;
6326 if (GET_CODE (operands
[2]) != CONST_INT
6327 || GET_CODE (operands
[3]) != CONST_INT
6328 || INTVAL (operands
[2]) > 64
6329 || INTVAL (operands
[3]) & 3)
6332 dstbase
= operands
[0];
6333 srcbase
= operands
[1];
6335 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6336 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6338 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6339 out_words_to_go
= INTVAL (operands
[2]) / 4;
6340 last_bytes
= INTVAL (operands
[2]) & 3;
6341 dstoffset
= srcoffset
= 0;
6343 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6344 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6346 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6348 if (in_words_to_go
> 4)
6349 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6350 srcbase
, &srcoffset
));
6352 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6353 FALSE
, srcbase
, &srcoffset
));
6355 if (out_words_to_go
)
6357 if (out_words_to_go
> 4)
6358 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6359 dstbase
, &dstoffset
));
6360 else if (out_words_to_go
!= 1)
6361 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6365 dstbase
, &dstoffset
));
6368 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6369 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6370 if (last_bytes
!= 0)
6372 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6378 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6379 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6382 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6383 if (out_words_to_go
)
6387 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6388 sreg
= copy_to_reg (mem
);
6390 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6391 emit_move_insn (mem
, sreg
);
6394 gcc_assert (!in_words_to_go
); /* Sanity check */
6399 gcc_assert (in_words_to_go
> 0);
6401 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6402 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6405 gcc_assert (!last_bytes
|| part_bytes_reg
);
6407 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6409 rtx tmp
= gen_reg_rtx (SImode
);
6411 /* The bytes we want are in the top end of the word. */
6412 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6413 GEN_INT (8 * (4 - last_bytes
))));
6414 part_bytes_reg
= tmp
;
6418 mem
= adjust_automodify_address (dstbase
, QImode
,
6419 plus_constant (dst
, last_bytes
- 1),
6420 dstoffset
+ last_bytes
- 1);
6421 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6425 tmp
= gen_reg_rtx (SImode
);
6426 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6427 part_bytes_reg
= tmp
;
6436 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6437 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6441 rtx tmp
= gen_reg_rtx (SImode
);
6442 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6443 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6444 part_bytes_reg
= tmp
;
6451 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6452 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6459 /* Select a dominance comparison mode if possible for a test of the general
6460 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6461 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6462 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6463 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6464 In all cases OP will be either EQ or NE, but we don't need to know which
6465 here. If we are unable to support a dominance comparison we return
6466 CC mode. This will then fail to match for the RTL expressions that
6467 generate this call. */
6469 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6471 enum rtx_code cond1
, cond2
;
6474 /* Currently we will probably get the wrong result if the individual
6475 comparisons are not simple. This also ensures that it is safe to
6476 reverse a comparison if necessary. */
6477 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6479 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6483 /* The if_then_else variant of this tests the second condition if the
6484 first passes, but is true if the first fails. Reverse the first
6485 condition to get a true "inclusive-or" expression. */
6486 if (cond_or
== DOM_CC_NX_OR_Y
)
6487 cond1
= reverse_condition (cond1
);
6489 /* If the comparisons are not equal, and one doesn't dominate the other,
6490 then we can't do this. */
6492 && !comparison_dominates_p (cond1
, cond2
)
6493 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6498 enum rtx_code temp
= cond1
;
6506 if (cond_or
== DOM_CC_X_AND_Y
)
6511 case EQ
: return CC_DEQmode
;
6512 case LE
: return CC_DLEmode
;
6513 case LEU
: return CC_DLEUmode
;
6514 case GE
: return CC_DGEmode
;
6515 case GEU
: return CC_DGEUmode
;
6516 default: gcc_unreachable ();
6520 if (cond_or
== DOM_CC_X_AND_Y
)
6536 if (cond_or
== DOM_CC_X_AND_Y
)
6552 if (cond_or
== DOM_CC_X_AND_Y
)
6568 if (cond_or
== DOM_CC_X_AND_Y
)
6583 /* The remaining cases only occur when both comparisons are the
6586 gcc_assert (cond1
== cond2
);
6590 gcc_assert (cond1
== cond2
);
6594 gcc_assert (cond1
== cond2
);
6598 gcc_assert (cond1
== cond2
);
6602 gcc_assert (cond1
== cond2
);
6611 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6613 /* All floating point compares return CCFP if it is an equality
6614 comparison, and CCFPE otherwise. */
6615 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6635 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6644 /* A compare with a shifted operand. Because of canonicalization, the
6645 comparison will have to be swapped when we emit the assembler. */
6646 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6647 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6648 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6649 || GET_CODE (x
) == ROTATERT
))
6652 /* This operation is performed swapped, but since we only rely on the Z
6653 flag we don't need an additional mode. */
6654 if (GET_MODE (y
) == SImode
&& REG_P (y
)
6655 && GET_CODE (x
) == NEG
6656 && (op
== EQ
|| op
== NE
))
6659 /* This is a special case that is used by combine to allow a
6660 comparison of a shifted byte load to be split into a zero-extend
6661 followed by a comparison of the shifted integer (only valid for
6662 equalities and unsigned inequalities). */
6663 if (GET_MODE (x
) == SImode
6664 && GET_CODE (x
) == ASHIFT
6665 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6666 && GET_CODE (XEXP (x
, 0)) == SUBREG
6667 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6668 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6669 && (op
== EQ
|| op
== NE
6670 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6671 && GET_CODE (y
) == CONST_INT
)
6674 /* A construct for a conditional compare, if the false arm contains
6675 0, then both conditions must be true, otherwise either condition
6676 must be true. Not all conditions are possible, so CCmode is
6677 returned if it can't be done. */
6678 if (GET_CODE (x
) == IF_THEN_ELSE
6679 && (XEXP (x
, 2) == const0_rtx
6680 || XEXP (x
, 2) == const1_rtx
)
6681 && COMPARISON_P (XEXP (x
, 0))
6682 && COMPARISON_P (XEXP (x
, 1)))
6683 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6684 INTVAL (XEXP (x
, 2)));
6686 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6687 if (GET_CODE (x
) == AND
6688 && COMPARISON_P (XEXP (x
, 0))
6689 && COMPARISON_P (XEXP (x
, 1)))
6690 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6693 if (GET_CODE (x
) == IOR
6694 && COMPARISON_P (XEXP (x
, 0))
6695 && COMPARISON_P (XEXP (x
, 1)))
6696 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6699 /* An operation (on Thumb) where we want to test for a single bit.
6700 This is done by shifting that bit up into the top bit of a
6701 scratch register; we can then branch on the sign bit. */
6703 && GET_MODE (x
) == SImode
6704 && (op
== EQ
|| op
== NE
)
6705 && (GET_CODE (x
) == ZERO_EXTRACT
))
6708 /* An operation that sets the condition codes as a side-effect, the
6709 V flag is not set correctly, so we can only use comparisons where
6710 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6712 if (GET_MODE (x
) == SImode
6714 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6715 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6716 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6717 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6718 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6719 || GET_CODE (x
) == LSHIFTRT
6720 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6721 || GET_CODE (x
) == ROTATERT
6722 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6725 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6728 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6729 && GET_CODE (x
) == PLUS
6730 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6736 /* X and Y are two things to compare using CODE. Emit the compare insn and
6737 return the rtx for register 0 in the proper mode. FP means this is a
6738 floating point compare: I don't think that it is needed on the arm. */
6740 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6742 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6743 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6745 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
6750 /* Generate a sequence of insns that will generate the correct return
6751 address mask depending on the physical architecture that the program
6754 arm_gen_return_addr_mask (void)
6756 rtx reg
= gen_reg_rtx (Pmode
);
6758 emit_insn (gen_return_addr_mask (reg
));
6763 arm_reload_in_hi (rtx
*operands
)
6765 rtx ref
= operands
[1];
6767 HOST_WIDE_INT offset
= 0;
6769 if (GET_CODE (ref
) == SUBREG
)
6771 offset
= SUBREG_BYTE (ref
);
6772 ref
= SUBREG_REG (ref
);
6775 if (GET_CODE (ref
) == REG
)
6777 /* We have a pseudo which has been spilt onto the stack; there
6778 are two cases here: the first where there is a simple
6779 stack-slot replacement and a second where the stack-slot is
6780 out of range, or is used as a subreg. */
6781 if (reg_equiv_mem
[REGNO (ref
)])
6783 ref
= reg_equiv_mem
[REGNO (ref
)];
6784 base
= find_replacement (&XEXP (ref
, 0));
6787 /* The slot is out of range, or was dressed up in a SUBREG. */
6788 base
= reg_equiv_address
[REGNO (ref
)];
6791 base
= find_replacement (&XEXP (ref
, 0));
6793 /* Handle the case where the address is too complex to be offset by 1. */
6794 if (GET_CODE (base
) == MINUS
6795 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6797 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6799 emit_set_insn (base_plus
, base
);
6802 else if (GET_CODE (base
) == PLUS
)
6804 /* The addend must be CONST_INT, or we would have dealt with it above. */
6805 HOST_WIDE_INT hi
, lo
;
6807 offset
+= INTVAL (XEXP (base
, 1));
6808 base
= XEXP (base
, 0);
6810 /* Rework the address into a legal sequence of insns. */
6811 /* Valid range for lo is -4095 -> 4095 */
6814 : -((-offset
) & 0xfff));
6816 /* Corner case, if lo is the max offset then we would be out of range
6817 once we have added the additional 1 below, so bump the msb into the
6818 pre-loading insn(s). */
6822 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6823 ^ (HOST_WIDE_INT
) 0x80000000)
6824 - (HOST_WIDE_INT
) 0x80000000);
6826 gcc_assert (hi
+ lo
== offset
);
6830 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6832 /* Get the base address; addsi3 knows how to handle constants
6833 that require more than one insn. */
6834 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6840 /* Operands[2] may overlap operands[0] (though it won't overlap
6841 operands[1]), that's why we asked for a DImode reg -- so we can
6842 use the bit that does not overlap. */
6843 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6844 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6846 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6848 emit_insn (gen_zero_extendqisi2 (scratch
,
6849 gen_rtx_MEM (QImode
,
6850 plus_constant (base
,
6852 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6853 gen_rtx_MEM (QImode
,
6854 plus_constant (base
,
6856 if (!BYTES_BIG_ENDIAN
)
6857 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6858 gen_rtx_IOR (SImode
,
6861 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6865 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6866 gen_rtx_IOR (SImode
,
6867 gen_rtx_ASHIFT (SImode
, scratch
,
6869 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
6872 /* Handle storing a half-word to memory during reload by synthesizing as two
6873 byte stores. Take care not to clobber the input values until after we
6874 have moved them somewhere safe. This code assumes that if the DImode
6875 scratch in operands[2] overlaps either the input value or output address
6876 in some way, then that value must die in this insn (we absolutely need
6877 two scratch registers for some corner cases). */
6879 arm_reload_out_hi (rtx
*operands
)
6881 rtx ref
= operands
[0];
6882 rtx outval
= operands
[1];
6884 HOST_WIDE_INT offset
= 0;
6886 if (GET_CODE (ref
) == SUBREG
)
6888 offset
= SUBREG_BYTE (ref
);
6889 ref
= SUBREG_REG (ref
);
6892 if (GET_CODE (ref
) == REG
)
6894 /* We have a pseudo which has been spilt onto the stack; there
6895 are two cases here: the first where there is a simple
6896 stack-slot replacement and a second where the stack-slot is
6897 out of range, or is used as a subreg. */
6898 if (reg_equiv_mem
[REGNO (ref
)])
6900 ref
= reg_equiv_mem
[REGNO (ref
)];
6901 base
= find_replacement (&XEXP (ref
, 0));
6904 /* The slot is out of range, or was dressed up in a SUBREG. */
6905 base
= reg_equiv_address
[REGNO (ref
)];
6908 base
= find_replacement (&XEXP (ref
, 0));
6910 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6912 /* Handle the case where the address is too complex to be offset by 1. */
6913 if (GET_CODE (base
) == MINUS
6914 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6916 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6918 /* Be careful not to destroy OUTVAL. */
6919 if (reg_overlap_mentioned_p (base_plus
, outval
))
6921 /* Updating base_plus might destroy outval, see if we can
6922 swap the scratch and base_plus. */
6923 if (!reg_overlap_mentioned_p (scratch
, outval
))
6926 scratch
= base_plus
;
6931 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6933 /* Be conservative and copy OUTVAL into the scratch now,
6934 this should only be necessary if outval is a subreg
6935 of something larger than a word. */
6936 /* XXX Might this clobber base? I can't see how it can,
6937 since scratch is known to overlap with OUTVAL, and
6938 must be wider than a word. */
6939 emit_insn (gen_movhi (scratch_hi
, outval
));
6940 outval
= scratch_hi
;
6944 emit_set_insn (base_plus
, base
);
6947 else if (GET_CODE (base
) == PLUS
)
6949 /* The addend must be CONST_INT, or we would have dealt with it above. */
6950 HOST_WIDE_INT hi
, lo
;
6952 offset
+= INTVAL (XEXP (base
, 1));
6953 base
= XEXP (base
, 0);
6955 /* Rework the address into a legal sequence of insns. */
6956 /* Valid range for lo is -4095 -> 4095 */
6959 : -((-offset
) & 0xfff));
6961 /* Corner case, if lo is the max offset then we would be out of range
6962 once we have added the additional 1 below, so bump the msb into the
6963 pre-loading insn(s). */
6967 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6968 ^ (HOST_WIDE_INT
) 0x80000000)
6969 - (HOST_WIDE_INT
) 0x80000000);
6971 gcc_assert (hi
+ lo
== offset
);
6975 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6977 /* Be careful not to destroy OUTVAL. */
6978 if (reg_overlap_mentioned_p (base_plus
, outval
))
6980 /* Updating base_plus might destroy outval, see if we
6981 can swap the scratch and base_plus. */
6982 if (!reg_overlap_mentioned_p (scratch
, outval
))
6985 scratch
= base_plus
;
6990 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6992 /* Be conservative and copy outval into scratch now,
6993 this should only be necessary if outval is a
6994 subreg of something larger than a word. */
6995 /* XXX Might this clobber base? I can't see how it
6996 can, since scratch is known to overlap with
6998 emit_insn (gen_movhi (scratch_hi
, outval
));
6999 outval
= scratch_hi
;
7003 /* Get the base address; addsi3 knows how to handle constants
7004 that require more than one insn. */
7005 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7011 if (BYTES_BIG_ENDIAN
)
7013 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7014 plus_constant (base
, offset
+ 1)),
7015 gen_lowpart (QImode
, outval
)));
7016 emit_insn (gen_lshrsi3 (scratch
,
7017 gen_rtx_SUBREG (SImode
, outval
, 0),
7019 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7020 gen_lowpart (QImode
, scratch
)));
7024 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7025 gen_lowpart (QImode
, outval
)));
7026 emit_insn (gen_lshrsi3 (scratch
,
7027 gen_rtx_SUBREG (SImode
, outval
, 0),
7029 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7030 plus_constant (base
, offset
+ 1)),
7031 gen_lowpart (QImode
, scratch
)));
7035 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7036 (padded to the size of a word) should be passed in a register. */
7039 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7041 if (TARGET_AAPCS_BASED
)
7042 return must_pass_in_stack_var_size (mode
, type
);
7044 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7048 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7049 Return true if an argument passed on the stack should be padded upwards,
7050 i.e. if the least-significant byte has useful data.
7051 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7052 aggregate types are placed in the lowest memory address. */
7055 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7057 if (!TARGET_AAPCS_BASED
)
7058 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7060 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7067 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7068 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7069 byte of the register has useful data, and return the opposite if the
7070 most significant byte does.
7071 For AAPCS, small aggregates and small complex types are always padded
7075 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7076 tree type
, int first ATTRIBUTE_UNUSED
)
7078 if (TARGET_AAPCS_BASED
7080 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7081 && int_size_in_bytes (type
) <= 4)
7084 /* Otherwise, use default padding. */
7085 return !BYTES_BIG_ENDIAN
;
7089 /* Print a symbolic form of X to the debug file, F. */
7091 arm_print_value (FILE *f
, rtx x
)
7093 switch (GET_CODE (x
))
7096 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7100 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7108 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7110 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7111 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7119 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7123 fprintf (f
, "`%s'", XSTR (x
, 0));
7127 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7131 arm_print_value (f
, XEXP (x
, 0));
7135 arm_print_value (f
, XEXP (x
, 0));
7137 arm_print_value (f
, XEXP (x
, 1));
7145 fprintf (f
, "????");
7150 /* Routines for manipulation of the constant pool. */
7152 /* Arm instructions cannot load a large constant directly into a
7153 register; they have to come from a pc relative load. The constant
7154 must therefore be placed in the addressable range of the pc
7155 relative load. Depending on the precise pc relative load
7156 instruction the range is somewhere between 256 bytes and 4k. This
7157 means that we often have to dump a constant inside a function, and
7158 generate code to branch around it.
7160 It is important to minimize this, since the branches will slow
7161 things down and make the code larger.
7163 Normally we can hide the table after an existing unconditional
7164 branch so that there is no interruption of the flow, but in the
7165 worst case the code looks like this:
7183 We fix this by performing a scan after scheduling, which notices
7184 which instructions need to have their operands fetched from the
7185 constant table and builds the table.
7187 The algorithm starts by building a table of all the constants that
7188 need fixing up and all the natural barriers in the function (places
7189 where a constant table can be dropped without breaking the flow).
7190 For each fixup we note how far the pc-relative replacement will be
7191 able to reach and the offset of the instruction into the function.
7193 Having built the table we then group the fixes together to form
7194 tables that are as large as possible (subject to addressing
7195 constraints) and emit each table of constants after the last
7196 barrier that is within range of all the instructions in the group.
7197 If a group does not contain a barrier, then we forcibly create one
7198 by inserting a jump instruction into the flow. Once the table has
7199 been inserted, the insns are then modified to reference the
7200 relevant entry in the pool.
7202 Possible enhancements to the algorithm (not implemented) are:
7204 1) For some processors and object formats, there may be benefit in
7205 aligning the pools to the start of cache lines; this alignment
7206 would need to be taken into account when calculating addressability
7209 /* These typedefs are located at the start of this file, so that
7210 they can be used in the prototypes there. This comment is to
7211 remind readers of that fact so that the following structures
7212 can be understood more easily.
7214 typedef struct minipool_node Mnode;
7215 typedef struct minipool_fixup Mfix; */
7217 struct minipool_node
7219 /* Doubly linked chain of entries. */
7222 /* The maximum offset into the code that this entry can be placed. While
7223 pushing fixes for forward references, all entries are sorted in order
7224 of increasing max_address. */
7225 HOST_WIDE_INT max_address
;
7226 /* Similarly for an entry inserted for a backwards ref. */
7227 HOST_WIDE_INT min_address
;
7228 /* The number of fixes referencing this entry. This can become zero
7229 if we "unpush" an entry. In this case we ignore the entry when we
7230 come to emit the code. */
7232 /* The offset from the start of the minipool. */
7233 HOST_WIDE_INT offset
;
7234 /* The value in table. */
7236 /* The mode of value. */
7237 enum machine_mode mode
;
7238 /* The size of the value. With iWMMXt enabled
7239 sizes > 4 also imply an alignment of 8-bytes. */
7243 struct minipool_fixup
7247 HOST_WIDE_INT address
;
7249 enum machine_mode mode
;
7253 HOST_WIDE_INT forwards
;
7254 HOST_WIDE_INT backwards
;
7257 /* Fixes less than a word need padding out to a word boundary. */
7258 #define MINIPOOL_FIX_SIZE(mode) \
7259 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7261 static Mnode
* minipool_vector_head
;
7262 static Mnode
* minipool_vector_tail
;
7263 static rtx minipool_vector_label
;
7265 /* The linked list of all minipool fixes required for this function. */
7266 Mfix
* minipool_fix_head
;
7267 Mfix
* minipool_fix_tail
;
7268 /* The fix entry for the current minipool, once it has been placed. */
7269 Mfix
* minipool_barrier
;
7271 /* Determines if INSN is the start of a jump table. Returns the end
7272 of the TABLE or NULL_RTX. */
7274 is_jump_table (rtx insn
)
7278 if (GET_CODE (insn
) == JUMP_INSN
7279 && JUMP_LABEL (insn
) != NULL
7280 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7281 == next_real_insn (insn
))
7283 && GET_CODE (table
) == JUMP_INSN
7284 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7285 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7291 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7292 #define JUMP_TABLES_IN_TEXT_SECTION 0
7295 static HOST_WIDE_INT
7296 get_jump_table_size (rtx insn
)
7298 /* ADDR_VECs only take room if read-only data does into the text
7300 if (JUMP_TABLES_IN_TEXT_SECTION
7301 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
7306 rtx body
= PATTERN (insn
);
7307 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7309 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
7315 /* Move a minipool fix MP from its current location to before MAX_MP.
7316 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7317 constraints may need updating. */
7319 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7320 HOST_WIDE_INT max_address
)
7322 /* The code below assumes these are different. */
7323 gcc_assert (mp
!= max_mp
);
7327 if (max_address
< mp
->max_address
)
7328 mp
->max_address
= max_address
;
7332 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7333 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7335 mp
->max_address
= max_address
;
7337 /* Unlink MP from its current position. Since max_mp is non-null,
7338 mp->prev must be non-null. */
7339 mp
->prev
->next
= mp
->next
;
7340 if (mp
->next
!= NULL
)
7341 mp
->next
->prev
= mp
->prev
;
7343 minipool_vector_tail
= mp
->prev
;
7345 /* Re-insert it before MAX_MP. */
7347 mp
->prev
= max_mp
->prev
;
7350 if (mp
->prev
!= NULL
)
7351 mp
->prev
->next
= mp
;
7353 minipool_vector_head
= mp
;
7356 /* Save the new entry. */
7359 /* Scan over the preceding entries and adjust their addresses as
7361 while (mp
->prev
!= NULL
7362 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7364 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7371 /* Add a constant to the minipool for a forward reference. Returns the
7372 node added or NULL if the constant will not fit in this pool. */
7374 add_minipool_forward_ref (Mfix
*fix
)
7376 /* If set, max_mp is the first pool_entry that has a lower
7377 constraint than the one we are trying to add. */
7378 Mnode
* max_mp
= NULL
;
7379 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7382 /* If this fix's address is greater than the address of the first
7383 entry, then we can't put the fix in this pool. We subtract the
7384 size of the current fix to ensure that if the table is fully
7385 packed we still have enough room to insert this value by shuffling
7386 the other fixes forwards. */
7387 if (minipool_vector_head
&&
7388 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7391 /* Scan the pool to see if a constant with the same value has
7392 already been added. While we are doing this, also note the
7393 location where we must insert the constant if it doesn't already
7395 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7397 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7398 && fix
->mode
== mp
->mode
7399 && (GET_CODE (fix
->value
) != CODE_LABEL
7400 || (CODE_LABEL_NUMBER (fix
->value
)
7401 == CODE_LABEL_NUMBER (mp
->value
)))
7402 && rtx_equal_p (fix
->value
, mp
->value
))
7404 /* More than one fix references this entry. */
7406 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7409 /* Note the insertion point if necessary. */
7411 && mp
->max_address
> max_address
)
7414 /* If we are inserting an 8-bytes aligned quantity and
7415 we have not already found an insertion point, then
7416 make sure that all such 8-byte aligned quantities are
7417 placed at the start of the pool. */
7418 if (ARM_DOUBLEWORD_ALIGN
7420 && fix
->fix_size
== 8
7421 && mp
->fix_size
!= 8)
7424 max_address
= mp
->max_address
;
7428 /* The value is not currently in the minipool, so we need to create
7429 a new entry for it. If MAX_MP is NULL, the entry will be put on
7430 the end of the list since the placement is less constrained than
7431 any existing entry. Otherwise, we insert the new fix before
7432 MAX_MP and, if necessary, adjust the constraints on the other
7434 mp
= xmalloc (sizeof (* mp
));
7435 mp
->fix_size
= fix
->fix_size
;
7436 mp
->mode
= fix
->mode
;
7437 mp
->value
= fix
->value
;
7439 /* Not yet required for a backwards ref. */
7440 mp
->min_address
= -65536;
7444 mp
->max_address
= max_address
;
7446 mp
->prev
= minipool_vector_tail
;
7448 if (mp
->prev
== NULL
)
7450 minipool_vector_head
= mp
;
7451 minipool_vector_label
= gen_label_rtx ();
7454 mp
->prev
->next
= mp
;
7456 minipool_vector_tail
= mp
;
7460 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7461 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7463 mp
->max_address
= max_address
;
7466 mp
->prev
= max_mp
->prev
;
7468 if (mp
->prev
!= NULL
)
7469 mp
->prev
->next
= mp
;
7471 minipool_vector_head
= mp
;
7474 /* Save the new entry. */
7477 /* Scan over the preceding entries and adjust their addresses as
7479 while (mp
->prev
!= NULL
7480 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7482 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7490 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7491 HOST_WIDE_INT min_address
)
7493 HOST_WIDE_INT offset
;
7495 /* The code below assumes these are different. */
7496 gcc_assert (mp
!= min_mp
);
7500 if (min_address
> mp
->min_address
)
7501 mp
->min_address
= min_address
;
7505 /* We will adjust this below if it is too loose. */
7506 mp
->min_address
= min_address
;
7508 /* Unlink MP from its current position. Since min_mp is non-null,
7509 mp->next must be non-null. */
7510 mp
->next
->prev
= mp
->prev
;
7511 if (mp
->prev
!= NULL
)
7512 mp
->prev
->next
= mp
->next
;
7514 minipool_vector_head
= mp
->next
;
7516 /* Reinsert it after MIN_MP. */
7518 mp
->next
= min_mp
->next
;
7520 if (mp
->next
!= NULL
)
7521 mp
->next
->prev
= mp
;
7523 minipool_vector_tail
= mp
;
7529 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7531 mp
->offset
= offset
;
7532 if (mp
->refcount
> 0)
7533 offset
+= mp
->fix_size
;
7535 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7536 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7542 /* Add a constant to the minipool for a backward reference. Returns the
7543 node added or NULL if the constant will not fit in this pool.
7545 Note that the code for insertion for a backwards reference can be
7546 somewhat confusing because the calculated offsets for each fix do
7547 not take into account the size of the pool (which is still under
7550 add_minipool_backward_ref (Mfix
*fix
)
7552 /* If set, min_mp is the last pool_entry that has a lower constraint
7553 than the one we are trying to add. */
7554 Mnode
*min_mp
= NULL
;
7555 /* This can be negative, since it is only a constraint. */
7556 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7559 /* If we can't reach the current pool from this insn, or if we can't
7560 insert this entry at the end of the pool without pushing other
7561 fixes out of range, then we don't try. This ensures that we
7562 can't fail later on. */
7563 if (min_address
>= minipool_barrier
->address
7564 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7565 >= minipool_barrier
->address
))
7568 /* Scan the pool to see if a constant with the same value has
7569 already been added. While we are doing this, also note the
7570 location where we must insert the constant if it doesn't already
7572 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7574 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7575 && fix
->mode
== mp
->mode
7576 && (GET_CODE (fix
->value
) != CODE_LABEL
7577 || (CODE_LABEL_NUMBER (fix
->value
)
7578 == CODE_LABEL_NUMBER (mp
->value
)))
7579 && rtx_equal_p (fix
->value
, mp
->value
)
7580 /* Check that there is enough slack to move this entry to the
7581 end of the table (this is conservative). */
7583 > (minipool_barrier
->address
7584 + minipool_vector_tail
->offset
7585 + minipool_vector_tail
->fix_size
)))
7588 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7592 mp
->min_address
+= fix
->fix_size
;
7595 /* Note the insertion point if necessary. */
7596 if (mp
->min_address
< min_address
)
7598 /* For now, we do not allow the insertion of 8-byte alignment
7599 requiring nodes anywhere but at the start of the pool. */
7600 if (ARM_DOUBLEWORD_ALIGN
7601 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7606 else if (mp
->max_address
7607 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7609 /* Inserting before this entry would push the fix beyond
7610 its maximum address (which can happen if we have
7611 re-located a forwards fix); force the new fix to come
7614 min_address
= mp
->min_address
+ fix
->fix_size
;
7616 /* If we are inserting an 8-bytes aligned quantity and
7617 we have not already found an insertion point, then
7618 make sure that all such 8-byte aligned quantities are
7619 placed at the start of the pool. */
7620 else if (ARM_DOUBLEWORD_ALIGN
7622 && fix
->fix_size
== 8
7623 && mp
->fix_size
< 8)
7626 min_address
= mp
->min_address
+ fix
->fix_size
;
7631 /* We need to create a new entry. */
7632 mp
= xmalloc (sizeof (* mp
));
7633 mp
->fix_size
= fix
->fix_size
;
7634 mp
->mode
= fix
->mode
;
7635 mp
->value
= fix
->value
;
7637 mp
->max_address
= minipool_barrier
->address
+ 65536;
7639 mp
->min_address
= min_address
;
7644 mp
->next
= minipool_vector_head
;
7646 if (mp
->next
== NULL
)
7648 minipool_vector_tail
= mp
;
7649 minipool_vector_label
= gen_label_rtx ();
7652 mp
->next
->prev
= mp
;
7654 minipool_vector_head
= mp
;
7658 mp
->next
= min_mp
->next
;
7662 if (mp
->next
!= NULL
)
7663 mp
->next
->prev
= mp
;
7665 minipool_vector_tail
= mp
;
7668 /* Save the new entry. */
7676 /* Scan over the following entries and adjust their offsets. */
7677 while (mp
->next
!= NULL
)
7679 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7680 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7683 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7685 mp
->next
->offset
= mp
->offset
;
7694 assign_minipool_offsets (Mfix
*barrier
)
7696 HOST_WIDE_INT offset
= 0;
7699 minipool_barrier
= barrier
;
7701 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7703 mp
->offset
= offset
;
7705 if (mp
->refcount
> 0)
7706 offset
+= mp
->fix_size
;
7710 /* Output the literal table */
7712 dump_minipool (rtx scan
)
7718 if (ARM_DOUBLEWORD_ALIGN
)
7719 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7720 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7728 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7729 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7731 scan
= emit_label_after (gen_label_rtx (), scan
);
7732 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7733 scan
= emit_label_after (minipool_vector_label
, scan
);
7735 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7737 if (mp
->refcount
> 0)
7742 ";; Offset %u, min %ld, max %ld ",
7743 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7744 (unsigned long) mp
->max_address
);
7745 arm_print_value (dump_file
, mp
->value
);
7746 fputc ('\n', dump_file
);
7749 switch (mp
->fix_size
)
7751 #ifdef HAVE_consttable_1
7753 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7757 #ifdef HAVE_consttable_2
7759 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7763 #ifdef HAVE_consttable_4
7765 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7769 #ifdef HAVE_consttable_8
7771 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7784 minipool_vector_head
= minipool_vector_tail
= NULL
;
7785 scan
= emit_insn_after (gen_consttable_end (), scan
);
7786 scan
= emit_barrier_after (scan
);
7789 /* Return the cost of forcibly inserting a barrier after INSN. */
7791 arm_barrier_cost (rtx insn
)
7793 /* Basing the location of the pool on the loop depth is preferable,
7794 but at the moment, the basic block information seems to be
7795 corrupt by this stage of the compilation. */
7797 rtx next
= next_nonnote_insn (insn
);
7799 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7802 switch (GET_CODE (insn
))
7805 /* It will always be better to place the table before the label, rather
7814 return base_cost
- 10;
7817 return base_cost
+ 10;
7821 /* Find the best place in the insn stream in the range
7822 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7823 Create the barrier by inserting a jump and add a new fix entry for
7826 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7828 HOST_WIDE_INT count
= 0;
7830 rtx from
= fix
->insn
;
7831 rtx selected
= from
;
7833 HOST_WIDE_INT selected_address
;
7835 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7836 rtx label
= gen_label_rtx ();
7838 selected_cost
= arm_barrier_cost (from
);
7839 selected_address
= fix
->address
;
7841 while (from
&& count
< max_count
)
7846 /* This code shouldn't have been called if there was a natural barrier
7848 gcc_assert (GET_CODE (from
) != BARRIER
);
7850 /* Count the length of this insn. */
7851 count
+= get_attr_length (from
);
7853 /* If there is a jump table, add its length. */
7854 tmp
= is_jump_table (from
);
7857 count
+= get_jump_table_size (tmp
);
7859 /* Jump tables aren't in a basic block, so base the cost on
7860 the dispatch insn. If we select this location, we will
7861 still put the pool after the table. */
7862 new_cost
= arm_barrier_cost (from
);
7864 if (count
< max_count
&& new_cost
<= selected_cost
)
7867 selected_cost
= new_cost
;
7868 selected_address
= fix
->address
+ count
;
7871 /* Continue after the dispatch table. */
7872 from
= NEXT_INSN (tmp
);
7876 new_cost
= arm_barrier_cost (from
);
7878 if (count
< max_count
&& new_cost
<= selected_cost
)
7881 selected_cost
= new_cost
;
7882 selected_address
= fix
->address
+ count
;
7885 from
= NEXT_INSN (from
);
7888 /* Create a new JUMP_INSN that branches around a barrier. */
7889 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7890 JUMP_LABEL (from
) = label
;
7891 barrier
= emit_barrier_after (from
);
7892 emit_label_after (label
, barrier
);
7894 /* Create a minipool barrier entry for the new barrier. */
7895 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7896 new_fix
->insn
= barrier
;
7897 new_fix
->address
= selected_address
;
7898 new_fix
->next
= fix
->next
;
7899 fix
->next
= new_fix
;
7904 /* Record that there is a natural barrier in the insn stream at
7907 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7909 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7912 fix
->address
= address
;
7915 if (minipool_fix_head
!= NULL
)
7916 minipool_fix_tail
->next
= fix
;
7918 minipool_fix_head
= fix
;
7920 minipool_fix_tail
= fix
;
7923 /* Record INSN, which will need fixing up to load a value from the
7924 minipool. ADDRESS is the offset of the insn since the start of the
7925 function; LOC is a pointer to the part of the insn which requires
7926 fixing; VALUE is the constant that must be loaded, which is of type
7929 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7930 enum machine_mode mode
, rtx value
)
7932 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7934 #ifdef AOF_ASSEMBLER
7935 /* PIC symbol references need to be converted into offsets into the
7937 /* XXX This shouldn't be done here. */
7938 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7939 value
= aof_pic_entry (value
);
7940 #endif /* AOF_ASSEMBLER */
7943 fix
->address
= address
;
7946 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7948 fix
->forwards
= get_attr_pool_range (insn
);
7949 fix
->backwards
= get_attr_neg_pool_range (insn
);
7950 fix
->minipool
= NULL
;
7952 /* If an insn doesn't have a range defined for it, then it isn't
7953 expecting to be reworked by this code. Better to stop now than
7954 to generate duff assembly code. */
7955 gcc_assert (fix
->forwards
|| fix
->backwards
);
7957 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7958 So there might be an empty word before the start of the pool.
7959 Hence we reduce the forward range by 4 to allow for this
7961 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7967 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7968 GET_MODE_NAME (mode
),
7969 INSN_UID (insn
), (unsigned long) address
,
7970 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7971 arm_print_value (dump_file
, fix
->value
);
7972 fprintf (dump_file
, "\n");
7975 /* Add it to the chain of fixes. */
7978 if (minipool_fix_head
!= NULL
)
7979 minipool_fix_tail
->next
= fix
;
7981 minipool_fix_head
= fix
;
7983 minipool_fix_tail
= fix
;
7986 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7987 Returns the number of insns needed, or 99 if we don't know how to
7990 arm_const_double_inline_cost (rtx val
)
7992 rtx lowpart
, highpart
;
7993 enum machine_mode mode
;
7995 mode
= GET_MODE (val
);
7997 if (mode
== VOIDmode
)
8000 gcc_assert (GET_MODE_SIZE (mode
) == 8);
8002 lowpart
= gen_lowpart (SImode
, val
);
8003 highpart
= gen_highpart_mode (SImode
, mode
, val
);
8005 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
8006 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
8008 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
8009 NULL_RTX
, NULL_RTX
, 0, 0)
8010 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
8011 NULL_RTX
, NULL_RTX
, 0, 0));
8014 /* Return true if it is worthwhile to split a 64-bit constant into two
8015 32-bit operations. This is the case if optimizing for size, or
8016 if we have load delay slots, or if one 32-bit part can be done with
8017 a single data operation. */
8019 arm_const_double_by_parts (rtx val
)
8021 enum machine_mode mode
= GET_MODE (val
);
8024 if (optimize_size
|| arm_ld_sched
)
8027 if (mode
== VOIDmode
)
8030 part
= gen_highpart_mode (SImode
, mode
, val
);
8032 gcc_assert (GET_CODE (part
) == CONST_INT
);
8034 if (const_ok_for_arm (INTVAL (part
))
8035 || const_ok_for_arm (~INTVAL (part
)))
8038 part
= gen_lowpart (SImode
, val
);
8040 gcc_assert (GET_CODE (part
) == CONST_INT
);
8042 if (const_ok_for_arm (INTVAL (part
))
8043 || const_ok_for_arm (~INTVAL (part
)))
8049 /* Scan INSN and note any of its operands that need fixing.
8050 If DO_PUSHES is false we do not actually push any of the fixups
8051 needed. The function returns TRUE if any fixups were needed/pushed.
8052 This is used by arm_memory_load_p() which needs to know about loads
8053 of constants that will be converted into minipool loads. */
8055 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8057 bool result
= false;
8060 extract_insn (insn
);
8062 if (!constrain_operands (1))
8063 fatal_insn_not_found (insn
);
8065 if (recog_data
.n_alternatives
== 0)
8068 /* Fill in recog_op_alt with information about the constraints of
8070 preprocess_constraints ();
8072 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8074 /* Things we need to fix can only occur in inputs. */
8075 if (recog_data
.operand_type
[opno
] != OP_IN
)
8078 /* If this alternative is a memory reference, then any mention
8079 of constants in this alternative is really to fool reload
8080 into allowing us to accept one there. We need to fix them up
8081 now so that we output the right code. */
8082 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8084 rtx op
= recog_data
.operand
[opno
];
8086 if (CONSTANT_P (op
))
8089 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8090 recog_data
.operand_mode
[opno
], op
);
8093 else if (GET_CODE (op
) == MEM
8094 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8095 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8099 rtx cop
= avoid_constant_pool_reference (op
);
8101 /* Casting the address of something to a mode narrower
8102 than a word can cause avoid_constant_pool_reference()
8103 to return the pool reference itself. That's no good to
8104 us here. Lets just hope that we can use the
8105 constant pool value directly. */
8107 cop
= get_pool_constant (XEXP (op
, 0));
8109 push_minipool_fix (insn
, address
,
8110 recog_data
.operand_loc
[opno
],
8111 recog_data
.operand_mode
[opno
], cop
);
8122 /* Gcc puts the pool in the wrong place for ARM, since we can only
8123 load addresses a limited distance around the pc. We do some
8124 special munging to move the constant pool values to the correct
8125 point in the code. */
8130 HOST_WIDE_INT address
= 0;
8133 minipool_fix_head
= minipool_fix_tail
= NULL
;
8135 /* The first insn must always be a note, or the code below won't
8136 scan it properly. */
8137 insn
= get_insns ();
8138 gcc_assert (GET_CODE (insn
) == NOTE
);
8140 /* Scan all the insns and record the operands that will need fixing. */
8141 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8143 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8144 && (arm_cirrus_insn_p (insn
)
8145 || GET_CODE (insn
) == JUMP_INSN
8146 || arm_memory_load_p (insn
)))
8147 cirrus_reorg (insn
);
8149 if (GET_CODE (insn
) == BARRIER
)
8150 push_minipool_barrier (insn
, address
);
8151 else if (INSN_P (insn
))
8155 note_invalid_constants (insn
, address
, true);
8156 address
+= get_attr_length (insn
);
8158 /* If the insn is a vector jump, add the size of the table
8159 and skip the table. */
8160 if ((table
= is_jump_table (insn
)) != NULL
)
8162 address
+= get_jump_table_size (table
);
8168 fix
= minipool_fix_head
;
8170 /* Now scan the fixups and perform the required changes. */
8175 Mfix
* last_added_fix
;
8176 Mfix
* last_barrier
= NULL
;
8179 /* Skip any further barriers before the next fix. */
8180 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8183 /* No more fixes. */
8187 last_added_fix
= NULL
;
8189 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8191 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8193 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8196 last_barrier
= ftmp
;
8198 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8201 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8204 /* If we found a barrier, drop back to that; any fixes that we
8205 could have reached but come after the barrier will now go in
8206 the next mini-pool. */
8207 if (last_barrier
!= NULL
)
8209 /* Reduce the refcount for those fixes that won't go into this
8211 for (fdel
= last_barrier
->next
;
8212 fdel
&& fdel
!= ftmp
;
8215 fdel
->minipool
->refcount
--;
8216 fdel
->minipool
= NULL
;
8219 ftmp
= last_barrier
;
8223 /* ftmp is first fix that we can't fit into this pool and
8224 there no natural barriers that we could use. Insert a
8225 new barrier in the code somewhere between the previous
8226 fix and this one, and arrange to jump around it. */
8227 HOST_WIDE_INT max_address
;
8229 /* The last item on the list of fixes must be a barrier, so
8230 we can never run off the end of the list of fixes without
8231 last_barrier being set. */
8234 max_address
= minipool_vector_head
->max_address
;
8235 /* Check that there isn't another fix that is in range that
8236 we couldn't fit into this pool because the pool was
8237 already too large: we need to put the pool before such an
8239 if (ftmp
->address
< max_address
)
8240 max_address
= ftmp
->address
;
8242 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8245 assign_minipool_offsets (last_barrier
);
8249 if (GET_CODE (ftmp
->insn
) != BARRIER
8250 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8257 /* Scan over the fixes we have identified for this pool, fixing them
8258 up and adding the constants to the pool itself. */
8259 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8260 this_fix
= this_fix
->next
)
8261 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8264 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8265 minipool_vector_label
),
8266 this_fix
->minipool
->offset
);
8267 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8270 dump_minipool (last_barrier
->insn
);
8274 /* From now on we must synthesize any constants that we can't handle
8275 directly. This can happen if the RTL gets split during final
8276 instruction generation. */
8277 after_arm_reorg
= 1;
8279 /* Free the minipool memory. */
8280 obstack_free (&minipool_obstack
, minipool_startobj
);
8283 /* Routines to output assembly language. */
8285 /* If the rtx is the correct value then return the string of the number.
8286 In this way we can ensure that valid double constants are generated even
8287 when cross compiling. */
8289 fp_immediate_constant (rtx x
)
8294 if (!fp_consts_inited
)
8297 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8298 for (i
= 0; i
< 8; i
++)
8299 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8300 return strings_fp
[i
];
8305 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8307 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8311 if (!fp_consts_inited
)
8314 for (i
= 0; i
< 8; i
++)
8315 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8316 return strings_fp
[i
];
8321 /* Output the operands of a LDM/STM instruction to STREAM.
8322 MASK is the ARM register set mask of which only bits 0-15 are important.
8323 REG is the base register, either the frame pointer or the stack pointer,
8324 INSTR is the possibly suffixed load or store instruction. */
8327 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8331 bool not_first
= FALSE
;
8333 fputc ('\t', stream
);
8334 asm_fprintf (stream
, instr
, reg
);
8335 fputs (", {", stream
);
8337 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8338 if (mask
& (1 << i
))
8341 fprintf (stream
, ", ");
8343 asm_fprintf (stream
, "%r", i
);
8347 fprintf (stream
, "}\n");
8351 /* Output a FLDMX instruction to STREAM.
8352 BASE if the register containing the address.
8353 REG and COUNT specify the register range.
8354 Extra registers may be added to avoid hardware bugs. */
8357 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
8361 /* Workaround ARM10 VFPr1 bug. */
8362 if (count
== 2 && !arm_arch6
)
8369 fputc ('\t', stream
);
8370 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
8372 for (i
= reg
; i
< reg
+ count
; i
++)
8375 fputs (", ", stream
);
8376 asm_fprintf (stream
, "d%d", i
);
8378 fputs ("}\n", stream
);
8383 /* Output the assembly for a store multiple. */
8386 vfp_output_fstmx (rtx
* operands
)
8393 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8394 p
= strlen (pattern
);
8396 gcc_assert (GET_CODE (operands
[1]) == REG
);
8398 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8399 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8401 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8403 strcpy (&pattern
[p
], "}");
8405 output_asm_insn (pattern
, operands
);
8410 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8411 number of bytes pushed. */
8414 vfp_emit_fstmx (int base_reg
, int count
)
8421 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8422 register pairs are stored by a store multiple insn. We avoid this
8423 by pushing an extra pair. */
8424 if (count
== 2 && !arm_arch6
)
8426 if (base_reg
== LAST_VFP_REGNUM
- 3)
8431 /* ??? The frame layout is implementation defined. We describe
8432 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8433 We really need some way of representing the whole block so that the
8434 unwinder can figure it out at runtime. */
8435 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8436 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8438 reg
= gen_rtx_REG (DFmode
, base_reg
);
8442 = gen_rtx_SET (VOIDmode
,
8443 gen_frame_mem (BLKmode
,
8444 gen_rtx_PRE_DEC (BLKmode
,
8445 stack_pointer_rtx
)),
8446 gen_rtx_UNSPEC (BLKmode
,
8450 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8451 plus_constant (stack_pointer_rtx
, -(count
* 8 + 4)));
8452 RTX_FRAME_RELATED_P (tmp
) = 1;
8453 XVECEXP (dwarf
, 0, 0) = tmp
;
8455 tmp
= gen_rtx_SET (VOIDmode
,
8456 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8458 RTX_FRAME_RELATED_P (tmp
) = 1;
8459 XVECEXP (dwarf
, 0, 1) = tmp
;
8461 for (i
= 1; i
< count
; i
++)
8463 reg
= gen_rtx_REG (DFmode
, base_reg
);
8465 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8467 tmp
= gen_rtx_SET (VOIDmode
,
8468 gen_frame_mem (DFmode
,
8469 plus_constant (stack_pointer_rtx
,
8472 RTX_FRAME_RELATED_P (tmp
) = 1;
8473 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8476 par
= emit_insn (par
);
8477 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8479 RTX_FRAME_RELATED_P (par
) = 1;
8481 return count
* 8 + 4;
8485 /* Output a 'call' insn. */
8487 output_call (rtx
*operands
)
8489 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8491 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8492 if (REGNO (operands
[0]) == LR_REGNUM
)
8494 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8495 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8498 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8500 if (TARGET_INTERWORK
|| arm_arch4t
)
8501 output_asm_insn ("bx%?\t%0", operands
);
8503 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8508 /* Output a 'call' insn that is a reference in memory. */
8510 output_call_mem (rtx
*operands
)
8512 if (TARGET_INTERWORK
&& !arm_arch5
)
8514 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8515 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8516 output_asm_insn ("bx%?\t%|ip", operands
);
8518 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8520 /* LR is used in the memory address. We load the address in the
8521 first instruction. It's safe to use IP as the target of the
8522 load since the call will kill it anyway. */
8523 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8525 output_asm_insn ("blx%?\t%|ip", operands
);
8528 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8530 output_asm_insn ("bx%?\t%|ip", operands
);
8532 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8537 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8538 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8545 /* Output a move from arm registers to an fpa registers.
8546 OPERANDS[0] is an fpa register.
8547 OPERANDS[1] is the first registers of an arm register pair. */
8549 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8551 int arm_reg0
= REGNO (operands
[1]);
8554 gcc_assert (arm_reg0
!= IP_REGNUM
);
8556 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8557 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8558 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8560 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8561 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8566 /* Output a move from an fpa register to arm registers.
8567 OPERANDS[0] is the first registers of an arm register pair.
8568 OPERANDS[1] is an fpa register. */
8570 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8572 int arm_reg0
= REGNO (operands
[0]);
8575 gcc_assert (arm_reg0
!= IP_REGNUM
);
8577 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8578 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8579 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8581 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8582 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8586 /* Output a move from arm registers to arm registers of a long double
8587 OPERANDS[0] is the destination.
8588 OPERANDS[1] is the source. */
8590 output_mov_long_double_arm_from_arm (rtx
*operands
)
8592 /* We have to be careful here because the two might overlap. */
8593 int dest_start
= REGNO (operands
[0]);
8594 int src_start
= REGNO (operands
[1]);
8598 if (dest_start
< src_start
)
8600 for (i
= 0; i
< 3; i
++)
8602 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8603 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8604 output_asm_insn ("mov%?\t%0, %1", ops
);
8609 for (i
= 2; i
>= 0; i
--)
8611 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8612 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8613 output_asm_insn ("mov%?\t%0, %1", ops
);
8621 /* Output a move from arm registers to an fpa registers.
8622 OPERANDS[0] is an fpa register.
8623 OPERANDS[1] is the first registers of an arm register pair. */
8625 output_mov_double_fpa_from_arm (rtx
*operands
)
8627 int arm_reg0
= REGNO (operands
[1]);
8630 gcc_assert (arm_reg0
!= IP_REGNUM
);
8632 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8633 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8634 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8635 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8639 /* Output a move from an fpa register to arm registers.
8640 OPERANDS[0] is the first registers of an arm register pair.
8641 OPERANDS[1] is an fpa register. */
8643 output_mov_double_arm_from_fpa (rtx
*operands
)
8645 int arm_reg0
= REGNO (operands
[0]);
8648 gcc_assert (arm_reg0
!= IP_REGNUM
);
8650 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8651 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8652 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8653 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8657 /* Output a move between double words.
8658 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8659 or MEM<-REG and all MEMs must be offsettable addresses. */
8661 output_move_double (rtx
*operands
)
8663 enum rtx_code code0
= GET_CODE (operands
[0]);
8664 enum rtx_code code1
= GET_CODE (operands
[1]);
8669 int reg0
= REGNO (operands
[0]);
8671 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8673 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
8675 switch (GET_CODE (XEXP (operands
[1], 0)))
8678 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8682 gcc_assert (TARGET_LDRD
);
8683 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8687 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8691 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8695 gcc_assert (TARGET_LDRD
);
8696 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8701 otherops
[0] = operands
[0];
8702 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8703 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8705 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8707 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8709 /* Registers overlap so split out the increment. */
8710 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8711 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8714 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8718 /* We only allow constant increments, so this is safe. */
8719 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8725 output_asm_insn ("adr%?\t%0, %1", operands
);
8726 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8730 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8731 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8733 otherops
[0] = operands
[0];
8734 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8735 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8737 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8739 if (GET_CODE (otherops
[2]) == CONST_INT
)
8741 switch ((int) INTVAL (otherops
[2]))
8744 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8747 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8750 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8755 && (GET_CODE (otherops
[2]) == REG
8756 || (GET_CODE (otherops
[2]) == CONST_INT
8757 && INTVAL (otherops
[2]) > -256
8758 && INTVAL (otherops
[2]) < 256)))
8760 if (reg_overlap_mentioned_p (otherops
[0],
8763 /* Swap base and index registers over to
8764 avoid a conflict. */
8765 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8766 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8768 /* If both registers conflict, it will usually
8769 have been fixed by a splitter. */
8770 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8772 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8773 output_asm_insn ("ldr%?d\t%0, [%1]",
8777 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops
);
8781 if (GET_CODE (otherops
[2]) == CONST_INT
)
8783 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8784 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8786 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8789 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8792 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8794 return "ldm%?ia\t%0, %M0";
8798 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8799 /* Take care of overlapping base/data reg. */
8800 if (reg_mentioned_p (operands
[0], operands
[1]))
8802 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8803 output_asm_insn ("ldr%?\t%0, %1", operands
);
8807 output_asm_insn ("ldr%?\t%0, %1", operands
);
8808 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8815 /* Constraints should ensure this. */
8816 gcc_assert (code0
== MEM
&& code1
== REG
);
8817 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
8819 switch (GET_CODE (XEXP (operands
[0], 0)))
8822 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8826 gcc_assert (TARGET_LDRD
);
8827 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8831 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8835 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8839 gcc_assert (TARGET_LDRD
);
8840 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8845 otherops
[0] = operands
[1];
8846 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8847 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8849 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8850 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8852 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8856 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8857 if (GET_CODE (otherops
[2]) == CONST_INT
)
8859 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8862 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8866 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8870 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8875 && (GET_CODE (otherops
[2]) == REG
8876 || (GET_CODE (otherops
[2]) == CONST_INT
8877 && INTVAL (otherops
[2]) > -256
8878 && INTVAL (otherops
[2]) < 256)))
8880 otherops
[0] = operands
[1];
8881 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8882 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8888 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8889 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8890 output_asm_insn ("str%?\t%1, %0", operands
);
8891 output_asm_insn ("str%?\t%1, %0", otherops
);
8898 /* Output an ADD r, s, #n where n may be too big for one instruction.
8899 If adding zero to one register, output nothing. */
8901 output_add_immediate (rtx
*operands
)
8903 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8905 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8908 output_multi_immediate (operands
,
8909 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8912 output_multi_immediate (operands
,
8913 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8920 /* Output a multiple immediate operation.
8921 OPERANDS is the vector of operands referred to in the output patterns.
8922 INSTR1 is the output pattern to use for the first constant.
8923 INSTR2 is the output pattern to use for subsequent constants.
8924 IMMED_OP is the index of the constant slot in OPERANDS.
8925 N is the constant value. */
8927 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8928 int immed_op
, HOST_WIDE_INT n
)
8930 #if HOST_BITS_PER_WIDE_INT > 32
8936 /* Quick and easy output. */
8937 operands
[immed_op
] = const0_rtx
;
8938 output_asm_insn (instr1
, operands
);
8943 const char * instr
= instr1
;
8945 /* Note that n is never zero here (which would give no output). */
8946 for (i
= 0; i
< 32; i
+= 2)
8950 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8951 output_asm_insn (instr
, operands
);
8961 /* Return the appropriate ARM instruction for the operation code.
8962 The returned result should not be overwritten. OP is the rtx of the
8963 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8966 arithmetic_instr (rtx op
, int shift_first_arg
)
8968 switch (GET_CODE (op
))
8974 return shift_first_arg
? "rsb" : "sub";
8990 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8991 for the operation code. The returned result should not be overwritten.
8992 OP is the rtx code of the shift.
8993 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8996 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8999 enum rtx_code code
= GET_CODE (op
);
9001 switch (GET_CODE (XEXP (op
, 1)))
9009 *amountp
= INTVAL (XEXP (op
, 1));
9031 gcc_assert (*amountp
!= -1);
9032 *amountp
= 32 - *amountp
;
9041 /* We never have to worry about the amount being other than a
9042 power of 2, since this case can never be reloaded from a reg. */
9043 gcc_assert (*amountp
!= -1);
9044 *amountp
= int_log2 (*amountp
);
9053 /* This is not 100% correct, but follows from the desire to merge
9054 multiplication by a power of 2 with the recognizer for a
9055 shift. >=32 is not a valid shift for "asl", so we must try and
9056 output a shift that produces the correct arithmetical result.
9057 Using lsr #32 is identical except for the fact that the carry bit
9058 is not set correctly if we set the flags; but we never use the
9059 carry bit from such an operation, so we can ignore that. */
9060 if (code
== ROTATERT
)
9061 /* Rotate is just modulo 32. */
9063 else if (*amountp
!= (*amountp
& 31))
9070 /* Shifts of 0 are no-ops. */
9078 /* Obtain the shift from the POWER of two. */
9080 static HOST_WIDE_INT
9081 int_log2 (HOST_WIDE_INT power
)
9083 HOST_WIDE_INT shift
= 0;
9085 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9087 gcc_assert (shift
<= 31);
9094 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9095 because /bin/as is horribly restrictive. The judgement about
9096 whether or not each character is 'printable' (and can be output as
9097 is) or not (and must be printed with an octal escape) must be made
9098 with reference to the *host* character set -- the situation is
9099 similar to that discussed in the comments above pp_c_char in
9100 c-pretty-print.c. */
9102 #define MAX_ASCII_LEN 51
9105 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9110 fputs ("\t.ascii\t\"", stream
);
9112 for (i
= 0; i
< len
; i
++)
9116 if (len_so_far
>= MAX_ASCII_LEN
)
9118 fputs ("\"\n\t.ascii\t\"", stream
);
9124 if (c
== '\\' || c
== '\"')
9126 putc ('\\', stream
);
9134 fprintf (stream
, "\\%03o", c
);
9139 fputs ("\"\n", stream
);
9142 /* Compute the register save mask for registers 0 through 12
9143 inclusive. This code is used by arm_compute_save_reg_mask. */
9145 static unsigned long
9146 arm_compute_save_reg0_reg12_mask (void)
9148 unsigned long func_type
= arm_current_func_type ();
9149 unsigned long save_reg_mask
= 0;
9152 if (IS_INTERRUPT (func_type
))
9154 unsigned int max_reg
;
9155 /* Interrupt functions must not corrupt any registers,
9156 even call clobbered ones. If this is a leaf function
9157 we can just examine the registers used by the RTL, but
9158 otherwise we have to assume that whatever function is
9159 called might clobber anything, and so we have to save
9160 all the call-clobbered registers as well. */
9161 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9162 /* FIQ handlers have registers r8 - r12 banked, so
9163 we only need to check r0 - r7, Normal ISRs only
9164 bank r14 and r15, so we must check up to r12.
9165 r13 is the stack pointer which is always preserved,
9166 so we do not need to consider it here. */
9171 for (reg
= 0; reg
<= max_reg
; reg
++)
9172 if (regs_ever_live
[reg
]
9173 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9174 save_reg_mask
|= (1 << reg
);
9176 /* Also save the pic base register if necessary. */
9178 && !TARGET_SINGLE_PIC_BASE
9179 && current_function_uses_pic_offset_table
)
9180 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9184 /* In the normal case we only need to save those registers
9185 which are call saved and which are used by this function. */
9186 for (reg
= 0; reg
<= 10; reg
++)
9187 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9188 save_reg_mask
|= (1 << reg
);
9190 /* Handle the frame pointer as a special case. */
9191 if (! TARGET_APCS_FRAME
9192 && ! frame_pointer_needed
9193 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9194 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9195 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9197 /* If we aren't loading the PIC register,
9198 don't stack it even though it may be live. */
9200 && !TARGET_SINGLE_PIC_BASE
9201 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9202 || current_function_uses_pic_offset_table
))
9203 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9206 /* Save registers so the exception handler can modify them. */
9207 if (current_function_calls_eh_return
)
9213 reg
= EH_RETURN_DATA_REGNO (i
);
9214 if (reg
== INVALID_REGNUM
)
9216 save_reg_mask
|= 1 << reg
;
9220 return save_reg_mask
;
9223 /* Compute a bit mask of which registers need to be
9224 saved on the stack for the current function. */
9226 static unsigned long
9227 arm_compute_save_reg_mask (void)
9229 unsigned int save_reg_mask
= 0;
9230 unsigned long func_type
= arm_current_func_type ();
9232 if (IS_NAKED (func_type
))
9233 /* This should never really happen. */
9236 /* If we are creating a stack frame, then we must save the frame pointer,
9237 IP (which will hold the old stack pointer), LR and the PC. */
9238 if (frame_pointer_needed
)
9240 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9245 /* Volatile functions do not return, so there
9246 is no need to save any other registers. */
9247 if (IS_VOLATILE (func_type
))
9248 return save_reg_mask
;
9250 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9252 /* Decide if we need to save the link register.
9253 Interrupt routines have their own banked link register,
9254 so they never need to save it.
9255 Otherwise if we do not use the link register we do not need to save
9256 it. If we are pushing other registers onto the stack however, we
9257 can save an instruction in the epilogue by pushing the link register
9258 now and then popping it back into the PC. This incurs extra memory
9259 accesses though, so we only do it when optimizing for size, and only
9260 if we know that we will not need a fancy return sequence. */
9261 if (regs_ever_live
[LR_REGNUM
]
9264 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9265 && !current_function_calls_eh_return
))
9266 save_reg_mask
|= 1 << LR_REGNUM
;
9268 if (cfun
->machine
->lr_save_eliminated
)
9269 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9271 if (TARGET_REALLY_IWMMXT
9272 && ((bit_count (save_reg_mask
)
9273 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9277 /* The total number of registers that are going to be pushed
9278 onto the stack is odd. We need to ensure that the stack
9279 is 64-bit aligned before we start to save iWMMXt registers,
9280 and also before we start to create locals. (A local variable
9281 might be a double or long long which we will load/store using
9282 an iWMMXt instruction). Therefore we need to push another
9283 ARM register, so that the stack will be 64-bit aligned. We
9284 try to avoid using the arg registers (r0 -r3) as they might be
9285 used to pass values in a tail call. */
9286 for (reg
= 4; reg
<= 12; reg
++)
9287 if ((save_reg_mask
& (1 << reg
)) == 0)
9291 save_reg_mask
|= (1 << reg
);
9294 cfun
->machine
->sibcall_blocked
= 1;
9295 save_reg_mask
|= (1 << 3);
9299 return save_reg_mask
;
9303 /* Compute a bit mask of which registers need to be
9304 saved on the stack for the current function. */
9305 static unsigned long
9306 thumb_compute_save_reg_mask (void)
9312 for (reg
= 0; reg
< 12; reg
++)
9313 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9317 && !TARGET_SINGLE_PIC_BASE
9318 && current_function_uses_pic_offset_table
)
9319 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9321 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9322 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9323 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9325 /* LR will also be pushed if any lo regs are pushed. */
9326 if (mask
& 0xff || thumb_force_lr_save ())
9327 mask
|= (1 << LR_REGNUM
);
9329 /* Make sure we have a low work register if we need one.
9330 We will need one if we are going to push a high register,
9331 but we are not currently intending to push a low register. */
9332 if ((mask
& 0xff) == 0
9333 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9335 /* Use thumb_find_work_register to choose which register
9336 we will use. If the register is live then we will
9337 have to push it. Use LAST_LO_REGNUM as our fallback
9338 choice for the register to select. */
9339 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9341 if (! call_used_regs
[reg
])
9349 /* Return the number of bytes required to save VFP registers. */
9351 arm_get_vfp_saved_size (void)
9358 /* Space for saved VFP registers. */
9359 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9362 for (regno
= FIRST_VFP_REGNUM
;
9363 regno
< LAST_VFP_REGNUM
;
9366 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9367 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9371 /* Workaround ARM10 VFPr1 bug. */
9372 if (count
== 2 && !arm_arch6
)
9374 saved
+= count
* 8 + 4;
9383 if (count
== 2 && !arm_arch6
)
9385 saved
+= count
* 8 + 4;
9392 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9393 everything bar the final return instruction. */
9395 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9397 char conditional
[10];
9400 unsigned long live_regs_mask
;
9401 unsigned long func_type
;
9402 arm_stack_offsets
*offsets
;
9404 func_type
= arm_current_func_type ();
9406 if (IS_NAKED (func_type
))
9409 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9411 /* If this function was declared non-returning, and we have
9412 found a tail call, then we have to trust that the called
9413 function won't return. */
9418 /* Otherwise, trap an attempted return by aborting. */
9420 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9422 assemble_external_libcall (ops
[1]);
9423 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9429 gcc_assert (!current_function_calls_alloca
|| really_return
);
9431 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9433 return_used_this_function
= 1;
9435 live_regs_mask
= arm_compute_save_reg_mask ();
9439 const char * return_reg
;
9441 /* If we do not have any special requirements for function exit
9442 (e.g. interworking, or ISR) then we can load the return address
9443 directly into the PC. Otherwise we must load it into LR. */
9445 && ! TARGET_INTERWORK
)
9446 return_reg
= reg_names
[PC_REGNUM
];
9448 return_reg
= reg_names
[LR_REGNUM
];
9450 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9452 /* There are three possible reasons for the IP register
9453 being saved. 1) a stack frame was created, in which case
9454 IP contains the old stack pointer, or 2) an ISR routine
9455 corrupted it, or 3) it was saved to align the stack on
9456 iWMMXt. In case 1, restore IP into SP, otherwise just
9458 if (frame_pointer_needed
)
9460 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9461 live_regs_mask
|= (1 << SP_REGNUM
);
9464 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
9467 /* On some ARM architectures it is faster to use LDR rather than
9468 LDM to load a single register. On other architectures, the
9469 cost is the same. In 26 bit mode, or for exception handlers,
9470 we have to use LDM to load the PC so that the CPSR is also
9472 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9473 if (live_regs_mask
== (1U << reg
))
9476 if (reg
<= LAST_ARM_REGNUM
9477 && (reg
!= LR_REGNUM
9479 || ! IS_INTERRUPT (func_type
)))
9481 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9482 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9489 /* Generate the load multiple instruction to restore the
9490 registers. Note we can get here, even if
9491 frame_pointer_needed is true, but only if sp already
9492 points to the base of the saved core registers. */
9493 if (live_regs_mask
& (1 << SP_REGNUM
))
9495 unsigned HOST_WIDE_INT stack_adjust
;
9497 offsets
= arm_get_frame_offsets ();
9498 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9499 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
9501 if (stack_adjust
&& arm_arch5
)
9502 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9505 /* If we can't use ldmib (SA110 bug),
9506 then try to pop r3 instead. */
9508 live_regs_mask
|= 1 << 3;
9509 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9513 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9515 p
= instr
+ strlen (instr
);
9517 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9518 if (live_regs_mask
& (1 << reg
))
9520 int l
= strlen (reg_names
[reg
]);
9526 memcpy (p
, ", ", 2);
9530 memcpy (p
, "%|", 2);
9531 memcpy (p
+ 2, reg_names
[reg
], l
);
9535 if (live_regs_mask
& (1 << LR_REGNUM
))
9537 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9538 /* If returning from an interrupt, restore the CPSR. */
9539 if (IS_INTERRUPT (func_type
))
9546 output_asm_insn (instr
, & operand
);
9548 /* See if we need to generate an extra instruction to
9549 perform the actual function return. */
9551 && func_type
!= ARM_FT_INTERWORKED
9552 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9554 /* The return has already been handled
9555 by loading the LR into the PC. */
9562 switch ((int) ARM_FUNC_TYPE (func_type
))
9566 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9569 case ARM_FT_INTERWORKED
:
9570 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9573 case ARM_FT_EXCEPTION
:
9574 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9578 /* Use bx if it's available. */
9579 if (arm_arch5
|| arm_arch4t
)
9580 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9582 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9586 output_asm_insn (instr
, & operand
);
9592 /* Write the function name into the code section, directly preceding
9593 the function prologue.
9595 Code will be output similar to this:
9597 .ascii "arm_poke_function_name", 0
9600 .word 0xff000000 + (t1 - t0)
9601 arm_poke_function_name
9603 stmfd sp!, {fp, ip, lr, pc}
9606 When performing a stack backtrace, code can inspect the value
9607 of 'pc' stored at 'fp' + 0. If the trace function then looks
9608 at location pc - 12 and the top 8 bits are set, then we know
9609 that there is a function name embedded immediately preceding this
9610 location and has length ((pc[-3]) & 0xff000000).
9612 We assume that pc is declared as a pointer to an unsigned long.
9614 It is of no benefit to output the function name if we are assembling
9615 a leaf function. These function types will not contain a stack
9616 backtrace structure, therefore it is not possible to determine the
9619 arm_poke_function_name (FILE *stream
, const char *name
)
9621 unsigned long alignlength
;
9622 unsigned long length
;
9625 length
= strlen (name
) + 1;
9626 alignlength
= ROUND_UP_WORD (length
);
9628 ASM_OUTPUT_ASCII (stream
, name
, length
);
9629 ASM_OUTPUT_ALIGN (stream
, 2);
9630 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9631 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9634 /* Place some comments into the assembler stream
9635 describing the current function. */
9637 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9639 unsigned long func_type
;
9643 thumb_output_function_prologue (f
, frame_size
);
9648 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
9650 func_type
= arm_current_func_type ();
9652 switch ((int) ARM_FUNC_TYPE (func_type
))
9657 case ARM_FT_INTERWORKED
:
9658 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9661 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9664 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9666 case ARM_FT_EXCEPTION
:
9667 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9671 if (IS_NAKED (func_type
))
9672 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9674 if (IS_VOLATILE (func_type
))
9675 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9677 if (IS_NESTED (func_type
))
9678 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9680 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9681 current_function_args_size
,
9682 current_function_pretend_args_size
, frame_size
);
9684 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9685 frame_pointer_needed
,
9686 cfun
->machine
->uses_anonymous_args
);
9688 if (cfun
->machine
->lr_save_eliminated
)
9689 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9691 if (current_function_calls_eh_return
)
9692 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9694 #ifdef AOF_ASSEMBLER
9696 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9699 return_used_this_function
= 0;
9703 arm_output_epilogue (rtx sibling
)
9706 unsigned long saved_regs_mask
;
9707 unsigned long func_type
;
9708 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9709 frame that is $fp + 4 for a non-variadic function. */
9710 int floats_offset
= 0;
9712 FILE * f
= asm_out_file
;
9713 unsigned int lrm_count
= 0;
9714 int really_return
= (sibling
== NULL
);
9716 arm_stack_offsets
*offsets
;
9718 /* If we have already generated the return instruction
9719 then it is futile to generate anything else. */
9720 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9723 func_type
= arm_current_func_type ();
9725 if (IS_NAKED (func_type
))
9726 /* Naked functions don't have epilogues. */
9729 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9733 /* A volatile function should never return. Call abort. */
9734 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9735 assemble_external_libcall (op
);
9736 output_asm_insn ("bl\t%a0", &op
);
9741 /* If we are throwing an exception, then we really must be doing a
9742 return, so we can't tail-call. */
9743 gcc_assert (!current_function_calls_eh_return
|| really_return
);
9745 offsets
= arm_get_frame_offsets ();
9746 saved_regs_mask
= arm_compute_save_reg_mask ();
9749 lrm_count
= bit_count (saved_regs_mask
);
9751 floats_offset
= offsets
->saved_args
;
9752 /* Compute how far away the floats will be. */
9753 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9754 if (saved_regs_mask
& (1 << reg
))
9757 if (frame_pointer_needed
)
9759 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9760 int vfp_offset
= offsets
->frame
;
9762 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9764 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9765 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9767 floats_offset
+= 12;
9768 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9769 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9774 start_reg
= LAST_FPA_REGNUM
;
9776 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9778 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9780 floats_offset
+= 12;
9782 /* We can't unstack more than four registers at once. */
9783 if (start_reg
- reg
== 3)
9785 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9786 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9787 start_reg
= reg
- 1;
9792 if (reg
!= start_reg
)
9793 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9794 reg
+ 1, start_reg
- reg
,
9795 FP_REGNUM
, floats_offset
- vfp_offset
);
9796 start_reg
= reg
- 1;
9800 /* Just in case the last register checked also needs unstacking. */
9801 if (reg
!= start_reg
)
9802 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9803 reg
+ 1, start_reg
- reg
,
9804 FP_REGNUM
, floats_offset
- vfp_offset
);
9807 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9811 /* The fldmx insn does not have base+offset addressing modes,
9812 so we use IP to hold the address. */
9813 saved_size
= arm_get_vfp_saved_size ();
9817 floats_offset
+= saved_size
;
9818 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9819 FP_REGNUM
, floats_offset
- vfp_offset
);
9821 start_reg
= FIRST_VFP_REGNUM
;
9822 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9824 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9825 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9827 if (start_reg
!= reg
)
9828 arm_output_fldmx (f
, IP_REGNUM
,
9829 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9830 (reg
- start_reg
) / 2);
9831 start_reg
= reg
+ 2;
9834 if (start_reg
!= reg
)
9835 arm_output_fldmx (f
, IP_REGNUM
,
9836 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9837 (reg
- start_reg
) / 2);
9842 /* The frame pointer is guaranteed to be non-double-word aligned.
9843 This is because it is set to (old_stack_pointer - 4) and the
9844 old_stack_pointer was double word aligned. Thus the offset to
9845 the iWMMXt registers to be loaded must also be non-double-word
9846 sized, so that the resultant address *is* double-word aligned.
9847 We can ignore floats_offset since that was already included in
9848 the live_regs_mask. */
9849 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9851 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9852 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9854 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9855 reg
, FP_REGNUM
, lrm_count
* 4);
9860 /* saved_regs_mask should contain the IP, which at the time of stack
9861 frame generation actually contains the old stack pointer. So a
9862 quick way to unwind the stack is just pop the IP register directly
9863 into the stack pointer. */
9864 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
9865 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9866 saved_regs_mask
|= (1 << SP_REGNUM
);
9868 /* There are two registers left in saved_regs_mask - LR and PC. We
9869 only need to restore the LR register (the return address), but to
9870 save time we can load it directly into the PC, unless we need a
9871 special function exit sequence, or we are not really returning. */
9873 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9874 && !current_function_calls_eh_return
)
9875 /* Delete the LR from the register mask, so that the LR on
9876 the stack is loaded into the PC in the register mask. */
9877 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9879 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9881 /* We must use SP as the base register, because SP is one of the
9882 registers being restored. If an interrupt or page fault
9883 happens in the ldm instruction, the SP might or might not
9884 have been restored. That would be bad, as then SP will no
9885 longer indicate the safe area of stack, and we can get stack
9886 corruption. Using SP as the base register means that it will
9887 be reset correctly to the original value, should an interrupt
9888 occur. If the stack pointer already points at the right
9889 place, then omit the subtraction. */
9890 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9891 || current_function_calls_alloca
)
9892 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9893 4 * bit_count (saved_regs_mask
));
9894 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9896 if (IS_INTERRUPT (func_type
))
9897 /* Interrupt handlers will have pushed the
9898 IP onto the stack, so restore it now. */
9899 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9903 /* Restore stack pointer if necessary. */
9904 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9906 operands
[0] = operands
[1] = stack_pointer_rtx
;
9907 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9908 output_add_immediate (operands
);
9911 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9913 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9914 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9915 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9920 start_reg
= FIRST_FPA_REGNUM
;
9922 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9924 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9926 if (reg
- start_reg
== 3)
9928 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9929 start_reg
, SP_REGNUM
);
9930 start_reg
= reg
+ 1;
9935 if (reg
!= start_reg
)
9936 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9937 start_reg
, reg
- start_reg
,
9940 start_reg
= reg
+ 1;
9944 /* Just in case the last register checked also needs unstacking. */
9945 if (reg
!= start_reg
)
9946 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9947 start_reg
, reg
- start_reg
, SP_REGNUM
);
9950 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9952 start_reg
= FIRST_VFP_REGNUM
;
9953 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9955 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9956 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9958 if (start_reg
!= reg
)
9959 arm_output_fldmx (f
, SP_REGNUM
,
9960 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9961 (reg
- start_reg
) / 2);
9962 start_reg
= reg
+ 2;
9965 if (start_reg
!= reg
)
9966 arm_output_fldmx (f
, SP_REGNUM
,
9967 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9968 (reg
- start_reg
) / 2);
9971 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9972 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9973 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9975 /* If we can, restore the LR into the PC. */
9976 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9978 && current_function_pretend_args_size
== 0
9979 && saved_regs_mask
& (1 << LR_REGNUM
)
9980 && !current_function_calls_eh_return
)
9982 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9983 saved_regs_mask
|= (1 << PC_REGNUM
);
9986 /* Load the registers off the stack. If we only have one register
9987 to load use the LDR instruction - it is faster. */
9988 if (saved_regs_mask
== (1 << LR_REGNUM
))
9990 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9992 else if (saved_regs_mask
)
9994 if (saved_regs_mask
& (1 << SP_REGNUM
))
9995 /* Note - write back to the stack register is not enabled
9996 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9997 in the list of registers and if we add writeback the
9998 instruction becomes UNPREDICTABLE. */
9999 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
10001 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
10004 if (current_function_pretend_args_size
)
10006 /* Unwind the pre-pushed regs. */
10007 operands
[0] = operands
[1] = stack_pointer_rtx
;
10008 operands
[2] = GEN_INT (current_function_pretend_args_size
);
10009 output_add_immediate (operands
);
10013 /* We may have already restored PC directly from the stack. */
10014 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10017 /* Stack adjustment for exception handler. */
10018 if (current_function_calls_eh_return
)
10019 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10020 ARM_EH_STACKADJ_REGNUM
);
10022 /* Generate the return instruction. */
10023 switch ((int) ARM_FUNC_TYPE (func_type
))
10027 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10030 case ARM_FT_EXCEPTION
:
10031 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10034 case ARM_FT_INTERWORKED
:
10035 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10039 if (arm_arch5
|| arm_arch4t
)
10040 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10042 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10050 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10051 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10053 arm_stack_offsets
*offsets
;
10059 /* Emit any call-via-reg trampolines that are needed for v4t support
10060 of call_reg and call_value_reg type insns. */
10061 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10063 rtx label
= cfun
->machine
->call_via
[regno
];
10067 function_section (current_function_decl
);
10068 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10069 CODE_LABEL_NUMBER (label
));
10070 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10074 /* ??? Probably not safe to set this here, since it assumes that a
10075 function will be emitted as assembly immediately after we generate
10076 RTL for it. This does not happen for inline functions. */
10077 return_used_this_function
= 0;
10081 /* We need to take into account any stack-frame rounding. */
10082 offsets
= arm_get_frame_offsets ();
10084 gcc_assert (!use_return_insn (FALSE
, NULL
)
10085 || !return_used_this_function
10086 || offsets
->saved_regs
== offsets
->outgoing_args
10087 || frame_pointer_needed
);
10089 /* Reset the ARM-specific per-function variables. */
10090 after_arm_reorg
= 0;
10094 /* Generate and emit an insn that we will recognize as a push_multi.
10095 Unfortunately, since this insn does not reflect very well the actual
10096 semantics of the operation, we need to annotate the insn for the benefit
10097 of DWARF2 frame unwind information. */
10099 emit_multi_reg_push (unsigned long mask
)
10102 int num_dwarf_regs
;
10106 int dwarf_par_index
;
10109 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10110 if (mask
& (1 << i
))
10113 gcc_assert (num_regs
&& num_regs
<= 16);
10115 /* We don't record the PC in the dwarf frame information. */
10116 num_dwarf_regs
= num_regs
;
10117 if (mask
& (1 << PC_REGNUM
))
10120 /* For the body of the insn we are going to generate an UNSPEC in
10121 parallel with several USEs. This allows the insn to be recognized
10122 by the push_multi pattern in the arm.md file. The insn looks
10123 something like this:
10126 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10127 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10128 (use (reg:SI 11 fp))
10129 (use (reg:SI 12 ip))
10130 (use (reg:SI 14 lr))
10131 (use (reg:SI 15 pc))
10134 For the frame note however, we try to be more explicit and actually
10135 show each register being stored into the stack frame, plus a (single)
10136 decrement of the stack pointer. We do it this way in order to be
10137 friendly to the stack unwinding code, which only wants to see a single
10138 stack decrement per instruction. The RTL we generate for the note looks
10139 something like this:
10142 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10143 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10144 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10145 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10146 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10149 This sequence is used both by the code to support stack unwinding for
10150 exceptions handlers and the code to generate dwarf2 frame debugging. */
10152 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10153 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10154 dwarf_par_index
= 1;
10156 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10158 if (mask
& (1 << i
))
10160 reg
= gen_rtx_REG (SImode
, i
);
10162 XVECEXP (par
, 0, 0)
10163 = gen_rtx_SET (VOIDmode
,
10164 gen_frame_mem (BLKmode
,
10165 gen_rtx_PRE_DEC (BLKmode
,
10166 stack_pointer_rtx
)),
10167 gen_rtx_UNSPEC (BLKmode
,
10168 gen_rtvec (1, reg
),
10169 UNSPEC_PUSH_MULT
));
10171 if (i
!= PC_REGNUM
)
10173 tmp
= gen_rtx_SET (VOIDmode
,
10174 gen_frame_mem (SImode
, stack_pointer_rtx
),
10176 RTX_FRAME_RELATED_P (tmp
) = 1;
10177 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10185 for (j
= 1, i
++; j
< num_regs
; i
++)
10187 if (mask
& (1 << i
))
10189 reg
= gen_rtx_REG (SImode
, i
);
10191 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10193 if (i
!= PC_REGNUM
)
10196 = gen_rtx_SET (VOIDmode
,
10197 gen_frame_mem (SImode
,
10198 plus_constant (stack_pointer_rtx
,
10201 RTX_FRAME_RELATED_P (tmp
) = 1;
10202 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10209 par
= emit_insn (par
);
10211 tmp
= gen_rtx_SET (VOIDmode
,
10213 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
10214 RTX_FRAME_RELATED_P (tmp
) = 1;
10215 XVECEXP (dwarf
, 0, 0) = tmp
;
10217 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10222 /* Calculate the size of the return value that is passed in registers. */
10224 arm_size_return_regs (void)
10226 enum machine_mode mode
;
10228 if (current_function_return_rtx
!= 0)
10229 mode
= GET_MODE (current_function_return_rtx
);
10231 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10233 return GET_MODE_SIZE (mode
);
10237 emit_sfm (int base_reg
, int count
)
10244 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10245 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10247 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10249 XVECEXP (par
, 0, 0)
10250 = gen_rtx_SET (VOIDmode
,
10251 gen_frame_mem (BLKmode
,
10252 gen_rtx_PRE_DEC (BLKmode
,
10253 stack_pointer_rtx
)),
10254 gen_rtx_UNSPEC (BLKmode
,
10255 gen_rtvec (1, reg
),
10256 UNSPEC_PUSH_MULT
));
10257 tmp
= gen_rtx_SET (VOIDmode
,
10258 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10259 RTX_FRAME_RELATED_P (tmp
) = 1;
10260 XVECEXP (dwarf
, 0, 1) = tmp
;
10262 for (i
= 1; i
< count
; i
++)
10264 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10265 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10267 tmp
= gen_rtx_SET (VOIDmode
,
10268 gen_frame_mem (XFmode
,
10269 plus_constant (stack_pointer_rtx
,
10272 RTX_FRAME_RELATED_P (tmp
) = 1;
10273 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10276 tmp
= gen_rtx_SET (VOIDmode
,
10278 plus_constant (stack_pointer_rtx
, -12 * count
));
10280 RTX_FRAME_RELATED_P (tmp
) = 1;
10281 XVECEXP (dwarf
, 0, 0) = tmp
;
10283 par
= emit_insn (par
);
10284 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10290 /* Return true if the current function needs to save/restore LR. */
10293 thumb_force_lr_save (void)
10295 return !cfun
->machine
->lr_save_eliminated
10296 && (!leaf_function_p ()
10297 || thumb_far_jump_used_p ()
10298 || regs_ever_live
[LR_REGNUM
]);
10302 /* Compute the distance from register FROM to register TO.
10303 These can be the arg pointer (26), the soft frame pointer (25),
10304 the stack pointer (13) or the hard frame pointer (11).
10305 In thumb mode r7 is used as the soft frame pointer, if needed.
10306 Typical stack layout looks like this:
10308 old stack pointer -> | |
10311 | | saved arguments for
10312 | | vararg functions
10315 hard FP & arg pointer -> | | \
10323 soft frame pointer -> | | /
10328 locals base pointer -> | | /
10333 current stack pointer -> | | /
10336 For a given function some or all of these stack components
10337 may not be needed, giving rise to the possibility of
10338 eliminating some of the registers.
10340 The values returned by this function must reflect the behavior
10341 of arm_expand_prologue() and arm_compute_save_reg_mask().
10343 The sign of the number returned reflects the direction of stack
10344 growth, so the values are positive for all eliminations except
10345 from the soft frame pointer to the hard frame pointer.
10347 SFP may point just inside the local variables block to ensure correct
10351 /* Calculate stack offsets. These are used to calculate register elimination
10352 offsets and in prologue/epilogue code. */
10354 static arm_stack_offsets
*
10355 arm_get_frame_offsets (void)
10357 struct arm_stack_offsets
*offsets
;
10358 unsigned long func_type
;
10361 HOST_WIDE_INT frame_size
;
10363 offsets
= &cfun
->machine
->stack_offsets
;
10365 /* We need to know if we are a leaf function. Unfortunately, it
10366 is possible to be called after start_sequence has been called,
10367 which causes get_insns to return the insns for the sequence,
10368 not the function, which will cause leaf_function_p to return
10369 the incorrect result.
10371 to know about leaf functions once reload has completed, and the
10372 frame size cannot be changed after that time, so we can safely
10373 use the cached value. */
10375 if (reload_completed
)
10378 /* Initially this is the size of the local variables. It will translated
10379 into an offset once we have determined the size of preceding data. */
10380 frame_size
= ROUND_UP_WORD (get_frame_size ());
10382 leaf
= leaf_function_p ();
10384 /* Space for variadic functions. */
10385 offsets
->saved_args
= current_function_pretend_args_size
;
10387 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10391 unsigned int regno
;
10393 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10395 /* We know that SP will be doubleword aligned on entry, and we must
10396 preserve that condition at any subroutine call. We also require the
10397 soft frame pointer to be doubleword aligned. */
10399 if (TARGET_REALLY_IWMMXT
)
10401 /* Check for the call-saved iWMMXt registers. */
10402 for (regno
= FIRST_IWMMXT_REGNUM
;
10403 regno
<= LAST_IWMMXT_REGNUM
;
10405 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10409 func_type
= arm_current_func_type ();
10410 if (! IS_VOLATILE (func_type
))
10412 /* Space for saved FPA registers. */
10413 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10414 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10417 /* Space for saved VFP registers. */
10418 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10419 saved
+= arm_get_vfp_saved_size ();
10422 else /* TARGET_THUMB */
10424 saved
= bit_count (thumb_compute_save_reg_mask ()) * 4;
10425 if (TARGET_BACKTRACE
)
10429 /* Saved registers include the stack frame. */
10430 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10431 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
10432 /* A leaf function does not need any stack alignment if it has nothing
10434 if (leaf
&& frame_size
== 0)
10436 offsets
->outgoing_args
= offsets
->soft_frame
;
10440 /* Ensure SFP has the correct alignment. */
10441 if (ARM_DOUBLEWORD_ALIGN
10442 && (offsets
->soft_frame
& 7))
10443 offsets
->soft_frame
+= 4;
10445 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
10446 offsets
->outgoing_args
= (offsets
->locals_base
10447 + current_function_outgoing_args_size
);
10449 if (ARM_DOUBLEWORD_ALIGN
)
10451 /* Ensure SP remains doubleword aligned. */
10452 if (offsets
->outgoing_args
& 7)
10453 offsets
->outgoing_args
+= 4;
10454 gcc_assert (!(offsets
->outgoing_args
& 7));
10461 /* Calculate the relative offsets for the different stack pointers. Positive
10462 offsets are in the direction of stack growth. */
10465 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10467 arm_stack_offsets
*offsets
;
10469 offsets
= arm_get_frame_offsets ();
10471 /* OK, now we have enough information to compute the distances.
10472 There must be an entry in these switch tables for each pair
10473 of registers in ELIMINABLE_REGS, even if some of the entries
10474 seem to be redundant or useless. */
10477 case ARG_POINTER_REGNUM
:
10480 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10483 case FRAME_POINTER_REGNUM
:
10484 /* This is the reverse of the soft frame pointer
10485 to hard frame pointer elimination below. */
10486 return offsets
->soft_frame
- offsets
->saved_args
;
10488 case ARM_HARD_FRAME_POINTER_REGNUM
:
10489 /* If there is no stack frame then the hard
10490 frame pointer and the arg pointer coincide. */
10491 if (offsets
->frame
== offsets
->saved_regs
)
10493 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10494 return (frame_pointer_needed
10495 && cfun
->static_chain_decl
!= NULL
10496 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10498 case STACK_POINTER_REGNUM
:
10499 /* If nothing has been pushed on the stack at all
10500 then this will return -4. This *is* correct! */
10501 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10504 gcc_unreachable ();
10506 gcc_unreachable ();
10508 case FRAME_POINTER_REGNUM
:
10511 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10514 case ARM_HARD_FRAME_POINTER_REGNUM
:
10515 /* The hard frame pointer points to the top entry in the
10516 stack frame. The soft frame pointer to the bottom entry
10517 in the stack frame. If there is no stack frame at all,
10518 then they are identical. */
10520 return offsets
->frame
- offsets
->soft_frame
;
10522 case STACK_POINTER_REGNUM
:
10523 return offsets
->outgoing_args
- offsets
->soft_frame
;
10526 gcc_unreachable ();
10528 gcc_unreachable ();
10531 /* You cannot eliminate from the stack pointer.
10532 In theory you could eliminate from the hard frame
10533 pointer to the stack pointer, but this will never
10534 happen, since if a stack frame is not needed the
10535 hard frame pointer will never be used. */
10536 gcc_unreachable ();
10541 /* Generate the prologue instructions for entry into an ARM function. */
10543 arm_expand_prologue (void)
10549 unsigned long live_regs_mask
;
10550 unsigned long func_type
;
10552 int saved_pretend_args
= 0;
10553 int saved_regs
= 0;
10554 unsigned HOST_WIDE_INT args_to_push
;
10555 arm_stack_offsets
*offsets
;
10557 func_type
= arm_current_func_type ();
10559 /* Naked functions don't have prologues. */
10560 if (IS_NAKED (func_type
))
10563 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10564 args_to_push
= current_function_pretend_args_size
;
10566 /* Compute which register we will have to save onto the stack. */
10567 live_regs_mask
= arm_compute_save_reg_mask ();
10569 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10571 if (frame_pointer_needed
)
10573 if (IS_INTERRUPT (func_type
))
10575 /* Interrupt functions must not corrupt any registers.
10576 Creating a frame pointer however, corrupts the IP
10577 register, so we must push it first. */
10578 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10580 /* Do not set RTX_FRAME_RELATED_P on this insn.
10581 The dwarf stack unwinding code only wants to see one
10582 stack decrement per function, and this is not it. If
10583 this instruction is labeled as being part of the frame
10584 creation sequence then dwarf2out_frame_debug_expr will
10585 die when it encounters the assignment of IP to FP
10586 later on, since the use of SP here establishes SP as
10587 the CFA register and not IP.
10589 Anyway this instruction is not really part of the stack
10590 frame creation although it is part of the prologue. */
10592 else if (IS_NESTED (func_type
))
10594 /* The Static chain register is the same as the IP register
10595 used as a scratch register during stack frame creation.
10596 To get around this need to find somewhere to store IP
10597 whilst the frame is being created. We try the following
10600 1. The last argument register.
10601 2. A slot on the stack above the frame. (This only
10602 works if the function is not a varargs function).
10603 3. Register r3, after pushing the argument registers
10606 Note - we only need to tell the dwarf2 backend about the SP
10607 adjustment in the second variant; the static chain register
10608 doesn't need to be unwound, as it doesn't contain a value
10609 inherited from the caller. */
10611 if (regs_ever_live
[3] == 0)
10612 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10613 else if (args_to_push
== 0)
10617 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10618 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
10621 /* Just tell the dwarf backend that we adjusted SP. */
10622 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10623 plus_constant (stack_pointer_rtx
,
10625 RTX_FRAME_RELATED_P (insn
) = 1;
10626 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10627 dwarf
, REG_NOTES (insn
));
10631 /* Store the args on the stack. */
10632 if (cfun
->machine
->uses_anonymous_args
)
10633 insn
= emit_multi_reg_push
10634 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10637 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10638 GEN_INT (- args_to_push
)));
10640 RTX_FRAME_RELATED_P (insn
) = 1;
10642 saved_pretend_args
= 1;
10643 fp_offset
= args_to_push
;
10646 /* Now reuse r3 to preserve IP. */
10647 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
10651 insn
= emit_set_insn (ip_rtx
,
10652 plus_constant (stack_pointer_rtx
, fp_offset
));
10653 RTX_FRAME_RELATED_P (insn
) = 1;
10658 /* Push the argument registers, or reserve space for them. */
10659 if (cfun
->machine
->uses_anonymous_args
)
10660 insn
= emit_multi_reg_push
10661 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10664 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10665 GEN_INT (- args_to_push
)));
10666 RTX_FRAME_RELATED_P (insn
) = 1;
10669 /* If this is an interrupt service routine, and the link register
10670 is going to be pushed, and we are not creating a stack frame,
10671 (which would involve an extra push of IP and a pop in the epilogue)
10672 subtracting four from LR now will mean that the function return
10673 can be done with a single instruction. */
10674 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10675 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10676 && ! frame_pointer_needed
)
10678 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
10680 emit_set_insn (lr
, plus_constant (lr
, -4));
10683 if (live_regs_mask
)
10685 insn
= emit_multi_reg_push (live_regs_mask
);
10686 saved_regs
+= bit_count (live_regs_mask
) * 4;
10687 RTX_FRAME_RELATED_P (insn
) = 1;
10691 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10692 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10694 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10695 insn
= gen_frame_mem (V2SImode
, insn
);
10696 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
10697 RTX_FRAME_RELATED_P (insn
) = 1;
10701 if (! IS_VOLATILE (func_type
))
10705 /* Save any floating point call-saved registers used by this
10707 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10709 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10710 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10712 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10713 insn
= gen_frame_mem (XFmode
, insn
);
10714 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
10715 RTX_FRAME_RELATED_P (insn
) = 1;
10721 start_reg
= LAST_FPA_REGNUM
;
10723 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10725 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10727 if (start_reg
- reg
== 3)
10729 insn
= emit_sfm (reg
, 4);
10730 RTX_FRAME_RELATED_P (insn
) = 1;
10732 start_reg
= reg
- 1;
10737 if (start_reg
!= reg
)
10739 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10740 RTX_FRAME_RELATED_P (insn
) = 1;
10741 saved_regs
+= (start_reg
- reg
) * 12;
10743 start_reg
= reg
- 1;
10747 if (start_reg
!= reg
)
10749 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10750 saved_regs
+= (start_reg
- reg
) * 12;
10751 RTX_FRAME_RELATED_P (insn
) = 1;
10754 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10756 start_reg
= FIRST_VFP_REGNUM
;
10758 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10760 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10761 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10763 if (start_reg
!= reg
)
10764 saved_regs
+= vfp_emit_fstmx (start_reg
,
10765 (reg
- start_reg
) / 2);
10766 start_reg
= reg
+ 2;
10769 if (start_reg
!= reg
)
10770 saved_regs
+= vfp_emit_fstmx (start_reg
,
10771 (reg
- start_reg
) / 2);
10775 if (frame_pointer_needed
)
10777 /* Create the new frame pointer. */
10778 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10779 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10780 RTX_FRAME_RELATED_P (insn
) = 1;
10782 if (IS_NESTED (func_type
))
10784 /* Recover the static chain register. */
10785 if (regs_ever_live
[3] == 0
10786 || saved_pretend_args
)
10787 insn
= gen_rtx_REG (SImode
, 3);
10788 else /* if (current_function_pretend_args_size == 0) */
10790 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
10791 insn
= gen_frame_mem (SImode
, insn
);
10794 emit_set_insn (ip_rtx
, insn
);
10795 /* Add a USE to stop propagate_one_insn() from barfing. */
10796 emit_insn (gen_prologue_use (ip_rtx
));
10800 offsets
= arm_get_frame_offsets ();
10801 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10803 /* This add can produce multiple insns for a large constant, so we
10804 need to get tricky. */
10805 rtx last
= get_last_insn ();
10807 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10808 - offsets
->outgoing_args
);
10810 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10814 last
= last
? NEXT_INSN (last
) : get_insns ();
10815 RTX_FRAME_RELATED_P (last
) = 1;
10817 while (last
!= insn
);
10819 /* If the frame pointer is needed, emit a special barrier that
10820 will prevent the scheduler from moving stores to the frame
10821 before the stack adjustment. */
10822 if (frame_pointer_needed
)
10823 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10824 hard_frame_pointer_rtx
));
10829 arm_load_pic_register (0UL);
10831 /* If we are profiling, make sure no instructions are scheduled before
10832 the call to mcount. Similarly if the user has requested no
10833 scheduling in the prolog. Similarly if we want non-call exceptions
10834 using the EABI unwinder, to prevent faulting instructions from being
10835 swapped with a stack adjustment. */
10836 if (current_function_profile
|| !TARGET_SCHED_PROLOG
10837 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
10838 emit_insn (gen_blockage ());
10840 /* If the link register is being kept alive, with the return address in it,
10841 then make sure that it does not get reused by the ce2 pass. */
10842 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10844 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10845 cfun
->machine
->lr_save_eliminated
= 1;
10849 /* If CODE is 'd', then the X is a condition operand and the instruction
10850 should only be executed if the condition is true.
10851 if CODE is 'D', then the X is a condition operand and the instruction
10852 should only be executed if the condition is false: however, if the mode
10853 of the comparison is CCFPEmode, then always execute the instruction -- we
10854 do this because in these circumstances !GE does not necessarily imply LT;
10855 in these cases the instruction pattern will take care to make sure that
10856 an instruction containing %d will follow, thereby undoing the effects of
10857 doing this instruction unconditionally.
10858 If CODE is 'N' then X is a floating point operand that must be negated
10860 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10861 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10863 arm_print_operand (FILE *stream
, rtx x
, int code
)
10868 fputs (ASM_COMMENT_START
, stream
);
10872 fputs (user_label_prefix
, stream
);
10876 fputs (REGISTER_PREFIX
, stream
);
10880 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10884 output_operand_lossage ("predicated Thumb instruction");
10887 if (current_insn_predicate
!= NULL
)
10889 output_operand_lossage
10890 ("predicated instruction in conditional sequence");
10894 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10896 else if (current_insn_predicate
)
10898 enum arm_cond_code code
;
10902 output_operand_lossage ("predicated Thumb instruction");
10906 code
= get_arm_condition_code (current_insn_predicate
);
10907 fputs (arm_condition_codes
[code
], stream
);
10914 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10915 r
= REAL_VALUE_NEGATE (r
);
10916 fprintf (stream
, "%s", fp_const_from_val (&r
));
10921 if (GET_CODE (x
) == CONST_INT
)
10924 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10925 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10929 putc ('~', stream
);
10930 output_addr_const (stream
, x
);
10935 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10938 /* Truncate Cirrus shift counts. */
10940 if (GET_CODE (x
) == CONST_INT
)
10942 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10945 arm_print_operand (stream
, x
, 0);
10949 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10955 const char * shift
= shift_op (x
, &val
);
10959 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10961 arm_print_operand (stream
, XEXP (x
, 1), 0);
10963 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10968 /* An explanation of the 'Q', 'R' and 'H' register operands:
10970 In a pair of registers containing a DI or DF value the 'Q'
10971 operand returns the register number of the register containing
10972 the least significant part of the value. The 'R' operand returns
10973 the register number of the register containing the most
10974 significant part of the value.
10976 The 'H' operand returns the higher of the two register numbers.
10977 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10978 same as the 'Q' operand, since the most significant part of the
10979 value is held in the lower number register. The reverse is true
10980 on systems where WORDS_BIG_ENDIAN is false.
10982 The purpose of these operands is to distinguish between cases
10983 where the endian-ness of the values is important (for example
10984 when they are added together), and cases where the endian-ness
10985 is irrelevant, but the order of register operations is important.
10986 For example when loading a value from memory into a register
10987 pair, the endian-ness does not matter. Provided that the value
10988 from the lower memory address is put into the lower numbered
10989 register, and the value from the higher address is put into the
10990 higher numbered register, the load will work regardless of whether
10991 the value being loaded is big-wordian or little-wordian. The
10992 order of the two register loads can matter however, if the address
10993 of the memory location is actually held in one of the registers
10994 being overwritten by the load. */
10996 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
10998 output_operand_lossage ("invalid operand for code '%c'", code
);
11002 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11006 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11008 output_operand_lossage ("invalid operand for code '%c'", code
);
11012 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11016 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11018 output_operand_lossage ("invalid operand for code '%c'", code
);
11022 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11026 asm_fprintf (stream
, "%r",
11027 GET_CODE (XEXP (x
, 0)) == REG
11028 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11032 asm_fprintf (stream
, "{%r-%r}",
11034 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11038 /* CONST_TRUE_RTX means always -- that's the default. */
11039 if (x
== const_true_rtx
)
11042 if (!COMPARISON_P (x
))
11044 output_operand_lossage ("invalid operand for code '%c'", code
);
11048 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11053 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11054 want to do that. */
11055 if (x
== const_true_rtx
)
11057 output_operand_lossage ("instruction never exectued");
11060 if (!COMPARISON_P (x
))
11062 output_operand_lossage ("invalid operand for code '%c'", code
);
11066 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11067 (get_arm_condition_code (x
))],
11071 /* Cirrus registers can be accessed in a variety of ways:
11072 single floating point (f)
11073 double floating point (d)
11075 64bit integer (dx). */
11076 case 'W': /* Cirrus register in F mode. */
11077 case 'X': /* Cirrus register in D mode. */
11078 case 'Y': /* Cirrus register in FX mode. */
11079 case 'Z': /* Cirrus register in DX mode. */
11080 gcc_assert (GET_CODE (x
) == REG
11081 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11083 fprintf (stream
, "mv%s%s",
11085 : code
== 'X' ? "d"
11086 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11090 /* Print cirrus register in the mode specified by the register's mode. */
11093 int mode
= GET_MODE (x
);
11095 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11097 output_operand_lossage ("invalid operand for code '%c'", code
);
11101 fprintf (stream
, "mv%s%s",
11102 mode
== DFmode
? "d"
11103 : mode
== SImode
? "fx"
11104 : mode
== DImode
? "dx"
11105 : "f", reg_names
[REGNO (x
)] + 2);
11111 if (GET_CODE (x
) != REG
11112 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11113 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11114 /* Bad value for wCG register number. */
11116 output_operand_lossage ("invalid operand for code '%c'", code
);
11121 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11124 /* Print an iWMMXt control register name. */
11126 if (GET_CODE (x
) != CONST_INT
11128 || INTVAL (x
) >= 16)
11129 /* Bad value for wC register number. */
11131 output_operand_lossage ("invalid operand for code '%c'", code
);
11137 static const char * wc_reg_names
[16] =
11139 "wCID", "wCon", "wCSSF", "wCASF",
11140 "wC4", "wC5", "wC6", "wC7",
11141 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11142 "wC12", "wC13", "wC14", "wC15"
11145 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11149 /* Print a VFP double precision register name. */
11152 int mode
= GET_MODE (x
);
11155 if (mode
!= DImode
&& mode
!= DFmode
)
11157 output_operand_lossage ("invalid operand for code '%c'", code
);
11161 if (GET_CODE (x
) != REG
11162 || !IS_VFP_REGNUM (REGNO (x
)))
11164 output_operand_lossage ("invalid operand for code '%c'", code
);
11168 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11171 output_operand_lossage ("invalid operand for code '%c'", code
);
11175 fprintf (stream
, "d%d", num
>> 1);
11182 output_operand_lossage ("missing operand");
11186 switch (GET_CODE (x
))
11189 asm_fprintf (stream
, "%r", REGNO (x
));
11193 output_memory_reference_mode
= GET_MODE (x
);
11194 output_address (XEXP (x
, 0));
11198 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11202 gcc_assert (GET_CODE (x
) != NEG
);
11203 fputc ('#', stream
);
11204 output_addr_const (stream
, x
);
11210 #ifndef AOF_ASSEMBLER
11211 /* Target hook for assembling integer objects. The ARM version needs to
11212 handle word-sized values specially. */
11214 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11216 if (size
== UNITS_PER_WORD
&& aligned_p
)
11218 fputs ("\t.word\t", asm_out_file
);
11219 output_addr_const (asm_out_file
, x
);
11221 /* Mark symbols as position independent. We only do this in the
11222 .text segment, not in the .data segment. */
11223 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
11224 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
11226 if (GET_CODE (x
) == SYMBOL_REF
11227 && (CONSTANT_POOL_ADDRESS_P (x
)
11228 || SYMBOL_REF_LOCAL_P (x
)))
11229 fputs ("(GOTOFF)", asm_out_file
);
11230 else if (GET_CODE (x
) == LABEL_REF
)
11231 fputs ("(GOTOFF)", asm_out_file
);
11233 fputs ("(GOT)", asm_out_file
);
11235 fputc ('\n', asm_out_file
);
11239 if (arm_vector_mode_supported_p (GET_MODE (x
)))
11243 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
11245 units
= CONST_VECTOR_NUNITS (x
);
11247 switch (GET_MODE (x
))
11249 case V2SImode
: size
= 4; break;
11250 case V4HImode
: size
= 2; break;
11251 case V8QImode
: size
= 1; break;
11253 gcc_unreachable ();
11256 for (i
= 0; i
< units
; i
++)
11260 elt
= CONST_VECTOR_ELT (x
, i
);
11262 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11268 return default_assemble_integer (x
, size
, aligned_p
);
11272 /* Add a function to the list of static constructors. */
11275 arm_elf_asm_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
11277 if (!TARGET_AAPCS_BASED
)
11279 default_named_section_asm_out_constructor (symbol
, priority
);
11283 /* Put these in the .init_array section, using a special relocation. */
11285 assemble_align (POINTER_SIZE
);
11286 fputs ("\t.word\t", asm_out_file
);
11287 output_addr_const (asm_out_file
, symbol
);
11288 fputs ("(target1)\n", asm_out_file
);
11292 /* A finite state machine takes care of noticing whether or not instructions
11293 can be conditionally executed, and thus decrease execution time and code
11294 size by deleting branch instructions. The fsm is controlled by
11295 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11297 /* The state of the fsm controlling condition codes are:
11298 0: normal, do nothing special
11299 1: make ASM_OUTPUT_OPCODE not output this instruction
11300 2: make ASM_OUTPUT_OPCODE not output this instruction
11301 3: make instructions conditional
11302 4: make instructions conditional
11304 State transitions (state->state by whom under condition):
11305 0 -> 1 final_prescan_insn if the `target' is a label
11306 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11307 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11308 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11309 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11310 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11311 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11312 (the target insn is arm_target_insn).
11314 If the jump clobbers the conditions then we use states 2 and 4.
11316 A similar thing can be done with conditional return insns.
11318 XXX In case the `target' is an unconditional branch, this conditionalising
11319 of the instructions always reduces code size, but not always execution
11320 time. But then, I want to reduce the code size to somewhere near what
11321 /bin/cc produces. */
11323 /* Returns the index of the ARM condition code string in
11324 `arm_condition_codes'. COMPARISON should be an rtx like
11325 `(eq (...) (...))'. */
11326 static enum arm_cond_code
11327 get_arm_condition_code (rtx comparison
)
11329 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11331 enum rtx_code comp_code
= GET_CODE (comparison
);
11333 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11334 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11335 XEXP (comparison
, 1));
11339 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11340 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11341 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11342 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11343 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11344 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11345 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11346 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11347 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11348 case CC_DLTUmode
: code
= ARM_CC
;
11351 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
11353 if (comp_code
== EQ
)
11354 return ARM_INVERSE_CONDITION_CODE (code
);
11360 case NE
: return ARM_NE
;
11361 case EQ
: return ARM_EQ
;
11362 case GE
: return ARM_PL
;
11363 case LT
: return ARM_MI
;
11364 default: gcc_unreachable ();
11370 case NE
: return ARM_NE
;
11371 case EQ
: return ARM_EQ
;
11372 default: gcc_unreachable ();
11378 case NE
: return ARM_MI
;
11379 case EQ
: return ARM_PL
;
11380 default: gcc_unreachable ();
11385 /* These encodings assume that AC=1 in the FPA system control
11386 byte. This allows us to handle all cases except UNEQ and
11390 case GE
: return ARM_GE
;
11391 case GT
: return ARM_GT
;
11392 case LE
: return ARM_LS
;
11393 case LT
: return ARM_MI
;
11394 case NE
: return ARM_NE
;
11395 case EQ
: return ARM_EQ
;
11396 case ORDERED
: return ARM_VC
;
11397 case UNORDERED
: return ARM_VS
;
11398 case UNLT
: return ARM_LT
;
11399 case UNLE
: return ARM_LE
;
11400 case UNGT
: return ARM_HI
;
11401 case UNGE
: return ARM_PL
;
11402 /* UNEQ and LTGT do not have a representation. */
11403 case UNEQ
: /* Fall through. */
11404 case LTGT
: /* Fall through. */
11405 default: gcc_unreachable ();
11411 case NE
: return ARM_NE
;
11412 case EQ
: return ARM_EQ
;
11413 case GE
: return ARM_LE
;
11414 case GT
: return ARM_LT
;
11415 case LE
: return ARM_GE
;
11416 case LT
: return ARM_GT
;
11417 case GEU
: return ARM_LS
;
11418 case GTU
: return ARM_CC
;
11419 case LEU
: return ARM_CS
;
11420 case LTU
: return ARM_HI
;
11421 default: gcc_unreachable ();
11427 case LTU
: return ARM_CS
;
11428 case GEU
: return ARM_CC
;
11429 default: gcc_unreachable ();
11435 case NE
: return ARM_NE
;
11436 case EQ
: return ARM_EQ
;
11437 case GE
: return ARM_GE
;
11438 case GT
: return ARM_GT
;
11439 case LE
: return ARM_LE
;
11440 case LT
: return ARM_LT
;
11441 case GEU
: return ARM_CS
;
11442 case GTU
: return ARM_HI
;
11443 case LEU
: return ARM_LS
;
11444 case LTU
: return ARM_CC
;
11445 default: gcc_unreachable ();
11448 default: gcc_unreachable ();
11453 arm_final_prescan_insn (rtx insn
)
11455 /* BODY will hold the body of INSN. */
11456 rtx body
= PATTERN (insn
);
11458 /* This will be 1 if trying to repeat the trick, and things need to be
11459 reversed if it appears to fail. */
11462 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11463 taken are clobbered, even if the rtl suggests otherwise. It also
11464 means that we have to grub around within the jump expression to find
11465 out what the conditions are when the jump isn't taken. */
11466 int jump_clobbers
= 0;
11468 /* If we start with a return insn, we only succeed if we find another one. */
11469 int seeking_return
= 0;
11471 /* START_INSN will hold the insn from where we start looking. This is the
11472 first insn after the following code_label if REVERSE is true. */
11473 rtx start_insn
= insn
;
11475 /* If in state 4, check if the target branch is reached, in order to
11476 change back to state 0. */
11477 if (arm_ccfsm_state
== 4)
11479 if (insn
== arm_target_insn
)
11481 arm_target_insn
= NULL
;
11482 arm_ccfsm_state
= 0;
11487 /* If in state 3, it is possible to repeat the trick, if this insn is an
11488 unconditional branch to a label, and immediately following this branch
11489 is the previous target label which is only used once, and the label this
11490 branch jumps to is not too far off. */
11491 if (arm_ccfsm_state
== 3)
11493 if (simplejump_p (insn
))
11495 start_insn
= next_nonnote_insn (start_insn
);
11496 if (GET_CODE (start_insn
) == BARRIER
)
11498 /* XXX Isn't this always a barrier? */
11499 start_insn
= next_nonnote_insn (start_insn
);
11501 if (GET_CODE (start_insn
) == CODE_LABEL
11502 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11503 && LABEL_NUSES (start_insn
) == 1)
11508 else if (GET_CODE (body
) == RETURN
)
11510 start_insn
= next_nonnote_insn (start_insn
);
11511 if (GET_CODE (start_insn
) == BARRIER
)
11512 start_insn
= next_nonnote_insn (start_insn
);
11513 if (GET_CODE (start_insn
) == CODE_LABEL
11514 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11515 && LABEL_NUSES (start_insn
) == 1)
11518 seeking_return
= 1;
11527 gcc_assert (!arm_ccfsm_state
|| reverse
);
11528 if (GET_CODE (insn
) != JUMP_INSN
)
11531 /* This jump might be paralleled with a clobber of the condition codes
11532 the jump should always come first */
11533 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11534 body
= XVECEXP (body
, 0, 0);
11537 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11538 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11541 int fail
= FALSE
, succeed
= FALSE
;
11542 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11543 int then_not_else
= TRUE
;
11544 rtx this_insn
= start_insn
, label
= 0;
11546 /* If the jump cannot be done with one instruction, we cannot
11547 conditionally execute the instruction in the inverse case. */
11548 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11554 /* Register the insn jumped to. */
11557 if (!seeking_return
)
11558 label
= XEXP (SET_SRC (body
), 0);
11560 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11561 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11562 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11564 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11565 then_not_else
= FALSE
;
11567 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11568 seeking_return
= 1;
11569 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11571 seeking_return
= 1;
11572 then_not_else
= FALSE
;
11575 gcc_unreachable ();
11577 /* See how many insns this branch skips, and what kind of insns. If all
11578 insns are okay, and the label or unconditional branch to the same
11579 label is not too far away, succeed. */
11580 for (insns_skipped
= 0;
11581 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11585 this_insn
= next_nonnote_insn (this_insn
);
11589 switch (GET_CODE (this_insn
))
11592 /* Succeed if it is the target label, otherwise fail since
11593 control falls in from somewhere else. */
11594 if (this_insn
== label
)
11598 arm_ccfsm_state
= 2;
11599 this_insn
= next_nonnote_insn (this_insn
);
11602 arm_ccfsm_state
= 1;
11610 /* Succeed if the following insn is the target label.
11612 If return insns are used then the last insn in a function
11613 will be a barrier. */
11614 this_insn
= next_nonnote_insn (this_insn
);
11615 if (this_insn
&& this_insn
== label
)
11619 arm_ccfsm_state
= 2;
11620 this_insn
= next_nonnote_insn (this_insn
);
11623 arm_ccfsm_state
= 1;
11631 /* The AAPCS says that conditional calls should not be
11632 used since they make interworking inefficient (the
11633 linker can't transform BL<cond> into BLX). That's
11634 only a problem if the machine has BLX. */
11641 /* Succeed if the following insn is the target label, or
11642 if the following two insns are a barrier and the
11644 this_insn
= next_nonnote_insn (this_insn
);
11645 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11646 this_insn
= next_nonnote_insn (this_insn
);
11648 if (this_insn
&& this_insn
== label
11649 && insns_skipped
< max_insns_skipped
)
11653 arm_ccfsm_state
= 2;
11654 this_insn
= next_nonnote_insn (this_insn
);
11657 arm_ccfsm_state
= 1;
11665 /* If this is an unconditional branch to the same label, succeed.
11666 If it is to another label, do nothing. If it is conditional,
11668 /* XXX Probably, the tests for SET and the PC are
11671 scanbody
= PATTERN (this_insn
);
11672 if (GET_CODE (scanbody
) == SET
11673 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11675 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11676 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11678 arm_ccfsm_state
= 2;
11681 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11684 /* Fail if a conditional return is undesirable (e.g. on a
11685 StrongARM), but still allow this if optimizing for size. */
11686 else if (GET_CODE (scanbody
) == RETURN
11687 && !use_return_insn (TRUE
, NULL
)
11690 else if (GET_CODE (scanbody
) == RETURN
11693 arm_ccfsm_state
= 2;
11696 else if (GET_CODE (scanbody
) == PARALLEL
)
11698 switch (get_attr_conds (this_insn
))
11708 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
11713 /* Instructions using or affecting the condition codes make it
11715 scanbody
= PATTERN (this_insn
);
11716 if (!(GET_CODE (scanbody
) == SET
11717 || GET_CODE (scanbody
) == PARALLEL
)
11718 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11721 /* A conditional cirrus instruction must be followed by
11722 a non Cirrus instruction. However, since we
11723 conditionalize instructions in this function and by
11724 the time we get here we can't add instructions
11725 (nops), because shorten_branches() has already been
11726 called, we will disable conditionalizing Cirrus
11727 instructions to be safe. */
11728 if (GET_CODE (scanbody
) != USE
11729 && GET_CODE (scanbody
) != CLOBBER
11730 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11740 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11741 arm_target_label
= CODE_LABEL_NUMBER (label
);
11744 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
11746 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11748 this_insn
= next_nonnote_insn (this_insn
);
11749 gcc_assert (!this_insn
11750 || (GET_CODE (this_insn
) != BARRIER
11751 && GET_CODE (this_insn
) != CODE_LABEL
));
11755 /* Oh, dear! we ran off the end.. give up. */
11756 recog (PATTERN (insn
), insn
, NULL
);
11757 arm_ccfsm_state
= 0;
11758 arm_target_insn
= NULL
;
11761 arm_target_insn
= this_insn
;
11765 gcc_assert (!reverse
);
11767 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11769 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11770 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11771 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11772 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11776 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11779 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11783 if (reverse
|| then_not_else
)
11784 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11787 /* Restore recog_data (getting the attributes of other insns can
11788 destroy this array, but final.c assumes that it remains intact
11789 across this call; since the insn has been recognized already we
11790 call recog direct). */
11791 recog (PATTERN (insn
), insn
, NULL
);
11795 /* Returns true if REGNO is a valid register
11796 for holding a quantity of type MODE. */
11798 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11800 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11801 return (regno
== CC_REGNUM
11802 || (TARGET_HARD_FLOAT
&& TARGET_VFP
11803 && regno
== VFPCC_REGNUM
));
11806 /* For the Thumb we only allow values bigger than SImode in
11807 registers 0 - 6, so that there is always a second low
11808 register available to hold the upper part of the value.
11809 We probably we ought to ensure that the register is the
11810 start of an even numbered register pair. */
11811 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11813 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
11814 && IS_CIRRUS_REGNUM (regno
))
11815 /* We have outlawed SI values in Cirrus registers because they
11816 reside in the lower 32 bits, but SF values reside in the
11817 upper 32 bits. This causes gcc all sorts of grief. We can't
11818 even split the registers into pairs because Cirrus SI values
11819 get sign extended to 64bits-- aldyh. */
11820 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11822 if (TARGET_HARD_FLOAT
&& TARGET_VFP
11823 && IS_VFP_REGNUM (regno
))
11825 if (mode
== SFmode
|| mode
== SImode
)
11828 /* DFmode values are only valid in even register pairs. */
11829 if (mode
== DFmode
)
11830 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11834 if (TARGET_REALLY_IWMMXT
)
11836 if (IS_IWMMXT_GR_REGNUM (regno
))
11837 return mode
== SImode
;
11839 if (IS_IWMMXT_REGNUM (regno
))
11840 return VALID_IWMMXT_REG_MODE (mode
);
11843 /* We allow any value to be stored in the general registers.
11844 Restrict doubleword quantities to even register pairs so that we can
11846 if (regno
<= LAST_ARM_REGNUM
)
11847 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11849 if (regno
== FRAME_POINTER_REGNUM
11850 || regno
== ARG_POINTER_REGNUM
)
11851 /* We only allow integers in the fake hard registers. */
11852 return GET_MODE_CLASS (mode
) == MODE_INT
;
11854 /* The only registers left are the FPA registers
11855 which we only allow to hold FP values. */
11856 return (TARGET_HARD_FLOAT
&& TARGET_FPA
11857 && GET_MODE_CLASS (mode
) == MODE_FLOAT
11858 && regno
>= FIRST_FPA_REGNUM
11859 && regno
<= LAST_FPA_REGNUM
);
11863 arm_regno_class (int regno
)
11867 if (regno
== STACK_POINTER_REGNUM
)
11869 if (regno
== CC_REGNUM
)
11876 if ( regno
<= LAST_ARM_REGNUM
11877 || regno
== FRAME_POINTER_REGNUM
11878 || regno
== ARG_POINTER_REGNUM
)
11879 return GENERAL_REGS
;
11881 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11884 if (IS_CIRRUS_REGNUM (regno
))
11885 return CIRRUS_REGS
;
11887 if (IS_VFP_REGNUM (regno
))
11890 if (IS_IWMMXT_REGNUM (regno
))
11891 return IWMMXT_REGS
;
11893 if (IS_IWMMXT_GR_REGNUM (regno
))
11894 return IWMMXT_GR_REGS
;
11899 /* Handle a special case when computing the offset
11900 of an argument from the frame pointer. */
11902 arm_debugger_arg_offset (int value
, rtx addr
)
11906 /* We are only interested if dbxout_parms() failed to compute the offset. */
11910 /* We can only cope with the case where the address is held in a register. */
11911 if (GET_CODE (addr
) != REG
)
11914 /* If we are using the frame pointer to point at the argument, then
11915 an offset of 0 is correct. */
11916 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11919 /* If we are using the stack pointer to point at the
11920 argument, then an offset of 0 is correct. */
11921 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11922 && REGNO (addr
) == SP_REGNUM
)
11925 /* Oh dear. The argument is pointed to by a register rather
11926 than being held in a register, or being stored at a known
11927 offset from the frame pointer. Since GDB only understands
11928 those two kinds of argument we must translate the address
11929 held in the register into an offset from the frame pointer.
11930 We do this by searching through the insns for the function
11931 looking to see where this register gets its value. If the
11932 register is initialized from the frame pointer plus an offset
11933 then we are in luck and we can continue, otherwise we give up.
11935 This code is exercised by producing debugging information
11936 for a function with arguments like this:
11938 double func (double a, double b, int c, double d) {return d;}
11940 Without this code the stab for parameter 'd' will be set to
11941 an offset of 0 from the frame pointer, rather than 8. */
11943 /* The if() statement says:
11945 If the insn is a normal instruction
11946 and if the insn is setting the value in a register
11947 and if the register being set is the register holding the address of the argument
11948 and if the address is computing by an addition
11949 that involves adding to a register
11950 which is the frame pointer
11955 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11957 if ( GET_CODE (insn
) == INSN
11958 && GET_CODE (PATTERN (insn
)) == SET
11959 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11960 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11961 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11962 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11963 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11966 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11975 warning (0, "unable to compute real location of stacked parameter");
11976 value
= 8; /* XXX magic hack */
11982 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11985 if ((MASK) & insn_flags) \
11986 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11987 BUILT_IN_MD, NULL, NULL_TREE); \
11991 struct builtin_description
11993 const unsigned int mask
;
11994 const enum insn_code icode
;
11995 const char * const name
;
11996 const enum arm_builtins code
;
11997 const enum rtx_code comparison
;
11998 const unsigned int flag
;
12001 static const struct builtin_description bdesc_2arg
[] =
12003 #define IWMMXT_BUILTIN(code, string, builtin) \
12004 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12005 ARM_BUILTIN_##builtin, 0, 0 },
12007 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12008 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12009 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12010 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12011 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12012 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12013 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12014 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12015 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12016 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12017 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12018 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12019 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12020 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12021 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12022 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12023 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12024 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12025 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12026 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12027 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12028 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12029 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12030 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12031 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12032 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12033 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12034 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12035 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12036 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12037 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12038 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12039 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12040 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12041 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12042 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12043 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12044 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12045 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12046 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12047 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12048 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12049 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12050 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12051 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12052 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12053 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12054 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12055 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12056 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12057 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12058 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12059 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12060 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12061 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12062 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12063 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12064 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12066 #define IWMMXT_BUILTIN2(code, builtin) \
12067 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12069 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12070 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12071 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12072 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12073 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12074 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12075 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12076 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12077 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12078 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12079 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12080 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12081 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12082 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12083 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12084 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12085 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12086 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12087 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12088 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12089 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12090 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12091 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12092 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12093 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12094 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12095 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12096 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12097 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12098 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12099 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
12100 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
12103 static const struct builtin_description bdesc_1arg
[] =
12105 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
12106 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
12107 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
12108 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
12109 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
12110 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
12111 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
12112 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
12113 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
12114 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
12115 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
12116 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
12117 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
12118 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
12119 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
12120 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
12121 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
12122 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
12125 /* Set up all the iWMMXt builtins. This is
12126 not called if TARGET_IWMMXT is zero. */
12129 arm_init_iwmmxt_builtins (void)
12131 const struct builtin_description
* d
;
12133 tree endlink
= void_list_node
;
12135 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12136 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12137 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12140 = build_function_type (integer_type_node
,
12141 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
12142 tree v8qi_ftype_v8qi_v8qi_int
12143 = build_function_type (V8QI_type_node
,
12144 tree_cons (NULL_TREE
, V8QI_type_node
,
12145 tree_cons (NULL_TREE
, V8QI_type_node
,
12146 tree_cons (NULL_TREE
,
12149 tree v4hi_ftype_v4hi_int
12150 = build_function_type (V4HI_type_node
,
12151 tree_cons (NULL_TREE
, V4HI_type_node
,
12152 tree_cons (NULL_TREE
, integer_type_node
,
12154 tree v2si_ftype_v2si_int
12155 = build_function_type (V2SI_type_node
,
12156 tree_cons (NULL_TREE
, V2SI_type_node
,
12157 tree_cons (NULL_TREE
, integer_type_node
,
12159 tree v2si_ftype_di_di
12160 = build_function_type (V2SI_type_node
,
12161 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12162 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12164 tree di_ftype_di_int
12165 = build_function_type (long_long_integer_type_node
,
12166 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12167 tree_cons (NULL_TREE
, integer_type_node
,
12169 tree di_ftype_di_int_int
12170 = build_function_type (long_long_integer_type_node
,
12171 tree_cons (NULL_TREE
, long_long_integer_type_node
,
12172 tree_cons (NULL_TREE
, integer_type_node
,
12173 tree_cons (NULL_TREE
,
12176 tree int_ftype_v8qi
12177 = build_function_type (integer_type_node
,
12178 tree_cons (NULL_TREE
, V8QI_type_node
,
12180 tree int_ftype_v4hi
12181 = build_function_type (integer_type_node
,
12182 tree_cons (NULL_TREE
, V4HI_type_node
,
12184 tree int_ftype_v2si
12185 = build_function_type (integer_type_node
,
12186 tree_cons (NULL_TREE
, V2SI_type_node
,
12188 tree int_ftype_v8qi_int
12189 = build_function_type (integer_type_node
,
12190 tree_cons (NULL_TREE
, V8QI_type_node
,
12191 tree_cons (NULL_TREE
, integer_type_node
,
12193 tree int_ftype_v4hi_int
12194 = build_function_type (integer_type_node
,
12195 tree_cons (NULL_TREE
, V4HI_type_node
,
12196 tree_cons (NULL_TREE
, integer_type_node
,
12198 tree int_ftype_v2si_int
12199 = build_function_type (integer_type_node
,
12200 tree_cons (NULL_TREE
, V2SI_type_node
,
12201 tree_cons (NULL_TREE
, integer_type_node
,
12203 tree v8qi_ftype_v8qi_int_int
12204 = build_function_type (V8QI_type_node
,
12205 tree_cons (NULL_TREE
, V8QI_type_node
,
12206 tree_cons (NULL_TREE
, integer_type_node
,
12207 tree_cons (NULL_TREE
,
12210 tree v4hi_ftype_v4hi_int_int
12211 = build_function_type (V4HI_type_node
,
12212 tree_cons (NULL_TREE
, V4HI_type_node
,
12213 tree_cons (NULL_TREE
, integer_type_node
,
12214 tree_cons (NULL_TREE
,
12217 tree v2si_ftype_v2si_int_int
12218 = build_function_type (V2SI_type_node
,
12219 tree_cons (NULL_TREE
, V2SI_type_node
,
12220 tree_cons (NULL_TREE
, integer_type_node
,
12221 tree_cons (NULL_TREE
,
12224 /* Miscellaneous. */
12225 tree v8qi_ftype_v4hi_v4hi
12226 = build_function_type (V8QI_type_node
,
12227 tree_cons (NULL_TREE
, V4HI_type_node
,
12228 tree_cons (NULL_TREE
, V4HI_type_node
,
12230 tree v4hi_ftype_v2si_v2si
12231 = build_function_type (V4HI_type_node
,
12232 tree_cons (NULL_TREE
, V2SI_type_node
,
12233 tree_cons (NULL_TREE
, V2SI_type_node
,
12235 tree v2si_ftype_v4hi_v4hi
12236 = build_function_type (V2SI_type_node
,
12237 tree_cons (NULL_TREE
, V4HI_type_node
,
12238 tree_cons (NULL_TREE
, V4HI_type_node
,
12240 tree v2si_ftype_v8qi_v8qi
12241 = build_function_type (V2SI_type_node
,
12242 tree_cons (NULL_TREE
, V8QI_type_node
,
12243 tree_cons (NULL_TREE
, V8QI_type_node
,
12245 tree v4hi_ftype_v4hi_di
12246 = build_function_type (V4HI_type_node
,
12247 tree_cons (NULL_TREE
, V4HI_type_node
,
12248 tree_cons (NULL_TREE
,
12249 long_long_integer_type_node
,
12251 tree v2si_ftype_v2si_di
12252 = build_function_type (V2SI_type_node
,
12253 tree_cons (NULL_TREE
, V2SI_type_node
,
12254 tree_cons (NULL_TREE
,
12255 long_long_integer_type_node
,
12257 tree void_ftype_int_int
12258 = build_function_type (void_type_node
,
12259 tree_cons (NULL_TREE
, integer_type_node
,
12260 tree_cons (NULL_TREE
, integer_type_node
,
12263 = build_function_type (long_long_unsigned_type_node
, endlink
);
12265 = build_function_type (long_long_integer_type_node
,
12266 tree_cons (NULL_TREE
, V8QI_type_node
,
12269 = build_function_type (long_long_integer_type_node
,
12270 tree_cons (NULL_TREE
, V4HI_type_node
,
12273 = build_function_type (long_long_integer_type_node
,
12274 tree_cons (NULL_TREE
, V2SI_type_node
,
12276 tree v2si_ftype_v4hi
12277 = build_function_type (V2SI_type_node
,
12278 tree_cons (NULL_TREE
, V4HI_type_node
,
12280 tree v4hi_ftype_v8qi
12281 = build_function_type (V4HI_type_node
,
12282 tree_cons (NULL_TREE
, V8QI_type_node
,
12285 tree di_ftype_di_v4hi_v4hi
12286 = build_function_type (long_long_unsigned_type_node
,
12287 tree_cons (NULL_TREE
,
12288 long_long_unsigned_type_node
,
12289 tree_cons (NULL_TREE
, V4HI_type_node
,
12290 tree_cons (NULL_TREE
,
12294 tree di_ftype_v4hi_v4hi
12295 = build_function_type (long_long_unsigned_type_node
,
12296 tree_cons (NULL_TREE
, V4HI_type_node
,
12297 tree_cons (NULL_TREE
, V4HI_type_node
,
12300 /* Normal vector binops. */
12301 tree v8qi_ftype_v8qi_v8qi
12302 = build_function_type (V8QI_type_node
,
12303 tree_cons (NULL_TREE
, V8QI_type_node
,
12304 tree_cons (NULL_TREE
, V8QI_type_node
,
12306 tree v4hi_ftype_v4hi_v4hi
12307 = build_function_type (V4HI_type_node
,
12308 tree_cons (NULL_TREE
, V4HI_type_node
,
12309 tree_cons (NULL_TREE
, V4HI_type_node
,
12311 tree v2si_ftype_v2si_v2si
12312 = build_function_type (V2SI_type_node
,
12313 tree_cons (NULL_TREE
, V2SI_type_node
,
12314 tree_cons (NULL_TREE
, V2SI_type_node
,
12316 tree di_ftype_di_di
12317 = build_function_type (long_long_unsigned_type_node
,
12318 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12319 tree_cons (NULL_TREE
,
12320 long_long_unsigned_type_node
,
12323 /* Add all builtins that are more or less simple operations on two
12325 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12327 /* Use one of the operands; the target can have a different mode for
12328 mask-generating compares. */
12329 enum machine_mode mode
;
12335 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12340 type
= v8qi_ftype_v8qi_v8qi
;
12343 type
= v4hi_ftype_v4hi_v4hi
;
12346 type
= v2si_ftype_v2si_v2si
;
12349 type
= di_ftype_di_di
;
12353 gcc_unreachable ();
12356 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12359 /* Add the remaining MMX insns with somewhat more complicated types. */
12360 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12361 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12362 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12364 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12365 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12366 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12367 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12368 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12369 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12371 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12372 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12373 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12374 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12375 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12376 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12378 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12379 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12380 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12381 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12382 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12383 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12385 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12386 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12387 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12388 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12389 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12390 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12392 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12394 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12395 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12396 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12397 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12399 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12400 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12401 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12402 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12403 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12404 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12405 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12406 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12407 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12409 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12410 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12411 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12413 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12414 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12415 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12417 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12418 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12419 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12420 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12421 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12422 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12424 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12425 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12426 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12427 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12428 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12429 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12430 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12431 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12432 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12433 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12434 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12435 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12437 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12438 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12439 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12440 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12442 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12443 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12444 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12445 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12446 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12447 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12448 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12452 arm_init_tls_builtins (void)
12455 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
12456 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
12458 ftype
= build_function_type (ptr_type_node
, void_list_node
);
12459 lang_hooks
.builtin_function ("__builtin_thread_pointer", ftype
,
12460 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
12461 NULL
, const_nothrow
);
12465 arm_init_builtins (void)
12467 arm_init_tls_builtins ();
12469 if (TARGET_REALLY_IWMMXT
)
12470 arm_init_iwmmxt_builtins ();
12473 /* Errors in the source file can cause expand_expr to return const0_rtx
12474 where we expect a vector. To avoid crashing, use one of the vector
12475 clear instructions. */
12478 safe_vector_operand (rtx x
, enum machine_mode mode
)
12480 if (x
!= const0_rtx
)
12482 x
= gen_reg_rtx (mode
);
12484 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12485 : gen_rtx_SUBREG (DImode
, x
, 0)));
12489 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12492 arm_expand_binop_builtin (enum insn_code icode
,
12493 tree arglist
, rtx target
)
12496 tree arg0
= TREE_VALUE (arglist
);
12497 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12498 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12499 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12500 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12501 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12502 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12504 if (VECTOR_MODE_P (mode0
))
12505 op0
= safe_vector_operand (op0
, mode0
);
12506 if (VECTOR_MODE_P (mode1
))
12507 op1
= safe_vector_operand (op1
, mode1
);
12510 || GET_MODE (target
) != tmode
12511 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12512 target
= gen_reg_rtx (tmode
);
12514 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
12516 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12517 op0
= copy_to_mode_reg (mode0
, op0
);
12518 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12519 op1
= copy_to_mode_reg (mode1
, op1
);
12521 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12528 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12531 arm_expand_unop_builtin (enum insn_code icode
,
12532 tree arglist
, rtx target
, int do_load
)
12535 tree arg0
= TREE_VALUE (arglist
);
12536 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12537 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12538 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12541 || GET_MODE (target
) != tmode
12542 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12543 target
= gen_reg_rtx (tmode
);
12545 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12548 if (VECTOR_MODE_P (mode0
))
12549 op0
= safe_vector_operand (op0
, mode0
);
12551 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12552 op0
= copy_to_mode_reg (mode0
, op0
);
12555 pat
= GEN_FCN (icode
) (target
, op0
);
12562 /* Expand an expression EXP that calls a built-in function,
12563 with result going to TARGET if that's convenient
12564 (and in mode MODE if that's convenient).
12565 SUBTARGET may be used as the target for computing one of EXP's operands.
12566 IGNORE is nonzero if the value is to be ignored. */
12569 arm_expand_builtin (tree exp
,
12571 rtx subtarget ATTRIBUTE_UNUSED
,
12572 enum machine_mode mode ATTRIBUTE_UNUSED
,
12573 int ignore ATTRIBUTE_UNUSED
)
12575 const struct builtin_description
* d
;
12576 enum insn_code icode
;
12577 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12578 tree arglist
= TREE_OPERAND (exp
, 1);
12586 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12588 enum machine_mode tmode
;
12589 enum machine_mode mode0
;
12590 enum machine_mode mode1
;
12591 enum machine_mode mode2
;
12595 case ARM_BUILTIN_TEXTRMSB
:
12596 case ARM_BUILTIN_TEXTRMUB
:
12597 case ARM_BUILTIN_TEXTRMSH
:
12598 case ARM_BUILTIN_TEXTRMUH
:
12599 case ARM_BUILTIN_TEXTRMSW
:
12600 case ARM_BUILTIN_TEXTRMUW
:
12601 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12602 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12603 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12604 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12605 : CODE_FOR_iwmmxt_textrmw
);
12607 arg0
= TREE_VALUE (arglist
);
12608 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12609 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12610 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12611 tmode
= insn_data
[icode
].operand
[0].mode
;
12612 mode0
= insn_data
[icode
].operand
[1].mode
;
12613 mode1
= insn_data
[icode
].operand
[2].mode
;
12615 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12616 op0
= copy_to_mode_reg (mode0
, op0
);
12617 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12619 /* @@@ better error message */
12620 error ("selector must be an immediate");
12621 return gen_reg_rtx (tmode
);
12624 || GET_MODE (target
) != tmode
12625 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12626 target
= gen_reg_rtx (tmode
);
12627 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12633 case ARM_BUILTIN_TINSRB
:
12634 case ARM_BUILTIN_TINSRH
:
12635 case ARM_BUILTIN_TINSRW
:
12636 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12637 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12638 : CODE_FOR_iwmmxt_tinsrw
);
12639 arg0
= TREE_VALUE (arglist
);
12640 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12641 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12642 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12643 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12644 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12645 tmode
= insn_data
[icode
].operand
[0].mode
;
12646 mode0
= insn_data
[icode
].operand
[1].mode
;
12647 mode1
= insn_data
[icode
].operand
[2].mode
;
12648 mode2
= insn_data
[icode
].operand
[3].mode
;
12650 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12651 op0
= copy_to_mode_reg (mode0
, op0
);
12652 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12653 op1
= copy_to_mode_reg (mode1
, op1
);
12654 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12656 /* @@@ better error message */
12657 error ("selector must be an immediate");
12661 || GET_MODE (target
) != tmode
12662 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12663 target
= gen_reg_rtx (tmode
);
12664 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12670 case ARM_BUILTIN_SETWCX
:
12671 arg0
= TREE_VALUE (arglist
);
12672 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12673 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12674 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12675 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12678 case ARM_BUILTIN_GETWCX
:
12679 arg0
= TREE_VALUE (arglist
);
12680 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12681 target
= gen_reg_rtx (SImode
);
12682 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12685 case ARM_BUILTIN_WSHUFH
:
12686 icode
= CODE_FOR_iwmmxt_wshufh
;
12687 arg0
= TREE_VALUE (arglist
);
12688 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12689 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12690 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12691 tmode
= insn_data
[icode
].operand
[0].mode
;
12692 mode1
= insn_data
[icode
].operand
[1].mode
;
12693 mode2
= insn_data
[icode
].operand
[2].mode
;
12695 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12696 op0
= copy_to_mode_reg (mode1
, op0
);
12697 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12699 /* @@@ better error message */
12700 error ("mask must be an immediate");
12704 || GET_MODE (target
) != tmode
12705 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12706 target
= gen_reg_rtx (tmode
);
12707 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12713 case ARM_BUILTIN_WSADB
:
12714 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12715 case ARM_BUILTIN_WSADH
:
12716 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12717 case ARM_BUILTIN_WSADBZ
:
12718 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12719 case ARM_BUILTIN_WSADHZ
:
12720 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12722 /* Several three-argument builtins. */
12723 case ARM_BUILTIN_WMACS
:
12724 case ARM_BUILTIN_WMACU
:
12725 case ARM_BUILTIN_WALIGN
:
12726 case ARM_BUILTIN_TMIA
:
12727 case ARM_BUILTIN_TMIAPH
:
12728 case ARM_BUILTIN_TMIATT
:
12729 case ARM_BUILTIN_TMIATB
:
12730 case ARM_BUILTIN_TMIABT
:
12731 case ARM_BUILTIN_TMIABB
:
12732 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12733 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12734 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12735 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12736 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12737 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12738 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12739 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12740 : CODE_FOR_iwmmxt_walign
);
12741 arg0
= TREE_VALUE (arglist
);
12742 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12743 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12744 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12745 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12746 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12747 tmode
= insn_data
[icode
].operand
[0].mode
;
12748 mode0
= insn_data
[icode
].operand
[1].mode
;
12749 mode1
= insn_data
[icode
].operand
[2].mode
;
12750 mode2
= insn_data
[icode
].operand
[3].mode
;
12752 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12753 op0
= copy_to_mode_reg (mode0
, op0
);
12754 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12755 op1
= copy_to_mode_reg (mode1
, op1
);
12756 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12757 op2
= copy_to_mode_reg (mode2
, op2
);
12759 || GET_MODE (target
) != tmode
12760 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12761 target
= gen_reg_rtx (tmode
);
12762 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12768 case ARM_BUILTIN_WZERO
:
12769 target
= gen_reg_rtx (DImode
);
12770 emit_insn (gen_iwmmxt_clrdi (target
));
12773 case ARM_BUILTIN_THREAD_POINTER
:
12774 return arm_load_tp (target
);
12780 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12781 if (d
->code
== (const enum arm_builtins
) fcode
)
12782 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12784 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12785 if (d
->code
== (const enum arm_builtins
) fcode
)
12786 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12788 /* @@@ Should really do something sensible here. */
12792 /* Return the number (counting from 0) of
12793 the least significant set bit in MASK. */
12796 number_of_first_bit_set (unsigned mask
)
12801 (mask
& (1 << bit
)) == 0;
12808 /* Emit code to push or pop registers to or from the stack. F is the
12809 assembly file. MASK is the registers to push or pop. PUSH is
12810 nonzero if we should push, and zero if we should pop. For debugging
12811 output, if pushing, adjust CFA_OFFSET by the amount of space added
12812 to the stack. REAL_REGS should have the same number of bits set as
12813 MASK, and will be used instead (in the same order) to describe which
12814 registers were saved - this is used to mark the save slots when we
12815 push high registers after moving them to low registers. */
12817 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
12818 unsigned long real_regs
)
12821 int lo_mask
= mask
& 0xFF;
12822 int pushed_words
= 0;
12826 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12828 /* Special case. Do not generate a POP PC statement here, do it in
12830 thumb_exit (f
, -1);
12834 if (ARM_EABI_UNWIND_TABLES
&& push
)
12836 fprintf (f
, "\t.save\t{");
12837 for (regno
= 0; regno
< 15; regno
++)
12839 if (real_regs
& (1 << regno
))
12841 if (real_regs
& ((1 << regno
) -1))
12843 asm_fprintf (f
, "%r", regno
);
12846 fprintf (f
, "}\n");
12849 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12851 /* Look at the low registers first. */
12852 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12856 asm_fprintf (f
, "%r", regno
);
12858 if ((lo_mask
& ~1) != 0)
12865 if (push
&& (mask
& (1 << LR_REGNUM
)))
12867 /* Catch pushing the LR. */
12871 asm_fprintf (f
, "%r", LR_REGNUM
);
12875 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12877 /* Catch popping the PC. */
12878 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12879 || current_function_calls_eh_return
)
12881 /* The PC is never poped directly, instead
12882 it is popped into r3 and then BX is used. */
12883 fprintf (f
, "}\n");
12885 thumb_exit (f
, -1);
12894 asm_fprintf (f
, "%r", PC_REGNUM
);
12898 fprintf (f
, "}\n");
12900 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12902 char *l
= dwarf2out_cfi_label ();
12903 int pushed_mask
= real_regs
;
12905 *cfa_offset
+= pushed_words
* 4;
12906 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12909 pushed_mask
= real_regs
;
12910 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12912 if (pushed_mask
& 1)
12913 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12918 /* Generate code to return from a thumb function.
12919 If 'reg_containing_return_addr' is -1, then the return address is
12920 actually on the stack, at the stack pointer. */
12922 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12924 unsigned regs_available_for_popping
;
12925 unsigned regs_to_pop
;
12927 unsigned available
;
12931 int restore_a4
= FALSE
;
12933 /* Compute the registers we need to pop. */
12937 if (reg_containing_return_addr
== -1)
12939 regs_to_pop
|= 1 << LR_REGNUM
;
12943 if (TARGET_BACKTRACE
)
12945 /* Restore the (ARM) frame pointer and stack pointer. */
12946 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12950 /* If there is nothing to pop then just emit the BX instruction and
12952 if (pops_needed
== 0)
12954 if (current_function_calls_eh_return
)
12955 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12957 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12960 /* Otherwise if we are not supporting interworking and we have not created
12961 a backtrace structure and the function was not entered in ARM mode then
12962 just pop the return address straight into the PC. */
12963 else if (!TARGET_INTERWORK
12964 && !TARGET_BACKTRACE
12965 && !is_called_in_ARM_mode (current_function_decl
)
12966 && !current_function_calls_eh_return
)
12968 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12972 /* Find out how many of the (return) argument registers we can corrupt. */
12973 regs_available_for_popping
= 0;
12975 /* If returning via __builtin_eh_return, the bottom three registers
12976 all contain information needed for the return. */
12977 if (current_function_calls_eh_return
)
12981 /* If we can deduce the registers used from the function's
12982 return value. This is more reliable that examining
12983 regs_ever_live[] because that will be set if the register is
12984 ever used in the function, not just if the register is used
12985 to hold a return value. */
12987 if (current_function_return_rtx
!= 0)
12988 mode
= GET_MODE (current_function_return_rtx
);
12990 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12992 size
= GET_MODE_SIZE (mode
);
12996 /* In a void function we can use any argument register.
12997 In a function that returns a structure on the stack
12998 we can use the second and third argument registers. */
12999 if (mode
== VOIDmode
)
13000 regs_available_for_popping
=
13001 (1 << ARG_REGISTER (1))
13002 | (1 << ARG_REGISTER (2))
13003 | (1 << ARG_REGISTER (3));
13005 regs_available_for_popping
=
13006 (1 << ARG_REGISTER (2))
13007 | (1 << ARG_REGISTER (3));
13009 else if (size
<= 4)
13010 regs_available_for_popping
=
13011 (1 << ARG_REGISTER (2))
13012 | (1 << ARG_REGISTER (3));
13013 else if (size
<= 8)
13014 regs_available_for_popping
=
13015 (1 << ARG_REGISTER (3));
13018 /* Match registers to be popped with registers into which we pop them. */
13019 for (available
= regs_available_for_popping
,
13020 required
= regs_to_pop
;
13021 required
!= 0 && available
!= 0;
13022 available
&= ~(available
& - available
),
13023 required
&= ~(required
& - required
))
13026 /* If we have any popping registers left over, remove them. */
13028 regs_available_for_popping
&= ~available
;
13030 /* Otherwise if we need another popping register we can use
13031 the fourth argument register. */
13032 else if (pops_needed
)
13034 /* If we have not found any free argument registers and
13035 reg a4 contains the return address, we must move it. */
13036 if (regs_available_for_popping
== 0
13037 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13039 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13040 reg_containing_return_addr
= LR_REGNUM
;
13042 else if (size
> 12)
13044 /* Register a4 is being used to hold part of the return value,
13045 but we have dire need of a free, low register. */
13048 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13051 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13053 /* The fourth argument register is available. */
13054 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13060 /* Pop as many registers as we can. */
13061 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13062 regs_available_for_popping
);
13064 /* Process the registers we popped. */
13065 if (reg_containing_return_addr
== -1)
13067 /* The return address was popped into the lowest numbered register. */
13068 regs_to_pop
&= ~(1 << LR_REGNUM
);
13070 reg_containing_return_addr
=
13071 number_of_first_bit_set (regs_available_for_popping
);
13073 /* Remove this register for the mask of available registers, so that
13074 the return address will not be corrupted by further pops. */
13075 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13078 /* If we popped other registers then handle them here. */
13079 if (regs_available_for_popping
)
13083 /* Work out which register currently contains the frame pointer. */
13084 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13086 /* Move it into the correct place. */
13087 asm_fprintf (f
, "\tmov\t%r, %r\n",
13088 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13090 /* (Temporarily) remove it from the mask of popped registers. */
13091 regs_available_for_popping
&= ~(1 << frame_pointer
);
13092 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13094 if (regs_available_for_popping
)
13098 /* We popped the stack pointer as well,
13099 find the register that contains it. */
13100 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13102 /* Move it into the stack register. */
13103 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
13105 /* At this point we have popped all necessary registers, so
13106 do not worry about restoring regs_available_for_popping
13107 to its correct value:
13109 assert (pops_needed == 0)
13110 assert (regs_available_for_popping == (1 << frame_pointer))
13111 assert (regs_to_pop == (1 << STACK_POINTER)) */
13115 /* Since we have just move the popped value into the frame
13116 pointer, the popping register is available for reuse, and
13117 we know that we still have the stack pointer left to pop. */
13118 regs_available_for_popping
|= (1 << frame_pointer
);
13122 /* If we still have registers left on the stack, but we no longer have
13123 any registers into which we can pop them, then we must move the return
13124 address into the link register and make available the register that
13126 if (regs_available_for_popping
== 0 && pops_needed
> 0)
13128 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
13130 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
13131 reg_containing_return_addr
);
13133 reg_containing_return_addr
= LR_REGNUM
;
13136 /* If we have registers left on the stack then pop some more.
13137 We know that at most we will want to pop FP and SP. */
13138 if (pops_needed
> 0)
13143 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13144 regs_available_for_popping
);
13146 /* We have popped either FP or SP.
13147 Move whichever one it is into the correct register. */
13148 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13149 move_to
= number_of_first_bit_set (regs_to_pop
);
13151 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
13153 regs_to_pop
&= ~(1 << move_to
);
13158 /* If we still have not popped everything then we must have only
13159 had one register available to us and we are now popping the SP. */
13160 if (pops_needed
> 0)
13164 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13165 regs_available_for_popping
);
13167 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
13169 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
13171 assert (regs_to_pop == (1 << STACK_POINTER))
13172 assert (pops_needed == 1)
13176 /* If necessary restore the a4 register. */
13179 if (reg_containing_return_addr
!= LR_REGNUM
)
13181 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13182 reg_containing_return_addr
= LR_REGNUM
;
13185 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13188 if (current_function_calls_eh_return
)
13189 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13191 /* Return to caller. */
13192 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13197 thumb_final_prescan_insn (rtx insn
)
13199 if (flag_print_asm_name
)
13200 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
13201 INSN_ADDRESSES (INSN_UID (insn
)));
13205 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
13207 unsigned HOST_WIDE_INT mask
= 0xff;
13210 if (val
== 0) /* XXX */
13213 for (i
= 0; i
< 25; i
++)
13214 if ((val
& (mask
<< i
)) == val
)
13220 /* Returns nonzero if the current function contains,
13221 or might contain a far jump. */
13223 thumb_far_jump_used_p (void)
13227 /* This test is only important for leaf functions. */
13228 /* assert (!leaf_function_p ()); */
13230 /* If we have already decided that far jumps may be used,
13231 do not bother checking again, and always return true even if
13232 it turns out that they are not being used. Once we have made
13233 the decision that far jumps are present (and that hence the link
13234 register will be pushed onto the stack) we cannot go back on it. */
13235 if (cfun
->machine
->far_jump_used
)
13238 /* If this function is not being called from the prologue/epilogue
13239 generation code then it must be being called from the
13240 INITIAL_ELIMINATION_OFFSET macro. */
13241 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
13243 /* In this case we know that we are being asked about the elimination
13244 of the arg pointer register. If that register is not being used,
13245 then there are no arguments on the stack, and we do not have to
13246 worry that a far jump might force the prologue to push the link
13247 register, changing the stack offsets. In this case we can just
13248 return false, since the presence of far jumps in the function will
13249 not affect stack offsets.
13251 If the arg pointer is live (or if it was live, but has now been
13252 eliminated and so set to dead) then we do have to test to see if
13253 the function might contain a far jump. This test can lead to some
13254 false negatives, since before reload is completed, then length of
13255 branch instructions is not known, so gcc defaults to returning their
13256 longest length, which in turn sets the far jump attribute to true.
13258 A false negative will not result in bad code being generated, but it
13259 will result in a needless push and pop of the link register. We
13260 hope that this does not occur too often.
13262 If we need doubleword stack alignment this could affect the other
13263 elimination offsets so we can't risk getting it wrong. */
13264 if (regs_ever_live
[ARG_POINTER_REGNUM
])
13265 cfun
->machine
->arg_pointer_live
= 1;
13266 else if (!cfun
->machine
->arg_pointer_live
)
13270 /* Check to see if the function contains a branch
13271 insn with the far jump attribute set. */
13272 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13274 if (GET_CODE (insn
) == JUMP_INSN
13275 /* Ignore tablejump patterns. */
13276 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13277 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13278 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13281 /* Record the fact that we have decided that
13282 the function does use far jumps. */
13283 cfun
->machine
->far_jump_used
= 1;
13291 /* Return nonzero if FUNC must be entered in ARM mode. */
13293 is_called_in_ARM_mode (tree func
)
13295 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
13297 /* Ignore the problem about functions whose address is taken. */
13298 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13302 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13308 /* The bits which aren't usefully expanded as rtl. */
13310 thumb_unexpanded_epilogue (void)
13313 unsigned long live_regs_mask
= 0;
13314 int high_regs_pushed
= 0;
13315 int had_to_push_lr
;
13318 if (return_used_this_function
)
13321 if (IS_NAKED (arm_current_func_type ()))
13324 live_regs_mask
= thumb_compute_save_reg_mask ();
13325 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13327 /* If we can deduce the registers used from the function's return value.
13328 This is more reliable that examining regs_ever_live[] because that
13329 will be set if the register is ever used in the function, not just if
13330 the register is used to hold a return value. */
13331 size
= arm_size_return_regs ();
13333 /* The prolog may have pushed some high registers to use as
13334 work registers. e.g. the testsuite file:
13335 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13336 compiles to produce:
13337 push {r4, r5, r6, r7, lr}
13341 as part of the prolog. We have to undo that pushing here. */
13343 if (high_regs_pushed
)
13345 unsigned long mask
= live_regs_mask
& 0xff;
13348 /* The available low registers depend on the size of the value we are
13356 /* Oh dear! We have no low registers into which we can pop
13359 ("no low registers available for popping high registers");
13361 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13362 if (live_regs_mask
& (1 << next_hi_reg
))
13365 while (high_regs_pushed
)
13367 /* Find lo register(s) into which the high register(s) can
13369 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13371 if (mask
& (1 << regno
))
13372 high_regs_pushed
--;
13373 if (high_regs_pushed
== 0)
13377 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13379 /* Pop the values into the low register(s). */
13380 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13382 /* Move the value(s) into the high registers. */
13383 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13385 if (mask
& (1 << regno
))
13387 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13390 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13391 if (live_regs_mask
& (1 << next_hi_reg
))
13396 live_regs_mask
&= ~0x0f00;
13399 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
13400 live_regs_mask
&= 0xff;
13402 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13404 /* Pop the return address into the PC. */
13405 if (had_to_push_lr
)
13406 live_regs_mask
|= 1 << PC_REGNUM
;
13408 /* Either no argument registers were pushed or a backtrace
13409 structure was created which includes an adjusted stack
13410 pointer, so just pop everything. */
13411 if (live_regs_mask
)
13412 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13415 /* We have either just popped the return address into the
13416 PC or it is was kept in LR for the entire function. */
13417 if (!had_to_push_lr
)
13418 thumb_exit (asm_out_file
, LR_REGNUM
);
13422 /* Pop everything but the return address. */
13423 if (live_regs_mask
)
13424 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13427 if (had_to_push_lr
)
13431 /* We have no free low regs, so save one. */
13432 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
13436 /* Get the return address into a temporary register. */
13437 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13438 1 << LAST_ARG_REGNUM
);
13442 /* Move the return address to lr. */
13443 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
13445 /* Restore the low register. */
13446 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
13451 regno
= LAST_ARG_REGNUM
;
13456 /* Remove the argument registers that were pushed onto the stack. */
13457 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13458 SP_REGNUM
, SP_REGNUM
,
13459 current_function_pretend_args_size
);
13461 thumb_exit (asm_out_file
, regno
);
13467 /* Functions to save and restore machine-specific function data. */
13468 static struct machine_function
*
13469 arm_init_machine_status (void)
13471 struct machine_function
*machine
;
13472 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13474 #if ARM_FT_UNKNOWN != 0
13475 machine
->func_type
= ARM_FT_UNKNOWN
;
13480 /* Return an RTX indicating where the return address to the
13481 calling function can be found. */
13483 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13488 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13491 /* Do anything needed before RTL is emitted for each function. */
13493 arm_init_expanders (void)
13495 /* Arrange to initialize and mark the machine per-function status. */
13496 init_machine_status
= arm_init_machine_status
;
13498 /* This is to stop the combine pass optimizing away the alignment
13499 adjustment of va_arg. */
13500 /* ??? It is claimed that this should not be necessary. */
13502 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13506 /* Like arm_compute_initial_elimination offset. Simpler because there
13507 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13508 to point at the base of the local variables after static stack
13509 space for a function has been allocated. */
13512 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13514 arm_stack_offsets
*offsets
;
13516 offsets
= arm_get_frame_offsets ();
13520 case ARG_POINTER_REGNUM
:
13523 case STACK_POINTER_REGNUM
:
13524 return offsets
->outgoing_args
- offsets
->saved_args
;
13526 case FRAME_POINTER_REGNUM
:
13527 return offsets
->soft_frame
- offsets
->saved_args
;
13529 case ARM_HARD_FRAME_POINTER_REGNUM
:
13530 return offsets
->saved_regs
- offsets
->saved_args
;
13532 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13533 return offsets
->locals_base
- offsets
->saved_args
;
13536 gcc_unreachable ();
13540 case FRAME_POINTER_REGNUM
:
13543 case STACK_POINTER_REGNUM
:
13544 return offsets
->outgoing_args
- offsets
->soft_frame
;
13546 case ARM_HARD_FRAME_POINTER_REGNUM
:
13547 return offsets
->saved_regs
- offsets
->soft_frame
;
13549 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13550 return offsets
->locals_base
- offsets
->soft_frame
;
13553 gcc_unreachable ();
13558 gcc_unreachable ();
13563 /* Generate the rest of a function's prologue. */
13565 thumb_expand_prologue (void)
13569 HOST_WIDE_INT amount
;
13570 arm_stack_offsets
*offsets
;
13571 unsigned long func_type
;
13573 unsigned long live_regs_mask
;
13575 func_type
= arm_current_func_type ();
13577 /* Naked functions don't have prologues. */
13578 if (IS_NAKED (func_type
))
13581 if (IS_INTERRUPT (func_type
))
13583 error ("interrupt Service Routines cannot be coded in Thumb mode");
13587 live_regs_mask
= thumb_compute_save_reg_mask ();
13588 /* Load the pic register before setting the frame pointer,
13589 so we can use r7 as a temporary work register. */
13591 arm_load_pic_register (live_regs_mask
);
13593 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13594 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
13595 stack_pointer_rtx
);
13597 offsets
= arm_get_frame_offsets ();
13598 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13603 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13604 GEN_INT (- amount
)));
13605 RTX_FRAME_RELATED_P (insn
) = 1;
13611 /* The stack decrement is too big for an immediate value in a single
13612 insn. In theory we could issue multiple subtracts, but after
13613 three of them it becomes more space efficient to place the full
13614 value in the constant pool and load into a register. (Also the
13615 ARM debugger really likes to see only one stack decrement per
13616 function). So instead we look for a scratch register into which
13617 we can load the decrement, and then we subtract this from the
13618 stack pointer. Unfortunately on the thumb the only available
13619 scratch registers are the argument registers, and we cannot use
13620 these as they may hold arguments to the function. Instead we
13621 attempt to locate a call preserved register which is used by this
13622 function. If we can find one, then we know that it will have
13623 been pushed at the start of the prologue and so we can corrupt
13625 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13626 if (live_regs_mask
& (1 << regno
)
13627 && !(frame_pointer_needed
13628 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13631 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13633 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13635 /* Choose an arbitrary, non-argument low register. */
13636 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13638 /* Save it by copying it into a high, scratch register. */
13639 emit_insn (gen_movsi (spare
, reg
));
13640 /* Add a USE to stop propagate_one_insn() from barfing. */
13641 emit_insn (gen_prologue_use (spare
));
13643 /* Decrement the stack. */
13644 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13645 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13646 stack_pointer_rtx
, reg
));
13647 RTX_FRAME_RELATED_P (insn
) = 1;
13648 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13649 plus_constant (stack_pointer_rtx
,
13651 RTX_FRAME_RELATED_P (dwarf
) = 1;
13653 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13656 /* Restore the low register's original value. */
13657 emit_insn (gen_movsi (reg
, spare
));
13659 /* Emit a USE of the restored scratch register, so that flow
13660 analysis will not consider the restore redundant. The
13661 register won't be used again in this function and isn't
13662 restored by the epilogue. */
13663 emit_insn (gen_prologue_use (reg
));
13667 reg
= gen_rtx_REG (SImode
, regno
);
13669 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13671 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13672 stack_pointer_rtx
, reg
));
13673 RTX_FRAME_RELATED_P (insn
) = 1;
13674 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13675 plus_constant (stack_pointer_rtx
,
13677 RTX_FRAME_RELATED_P (dwarf
) = 1;
13679 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13685 if (frame_pointer_needed
)
13687 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
13690 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13691 stack_pointer_rtx
, GEN_INT (amount
)));
13694 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
13695 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
13696 hard_frame_pointer_rtx
,
13697 stack_pointer_rtx
));
13698 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
13699 plus_constant (stack_pointer_rtx
, amount
));
13700 RTX_FRAME_RELATED_P (dwarf
) = 1;
13701 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13705 RTX_FRAME_RELATED_P (insn
) = 1;
13708 /* If we are profiling, make sure no instructions are scheduled before
13709 the call to mcount. Similarly if the user has requested no
13710 scheduling in the prolog. Similarly if we want non-call exceptions
13711 using the EABI unwinder, to prevent faulting instructions from being
13712 swapped with a stack adjustment. */
13713 if (current_function_profile
|| !TARGET_SCHED_PROLOG
13714 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
13715 emit_insn (gen_blockage ());
13717 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13718 if (live_regs_mask
& 0xff)
13719 cfun
->machine
->lr_save_eliminated
= 0;
13721 /* If the link register is being kept alive, with the return address in it,
13722 then make sure that it does not get reused by the ce2 pass. */
13723 if (cfun
->machine
->lr_save_eliminated
)
13724 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13729 thumb_expand_epilogue (void)
13731 HOST_WIDE_INT amount
;
13732 arm_stack_offsets
*offsets
;
13735 /* Naked functions don't have prologues. */
13736 if (IS_NAKED (arm_current_func_type ()))
13739 offsets
= arm_get_frame_offsets ();
13740 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13742 if (frame_pointer_needed
)
13744 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13745 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13751 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13752 GEN_INT (amount
)));
13755 /* r3 is always free in the epilogue. */
13756 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13758 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13759 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13763 /* Emit a USE (stack_pointer_rtx), so that
13764 the stack adjustment will not be deleted. */
13765 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13767 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
13768 emit_insn (gen_blockage ());
13770 /* Emit a clobber for each insn that will be restored in the epilogue,
13771 so that flow2 will get register lifetimes correct. */
13772 for (regno
= 0; regno
< 13; regno
++)
13773 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13774 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13776 if (! regs_ever_live
[LR_REGNUM
])
13777 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13781 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13783 unsigned long live_regs_mask
= 0;
13784 unsigned long l_mask
;
13785 unsigned high_regs_pushed
= 0;
13786 int cfa_offset
= 0;
13789 if (IS_NAKED (arm_current_func_type ()))
13792 if (is_called_in_ARM_mode (current_function_decl
))
13796 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
13797 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
13799 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13801 /* Generate code sequence to switch us into Thumb mode. */
13802 /* The .code 32 directive has already been emitted by
13803 ASM_DECLARE_FUNCTION_NAME. */
13804 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13805 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13807 /* Generate a label, so that the debugger will notice the
13808 change in instruction sets. This label is also used by
13809 the assembler to bypass the ARM code when this function
13810 is called from a Thumb encoded function elsewhere in the
13811 same file. Hence the definition of STUB_NAME here must
13812 agree with the definition in gas/config/tc-arm.c. */
13814 #define STUB_NAME ".real_start_of"
13816 fprintf (f
, "\t.code\t16\n");
13818 if (arm_dllexport_name_p (name
))
13819 name
= arm_strip_name_encoding (name
);
13821 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13822 fprintf (f
, "\t.thumb_func\n");
13823 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13826 if (current_function_pretend_args_size
)
13828 /* Output unwind directive for the stack adjustment. */
13829 if (ARM_EABI_UNWIND_TABLES
)
13830 fprintf (f
, "\t.pad #%d\n",
13831 current_function_pretend_args_size
);
13833 if (cfun
->machine
->uses_anonymous_args
)
13837 fprintf (f
, "\tpush\t{");
13839 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13841 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13842 regno
<= LAST_ARG_REGNUM
;
13844 asm_fprintf (f
, "%r%s", regno
,
13845 regno
== LAST_ARG_REGNUM
? "" : ", ");
13847 fprintf (f
, "}\n");
13850 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13851 SP_REGNUM
, SP_REGNUM
,
13852 current_function_pretend_args_size
);
13854 /* We don't need to record the stores for unwinding (would it
13855 help the debugger any if we did?), but record the change in
13856 the stack pointer. */
13857 if (dwarf2out_do_frame ())
13859 char *l
= dwarf2out_cfi_label ();
13861 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13862 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13866 /* Get the registers we are going to push. */
13867 live_regs_mask
= thumb_compute_save_reg_mask ();
13868 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13869 l_mask
= live_regs_mask
& 0x40ff;
13870 /* Then count how many other high registers will need to be pushed. */
13871 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
13873 if (TARGET_BACKTRACE
)
13876 unsigned work_register
;
13878 /* We have been asked to create a stack backtrace structure.
13879 The code looks like this:
13883 0 sub SP, #16 Reserve space for 4 registers.
13884 2 push {R7} Push low registers.
13885 4 add R7, SP, #20 Get the stack pointer before the push.
13886 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13887 8 mov R7, PC Get hold of the start of this code plus 12.
13888 10 str R7, [SP, #16] Store it.
13889 12 mov R7, FP Get hold of the current frame pointer.
13890 14 str R7, [SP, #4] Store it.
13891 16 mov R7, LR Get hold of the current return address.
13892 18 str R7, [SP, #12] Store it.
13893 20 add R7, SP, #16 Point at the start of the backtrace structure.
13894 22 mov FP, R7 Put this value into the frame pointer. */
13896 work_register
= thumb_find_work_register (live_regs_mask
);
13898 if (ARM_EABI_UNWIND_TABLES
)
13899 asm_fprintf (f
, "\t.pad #16\n");
13902 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13903 SP_REGNUM
, SP_REGNUM
);
13905 if (dwarf2out_do_frame ())
13907 char *l
= dwarf2out_cfi_label ();
13909 cfa_offset
= cfa_offset
+ 16;
13910 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13915 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13916 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
13921 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13922 offset
+ 16 + current_function_pretend_args_size
);
13924 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13927 /* Make sure that the instruction fetching the PC is in the right place
13928 to calculate "start of backtrace creation code + 12". */
13931 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13932 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13934 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13935 ARM_HARD_FRAME_POINTER_REGNUM
);
13936 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13941 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13942 ARM_HARD_FRAME_POINTER_REGNUM
);
13943 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13945 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13946 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13950 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13951 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13953 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13955 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13956 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13958 /* Optimization: If we are not pushing any low registers but we are going
13959 to push some high registers then delay our first push. This will just
13960 be a push of LR and we can combine it with the push of the first high
13962 else if ((l_mask
& 0xff) != 0
13963 || (high_regs_pushed
== 0 && l_mask
))
13964 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
13966 if (high_regs_pushed
)
13968 unsigned pushable_regs
;
13969 unsigned next_hi_reg
;
13971 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13972 if (live_regs_mask
& (1 << next_hi_reg
))
13975 pushable_regs
= l_mask
& 0xff;
13977 if (pushable_regs
== 0)
13978 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
13980 while (high_regs_pushed
> 0)
13982 unsigned long real_regs_mask
= 0;
13984 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13986 if (pushable_regs
& (1 << regno
))
13988 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13990 high_regs_pushed
--;
13991 real_regs_mask
|= (1 << next_hi_reg
);
13993 if (high_regs_pushed
)
13995 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13997 if (live_regs_mask
& (1 << next_hi_reg
))
14002 pushable_regs
&= ~((1 << regno
) - 1);
14008 /* If we had to find a work register and we have not yet
14009 saved the LR then add it to the list of regs to push. */
14010 if (l_mask
== (1 << LR_REGNUM
))
14012 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14014 real_regs_mask
| (1 << LR_REGNUM
));
14018 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14023 /* Handle the case of a double word load into a low register from
14024 a computed memory address. The computed address may involve a
14025 register which is overwritten by the load. */
14027 thumb_load_double_from_address (rtx
*operands
)
14035 gcc_assert (GET_CODE (operands
[0]) == REG
);
14036 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14038 /* Get the memory address. */
14039 addr
= XEXP (operands
[1], 0);
14041 /* Work out how the memory address is computed. */
14042 switch (GET_CODE (addr
))
14045 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14047 if (REGNO (operands
[0]) == REGNO (addr
))
14049 output_asm_insn ("ldr\t%H0, %2", operands
);
14050 output_asm_insn ("ldr\t%0, %1", operands
);
14054 output_asm_insn ("ldr\t%0, %1", operands
);
14055 output_asm_insn ("ldr\t%H0, %2", operands
);
14060 /* Compute <address> + 4 for the high order load. */
14061 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14063 output_asm_insn ("ldr\t%0, %1", operands
);
14064 output_asm_insn ("ldr\t%H0, %2", operands
);
14068 arg1
= XEXP (addr
, 0);
14069 arg2
= XEXP (addr
, 1);
14071 if (CONSTANT_P (arg1
))
14072 base
= arg2
, offset
= arg1
;
14074 base
= arg1
, offset
= arg2
;
14076 gcc_assert (GET_CODE (base
) == REG
);
14078 /* Catch the case of <address> = <reg> + <reg> */
14079 if (GET_CODE (offset
) == REG
)
14081 int reg_offset
= REGNO (offset
);
14082 int reg_base
= REGNO (base
);
14083 int reg_dest
= REGNO (operands
[0]);
14085 /* Add the base and offset registers together into the
14086 higher destination register. */
14087 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14088 reg_dest
+ 1, reg_base
, reg_offset
);
14090 /* Load the lower destination register from the address in
14091 the higher destination register. */
14092 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14093 reg_dest
, reg_dest
+ 1);
14095 /* Load the higher destination register from its own address
14097 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14098 reg_dest
+ 1, reg_dest
+ 1);
14102 /* Compute <address> + 4 for the high order load. */
14103 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14105 /* If the computed address is held in the low order register
14106 then load the high order register first, otherwise always
14107 load the low order register first. */
14108 if (REGNO (operands
[0]) == REGNO (base
))
14110 output_asm_insn ("ldr\t%H0, %2", operands
);
14111 output_asm_insn ("ldr\t%0, %1", operands
);
14115 output_asm_insn ("ldr\t%0, %1", operands
);
14116 output_asm_insn ("ldr\t%H0, %2", operands
);
14122 /* With no registers to worry about we can just load the value
14124 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14126 output_asm_insn ("ldr\t%H0, %2", operands
);
14127 output_asm_insn ("ldr\t%0, %1", operands
);
14131 gcc_unreachable ();
14138 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
14145 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14148 operands
[4] = operands
[5];
14151 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
14152 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
14156 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14159 operands
[4] = operands
[5];
14162 if (REGNO (operands
[5]) > REGNO (operands
[6]))
14165 operands
[5] = operands
[6];
14168 if (REGNO (operands
[4]) > REGNO (operands
[5]))
14171 operands
[4] = operands
[5];
14175 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
14176 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
14180 gcc_unreachable ();
14186 /* Output a call-via instruction for thumb state. */
14188 thumb_call_via_reg (rtx reg
)
14190 int regno
= REGNO (reg
);
14193 gcc_assert (regno
< LR_REGNUM
);
14195 /* If we are in the normal text section we can use a single instance
14196 per compilation unit. If we are doing function sections, then we need
14197 an entry per section, since we can't rely on reachability. */
14198 if (in_text_section ())
14200 thumb_call_reg_needed
= 1;
14202 if (thumb_call_via_label
[regno
] == NULL
)
14203 thumb_call_via_label
[regno
] = gen_label_rtx ();
14204 labelp
= thumb_call_via_label
+ regno
;
14208 if (cfun
->machine
->call_via
[regno
] == NULL
)
14209 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
14210 labelp
= cfun
->machine
->call_via
+ regno
;
14213 output_asm_insn ("bl\t%a0", labelp
);
14217 /* Routines for generating rtl. */
14219 thumb_expand_movmemqi (rtx
*operands
)
14221 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
14222 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
14223 HOST_WIDE_INT len
= INTVAL (operands
[2]);
14224 HOST_WIDE_INT offset
= 0;
14228 emit_insn (gen_movmem12b (out
, in
, out
, in
));
14234 emit_insn (gen_movmem8b (out
, in
, out
, in
));
14240 rtx reg
= gen_reg_rtx (SImode
);
14241 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
14242 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
14249 rtx reg
= gen_reg_rtx (HImode
);
14250 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
14251 plus_constant (in
, offset
))));
14252 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
14260 rtx reg
= gen_reg_rtx (QImode
);
14261 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
14262 plus_constant (in
, offset
))));
14263 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
14269 thumb_reload_out_hi (rtx
*operands
)
14271 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
14274 /* Handle reading a half-word from memory during reload. */
14276 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
14278 gcc_unreachable ();
14281 /* Return the length of a function name prefix
14282 that starts with the character 'c'. */
14284 arm_get_strip_length (int c
)
14288 ARM_NAME_ENCODING_LENGTHS
14293 /* Return a pointer to a function's name with any
14294 and all prefix encodings stripped from it. */
14296 arm_strip_name_encoding (const char *name
)
14300 while ((skip
= arm_get_strip_length (* name
)))
14306 /* If there is a '*' anywhere in the name's prefix, then
14307 emit the stripped name verbatim, otherwise prepend an
14308 underscore if leading underscores are being used. */
14310 arm_asm_output_labelref (FILE *stream
, const char *name
)
14315 while ((skip
= arm_get_strip_length (* name
)))
14317 verbatim
|= (*name
== '*');
14322 fputs (name
, stream
);
14324 asm_fprintf (stream
, "%U%s", name
);
14328 arm_file_end (void)
14332 if (! thumb_call_reg_needed
)
14336 asm_fprintf (asm_out_file
, "\t.code 16\n");
14337 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
14339 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14341 rtx label
= thumb_call_via_label
[regno
];
14345 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14346 CODE_LABEL_NUMBER (label
));
14347 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14354 #ifdef AOF_ASSEMBLER
14355 /* Special functions only needed when producing AOF syntax assembler. */
14359 struct pic_chain
* next
;
14360 const char * symname
;
14363 static struct pic_chain
* aof_pic_chain
= NULL
;
14366 aof_pic_entry (rtx x
)
14368 struct pic_chain
** chainp
;
14371 if (aof_pic_label
== NULL_RTX
)
14373 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14376 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14377 offset
+= 4, chainp
= &(*chainp
)->next
)
14378 if ((*chainp
)->symname
== XSTR (x
, 0))
14379 return plus_constant (aof_pic_label
, offset
);
14381 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14382 (*chainp
)->next
= NULL
;
14383 (*chainp
)->symname
= XSTR (x
, 0);
14384 return plus_constant (aof_pic_label
, offset
);
14388 aof_dump_pic_table (FILE *f
)
14390 struct pic_chain
* chain
;
14392 if (aof_pic_chain
== NULL
)
14395 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14396 PIC_OFFSET_TABLE_REGNUM
,
14397 PIC_OFFSET_TABLE_REGNUM
);
14398 fputs ("|x$adcons|\n", f
);
14400 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14402 fputs ("\tDCD\t", f
);
14403 assemble_name (f
, chain
->symname
);
14408 int arm_text_section_count
= 1;
14411 aof_text_section (void )
14413 static char buf
[100];
14414 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14415 arm_text_section_count
++);
14417 strcat (buf
, ", PIC, REENTRANT");
14421 static int arm_data_section_count
= 1;
14424 aof_data_section (void)
14426 static char buf
[100];
14427 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14431 /* The AOF assembler is religiously strict about declarations of
14432 imported and exported symbols, so that it is impossible to declare
14433 a function as imported near the beginning of the file, and then to
14434 export it later on. It is, however, possible to delay the decision
14435 until all the functions in the file have been compiled. To get
14436 around this, we maintain a list of the imports and exports, and
14437 delete from it any that are subsequently defined. At the end of
14438 compilation we spit the remainder of the list out before the END
14443 struct import
* next
;
14447 static struct import
* imports_list
= NULL
;
14450 aof_add_import (const char *name
)
14452 struct import
* new;
14454 for (new = imports_list
; new; new = new->next
)
14455 if (new->name
== name
)
14458 new = (struct import
*) xmalloc (sizeof (struct import
));
14459 new->next
= imports_list
;
14460 imports_list
= new;
14465 aof_delete_import (const char *name
)
14467 struct import
** old
;
14469 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14471 if ((*old
)->name
== name
)
14473 *old
= (*old
)->next
;
14479 int arm_main_function
= 0;
14482 aof_dump_imports (FILE *f
)
14484 /* The AOF assembler needs this to cause the startup code to be extracted
14485 from the library. Brining in __main causes the whole thing to work
14487 if (arm_main_function
)
14490 fputs ("\tIMPORT __main\n", f
);
14491 fputs ("\tDCD __main\n", f
);
14494 /* Now dump the remaining imports. */
14495 while (imports_list
)
14497 fprintf (f
, "\tIMPORT\t");
14498 assemble_name (f
, imports_list
->name
);
14500 imports_list
= imports_list
->next
;
14505 aof_globalize_label (FILE *stream
, const char *name
)
14507 default_globalize_label (stream
, name
);
14508 if (! strcmp (name
, "main"))
14509 arm_main_function
= 1;
14513 aof_file_start (void)
14515 fputs ("__r0\tRN\t0\n", asm_out_file
);
14516 fputs ("__a1\tRN\t0\n", asm_out_file
);
14517 fputs ("__a2\tRN\t1\n", asm_out_file
);
14518 fputs ("__a3\tRN\t2\n", asm_out_file
);
14519 fputs ("__a4\tRN\t3\n", asm_out_file
);
14520 fputs ("__v1\tRN\t4\n", asm_out_file
);
14521 fputs ("__v2\tRN\t5\n", asm_out_file
);
14522 fputs ("__v3\tRN\t6\n", asm_out_file
);
14523 fputs ("__v4\tRN\t7\n", asm_out_file
);
14524 fputs ("__v5\tRN\t8\n", asm_out_file
);
14525 fputs ("__v6\tRN\t9\n", asm_out_file
);
14526 fputs ("__sl\tRN\t10\n", asm_out_file
);
14527 fputs ("__fp\tRN\t11\n", asm_out_file
);
14528 fputs ("__ip\tRN\t12\n", asm_out_file
);
14529 fputs ("__sp\tRN\t13\n", asm_out_file
);
14530 fputs ("__lr\tRN\t14\n", asm_out_file
);
14531 fputs ("__pc\tRN\t15\n", asm_out_file
);
14532 fputs ("__f0\tFN\t0\n", asm_out_file
);
14533 fputs ("__f1\tFN\t1\n", asm_out_file
);
14534 fputs ("__f2\tFN\t2\n", asm_out_file
);
14535 fputs ("__f3\tFN\t3\n", asm_out_file
);
14536 fputs ("__f4\tFN\t4\n", asm_out_file
);
14537 fputs ("__f5\tFN\t5\n", asm_out_file
);
14538 fputs ("__f6\tFN\t6\n", asm_out_file
);
14539 fputs ("__f7\tFN\t7\n", asm_out_file
);
14544 aof_file_end (void)
14547 aof_dump_pic_table (asm_out_file
);
14549 aof_dump_imports (asm_out_file
);
14550 fputs ("\tEND\n", asm_out_file
);
14552 #endif /* AOF_ASSEMBLER */
14555 /* Symbols in the text segment can be accessed without indirecting via the
14556 constant pool; it may take an extra binary operation, but this is still
14557 faster than indirecting via memory. Don't do this when not optimizing,
14558 since we won't be calculating al of the offsets necessary to do this
14562 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14564 /* This doesn't work with AOF syntax, since the string table may be in
14565 a different AREA. */
14566 #ifndef AOF_ASSEMBLER
14567 if (optimize
> 0 && TREE_CONSTANT (decl
))
14568 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14571 /* If we are referencing a function that is weak then encode a long call
14572 flag in the function name, otherwise if the function is static or
14573 or known to be defined in this file then encode a short call flag. */
14574 if (first
&& DECL_P (decl
))
14576 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14577 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14578 else if (! TREE_PUBLIC (decl
))
14579 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14582 default_encode_section_info (decl
, rtl
, first
);
14584 #endif /* !ARM_PE */
14587 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14589 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14590 && !strcmp (prefix
, "L"))
14592 arm_ccfsm_state
= 0;
14593 arm_target_insn
= NULL
;
14595 default_internal_label (stream
, prefix
, labelno
);
14598 /* Output code to add DELTA to the first argument, and then jump
14599 to FUNCTION. Used for C++ multiple inheritance. */
14601 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14602 HOST_WIDE_INT delta
,
14603 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14606 static int thunk_label
= 0;
14608 int mi_delta
= delta
;
14609 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14611 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14614 mi_delta
= - mi_delta
;
14617 int labelno
= thunk_label
++;
14618 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14619 fputs ("\tldr\tr12, ", file
);
14620 assemble_name (file
, label
);
14621 fputc ('\n', file
);
14623 while (mi_delta
!= 0)
14625 if ((mi_delta
& (3 << shift
)) == 0)
14629 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14630 mi_op
, this_regno
, this_regno
,
14631 mi_delta
& (0xff << shift
));
14632 mi_delta
&= ~(0xff << shift
);
14638 fprintf (file
, "\tbx\tr12\n");
14639 ASM_OUTPUT_ALIGN (file
, 2);
14640 assemble_name (file
, label
);
14641 fputs (":\n", file
);
14642 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14646 fputs ("\tb\t", file
);
14647 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14648 if (NEED_PLT_RELOC
)
14649 fputs ("(PLT)", file
);
14650 fputc ('\n', file
);
14655 arm_emit_vector_const (FILE *file
, rtx x
)
14658 const char * pattern
;
14660 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
14662 switch (GET_MODE (x
))
14664 case V2SImode
: pattern
= "%08x"; break;
14665 case V4HImode
: pattern
= "%04x"; break;
14666 case V8QImode
: pattern
= "%02x"; break;
14667 default: gcc_unreachable ();
14670 fprintf (file
, "0x");
14671 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14675 element
= CONST_VECTOR_ELT (x
, i
);
14676 fprintf (file
, pattern
, INTVAL (element
));
14683 arm_output_load_gr (rtx
*operands
)
14690 if (GET_CODE (operands
[1]) != MEM
14691 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14692 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14693 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14694 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14695 return "wldrw%?\t%0, %1";
14697 /* Fix up an out-of-range load of a GR register. */
14698 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14699 wcgr
= operands
[0];
14701 output_asm_insn ("ldr%?\t%0, %1", operands
);
14703 operands
[0] = wcgr
;
14705 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14706 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14712 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14713 int incoming ATTRIBUTE_UNUSED
)
14716 /* FIXME: The ARM backend has special code to handle structure
14717 returns, and will reserve its own hidden first argument. So
14718 if this macro is enabled a *second* hidden argument will be
14719 reserved, which will break binary compatibility with old
14720 toolchains and also thunk handling. One day this should be
14724 /* Register in which address to store a structure value
14725 is passed to a function. */
14726 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14730 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14732 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14733 named arg and all anonymous args onto the stack.
14734 XXX I know the prologue shouldn't be pushing registers, but it is faster
14738 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14739 enum machine_mode mode ATTRIBUTE_UNUSED
,
14740 tree type ATTRIBUTE_UNUSED
,
14742 int second_time ATTRIBUTE_UNUSED
)
14744 cfun
->machine
->uses_anonymous_args
= 1;
14745 if (cum
->nregs
< NUM_ARG_REGS
)
14746 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14749 /* Return nonzero if the CONSUMER instruction (a store) does not need
14750 PRODUCER's value to calculate the address. */
14753 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14755 rtx value
= PATTERN (producer
);
14756 rtx addr
= PATTERN (consumer
);
14758 if (GET_CODE (value
) == COND_EXEC
)
14759 value
= COND_EXEC_CODE (value
);
14760 if (GET_CODE (value
) == PARALLEL
)
14761 value
= XVECEXP (value
, 0, 0);
14762 value
= XEXP (value
, 0);
14763 if (GET_CODE (addr
) == COND_EXEC
)
14764 addr
= COND_EXEC_CODE (addr
);
14765 if (GET_CODE (addr
) == PARALLEL
)
14766 addr
= XVECEXP (addr
, 0, 0);
14767 addr
= XEXP (addr
, 0);
14769 return !reg_overlap_mentioned_p (value
, addr
);
14772 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14773 have an early register shift value or amount dependency on the
14774 result of PRODUCER. */
14777 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14779 rtx value
= PATTERN (producer
);
14780 rtx op
= PATTERN (consumer
);
14783 if (GET_CODE (value
) == COND_EXEC
)
14784 value
= COND_EXEC_CODE (value
);
14785 if (GET_CODE (value
) == PARALLEL
)
14786 value
= XVECEXP (value
, 0, 0);
14787 value
= XEXP (value
, 0);
14788 if (GET_CODE (op
) == COND_EXEC
)
14789 op
= COND_EXEC_CODE (op
);
14790 if (GET_CODE (op
) == PARALLEL
)
14791 op
= XVECEXP (op
, 0, 0);
14794 early_op
= XEXP (op
, 0);
14795 /* This is either an actual independent shift, or a shift applied to
14796 the first operand of another operation. We want the whole shift
14798 if (GET_CODE (early_op
) == REG
)
14801 return !reg_overlap_mentioned_p (value
, early_op
);
14804 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14805 have an early register shift value dependency on the result of
14809 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14811 rtx value
= PATTERN (producer
);
14812 rtx op
= PATTERN (consumer
);
14815 if (GET_CODE (value
) == COND_EXEC
)
14816 value
= COND_EXEC_CODE (value
);
14817 if (GET_CODE (value
) == PARALLEL
)
14818 value
= XVECEXP (value
, 0, 0);
14819 value
= XEXP (value
, 0);
14820 if (GET_CODE (op
) == COND_EXEC
)
14821 op
= COND_EXEC_CODE (op
);
14822 if (GET_CODE (op
) == PARALLEL
)
14823 op
= XVECEXP (op
, 0, 0);
14826 early_op
= XEXP (op
, 0);
14828 /* This is either an actual independent shift, or a shift applied to
14829 the first operand of another operation. We want the value being
14830 shifted, in either case. */
14831 if (GET_CODE (early_op
) != REG
)
14832 early_op
= XEXP (early_op
, 0);
14834 return !reg_overlap_mentioned_p (value
, early_op
);
14837 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14838 have an early register mult dependency on the result of
14842 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14844 rtx value
= PATTERN (producer
);
14845 rtx op
= PATTERN (consumer
);
14847 if (GET_CODE (value
) == COND_EXEC
)
14848 value
= COND_EXEC_CODE (value
);
14849 if (GET_CODE (value
) == PARALLEL
)
14850 value
= XVECEXP (value
, 0, 0);
14851 value
= XEXP (value
, 0);
14852 if (GET_CODE (op
) == COND_EXEC
)
14853 op
= COND_EXEC_CODE (op
);
14854 if (GET_CODE (op
) == PARALLEL
)
14855 op
= XVECEXP (op
, 0, 0);
14858 return (GET_CODE (op
) == PLUS
14859 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14863 /* We can't rely on the caller doing the proper promotion when
14864 using APCS or ATPCS. */
14867 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14869 return !TARGET_AAPCS_BASED
;
14873 /* AAPCS based ABIs use short enums by default. */
14876 arm_default_short_enums (void)
14878 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
14882 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14885 arm_align_anon_bitfield (void)
14887 return TARGET_AAPCS_BASED
;
14891 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14894 arm_cxx_guard_type (void)
14896 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14900 /* The EABI says test the least significant bit of a guard variable. */
14903 arm_cxx_guard_mask_bit (void)
14905 return TARGET_AAPCS_BASED
;
14909 /* The EABI specifies that all array cookies are 8 bytes long. */
14912 arm_get_cookie_size (tree type
)
14916 if (!TARGET_AAPCS_BASED
)
14917 return default_cxx_get_cookie_size (type
);
14919 size
= build_int_cst (sizetype
, 8);
14924 /* The EABI says that array cookies should also contain the element size. */
14927 arm_cookie_has_size (void)
14929 return TARGET_AAPCS_BASED
;
14933 /* The EABI says constructors and destructors should return a pointer to
14934 the object constructed/destroyed. */
14937 arm_cxx_cdtor_returns_this (void)
14939 return TARGET_AAPCS_BASED
;
14942 /* The EABI says that an inline function may never be the key
14946 arm_cxx_key_method_may_be_inline (void)
14948 return !TARGET_AAPCS_BASED
;
14952 arm_cxx_determine_class_data_visibility (tree decl
)
14954 if (!TARGET_AAPCS_BASED
)
14957 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14958 is exported. However, on systems without dynamic vague linkage,
14959 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14960 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
14961 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
14963 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
14964 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
14968 arm_cxx_class_data_always_comdat (void)
14970 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14971 vague linkage if the class has no key function. */
14972 return !TARGET_AAPCS_BASED
;
14976 /* The EABI says __aeabi_atexit should be used to register static
14980 arm_cxx_use_aeabi_atexit (void)
14982 return TARGET_AAPCS_BASED
;
14987 arm_set_return_address (rtx source
, rtx scratch
)
14989 arm_stack_offsets
*offsets
;
14990 HOST_WIDE_INT delta
;
14992 unsigned long saved_regs
;
14994 saved_regs
= arm_compute_save_reg_mask ();
14996 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14997 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15000 if (frame_pointer_needed
)
15001 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
15004 /* LR will be the first saved register. */
15005 offsets
= arm_get_frame_offsets ();
15006 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
15011 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
15012 GEN_INT (delta
& ~4095)));
15017 addr
= stack_pointer_rtx
;
15019 addr
= plus_constant (addr
, delta
);
15021 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15027 thumb_set_return_address (rtx source
, rtx scratch
)
15029 arm_stack_offsets
*offsets
;
15030 HOST_WIDE_INT delta
;
15033 unsigned long mask
;
15035 emit_insn (gen_rtx_USE (VOIDmode
, source
));
15037 mask
= thumb_compute_save_reg_mask ();
15038 if (mask
& (1 << LR_REGNUM
))
15040 offsets
= arm_get_frame_offsets ();
15042 /* Find the saved regs. */
15043 if (frame_pointer_needed
)
15045 delta
= offsets
->soft_frame
- offsets
->saved_args
;
15046 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
15050 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
15053 /* Allow for the stack frame. */
15054 if (TARGET_BACKTRACE
)
15056 /* The link register is always the first saved register. */
15059 /* Construct the address. */
15060 addr
= gen_rtx_REG (SImode
, reg
);
15061 if ((reg
!= SP_REGNUM
&& delta
>= 128)
15064 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
15065 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
15069 addr
= plus_constant (addr
, delta
);
15071 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
15074 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
15077 /* Implements target hook vector_mode_supported_p. */
15079 arm_vector_mode_supported_p (enum machine_mode mode
)
15081 if ((mode
== V2SImode
)
15082 || (mode
== V4HImode
)
15083 || (mode
== V8QImode
))
15089 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15090 ARM insns and therefore guarantee that the shift count is modulo 256.
15091 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15092 guarantee no particular behavior for out-of-range counts. */
15094 static unsigned HOST_WIDE_INT
15095 arm_shift_truncation_mask (enum machine_mode mode
)
15097 return mode
== SImode
? 255 : 0;
15101 /* Map internal gcc register numbers to DWARF2 register numbers. */
15104 arm_dbx_register_number (unsigned int regno
)
15109 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15110 compatibility. The EABI defines them as registers 96-103. */
15111 if (IS_FPA_REGNUM (regno
))
15112 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
15114 if (IS_VFP_REGNUM (regno
))
15115 return 64 + regno
- FIRST_VFP_REGNUM
;
15117 if (IS_IWMMXT_GR_REGNUM (regno
))
15118 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
15120 if (IS_IWMMXT_REGNUM (regno
))
15121 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
15123 gcc_unreachable ();
15127 #ifdef TARGET_UNWIND_INFO
15128 /* Emit unwind directives for a store-multiple instruction. This should
15129 only ever be generated by the function prologue code, so we expect it
15130 to have a particular form. */
15133 arm_unwind_emit_stm (FILE * asm_out_file
, rtx p
)
15136 HOST_WIDE_INT offset
;
15137 HOST_WIDE_INT nregs
;
15143 /* First insn will adjust the stack pointer. */
15144 e
= XVECEXP (p
, 0, 0);
15145 if (GET_CODE (e
) != SET
15146 || GET_CODE (XEXP (e
, 0)) != REG
15147 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15148 || GET_CODE (XEXP (e
, 1)) != PLUS
)
15151 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
15152 nregs
= XVECLEN (p
, 0) - 1;
15154 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
15157 /* The function prologue may also push pc, but not annotate it as it is
15158 never restored. We turn this into a stack pointer adjustment. */
15159 if (nregs
* 4 == offset
- 4)
15161 fprintf (asm_out_file
, "\t.pad #4\n");
15166 else if (IS_VFP_REGNUM (reg
))
15168 /* FPA register saves use an additional word. */
15172 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
15174 /* FPA registers are done differently. */
15175 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
15179 /* Unknown register type. */
15182 /* If the stack increment doesn't match the size of the saved registers,
15183 something has gone horribly wrong. */
15184 if (offset
!= nregs
* reg_size
)
15187 fprintf (asm_out_file
, "\t.save {");
15191 /* The remaining insns will describe the stores. */
15192 for (i
= 1; i
<= nregs
; i
++)
15194 /* Expect (set (mem <addr>) (reg)).
15195 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15196 e
= XVECEXP (p
, 0, i
);
15197 if (GET_CODE (e
) != SET
15198 || GET_CODE (XEXP (e
, 0)) != MEM
15199 || GET_CODE (XEXP (e
, 1)) != REG
)
15202 reg
= REGNO (XEXP (e
, 1));
15207 fprintf (asm_out_file
, ", ");
15208 /* We can't use %r for vfp because we need to use the
15209 double precision register names. */
15210 if (IS_VFP_REGNUM (reg
))
15211 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
15213 asm_fprintf (asm_out_file
, "%r", reg
);
15215 #ifdef ENABLE_CHECKING
15216 /* Check that the addresses are consecutive. */
15217 e
= XEXP (XEXP (e
, 0), 0);
15218 if (GET_CODE (e
) == PLUS
)
15220 offset
+= reg_size
;
15221 if (GET_CODE (XEXP (e
, 0)) != REG
15222 || REGNO (XEXP (e
, 0)) != SP_REGNUM
15223 || GET_CODE (XEXP (e
, 1)) != CONST_INT
15224 || offset
!= INTVAL (XEXP (e
, 1)))
15228 || GET_CODE (e
) != REG
15229 || REGNO (e
) != SP_REGNUM
)
15233 fprintf (asm_out_file
, "}\n");
15236 /* Emit unwind directives for a SET. */
15239 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
15246 switch (GET_CODE (e0
))
15249 /* Pushing a single register. */
15250 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
15251 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
15252 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
15255 asm_fprintf (asm_out_file
, "\t.save ");
15256 if (IS_VFP_REGNUM (REGNO (e1
)))
15257 asm_fprintf(asm_out_file
, "{d%d}\n",
15258 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
15260 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
15264 if (REGNO (e0
) == SP_REGNUM
)
15266 /* A stack increment. */
15267 if (GET_CODE (e1
) != PLUS
15268 || GET_CODE (XEXP (e1
, 0)) != REG
15269 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
15270 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15273 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
15274 -INTVAL (XEXP (e1
, 1)));
15276 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
15278 HOST_WIDE_INT offset
;
15281 if (GET_CODE (e1
) == PLUS
)
15283 if (GET_CODE (XEXP (e1
, 0)) != REG
15284 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
15286 reg
= REGNO (XEXP (e1
, 0));
15287 offset
= INTVAL (XEXP (e1
, 1));
15288 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
15289 HARD_FRAME_POINTER_REGNUM
, reg
,
15290 INTVAL (XEXP (e1
, 1)));
15292 else if (GET_CODE (e1
) == REG
)
15295 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
15296 HARD_FRAME_POINTER_REGNUM
, reg
);
15301 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
15303 /* Move from sp to reg. */
15304 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
15316 /* Emit unwind directives for the given insn. */
15319 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
15323 if (!ARM_EABI_UNWIND_TABLES
)
15326 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
15329 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
15331 pat
= XEXP (pat
, 0);
15333 pat
= PATTERN (insn
);
15335 switch (GET_CODE (pat
))
15338 arm_unwind_emit_set (asm_out_file
, pat
);
15342 /* Store multiple. */
15343 arm_unwind_emit_stm (asm_out_file
, pat
);
15352 /* Output a reference from a function exception table to the type_info
15353 object X. The EABI specifies that the symbol should be relocated by
15354 an R_ARM_TARGET2 relocation. */
15357 arm_output_ttype (rtx x
)
15359 fputs ("\t.word\t", asm_out_file
);
15360 output_addr_const (asm_out_file
, x
);
15361 /* Use special relocations for symbol references. */
15362 if (GET_CODE (x
) != CONST_INT
)
15363 fputs ("(TARGET2)", asm_out_file
);
15364 fputc ('\n', asm_out_file
);
15368 #endif /* TARGET_UNWIND_INFO */
15371 /* Output unwind directives for the start/end of a function. */
15374 arm_output_fn_unwind (FILE * f
, bool prologue
)
15376 if (!ARM_EABI_UNWIND_TABLES
)
15380 fputs ("\t.fnstart\n", f
);
15382 fputs ("\t.fnend\n", f
);
15386 arm_emit_tls_decoration (FILE *fp
, rtx x
)
15388 enum tls_reloc reloc
;
15391 val
= XVECEXP (x
, 0, 0);
15392 reloc
= INTVAL (XVECEXP (x
, 0, 1));
15394 output_addr_const (fp
, val
);
15399 fputs ("(tlsgd)", fp
);
15402 fputs ("(tlsldm)", fp
);
15405 fputs ("(tlsldo)", fp
);
15408 fputs ("(gottpoff)", fp
);
15411 fputs ("(tpoff)", fp
);
15414 gcc_unreachable ();
15422 fputs (" + (. - ", fp
);
15423 output_addr_const (fp
, XVECEXP (x
, 0, 2));
15425 output_addr_const (fp
, XVECEXP (x
, 0, 3));
15436 arm_output_addr_const_extra (FILE *fp
, rtx x
)
15438 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
15439 return arm_emit_tls_decoration (fp
, x
);
15440 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
15443 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
15445 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
15446 assemble_name_raw (fp
, label
);
15450 else if (GET_CODE (x
) == CONST_VECTOR
)
15451 return arm_emit_vector_const (fp
, x
);
15456 #include "gt-arm.h"