| commit | 5636919b5c909fee54a6ef5226475ecae012ad02 | |
| author | Ralf Baechle <ralf@linux-mips.org> | |
| Sat, 28 Feb 2009 09:44:28 +0000 (28 09:44 +0000) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Mon, 8 Jun 2009 15:57:51 +0000 (8 16:57 +0100) | ||
| tree | c77fa89c56ee2d493fb82117ab5dbc5b28a8deeb | treesnapshot (tar.gz zip) |
| parent | 3a553147eaad5d4de90ab1f695aa13ddbea684ec | commitdiff |
MIPS: Outline udelay and fix a few issues.
Outlining fixes the issue were on certain CPUs such as the R10000 family
the delay loop would need an extra cycle if it overlaps a cacheline
boundary.
The rewrite also fixes build errors with GCC 4.4 which was changed in
way incompatible with the kernel's inline assembly.
Relying on pure C for computation of the delay value removes the need for
explicit. The price we pay is a slight slowdown of the computation - to
be fixed on another day.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Outlining fixes the issue were on certain CPUs such as the R10000 family
the delay loop would need an extra cycle if it overlaps a cacheline
boundary.
The rewrite also fixes build errors with GCC 4.4 which was changed in
way incompatible with the kernel's inline assembly.
Relying on pure C for computation of the delay value removes the need for
explicit. The price we pay is a slight slowdown of the computation - to
be fixed on another day.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>