include/asm-arm/arch-moxacpu/cpe/a320c.h

   1 /*
   2 Author :        Victor Yu.
   3 Date :          11-04-2005
   4 */
   5
   6 #ifndef     _A320C_H_
   7 #define     _A320C_H_
   8
   9 /*****************************************************************
  10     IO Mapping
  11 *****************************************************************/
  12 #define IO_BASE                         0xf0000000
  13 #define MEM_ADDRESS(x)                  ((x&0x0fffffff)+IO_BASE)
  14 #define IO_ADDRESS(x)                   (((x>>4)&0xffff0000)+(x&0xffff)+IO_BASE)
  15 #define PHY_ADDRESS(x)                  (((x<<4)&0xfff00000)+(x&0xffff))
  16
  17 /******************************************************************
  18     AHB/APB device register mapping
  19  *****************************************************************/
  20 #define CPE_AHB_BASE                    0x90100000
  21 #define CPE_SRAMC_BASE                  0x90200000
  22 #define CPE_SDRAMC_BASE                 0x90300000
  23 #define CPE_AHBDMA_BASE                 0x90400000
  24 #define CPE_APBDMA_BASE                 0x90500000
  25 #define CPE_PMU_BASE                    0x98100000
  26 #define CPE_TIMER_BASE                  0x98400000
  27 #define CPE_TIMER1_BASE                 0x98400000
  28 #define CPE_TIMER2_BASE                 0x98400010
  29 #define CPE_GPIO_BASE                   0x98700000
  30 #define CPE_IC_BASE                     0x98800000
  31 #define CPE_SD_BASE                     0x98e00000
  32 #define CPE_PCI_BASE                    0x90c00000
  33 #define CPE_PCI_MEM                     0xa0000000
  34 #define CPE_FTMAC_BASE                  0x90900000
  35 #define CPE_FTMAC2_BASE                 0x92000000   //2nd MAC
  36 #define CPE_USBDEV_BASE                 0x90b00000   //USB device
  37
  38 #define MEM_PHY_ADDRESS(x)              ((x&0x0fffffff)+CPE_PCI_MEM)
  39
  40 #ifdef CONFIG_ARCH_CPE
  41 #define CPE_LCD_BASE                    0x90600000
  42 #define CPE_UART1_BASE                  0x98200000
  43 #define CPE_UART2_BASE                  0x98300000
  44 #define CPE_SSP2_BASE                   0x98b00000
  45 #define CPE_SSP1_BASE                   0x99400000
  46 #define CPE_A321_IC_BASE                0xb0800000
  47 #define CPE_HOST20_BASE                 0x92000000
  48 #define CPE_KBD_BASE                    0xb1300000
  49 #define CPE_MOUSE_BASE                  0x99b00000
  50 #endif  // CONFIG_ARCH_CPE
  51
  52 #ifdef CONFIG_ARCH_MOXACPU
  53 #define CPE_UART_BASE                   0x98200000
  54 #define CPE_UART1_BASE                  0x98200000
  55 #define CPE_UART2_BASE                  0x98200020
  56 #define CPE_UART3_BASE                  0x98200040
  57 #define CPE_UART4_BASE                  0x98200060
  58 #define CPE_UART5_BASE                  0x98200080
  59 #define CPE_UART6_BASE                  0x982000a0
  60 #define CPE_UART_INT_VEC_BASE           0x982000c0
  61 #define CPE_UART_MODE_BASE              0x982000e4
  62 #define CPE_SPI_BASE                    0x98b00000
  63 #define CPE_USBHOST_BASE                0x90a00000
  64 #define CPE_AES_DES_BASE                0x90f00000
  65 #define CPE_AC97_BASE                   0x99400000
  66 #define CPE_RTC_BASE                    0x98600000
  67 #define CPE_WATCHDOG_BASE               0x98500000
  68 #define CPE_EBI_BASE                    0x92300000
  69 //#if defined CONFIG_ARCH_W311
  70 //#define CPE_WLAN_LED_REG_BASE         0x84000000
  71 //#endif
  72 #endif  // CONFIG_ARCH_MOXACPU
  73
  74 /**********************************************
  75 virtual address
  76 **********************************************/
  77 #define CPE_AHB_VA_BASE                 IO_ADDRESS(CPE_AHB_BASE)
  78 #define CPE_SRAMC_VA_BASEi              IO_ADDRESS(CPE_SRAMC_BASE)
  79 #define CPE_SDRAMC_VA_BASE              IO_ADDRESS(CPE_SDRAMC_BASE)
  80 #define CPE_AHBDMA_VA_BASE              IO_ADDRESS(CPE_AHBDMA_BASE)
  81 #define CPE_APBDMA_VA_BASE              IO_ADDRESS(CPE_APBDMA_BASE)
  82 #define CPE_PMU_VA_BASE                 IO_ADDRESS(CPE_PMU_BASE)
  83 #define CPE_TIMER_VA_BASE               IO_ADDRESS(CPE_TIMER_BASE)
  84 #define CPE_TIMER1_VA_BASE              IO_ADDRESS(CPE_TIMER1_BASE)
  85 #define CPE_TIMER2_VA_BASE              IO_ADDRESS(CPE_TIMER2_BASE)
  86 #define CPE_GPIO_VA_BASE                IO_ADDRESS(CPE_GPIO_BASE)
  87 #define CPE_IC_VA_BASE                  IO_ADDRESS(CPE_IC_BASE)
  88 #define CPE_SD_VA_BASE                  IO_ADDRESS(CPE_SD_BASE)
  89 #define CPE_PCI_VA_BASE                 IO_ADDRESS(CPE_PCI_BASE)
  90 #define CPE_PCI_VA_MEM                  IO_ADDRESS(CPE_PCI_MEM)
  91 #define CPE_FTMAC_VA_BASE               IO_ADDRESS(CPE_FTMAC_BASE)
  92 #define CPE_FTMAC2_VA_BASE              IO_ADDRESS(CPE_FTMAC2_BASE)     //2nd MAC
  93 #define CPE_USBDEV_VA_BASE              IO_ADDRESS(CPE_USBDEV_BASE)     //USB device
  94
  95 #ifdef CONFIG_ARCH_CPE
  96 #define CPE_LCD_VA_BASE                 IO_ADDRESS(CPE_LCD_BASE)
  97 #define CPE_UART1_VA_BASE               IO_ADDRESS(CPE_UART1_BASE)
  98 #define CPE_UART2_VA_BASE               IO_ADDRESS(CPE_UART2_BASE)
  99 #define CPE_SSP2_VA_BASE                IO_ADDRESS(CPE_SSP2_BASE)
 100 #define CPE_SSP1_VA_BASE                IO_ADDRESS(CPE_SSP1_BASE)
 101 #define CPE_A321_IC_VA_BASE             IO_ADDRESS(CPE_A321_IC_BASE)
 102 #define CPE_HOST20_VA_BASE              IO_ADDRESS(CPE_HOST20_BASE)
 103 #define CPE_KBD_VA_BASE                 IO_ADDRESS(CPE_KBD_BASE)
 104 #define CPE_MOUSE_VA_BASE               IO_ADDRESS(CPE_MOUSE_BASE)
 105 #endif  // CONFIG_ARCH_CPE
 106
 107 #ifdef CONFIG_ARCH_MOXACPU
 108 #define CPE_UART_VA_BASE                IO_ADDRESS(CPE_UART_BASE)
 109 #define CPE_UART1_VA_BASE               IO_ADDRESS(CPE_UART1_BASE)
 110 #define CPE_UART2_VA_BASE               IO_ADDRESS(CPE_UART2_BASE)
 111 #define CPE_UART3_VA_BASE               IO_ADDRESS(CPE_UART3_BASE)
 112 #define CPE_UART4_VA_BASE               IO_ADDRESS(CPE_UART4_BASE)
 113 #define CPE_UART5_VA_BASE               IO_ADDRESS(CPE_UART5_BASE)
 114 #define CPE_UART6_VA_BASE               IO_ADDRESS(CPE_UART6_BASE)
 115 #define CPE_UART_INT_VEC_VA_BASE        IO_ADDRESS(CPE_UART_INT_VEC_BASE)
 116 #define CPE_UART_MODE_VA_BASE           IO_ADDRESS(CPE_UART_MODE_BASE)
 117 #define CPE_SPI_VA_BASE                 IO_ADDRESS(CPE_SPI_BASE)
 118 #define CPE_USBHOST_VA_BASE             IO_ADDRESS(CPE_USBHOST_BASE)
 119 #define CPE_AES_DES_VA_BASE             IO_ADDRESS(CPE_AES_DES_BASE)
 120 #define CPE_AC97_VA_BASE                IO_ADDRESS(CPE_AC97_BASE)
 121 #define CPE_RTC_VA_BASE                 IO_ADDRESS(CPE_RTC_BASE)
 122 #define CPE_WATCHDOG_VA_BASE            IO_ADDRESS(CPE_WATCHDOG_BASE)
 123 #define CPE_EBI_VA_BASE                 IO_ADDRESS(CPE_EBI_BASE)
 124 //#if defined CONFIG_ARCH_W311
 125 //#define CPE_WLAN_LED_REG_VA_BASE      IO_ADDRESS( CPE_WLAN_LED_REG_BASE)
 126 //#endif
 127 #endif  // CONFIG_ARCH_MOXACPU
 128
 129 /*****************************************************************
 130     Clock Setting
 131 *****************************************************************/
 132 #define AHB_CLK                         96000000
 133 #define APB_CLK                         48000000
 134 //#define fMCLK_MHz                     48000000
 135 #define fMCLK_MHz                       APB_CLK
 136 #define CONFIG_UART_CLK                 14745600
 137 #define CONFIG_SYS_CLK                  192000000
 138 #ifdef CONFIG_ARCH_MOXACPU
 139 #define CONFIG_SERIAL_CPE_DEFAULT_BAUD  115200
 140 #else   // CONFIG_ARCH_MOXACPU
 141 #define CONFIG_SERIAL_CPE_DEFAULT_BAUD  38400
 142 #endif  // CONFIG_ARCH_MOXACPU
 143
 144 /*****************************************************************
 145     IRQ
 146 *****************************************************************/
 147 /*
 148 interrupt:
 149 Following is used for Faraday CPU & demo board. (A320 & A321).
 150  0-31       A320 irq
 151  32-63      A320 fiq
 152  64-95      A321 irq
 153  96-127     A321 fiq
 154  150-160    Virtual IRQ (PCI)
 155  160-199    Virtual IRQ (reserved)
 156
 157 Following is used for Moxa CPU.
 158  0-31       F526 irq
 159  32-63      F526 fiq
 160  64 - 67    Virtual IRQ (PCI)
 161  68 - 99    Virtual IRQ (reserved)
 162  */
 163 #define CPE_NR_IRQS                     32
 164 #define CPE_NR_FIQS                     32
 165 #define CPE_NR_BASIC_IRQS               (CPE_NR_IRQS+CPE_NR_FIQS)
 166
 167 #ifdef CONFIG_ARCH_CPE
 168 #define NR_IRQS                         200
 169 #define CPE_A321_IRQ_START              CPE_NR_BASIC_IRQS
 170 #define CPE_VIRQ_START                  150
 171 #endif  // CONFIG_ARCH_CPE
 172
 173 #ifdef CONFIG_ARCH_MOXACPU
 174 #define CPE_VIRQ_START                  CPE_NR_BASIC_IRQS
 175 #define NR_IRQS                         (CPE_NR_BASIC_IRQS+16)
 176 #endif  // CONFIG_ARCH_MOXACPU
 177
 178 #define VIRQ_PCI_A                      (0+CPE_VIRQ_START)
 179 #define VIRQ_PCI_B                      (1+CPE_VIRQ_START)
 180 #define VIRQ_PCI_C                      (2+CPE_VIRQ_START)
 181 #define VIRQ_PCI_D                      (3+CPE_VIRQ_START)
 182
 183 //irq number
 184 #define IRQ_GPIO                        13
 185 #define IRQ_MAC                         25
 186 #define IRQ_TIMER1                      19
 187 #define IRQ_TIMER2                      14
 188 #define IRQ_TIMER3                      15
 189
 190 #ifdef CONFIG_ARCH_CPE
 191 #define IRQ_SSP1                        2
 192 #define IRQ_I2C                         3
 193 #define IRQ_SSP2                        6
 194 #define IRQ_UART1                       10
 195 #define IRQ_UART2                       11
 196 #define IRQ_APB_BRIDGE                  24
 197 #define IRQ_CPE_AHB_DMA                 21
 198 #define IRQ_CPE_APB_DMA                 24
 199 #define IRQ_TOUCH                       28
 200 #define IRQ_EXT_A321                    30
 201 #define IRQ_USBDEV                      26   //USB device
 202
 203 #define IRQ_A321_PCI                    (28+CPE_A321_IRQ_START)
 204 #define IRQ_A321_KBD                    (4+CPE_A321_IRQ_START)
 205 #define IRQ_A321_MOUSE                  (9+CPE_A321_IRQ_START)
 206 #define IRQ_A321_MAC2                   (9+CPE_A321_IRQ_START)  //2nd MAC
 207 #endif  // CONFIG_ARCH_CPE
 208
 209 #ifdef CONFIG_ARCH_MOXACPU
 210 #define IRQ_UART                        31
 211 #define IRQ_AES_DES                     29
 212 #define IRQ_USBHOST                     28
 213 #define IRQ_MAC2                        27
 214 #define IRQ_PCI                         26
 215 #define IRQ_APBDMA                      24
 216 #define IRQ_DMAC_ERR                    23
 217 #define IRQ_DMAC_TC                     22
 218 #define IRQ_DMAC                        21
 219 #define IRQ_RTC_SECOND                  18
 220 #define IRQ_RTC_ALARM                   17
 221 #define IRQ_WATCHDOG                    16
 222 #define IRQ_USBDEV_RESUME               12
 223 #define IRQ_USBDEV                      11
 224 #define IRQ_PMU                         8
 225 #define IRQ_AC97                        6
 226 #define IRQ_SD                          5
 227 #define IRQ_SPI                         2
 228 #endif  // CONFIG_ARCH_MOXACPU
 229
 230 #define LEVEL                           0
 231 #define EDGE                            1
 232 #define H_ACTIVE                        0
 233 #define L_ACTIVE                        1
 234
 235 #define IRQ_SOURCE_REG                  0
 236 #define IRQ_MASK_REG                    0x04
 237 #define IRQ_CLEAR_REG                   0x08
 238 #define IRQ_MODE_REG                    0x0c
 239 #define IRQ_LEVEL_REG                   0x10
 240 #define IRQ_STATUS_REG                  0x14
 241
 242 #define FIQ_SOURCE_REG                  0x20
 243 #define FIQ_MASK_REG                    0x24
 244 #define FIQ_CLEAR_REG                   0x28
 245 #define FIQ_MODE_REG                    0x2c
 246 #define FIQ_LEVEL_REG                   0x30
 247 #define FIQ_STATUS_REG                  0x34
 248
 249
 250 /*****************************************************************
 251     Flash
 252 *****************************************************************/
 253 #ifdef CONFIG_ARCH_CPE
 254 #define CPE_FLASH_BASE                  0x80400000
 255 #define CPE_FLASH_SZ                    0x02000000
 256 #define CPE_FLASH_VA_BASE               IO_ADDRESS(CPE_FLASH_BASE)
 257 #endif  // CONFIG_ARCH_CPE
 258
 259 #ifdef CONFIG_ARCH_MOXACPU
 260 #define CPE_FLASH_BASE                  0x80000000
 261 #define CPE_FLASH_SZ                    0x01000000
 262 #define CPE_FLASH_VA_BASE               0xf4000000
 263 #ifdef CONFIG_ARCH_IA241_32128  // add by Victor Yu. 05-22-2007
 264 #define CPE_FLASH_BASE2                 0x88000000
 265 #define CPE_FLASH_VA_BASE2              0xf5000000
 266 #endif  // CONFIG_ARCH_IA241_32128
 267 #endif
 268
 269 /*****************************************************************
 270     PCI
 271 *****************************************************************/
 272 #define PCI_IO_VA_BASE                  (CPE_PCI_VA_BASE+SZ_4K)
 273 #define PCI_IO_VA_SIZE                  (SZ_64K-SZ_4K)
 274 #define PCI_IO_VA_END                   (CPE_PCI_VA_BASE+SZ_64K)
 275 #define CPE_PCI_IO_BASE                 (CPE_PCI_BASE+SZ_4K)
 276 #define CPE_PCI_IO_SIZE                 PCI_IO_VA_SIZE
 277 #define CPE_PCI_IO_END                  (CPE_PCI_BASE+SZ_64K)
 278
 279 #define PCI_MEM_BASE                    CPE_PCI_MEM
 280 #if 0   // mask by Victor Yu. 10-27-2005
 281 #define PCI_MEM_SIZE                    SZ_1M
 282 #else   // add by Victor Yu. 10-27-2005, change the size
 283 #define PCI_MEM_SIZE                    SZ_32M
 284 #endif
 285 #define PCI_MEM_END                     (CPE_PCI_MEM+PCI_MEM_SIZE)
 286 #define PCI_MEM_VA_BASE                 MEM_ADDRESS(CPE_PCI_MEM)
 287 #define PCI_MEM_VA_END                  (PCI_MEM_VA_BASE+PCI_MEM_SIZE)
 288
 289 #define PCI_BRIDGE_DEVID                0x4321
 290 #define PCI_BRIDGE_VENID                0x159b
 291
 292 /*****************************************************************
 293     PMU
 294 *****************************************************************/
 295 #define PMU_SSP_DMA_CHANNEL             0x2
 296
 297 #endif  // _A320C_H