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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / ns83820.c
blobc2551c5fbdd111d58e23b7f42ea3aac484e7fc03
1 #define _VERSION "0.20"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 *
67 * Driver Overview
68 * ===============
69 *
70 * This driver was originally written for the National Semiconductor
71 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
72 * this code will turn out to be a) clean, b) correct, and c) fast.
73 * With that in mind, I'm aiming to split the code up as much as
74 * reasonably possible. At present there are X major sections that
75 * break down into a) packet receive, b) packet transmit, c) link
76 * management, d) initialization and configuration. Where possible,
77 * these code paths are designed to run in parallel.
78 *
79 * This driver has been tested and found to work with the following
80 * cards (in no particular order):
81 *
82 * Cameo SOHO-GA2000T SOHO-GA2500T
83 * D-Link DGE-500T
84 * PureData PDP8023Z-TG
85 * SMC SMC9452TX SMC9462TX
86 * Netgear GA621
87 *
88 * Special thanks to SMC for providing hardware to test this driver on.
89 *
90 * Reports of success or failure would be greatly appreciated.
91 */
92 //#define dprintk printk
93 #define dprintk(x...) do { } while (0)
94
95 #include <linux/module.h>
96 #include <linux/types.h>
97 #include <linux/pci.h>
98 #include <linux/netdevice.h>
99 #include <linux/etherdevice.h>
100 #include <linux/delay.h>
101 #include <linux/smp_lock.h>
102 #include <linux/workqueue.h>
103 #include <linux/init.h>
104 #include <linux/ip.h> /* for iph */
105 #include <linux/in.h> /* for IPPROTO_... */
106 #include <linux/eeprom.h>
107 #include <linux/compiler.h>
108 #include <linux/prefetch.h>
109 #include <linux/ethtool.h>
110 #include <linux/timer.h>
111
112 #include <asm/io.h>
113 #include <asm/uaccess.h>
114 #include <asm/system.h>
115
116 #define DRV_NAME "ns83820"
117
118 /* Global parameters. See MODULE_PARM near the bottom. */
119 static int ihr = 2;
120 static int reset_phy = 0;
121 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
122
123 /* Dprintk is used for more interesting debug events */
124 #undef Dprintk
125 #define Dprintk dprintk
126
127 #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
128 #define USE_64BIT_ADDR "+"
129 #endif
130
131 #if defined(USE_64BIT_ADDR)
132 #define VERSION _VERSION USE_64BIT_ADDR
133 #define TRY_DAC 1
134 #else
135 #define VERSION _VERSION
136 #define TRY_DAC 0
137 #endif
138
139 /* tunables */
140 #define RX_BUF_SIZE 1500 /* 8192 */
141
142 /* Must not exceed ~65000. */
143 #define NR_RX_DESC 64
144 #define NR_TX_DESC 128
145
146 /* not tunable */
147 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
148
149 #define MIN_TX_DESC_FREE 8
150
151 /* register defines */
152 #define CFGCS 0x04
153
154 #define CR_TXE 0x00000001
155 #define CR_TXD 0x00000002
156 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
157 * The Receive engine skips one descriptor and moves
158 * onto the next one!! */
159 #define CR_RXE 0x00000004
160 #define CR_RXD 0x00000008
161 #define CR_TXR 0x00000010
162 #define CR_RXR 0x00000020
163 #define CR_SWI 0x00000080
164 #define CR_RST 0x00000100
165
166 #define PTSCR_EEBIST_FAIL 0x00000001
167 #define PTSCR_EEBIST_EN 0x00000002
168 #define PTSCR_EELOAD_EN 0x00000004
169 #define PTSCR_RBIST_FAIL 0x000001b8
170 #define PTSCR_RBIST_DONE 0x00000200
171 #define PTSCR_RBIST_EN 0x00000400
172 #define PTSCR_RBIST_RST 0x00002000
173
174 #define MEAR_EEDI 0x00000001
175 #define MEAR_EEDO 0x00000002
176 #define MEAR_EECLK 0x00000004
177 #define MEAR_EESEL 0x00000008
178 #define MEAR_MDIO 0x00000010
179 #define MEAR_MDDIR 0x00000020
180 #define MEAR_MDC 0x00000040
181
182 #define ISR_TXDESC3 0x40000000
183 #define ISR_TXDESC2 0x20000000
184 #define ISR_TXDESC1 0x10000000
185 #define ISR_TXDESC0 0x08000000
186 #define ISR_RXDESC3 0x04000000
187 #define ISR_RXDESC2 0x02000000
188 #define ISR_RXDESC1 0x01000000
189 #define ISR_RXDESC0 0x00800000
190 #define ISR_TXRCMP 0x00400000
191 #define ISR_RXRCMP 0x00200000
192 #define ISR_DPERR 0x00100000
193 #define ISR_SSERR 0x00080000
194 #define ISR_RMABT 0x00040000
195 #define ISR_RTABT 0x00020000
196 #define ISR_RXSOVR 0x00010000
197 #define ISR_HIBINT 0x00008000
198 #define ISR_PHY 0x00004000
199 #define ISR_PME 0x00002000
200 #define ISR_SWI 0x00001000
201 #define ISR_MIB 0x00000800
202 #define ISR_TXURN 0x00000400
203 #define ISR_TXIDLE 0x00000200
204 #define ISR_TXERR 0x00000100
205 #define ISR_TXDESC 0x00000080
206 #define ISR_TXOK 0x00000040
207 #define ISR_RXORN 0x00000020
208 #define ISR_RXIDLE 0x00000010
209 #define ISR_RXEARLY 0x00000008
210 #define ISR_RXERR 0x00000004
211 #define ISR_RXDESC 0x00000002
212 #define ISR_RXOK 0x00000001
213
214 #define TXCFG_CSI 0x80000000
215 #define TXCFG_HBI 0x40000000
216 #define TXCFG_MLB 0x20000000
217 #define TXCFG_ATP 0x10000000
218 #define TXCFG_ECRETRY 0x00800000
219 #define TXCFG_BRST_DIS 0x00080000
220 #define TXCFG_MXDMA1024 0x00000000
221 #define TXCFG_MXDMA512 0x00700000
222 #define TXCFG_MXDMA256 0x00600000
223 #define TXCFG_MXDMA128 0x00500000
224 #define TXCFG_MXDMA64 0x00400000
225 #define TXCFG_MXDMA32 0x00300000
226 #define TXCFG_MXDMA16 0x00200000
227 #define TXCFG_MXDMA8 0x00100000
228
229 #define CFG_LNKSTS 0x80000000
230 #define CFG_SPDSTS 0x60000000
231 #define CFG_SPDSTS1 0x40000000
232 #define CFG_SPDSTS0 0x20000000
233 #define CFG_DUPSTS 0x10000000
234 #define CFG_TBI_EN 0x01000000
235 #define CFG_MODE_1000 0x00400000
236 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
237 * Read the Phy response and then configure the MAC accordingly */
238 #define CFG_AUTO_1000 0x00200000
239 #define CFG_PINT_CTL 0x001c0000
240 #define CFG_PINT_DUPSTS 0x00100000
241 #define CFG_PINT_LNKSTS 0x00080000
242 #define CFG_PINT_SPDSTS 0x00040000
243 #define CFG_TMRTEST 0x00020000
244 #define CFG_MRM_DIS 0x00010000
245 #define CFG_MWI_DIS 0x00008000
246 #define CFG_T64ADDR 0x00004000
247 #define CFG_PCI64_DET 0x00002000
248 #define CFG_DATA64_EN 0x00001000
249 #define CFG_M64ADDR 0x00000800
250 #define CFG_PHY_RST 0x00000400
251 #define CFG_PHY_DIS 0x00000200
252 #define CFG_EXTSTS_EN 0x00000100
253 #define CFG_REQALG 0x00000080
254 #define CFG_SB 0x00000040
255 #define CFG_POW 0x00000020
256 #define CFG_EXD 0x00000010
257 #define CFG_PESEL 0x00000008
258 #define CFG_BROM_DIS 0x00000004
259 #define CFG_EXT_125 0x00000002
260 #define CFG_BEM 0x00000001
261
262 #define EXTSTS_UDPPKT 0x00200000
263 #define EXTSTS_TCPPKT 0x00080000
264 #define EXTSTS_IPPKT 0x00020000
265
266 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268 #define MIBC_MIBS 0x00000008
269 #define MIBC_ACLR 0x00000004
270 #define MIBC_FRZ 0x00000002
271 #define MIBC_WRN 0x00000001
272
273 #define PCR_PSEN (1 << 31)
274 #define PCR_PS_MCAST (1 << 30)
275 #define PCR_PS_DA (1 << 29)
276 #define PCR_STHI_8 (3 << 23)
277 #define PCR_STLO_4 (1 << 23)
278 #define PCR_FFHI_8K (3 << 21)
279 #define PCR_FFLO_4K (1 << 21)
280 #define PCR_PAUSE_CNT 0xFFFE
281
282 #define RXCFG_AEP 0x80000000
283 #define RXCFG_ARP 0x40000000
284 #define RXCFG_STRIPCRC 0x20000000
285 #define RXCFG_RX_FD 0x10000000
286 #define RXCFG_ALP 0x08000000
287 #define RXCFG_AIRL 0x04000000
288 #define RXCFG_MXDMA512 0x00700000
289 #define RXCFG_DRTH 0x0000003e
290 #define RXCFG_DRTH0 0x00000002
291
292 #define RFCR_RFEN 0x80000000
293 #define RFCR_AAB 0x40000000
294 #define RFCR_AAM 0x20000000
295 #define RFCR_AAU 0x10000000
296 #define RFCR_APM 0x08000000
297 #define RFCR_APAT 0x07800000
298 #define RFCR_APAT3 0x04000000
299 #define RFCR_APAT2 0x02000000
300 #define RFCR_APAT1 0x01000000
301 #define RFCR_APAT0 0x00800000
302 #define RFCR_AARP 0x00400000
303 #define RFCR_MHEN 0x00200000
304 #define RFCR_UHEN 0x00100000
305 #define RFCR_ULM 0x00080000
306
307 #define VRCR_RUDPE 0x00000080
308 #define VRCR_RTCPE 0x00000040
309 #define VRCR_RIPE 0x00000020
310 #define VRCR_IPEN 0x00000010
311 #define VRCR_DUTF 0x00000008
312 #define VRCR_DVTF 0x00000004
313 #define VRCR_VTREN 0x00000002
314 #define VRCR_VTDEN 0x00000001
315
316 #define VTCR_PPCHK 0x00000008
317 #define VTCR_GCHK 0x00000004
318 #define VTCR_VPPTI 0x00000002
319 #define VTCR_VGTI 0x00000001
320
321 #define CR 0x00
322 #define CFG 0x04
323 #define MEAR 0x08
324 #define PTSCR 0x0c
325 #define ISR 0x10
326 #define IMR 0x14
327 #define IER 0x18
328 #define IHR 0x1c
329 #define TXDP 0x20
330 #define TXDP_HI 0x24
331 #define TXCFG 0x28
332 #define GPIOR 0x2c
333 #define RXDP 0x30
334 #define RXDP_HI 0x34
335 #define RXCFG 0x38
336 #define PQCR 0x3c
337 #define WCSR 0x40
338 #define PCR 0x44
339 #define RFCR 0x48
340 #define RFDR 0x4c
341
342 #define SRR 0x58
343
344 #define VRCR 0xbc
345 #define VTCR 0xc0
346 #define VDR 0xc4
347 #define CCSR 0xcc
348
349 #define TBICR 0xe0
350 #define TBISR 0xe4
351 #define TANAR 0xe8
352 #define TANLPAR 0xec
353 #define TANER 0xf0
354 #define TESR 0xf4
355
356 #define TBICR_MR_AN_ENABLE 0x00001000
357 #define TBICR_MR_RESTART_AN 0x00000200
358
359 #define TBISR_MR_LINK_STATUS 0x00000020
360 #define TBISR_MR_AN_COMPLETE 0x00000004
361
362 #define TANAR_PS2 0x00000100
363 #define TANAR_PS1 0x00000080
364 #define TANAR_HALF_DUP 0x00000040
365 #define TANAR_FULL_DUP 0x00000020
366
367 #define GPIOR_GP5_OE 0x00000200
368 #define GPIOR_GP4_OE 0x00000100
369 #define GPIOR_GP3_OE 0x00000080
370 #define GPIOR_GP2_OE 0x00000040
371 #define GPIOR_GP1_OE 0x00000020
372 #define GPIOR_GP3_OUT 0x00000004
373 #define GPIOR_GP1_OUT 0x00000001
374
375 #define LINK_AUTONEGOTIATE 0x01
376 #define LINK_DOWN 0x02
377 #define LINK_UP 0x04
378
379 #ifdef USE_64BIT_ADDR
380 #define HW_ADDR_LEN 8
381 #define desc_addr_set(desc, addr) \
382 do { \
383 u64 __addr = (addr); \
384 (desc)[0] = cpu_to_le32(__addr); \
385 (desc)[1] = cpu_to_le32(__addr >> 32); \
386 } while(0)
387 #define desc_addr_get(desc) \
388 (((u64)le32_to_cpu((desc)[1]) << 32) \
389 | le32_to_cpu((desc)[0]))
390 #else
391 #define HW_ADDR_LEN 4
392 #define desc_addr_set(desc, addr) ((desc)[0] = cpu_to_le32(addr))
393 #define desc_addr_get(desc) (le32_to_cpu((desc)[0]))
394 #endif
395
396 #define DESC_LINK 0
397 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
398 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
399 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
400
401 #define CMDSTS_OWN 0x80000000
402 #define CMDSTS_MORE 0x40000000
403 #define CMDSTS_INTR 0x20000000
404 #define CMDSTS_ERR 0x10000000
405 #define CMDSTS_OK 0x08000000
406 #define CMDSTS_LEN_MASK 0x0000ffff
407
408 #define CMDSTS_DEST_MASK 0x01800000
409 #define CMDSTS_DEST_SELF 0x00800000
410 #define CMDSTS_DEST_MULTI 0x01000000
411
412 #define DESC_SIZE 8 /* Should be cache line sized */
413
414 struct rx_info {
415 spinlock_t lock;
416 int up;
417 long idle;
418
419 struct sk_buff *skbs[NR_RX_DESC];
420
421 u32 *next_rx_desc;
422 u16 next_rx, next_empty;
423
424 u32 *descs;
425 dma_addr_t phy_descs;
426 };
427
428
429 struct ns83820 {
430 struct net_device_stats stats;
431 u8 *base;
432
433 struct pci_dev *pci_dev;
434
435 struct rx_info rx_info;
436 struct tasklet_struct rx_tasklet;
437
438 unsigned ihr;
439 struct work_struct tq_refill;
440
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock;
443
444 u32 CFG_cache;
445
446 u32 MEAR_cache;
447 u32 IMR_cache;
448 struct eeprom ee;
449
450 unsigned linkstate;
451
452 spinlock_t tx_lock;
453
454 u16 tx_done_idx;
455 u16 tx_idx;
456 volatile u16 tx_free_idx; /* idx of free desc chain */
457 u16 tx_intr_idx;
458
459 atomic_t nr_tx_skbs;
460 struct sk_buff *tx_skbs[NR_TX_DESC];
461
462 char pad[16] __attribute__((aligned(16)));
463 u32 *tx_descs;
464 dma_addr_t tx_phy_descs;
465
466 struct timer_list tx_watchdog;
467 };
468
469 static inline struct ns83820 *PRIV(struct net_device *dev)
470 {
471 return netdev_priv(dev);
472 }
473
474 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
475
476 static inline void kick_rx(struct net_device *ndev)
477 {
478 struct ns83820 *dev = PRIV(ndev);
479 dprintk("kick_rx: maybe kicking\n");
480 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
481 dprintk("actually kicking\n");
482 writel(dev->rx_info.phy_descs +
483 (4 * DESC_SIZE * dev->rx_info.next_rx),
484 dev->base + RXDP);
485 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
486 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
487 ndev->name);
488 __kick_rx(dev);
489 }
490 }
491
492 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
493 #define start_tx_okay(dev) \
494 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
495
496
497 /* Packet Receiver
498 *
499 * The hardware supports linked lists of receive descriptors for
500 * which ownership is transfered back and forth by means of an
501 * ownership bit. While the hardware does support the use of a
502 * ring for receive descriptors, we only make use of a chain in
503 * an attempt to reduce bus traffic under heavy load scenarios.
504 * This will also make bugs a bit more obvious. The current code
505 * only makes use of a single rx chain; I hope to implement
506 * priority based rx for version 1.0. Goal: even under overload
507 * conditions, still route realtime traffic with as low jitter as
508 * possible.
509 */
510 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
511 {
512 desc_addr_set(desc + DESC_LINK, link);
513 desc_addr_set(desc + DESC_BUFPTR, buf);
514 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
515 mb();
516 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
517 }
518
519 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
520 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
521 {
522 unsigned next_empty;
523 u32 cmdsts;
524 u32 *sg;
525 dma_addr_t buf;
526
527 next_empty = dev->rx_info.next_empty;
528
529 /* don't overrun last rx marker */
530 if (unlikely(nr_rx_empty(dev) <= 2)) {
531 kfree_skb(skb);
532 return 1;
533 }
534
535 #if 0
536 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
537 dev->rx_info.next_empty,
538 dev->rx_info.nr_used,
539 dev->rx_info.next_rx
540 );
541 #endif
542
543 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
544 if (unlikely(NULL != dev->rx_info.skbs[next_empty]))
545 BUG();
546 dev->rx_info.skbs[next_empty] = skb;
547
548 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
549 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
550 buf = pci_map_single(dev->pci_dev, skb->tail,
551 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
552 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
553 /* update link of previous rx */
554 if (likely(next_empty != dev->rx_info.next_rx))
555 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
556
557 return 0;
558 }
559
560 static inline int rx_refill(struct net_device *ndev, int gfp)
561 {
562 struct ns83820 *dev = PRIV(ndev);
563 unsigned i;
564 unsigned long flags = 0;
565
566 if (unlikely(nr_rx_empty(dev) <= 2))
567 return 0;
568
569 dprintk("rx_refill(%p)\n", ndev);
570 if (gfp == GFP_ATOMIC)
571 spin_lock_irqsave(&dev->rx_info.lock, flags);
572 for (i=0; i<NR_RX_DESC; i++) {
573 struct sk_buff *skb;
574 long res;
575 /* extra 16 bytes for alignment */
576 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
577 if (unlikely(!skb))
578 break;
579
580 res = (long)skb->tail & 0xf;
581 res = 0x10 - res;
582 res &= 0xf;
583 skb_reserve(skb, res);
584
585 skb->dev = ndev;
586 if (gfp != GFP_ATOMIC)
587 spin_lock_irqsave(&dev->rx_info.lock, flags);
588 res = ns83820_add_rx_skb(dev, skb);
589 if (gfp != GFP_ATOMIC)
590 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
591 if (res) {
592 i = 1;
593 break;
594 }
595 }
596 if (gfp == GFP_ATOMIC)
597 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
598
599 return i ? 0 : -ENOMEM;
600 }
601
602 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
603 static void fastcall rx_refill_atomic(struct net_device *ndev)
604 {
605 rx_refill(ndev, GFP_ATOMIC);
606 }
607
608 /* REFILL */
609 static inline void queue_refill(void *_dev)
610 {
611 struct net_device *ndev = _dev;
612 struct ns83820 *dev = PRIV(ndev);
613
614 rx_refill(ndev, GFP_KERNEL);
615 if (dev->rx_info.up)
616 kick_rx(ndev);
617 }
618
619 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
620 {
621 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
622 }
623
624 static void FASTCALL(phy_intr(struct net_device *ndev));
625 static void fastcall phy_intr(struct net_device *ndev)
626 {
627 struct ns83820 *dev = PRIV(ndev);
628 static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
629 u32 cfg, new_cfg;
630 u32 tbisr, tanar, tanlpar;
631 int speed, fullduplex, newlinkstate;
632
633 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
634
635 if (dev->CFG_cache & CFG_TBI_EN) {
636 /* we have an optical transceiver */
637 tbisr = readl(dev->base + TBISR);
638 tanar = readl(dev->base + TANAR);
639 tanlpar = readl(dev->base + TANLPAR);
640 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
641 tbisr, tanar, tanlpar);
642
643 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
644 && (tanar & TANAR_FULL_DUP)) ) {
645
646 /* both of us are full duplex */
647 writel(readl(dev->base + TXCFG)
648 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
649 dev->base + TXCFG);
650 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
651 dev->base + RXCFG);
652 /* Light up full duplex LED */
653 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
654 dev->base + GPIOR);
655
656 } else if(((tanlpar & TANAR_HALF_DUP)
657 && (tanar & TANAR_HALF_DUP))
658 || ((tanlpar & TANAR_FULL_DUP)
659 && (tanar & TANAR_HALF_DUP))
660 || ((tanlpar & TANAR_HALF_DUP)
661 && (tanar & TANAR_FULL_DUP))) {
662
663 /* one or both of us are half duplex */
664 writel((readl(dev->base + TXCFG)
665 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
666 dev->base + TXCFG);
667 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
668 dev->base + RXCFG);
669 /* Turn off full duplex LED */
670 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
671 dev->base + GPIOR);
672 }
673
674 speed = 4; /* 1000F */
675
676 } else {
677 /* we have a copper transceiver */
678 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
679
680 if (cfg & CFG_SPDSTS1)
681 new_cfg |= CFG_MODE_1000;
682 else
683 new_cfg &= ~CFG_MODE_1000;
684
685 speed = ((cfg / CFG_SPDSTS0) & 3);
686 fullduplex = (cfg & CFG_DUPSTS);
687
688 if (fullduplex)
689 new_cfg |= CFG_SB;
690
691 if ((cfg & CFG_LNKSTS) &&
692 ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) {
693 writel(new_cfg, dev->base + CFG);
694 dev->CFG_cache = new_cfg;
695 }
696
697 dev->CFG_cache &= ~CFG_SPDSTS;
698 dev->CFG_cache |= cfg & CFG_SPDSTS;
699 }
700
701 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
702
703 if (newlinkstate & LINK_UP
704 && dev->linkstate != newlinkstate) {
705 netif_start_queue(ndev);
706 netif_wake_queue(ndev);
707 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
708 ndev->name,
709 speeds[speed],
710 fullduplex ? "full" : "half");
711 } else if (newlinkstate & LINK_DOWN
712 && dev->linkstate != newlinkstate) {
713 netif_stop_queue(ndev);
714 printk(KERN_INFO "%s: link now down.\n", ndev->name);
715 }
716
717 dev->linkstate = newlinkstate;
718 }
719
720 static int ns83820_setup_rx(struct net_device *ndev)
721 {
722 struct ns83820 *dev = PRIV(ndev);
723 unsigned i;
724 int ret;
725
726 dprintk("ns83820_setup_rx(%p)\n", ndev);
727
728 dev->rx_info.idle = 1;
729 dev->rx_info.next_rx = 0;
730 dev->rx_info.next_rx_desc = dev->rx_info.descs;
731 dev->rx_info.next_empty = 0;
732
733 for (i=0; i<NR_RX_DESC; i++)
734 clear_rx_desc(dev, i);
735
736 writel(0, dev->base + RXDP_HI);
737 writel(dev->rx_info.phy_descs, dev->base + RXDP);
738
739 ret = rx_refill(ndev, GFP_KERNEL);
740 if (!ret) {
741 dprintk("starting receiver\n");
742 /* prevent the interrupt handler from stomping on us */
743 spin_lock_irq(&dev->rx_info.lock);
744
745 writel(0x0001, dev->base + CCSR);
746 writel(0, dev->base + RFCR);
747 writel(0x7fc00000, dev->base + RFCR);
748 writel(0xffc00000, dev->base + RFCR);
749
750 dev->rx_info.up = 1;
751
752 phy_intr(ndev);
753
754 /* Okay, let it rip */
755 spin_lock_irq(&dev->misc_lock);
756 dev->IMR_cache |= ISR_PHY;
757 dev->IMR_cache |= ISR_RXRCMP;
758 //dev->IMR_cache |= ISR_RXERR;
759 //dev->IMR_cache |= ISR_RXOK;
760 dev->IMR_cache |= ISR_RXORN;
761 dev->IMR_cache |= ISR_RXSOVR;
762 dev->IMR_cache |= ISR_RXDESC;
763 dev->IMR_cache |= ISR_RXIDLE;
764 dev->IMR_cache |= ISR_TXDESC;
765 dev->IMR_cache |= ISR_TXIDLE;
766
767 writel(dev->IMR_cache, dev->base + IMR);
768 writel(1, dev->base + IER);
769 spin_unlock_irq(&dev->misc_lock);
770
771 kick_rx(ndev);
772
773 spin_unlock_irq(&dev->rx_info.lock);
774 }
775 return ret;
776 }
777
778 static void ns83820_cleanup_rx(struct ns83820 *dev)
779 {
780 unsigned i;
781 unsigned long flags;
782
783 dprintk("ns83820_cleanup_rx(%p)\n", dev);
784
785 /* disable receive interrupts */
786 spin_lock_irqsave(&dev->misc_lock, flags);
787 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
788 writel(dev->IMR_cache, dev->base + IMR);
789 spin_unlock_irqrestore(&dev->misc_lock, flags);
790
791 /* synchronize with the interrupt handler and kill it */
792 dev->rx_info.up = 0;
793 synchronize_irq(dev->pci_dev->irq);
794
795 /* touch the pci bus... */
796 readl(dev->base + IMR);
797
798 /* assumes the transmitter is already disabled and reset */
799 writel(0, dev->base + RXDP_HI);
800 writel(0, dev->base + RXDP);
801
802 for (i=0; i<NR_RX_DESC; i++) {
803 struct sk_buff *skb = dev->rx_info.skbs[i];
804 dev->rx_info.skbs[i] = NULL;
805 clear_rx_desc(dev, i);
806 if (skb)
807 kfree_skb(skb);
808 }
809 }
810
811 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
812 static void fastcall ns83820_rx_kick(struct net_device *ndev)
813 {
814 struct ns83820 *dev = PRIV(ndev);
815 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
816 if (dev->rx_info.up) {
817 rx_refill_atomic(ndev);
818 kick_rx(ndev);
819 }
820 }
821
822 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
823 schedule_work(&dev->tq_refill);
824 else
825 kick_rx(ndev);
826 if (dev->rx_info.idle)
827 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
828 }
829
830 /* rx_irq
831 *
832 */
833 static void FASTCALL(rx_irq(struct net_device *ndev));
834 static void fastcall rx_irq(struct net_device *ndev)
835 {
836 struct ns83820 *dev = PRIV(ndev);
837 struct rx_info *info = &dev->rx_info;
838 unsigned next_rx;
839 u32 cmdsts, *desc;
840 unsigned long flags;
841 int nr = 0;
842
843 dprintk("rx_irq(%p)\n", ndev);
844 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
845 readl(dev->base + RXDP),
846 (long)(dev->rx_info.phy_descs),
847 (int)dev->rx_info.next_rx,
848 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
849 (int)dev->rx_info.next_empty,
850 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
851 );
852
853 spin_lock_irqsave(&info->lock, flags);
854 if (!info->up)
855 goto out;
856
857 dprintk("walking descs\n");
858 next_rx = info->next_rx;
859 desc = info->next_rx_desc;
860 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
861 (cmdsts != CMDSTS_OWN)) {
862 struct sk_buff *skb;
863 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
864 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
865
866 dprintk("cmdsts: %08x\n", cmdsts);
867 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
868 dprintk("extsts: %08x\n", extsts);
869
870 skb = info->skbs[next_rx];
871 info->skbs[next_rx] = NULL;
872 info->next_rx = (next_rx + 1) % NR_RX_DESC;
873
874 mb();
875 clear_rx_desc(dev, next_rx);
876
877 pci_unmap_single(dev->pci_dev, bufptr,
878 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
879 if (likely(CMDSTS_OK & cmdsts)) {
880 int len = cmdsts & 0xffff;
881 skb_put(skb, len);
882 if (unlikely(!skb))
883 goto netdev_mangle_me_harder_failed;
884 if (cmdsts & CMDSTS_DEST_MULTI)
885 dev->stats.multicast ++;
886 dev->stats.rx_packets ++;
887 dev->stats.rx_bytes += len;
888 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
889 skb->ip_summed = CHECKSUM_UNNECESSARY;
890 } else {
891 skb->ip_summed = CHECKSUM_NONE;
892 }
893 skb->protocol = eth_type_trans(skb, ndev);
894 if (NET_RX_DROP == netif_rx(skb)) {
895 netdev_mangle_me_harder_failed:
896 dev->stats.rx_dropped ++;
897 }
898 } else {
899 kfree_skb(skb);
900 }
901
902 nr++;
903 next_rx = info->next_rx;
904 desc = info->descs + (DESC_SIZE * next_rx);
905 }
906 info->next_rx = next_rx;
907 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
908
909 out:
910 if (0 && !nr) {
911 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
912 }
913
914 spin_unlock_irqrestore(&info->lock, flags);
915 }
916
917 static void rx_action(unsigned long _dev)
918 {
919 struct net_device *ndev = (void *)_dev;
920 struct ns83820 *dev = PRIV(ndev);
921 rx_irq(ndev);
922 writel(ihr, dev->base + IHR);
923
924 spin_lock_irq(&dev->misc_lock);
925 dev->IMR_cache |= ISR_RXDESC;
926 writel(dev->IMR_cache, dev->base + IMR);
927 spin_unlock_irq(&dev->misc_lock);
928
929 rx_irq(ndev);
930 ns83820_rx_kick(ndev);
931 }
932
933 /* Packet Transmit code
934 */
935 static inline void kick_tx(struct ns83820 *dev)
936 {
937 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
938 dev, dev->tx_idx, dev->tx_free_idx);
939 writel(CR_TXE, dev->base + CR);
940 }
941
942 /* No spinlock needed on the transmit irq path as the interrupt handler is
943 * serialized.
944 */
945 static void do_tx_done(struct net_device *ndev)
946 {
947 struct ns83820 *dev = PRIV(ndev);
948 u32 cmdsts, tx_done_idx, *desc;
949
950 spin_lock_irq(&dev->tx_lock);
951
952 dprintk("do_tx_done(%p)\n", ndev);
953 tx_done_idx = dev->tx_done_idx;
954 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
955
956 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
957 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
958 while ((tx_done_idx != dev->tx_free_idx) &&
959 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
960 struct sk_buff *skb;
961 unsigned len;
962 dma_addr_t addr;
963
964 if (cmdsts & CMDSTS_ERR)
965 dev->stats.tx_errors ++;
966 if (cmdsts & CMDSTS_OK)
967 dev->stats.tx_packets ++;
968 if (cmdsts & CMDSTS_OK)
969 dev->stats.tx_bytes += cmdsts & 0xffff;
970
971 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
972 tx_done_idx, dev->tx_free_idx, cmdsts);
973 skb = dev->tx_skbs[tx_done_idx];
974 dev->tx_skbs[tx_done_idx] = NULL;
975 dprintk("done(%p)\n", skb);
976
977 len = cmdsts & CMDSTS_LEN_MASK;
978 addr = desc_addr_get(desc + DESC_BUFPTR);
979 if (skb) {
980 pci_unmap_single(dev->pci_dev,
981 addr,
982 len,
983 PCI_DMA_TODEVICE);
984 dev_kfree_skb_irq(skb);
985 atomic_dec(&dev->nr_tx_skbs);
986 } else
987 pci_unmap_page(dev->pci_dev,
988 addr,
989 len,
990 PCI_DMA_TODEVICE);
991
992 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
993 dev->tx_done_idx = tx_done_idx;
994 desc[DESC_CMDSTS] = cpu_to_le32(0);
995 mb();
996 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
997 }
998
999 /* Allow network stack to resume queueing packets after we've
1000 * finished transmitting at least 1/4 of the packets in the queue.
1001 */
1002 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1003 dprintk("start_queue(%p)\n", ndev);
1004 netif_start_queue(ndev);
1005 netif_wake_queue(ndev);
1006 }
1007 spin_unlock_irq(&dev->tx_lock);
1008 }
1009
1010 static void ns83820_cleanup_tx(struct ns83820 *dev)
1011 {
1012 unsigned i;
1013
1014 for (i=0; i<NR_TX_DESC; i++) {
1015 struct sk_buff *skb = dev->tx_skbs[i];
1016 dev->tx_skbs[i] = NULL;
1017 if (skb) {
1018 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
1019 pci_unmap_single(dev->pci_dev,
1020 desc_addr_get(desc + DESC_BUFPTR),
1021 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1022 PCI_DMA_TODEVICE);
1023 dev_kfree_skb_irq(skb);
1024 atomic_dec(&dev->nr_tx_skbs);
1025 }
1026 }
1027
1028 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1029 }
1030
1031 /* transmit routine. This code relies on the network layer serializing
1032 * its calls in, but will run happily in parallel with the interrupt
1033 * handler. This code currently has provisions for fragmenting tx buffers
1034 * while trying to track down a bug in either the zero copy code or
1035 * the tx fifo (hence the MAX_FRAG_LEN).
1036 */
1037 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1038 {
1039 struct ns83820 *dev = PRIV(ndev);
1040 u32 free_idx, cmdsts, extsts;
1041 int nr_free, nr_frags;
1042 unsigned tx_done_idx, last_idx;
1043 dma_addr_t buf;
1044 unsigned len;
1045 skb_frag_t *frag;
1046 int stopped = 0;
1047 int do_intr = 0;
1048 volatile u32 *first_desc;
1049
1050 dprintk("ns83820_hard_start_xmit\n");
1051
1052 nr_frags = skb_shinfo(skb)->nr_frags;
1053 again:
1054 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1055 netif_stop_queue(ndev);
1056 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1057 return 1;
1058 netif_start_queue(ndev);
1059 }
1060
1061 last_idx = free_idx = dev->tx_free_idx;
1062 tx_done_idx = dev->tx_done_idx;
1063 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1064 nr_free -= 1;
1065 if (nr_free <= nr_frags) {
1066 dprintk("stop_queue - not enough(%p)\n", ndev);
1067 netif_stop_queue(ndev);
1068
1069 /* Check again: we may have raced with a tx done irq */
1070 if (dev->tx_done_idx != tx_done_idx) {
1071 dprintk("restart queue(%p)\n", ndev);
1072 netif_start_queue(ndev);
1073 goto again;
1074 }
1075 return 1;
1076 }
1077
1078 if (free_idx == dev->tx_intr_idx) {
1079 do_intr = 1;
1080 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1081 }
1082
1083 nr_free -= nr_frags;
1084 if (nr_free < MIN_TX_DESC_FREE) {
1085 dprintk("stop_queue - last entry(%p)\n", ndev);
1086 netif_stop_queue(ndev);
1087 stopped = 1;
1088 }
1089
1090 frag = skb_shinfo(skb)->frags;
1091 if (!nr_frags)
1092 frag = NULL;
1093 extsts = 0;
1094 if (skb->ip_summed == CHECKSUM_HW) {
1095 extsts |= EXTSTS_IPPKT;
1096 if (IPPROTO_TCP == skb->nh.iph->protocol)
1097 extsts |= EXTSTS_TCPPKT;
1098 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1099 extsts |= EXTSTS_UDPPKT;
1100 }
1101
1102 len = skb->len;
1103 if (nr_frags)
1104 len -= skb->data_len;
1105 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1106
1107 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1108
1109 for (;;) {
1110 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1111 u32 residue = 0;
1112
1113 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1114 (unsigned long long)buf);
1115 last_idx = free_idx;
1116 free_idx = (free_idx + 1) % NR_TX_DESC;
1117 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1118 desc_addr_set(desc + DESC_BUFPTR, buf);
1119 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1120
1121 cmdsts = ((nr_frags|residue) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1122 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1123 cmdsts |= len;
1124 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1125
1126 if (residue) {
1127 buf += len;
1128 len = residue;
1129 continue;
1130 }
1131
1132 if (!nr_frags)
1133 break;
1134
1135 buf = pci_map_page(dev->pci_dev, frag->page,
1136 frag->page_offset,
1137 frag->size, PCI_DMA_TODEVICE);
1138 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1139 (long long)buf, (long) page_to_pfn(frag->page),
1140 frag->page_offset);
1141 len = frag->size;
1142 frag++;
1143 nr_frags--;
1144 }
1145 dprintk("done pkt\n");
1146
1147 spin_lock_irq(&dev->tx_lock);
1148 dev->tx_skbs[last_idx] = skb;
1149 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1150 dev->tx_free_idx = free_idx;
1151 atomic_inc(&dev->nr_tx_skbs);
1152 spin_unlock_irq(&dev->tx_lock);
1153
1154 kick_tx(dev);
1155
1156 /* Check again: we may have raced with a tx done irq */
1157 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1158 netif_start_queue(ndev);
1159
1160 /* set the transmit start time to catch transmit timeouts */
1161 ndev->trans_start = jiffies;
1162 return 0;
1163 }
1164
1165 static void ns83820_update_stats(struct ns83820 *dev)
1166 {
1167 u8 *base = dev->base;
1168
1169 /* the DP83820 will freeze counters, so we need to read all of them */
1170 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1171 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1172 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1173 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1174 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1175 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1176 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1177 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1178 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1179 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1180 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1181 }
1182
1183 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1184 {
1185 struct ns83820 *dev = PRIV(ndev);
1186
1187 /* somewhat overkill */
1188 spin_lock_irq(&dev->misc_lock);
1189 ns83820_update_stats(dev);
1190 spin_unlock_irq(&dev->misc_lock);
1191
1192 return &dev->stats;
1193 }
1194
1195 static int ns83820_ethtool_ioctl (struct ns83820 *dev, void __user *useraddr)
1196 {
1197 u32 ethcmd;
1198
1199 if (copy_from_user(&ethcmd, useraddr, sizeof (ethcmd)))
1200 return -EFAULT;
1201
1202 switch (ethcmd) {
1203 case ETHTOOL_GDRVINFO:
1204 {
1205 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1206 strcpy(info.driver, "ns83820");
1207 strcpy(info.version, VERSION);
1208 strcpy(info.bus_info, pci_name(dev->pci_dev));
1209 if (copy_to_user(useraddr, &info, sizeof (info)))
1210 return -EFAULT;
1211 return 0;
1212 }
1213
1214 /* get link status */
1215 case ETHTOOL_GLINK: {
1216 struct ethtool_value edata = { ETHTOOL_GLINK };
1217 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1218
1219 if (cfg & CFG_LNKSTS)
1220 edata.data = 1;
1221 else
1222 edata.data = 0;
1223 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1224 return -EFAULT;
1225 return 0;
1226 }
1227
1228 default:
1229 break;
1230 }
1231
1232 return -EOPNOTSUPP;
1233 }
1234
1235 static int ns83820_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1236 {
1237 struct ns83820 *dev = PRIV(ndev);
1238
1239 switch(cmd) {
1240 case SIOCETHTOOL:
1241 return ns83820_ethtool_ioctl(dev, rq->ifr_data);
1242
1243 default:
1244 return -EOPNOTSUPP;
1245 }
1246 }
1247
1248 static void ns83820_mib_isr(struct ns83820 *dev)
1249 {
1250 spin_lock(&dev->misc_lock);
1251 ns83820_update_stats(dev);
1252 spin_unlock(&dev->misc_lock);
1253 }
1254
1255 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1256 static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1257 {
1258 struct net_device *ndev = data;
1259 struct ns83820 *dev = PRIV(ndev);
1260 u32 isr;
1261 dprintk("ns83820_irq(%p)\n", ndev);
1262
1263 dev->ihr = 0;
1264
1265 isr = readl(dev->base + ISR);
1266 dprintk("irq: %08x\n", isr);
1267 ns83820_do_isr(ndev, isr);
1268 return IRQ_HANDLED;
1269 }
1270
1271 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1272 {
1273 struct ns83820 *dev = PRIV(ndev);
1274 #ifdef DEBUG
1275 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1276 Dprintk("odd isr? 0x%08x\n", isr);
1277 #endif
1278
1279 if (ISR_RXIDLE & isr) {
1280 dev->rx_info.idle = 1;
1281 Dprintk("oh dear, we are idle\n");
1282 ns83820_rx_kick(ndev);
1283 }
1284
1285 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1286 prefetch(dev->rx_info.next_rx_desc);
1287
1288 spin_lock_irq(&dev->misc_lock);
1289 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1290 writel(dev->IMR_cache, dev->base + IMR);
1291 spin_unlock_irq(&dev->misc_lock);
1292
1293 tasklet_schedule(&dev->rx_tasklet);
1294 //rx_irq(ndev);
1295 //writel(4, dev->base + IHR);
1296 }
1297
1298 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1299 ns83820_rx_kick(ndev);
1300
1301 if (unlikely(ISR_RXSOVR & isr)) {
1302 //printk("overrun: rxsovr\n");
1303 dev->stats.rx_fifo_errors ++;
1304 }
1305
1306 if (unlikely(ISR_RXORN & isr)) {
1307 //printk("overrun: rxorn\n");
1308 dev->stats.rx_fifo_errors ++;
1309 }
1310
1311 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1312 writel(CR_RXE, dev->base + CR);
1313
1314 if (ISR_TXIDLE & isr) {
1315 u32 txdp;
1316 txdp = readl(dev->base + TXDP);
1317 dprintk("txdp: %08x\n", txdp);
1318 txdp -= dev->tx_phy_descs;
1319 dev->tx_idx = txdp / (DESC_SIZE * 4);
1320 if (dev->tx_idx >= NR_TX_DESC) {
1321 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1322 dev->tx_idx = 0;
1323 }
1324 /* The may have been a race between a pci originated read
1325 * and the descriptor update from the cpu. Just in case,
1326 * kick the transmitter if the hardware thinks it is on a
1327 * different descriptor than we are.
1328 */
1329 if (dev->tx_idx != dev->tx_free_idx)
1330 kick_tx(dev);
1331 }
1332
1333 /* Defer tx ring processing until more than a minimum amount of
1334 * work has accumulated
1335 */
1336 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1337 do_tx_done(ndev);
1338
1339 /* Disable TxOk if there are no outstanding tx packets.
1340 */
1341 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1342 (dev->IMR_cache & ISR_TXOK)) {
1343 spin_lock_irq(&dev->misc_lock);
1344 dev->IMR_cache &= ~ISR_TXOK;
1345 writel(dev->IMR_cache, dev->base + IMR);
1346 spin_unlock_irq(&dev->misc_lock);
1347 }
1348 }
1349
1350 /* The TxIdle interrupt can come in before the transmit has
1351 * completed. Normally we reap packets off of the combination
1352 * of TxDesc and TxIdle and leave TxOk disabled (since it
1353 * occurs on every packet), but when no further irqs of this
1354 * nature are expected, we must enable TxOk.
1355 */
1356 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1357 spin_lock_irq(&dev->misc_lock);
1358 dev->IMR_cache |= ISR_TXOK;
1359 writel(dev->IMR_cache, dev->base + IMR);
1360 spin_unlock_irq(&dev->misc_lock);
1361 }
1362
1363 /* MIB interrupt: one of the statistics counters is about to overflow */
1364 if (unlikely(ISR_MIB & isr))
1365 ns83820_mib_isr(dev);
1366
1367 /* PHY: Link up/down/negotiation state change */
1368 if (unlikely(ISR_PHY & isr))
1369 phy_intr(ndev);
1370
1371 #if 0 /* Still working on the interrupt mitigation strategy */
1372 if (dev->ihr)
1373 writel(dev->ihr, dev->base + IHR);
1374 #endif
1375 }
1376
1377 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1378 {
1379 Dprintk("resetting chip...\n");
1380 writel(which, dev->base + CR);
1381 do {
1382 schedule();
1383 } while (readl(dev->base + CR) & which);
1384 Dprintk("okay!\n");
1385 }
1386
1387 static int ns83820_stop(struct net_device *ndev)
1388 {
1389 struct ns83820 *dev = PRIV(ndev);
1390
1391 /* FIXME: protect against interrupt handler? */
1392 del_timer_sync(&dev->tx_watchdog);
1393
1394 /* disable interrupts */
1395 writel(0, dev->base + IMR);
1396 writel(0, dev->base + IER);
1397 readl(dev->base + IER);
1398
1399 dev->rx_info.up = 0;
1400 synchronize_irq(dev->pci_dev->irq);
1401
1402 ns83820_do_reset(dev, CR_RST);
1403
1404 synchronize_irq(dev->pci_dev->irq);
1405
1406 spin_lock_irq(&dev->misc_lock);
1407 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1408 spin_unlock_irq(&dev->misc_lock);
1409
1410 ns83820_cleanup_rx(dev);
1411 ns83820_cleanup_tx(dev);
1412
1413 return 0;
1414 }
1415
1416 static void ns83820_tx_timeout(struct net_device *ndev)
1417 {
1418 struct ns83820 *dev = PRIV(ndev);
1419 u32 tx_done_idx, *desc;
1420 unsigned long flags;
1421
1422 local_irq_save(flags);
1423
1424 tx_done_idx = dev->tx_done_idx;
1425 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1426
1427 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1428 ndev->name,
1429 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1430
1431 #if defined(DEBUG)
1432 {
1433 u32 isr;
1434 isr = readl(dev->base + ISR);
1435 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1436 ns83820_do_isr(ndev, isr);
1437 }
1438 #endif
1439
1440 do_tx_done(ndev);
1441
1442 tx_done_idx = dev->tx_done_idx;
1443 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1444
1445 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1446 ndev->name,
1447 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1448
1449 local_irq_restore(flags);
1450 }
1451
1452 static void ns83820_tx_watch(unsigned long data)
1453 {
1454 struct net_device *ndev = (void *)data;
1455 struct ns83820 *dev = PRIV(ndev);
1456
1457 #if defined(DEBUG)
1458 printk("ns83820_tx_watch: %u %u %d\n",
1459 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1460 );
1461 #endif
1462
1463 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1464 dev->tx_done_idx != dev->tx_free_idx) {
1465 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1466 ndev->name,
1467 dev->tx_done_idx, dev->tx_free_idx,
1468 atomic_read(&dev->nr_tx_skbs));
1469 ns83820_tx_timeout(ndev);
1470 }
1471
1472 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1473 }
1474
1475 static int ns83820_open(struct net_device *ndev)
1476 {
1477 struct ns83820 *dev = PRIV(ndev);
1478 unsigned i;
1479 u32 desc;
1480 int ret;
1481
1482 dprintk("ns83820_open\n");
1483
1484 writel(0, dev->base + PQCR);
1485
1486 ret = ns83820_setup_rx(ndev);
1487 if (ret)
1488 goto failed;
1489
1490 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1491 for (i=0; i<NR_TX_DESC; i++) {
1492 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1493 = cpu_to_le32(
1494 dev->tx_phy_descs
1495 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1496 }
1497
1498 dev->tx_idx = 0;
1499 dev->tx_done_idx = 0;
1500 desc = dev->tx_phy_descs;
1501 writel(0, dev->base + TXDP_HI);
1502 writel(desc, dev->base + TXDP);
1503
1504 init_timer(&dev->tx_watchdog);
1505 dev->tx_watchdog.data = (unsigned long)ndev;
1506 dev->tx_watchdog.function = ns83820_tx_watch;
1507 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1508
1509 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1510
1511 return 0;
1512
1513 failed:
1514 ns83820_stop(ndev);
1515 return ret;
1516 }
1517
1518 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1519 {
1520 unsigned i;
1521 for (i=0; i<3; i++) {
1522 u32 data;
1523 #if 0 /* I've left this in as an example of how to use eeprom.h */
1524 data = eeprom_readw(&dev->ee, 0xa + 2 - i);
1525 #else
1526 /* Read from the perfect match memory: this is loaded by
1527 * the chip from the EEPROM via the EELOAD self test.
1528 */
1529 writel(i*2, dev->base + RFCR);
1530 data = readl(dev->base + RFDR);
1531 #endif
1532 *mac++ = data;
1533 *mac++ = data >> 8;
1534 }
1535 }
1536
1537 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1538 {
1539 if (new_mtu > RX_BUF_SIZE)
1540 return -EINVAL;
1541 ndev->mtu = new_mtu;
1542 return 0;
1543 }
1544
1545 static void ns83820_set_multicast(struct net_device *ndev)
1546 {
1547 struct ns83820 *dev = PRIV(ndev);
1548 u8 *rfcr = dev->base + RFCR;
1549 u32 and_mask = 0xffffffff;
1550 u32 or_mask = 0;
1551 u32 val;
1552
1553 if (ndev->flags & IFF_PROMISC)
1554 or_mask |= RFCR_AAU | RFCR_AAM;
1555 else
1556 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1557
1558 if (ndev->flags & IFF_ALLMULTI)
1559 or_mask |= RFCR_AAM;
1560 else
1561 and_mask &= ~RFCR_AAM;
1562
1563 spin_lock_irq(&dev->misc_lock);
1564 val = (readl(rfcr) & and_mask) | or_mask;
1565 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1566 writel(val & ~RFCR_RFEN, rfcr);
1567 writel(val, rfcr);
1568 spin_unlock_irq(&dev->misc_lock);
1569 }
1570
1571 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1572 {
1573 struct ns83820 *dev = PRIV(ndev);
1574 int timed_out = 0;
1575 long start;
1576 u32 status;
1577 int loops = 0;
1578
1579 dprintk("%s: start %s\n", ndev->name, name);
1580
1581 start = jiffies;
1582
1583 writel(enable, dev->base + PTSCR);
1584 for (;;) {
1585 loops++;
1586 status = readl(dev->base + PTSCR);
1587 if (!(status & enable))
1588 break;
1589 if (status & done)
1590 break;
1591 if (status & fail)
1592 break;
1593 if ((jiffies - start) >= HZ) {
1594 timed_out = 1;
1595 break;
1596 }
1597 set_current_state(TASK_UNINTERRUPTIBLE);
1598 schedule_timeout(1);
1599 }
1600
1601 if (status & fail)
1602 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1603 ndev->name, name, status, fail);
1604 else if (timed_out)
1605 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1606 ndev->name, name, status);
1607
1608 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1609 }
1610
1611 #ifdef PHY_CODE_IS_FINISHED
1612 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1613 {
1614 /* drive MDC low */
1615 dev->MEAR_cache &= ~MEAR_MDC;
1616 writel(dev->MEAR_cache, dev->base + MEAR);
1617 readl(dev->base + MEAR);
1618
1619 /* enable output, set bit */
1620 dev->MEAR_cache |= MEAR_MDDIR;
1621 if (bit)
1622 dev->MEAR_cache |= MEAR_MDIO;
1623 else
1624 dev->MEAR_cache &= ~MEAR_MDIO;
1625
1626 /* set the output bit */
1627 writel(dev->MEAR_cache, dev->base + MEAR);
1628 readl(dev->base + MEAR);
1629
1630 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1631 udelay(1);
1632
1633 /* drive MDC high causing the data bit to be latched */
1634 dev->MEAR_cache |= MEAR_MDC;
1635 writel(dev->MEAR_cache, dev->base + MEAR);
1636 readl(dev->base + MEAR);
1637
1638 /* Wait again... */
1639 udelay(1);
1640 }
1641
1642 static int ns83820_mii_read_bit(struct ns83820 *dev)
1643 {
1644 int bit;
1645
1646 /* drive MDC low, disable output */
1647 dev->MEAR_cache &= ~MEAR_MDC;
1648 dev->MEAR_cache &= ~MEAR_MDDIR;
1649 writel(dev->MEAR_cache, dev->base + MEAR);
1650 readl(dev->base + MEAR);
1651
1652 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1653 udelay(1);
1654
1655 /* drive MDC high causing the data bit to be latched */
1656 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1657 dev->MEAR_cache |= MEAR_MDC;
1658 writel(dev->MEAR_cache, dev->base + MEAR);
1659
1660 /* Wait again... */
1661 udelay(1);
1662
1663 return bit;
1664 }
1665
1666 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1667 {
1668 unsigned data = 0;
1669 int i;
1670
1671 /* read some garbage so that we eventually sync up */
1672 for (i=0; i<64; i++)
1673 ns83820_mii_read_bit(dev);
1674
1675 ns83820_mii_write_bit(dev, 0); /* start */
1676 ns83820_mii_write_bit(dev, 1);
1677 ns83820_mii_write_bit(dev, 1); /* opcode read */
1678 ns83820_mii_write_bit(dev, 0);
1679
1680 /* write out the phy address: 5 bits, msb first */
1681 for (i=0; i<5; i++)
1682 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1683
1684 /* write out the register address, 5 bits, msb first */
1685 for (i=0; i<5; i++)
1686 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1687
1688 ns83820_mii_read_bit(dev); /* turn around cycles */
1689 ns83820_mii_read_bit(dev);
1690
1691 /* read in the register data, 16 bits msb first */
1692 for (i=0; i<16; i++) {
1693 data <<= 1;
1694 data |= ns83820_mii_read_bit(dev);
1695 }
1696
1697 return data;
1698 }
1699
1700 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1701 {
1702 int i;
1703
1704 /* read some garbage so that we eventually sync up */
1705 for (i=0; i<64; i++)
1706 ns83820_mii_read_bit(dev);
1707
1708 ns83820_mii_write_bit(dev, 0); /* start */
1709 ns83820_mii_write_bit(dev, 1);
1710 ns83820_mii_write_bit(dev, 0); /* opcode read */
1711 ns83820_mii_write_bit(dev, 1);
1712
1713 /* write out the phy address: 5 bits, msb first */
1714 for (i=0; i<5; i++)
1715 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1716
1717 /* write out the register address, 5 bits, msb first */
1718 for (i=0; i<5; i++)
1719 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1720
1721 ns83820_mii_read_bit(dev); /* turn around cycles */
1722 ns83820_mii_read_bit(dev);
1723
1724 /* read in the register data, 16 bits msb first */
1725 for (i=0; i<16; i++)
1726 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1727
1728 return data;
1729 }
1730
1731 static void ns83820_probe_phy(struct net_device *ndev)
1732 {
1733 struct ns83820 *dev = PRIV(ndev);
1734 static int first;
1735 int i;
1736 #define MII_PHYIDR1 0x02
1737 #define MII_PHYIDR2 0x03
1738
1739 #if 0
1740 if (!first) {
1741 unsigned tmp;
1742 ns83820_mii_read_reg(dev, 1, 0x09);
1743 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1744
1745 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1746 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1747 udelay(1300);
1748 ns83820_mii_read_reg(dev, 1, 0x09);
1749 }
1750 #endif
1751 first = 1;
1752
1753 for (i=1; i<2; i++) {
1754 int j;
1755 unsigned a, b;
1756 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1757 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1758
1759 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1760 // ndev->name, i, a, b);
1761
1762 for (j=0; j<0x16; j+=4) {
1763 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1764 ndev->name, j,
1765 ns83820_mii_read_reg(dev, i, 0 + j),
1766 ns83820_mii_read_reg(dev, i, 1 + j),
1767 ns83820_mii_read_reg(dev, i, 2 + j),
1768 ns83820_mii_read_reg(dev, i, 3 + j)
1769 );
1770 }
1771 }
1772 {
1773 unsigned a, b;
1774 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1775 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1776 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1777 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1778
1779 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1780 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1781 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1782 dprintk("version: 0x%04x 0x%04x\n", a, b);
1783 }
1784 }
1785 #endif
1786
1787 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1788 {
1789 struct net_device *ndev;
1790 struct ns83820 *dev;
1791 long addr;
1792 int err;
1793 int using_dac = 0;
1794
1795 /* See if we can set the dma mask early on; failure is fatal. */
1796 if (TRY_DAC && !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) {
1797 using_dac = 1;
1798 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) {
1799 using_dac = 0;
1800 } else {
1801 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n");
1802 return -ENODEV;
1803 }
1804
1805 ndev = alloc_etherdev(sizeof(struct ns83820));
1806 dev = PRIV(ndev);
1807 err = -ENOMEM;
1808 if (!dev)
1809 goto out;
1810
1811 spin_lock_init(&dev->rx_info.lock);
1812 spin_lock_init(&dev->tx_lock);
1813 spin_lock_init(&dev->misc_lock);
1814 dev->pci_dev = pci_dev;
1815
1816 dev->ee.cache = &dev->MEAR_cache;
1817 dev->ee.lock = &dev->misc_lock;
1818 SET_MODULE_OWNER(ndev);
1819 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1820
1821 INIT_WORK(&dev->tq_refill, queue_refill, ndev);
1822 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1823
1824 err = pci_enable_device(pci_dev);
1825 if (err) {
1826 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err);
1827 goto out_free;
1828 }
1829
1830 pci_set_master(pci_dev);
1831 addr = pci_resource_start(pci_dev, 1);
1832 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1833 dev->tx_descs = pci_alloc_consistent(pci_dev,
1834 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1835 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1836 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1837 err = -ENOMEM;
1838 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1839 goto out_disable;
1840
1841 dprintk("%p: %08lx %p: %08lx\n",
1842 dev->tx_descs, (long)dev->tx_phy_descs,
1843 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1844
1845 /* disable interrupts */
1846 writel(0, dev->base + IMR);
1847 writel(0, dev->base + IER);
1848 readl(dev->base + IER);
1849
1850 dev->IMR_cache = 0;
1851
1852 setup_ee_mem_bitbanger(&dev->ee, (long)dev->base + MEAR, 3, 2, 1, 0,
1853 0);
1854
1855 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
1856 DRV_NAME, ndev);
1857 if (err) {
1858 printk(KERN_INFO "ns83820: unable to register irq %d\n",
1859 pci_dev->irq);
1860 goto out_disable;
1861 }
1862
1863 /*
1864 * FIXME: we are holding rtnl_lock() over obscenely long area only
1865 * because some of the setup code uses dev->name. It's Wrong(tm) -
1866 * we should be using driver-specific names for all that stuff.
1867 * For now that will do, but we really need to come back and kill
1868 * most of the dev_alloc_name() users later.
1869 */
1870 rtnl_lock();
1871 err = dev_alloc_name(ndev, ndev->name);
1872 if (err < 0) {
1873 printk(KERN_INFO "ns83820: unable to get netdev name: %d\n", err);
1874 goto out_free_irq;
1875 }
1876
1877 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1878 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1879 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1880
1881 ndev->open = ns83820_open;
1882 ndev->stop = ns83820_stop;
1883 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1884 ndev->get_stats = ns83820_get_stats;
1885 ndev->change_mtu = ns83820_change_mtu;
1886 ndev->set_multicast_list = ns83820_set_multicast;
1887 ndev->do_ioctl = ns83820_ioctl;
1888 ndev->tx_timeout = ns83820_tx_timeout;
1889 ndev->watchdog_timeo = 5 * HZ;
1890
1891 pci_set_drvdata(pci_dev, ndev);
1892
1893 ns83820_do_reset(dev, CR_RST);
1894
1895 /* Must reset the ram bist before running it */
1896 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1897 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1898 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1899 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1900 PTSCR_EEBIST_FAIL);
1901 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1902
1903 /* I love config registers */
1904 dev->CFG_cache = readl(dev->base + CFG);
1905
1906 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1907 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1908 ndev->name);
1909 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1910 if (!(dev->CFG_cache & CFG_DATA64_EN))
1911 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1912 ndev->name);
1913 } else
1914 dev->CFG_cache &= ~(CFG_DATA64_EN);
1915
1916 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1917 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1918 CFG_M64ADDR);
1919 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1920 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1921 dev->CFG_cache |= CFG_REQALG;
1922 dev->CFG_cache |= CFG_POW;
1923 dev->CFG_cache |= CFG_TMRTEST;
1924
1925 /* When compiled with 64 bit addressing, we must always enable
1926 * the 64 bit descriptor format.
1927 */
1928 #ifdef USE_64BIT_ADDR
1929 dev->CFG_cache |= CFG_M64ADDR;
1930 #endif
1931 if (using_dac)
1932 dev->CFG_cache |= CFG_T64ADDR;
1933
1934 /* Big endian mode does not seem to do what the docs suggest */
1935 dev->CFG_cache &= ~CFG_BEM;
1936
1937 /* setup optical transceiver if we have one */
1938 if (dev->CFG_cache & CFG_TBI_EN) {
1939 printk(KERN_INFO "%s: enabling optical transceiver\n",
1940 ndev->name);
1941 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1942
1943 /* setup auto negotiation feature advertisement */
1944 writel(readl(dev->base + TANAR)
1945 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1946 dev->base + TANAR);
1947
1948 /* start auto negotiation */
1949 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1950 dev->base + TBICR);
1951 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1952 dev->linkstate = LINK_AUTONEGOTIATE;
1953
1954 dev->CFG_cache |= CFG_MODE_1000;
1955 }
1956
1957 writel(dev->CFG_cache, dev->base + CFG);
1958 dprintk("CFG: %08x\n", dev->CFG_cache);
1959
1960 if (reset_phy) {
1961 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1962 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1963 set_current_state(TASK_UNINTERRUPTIBLE);
1964 schedule_timeout((HZ+99)/100);
1965 writel(dev->CFG_cache, dev->base + CFG);
1966 }
1967
1968 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1969 * the PCI layer. FIXME.
1970 */
1971 if (readl(dev->base + SRR))
1972 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
1973 #endif
1974
1975 /* Note! The DMA burst size interacts with packet
1976 * transmission, such that the largest packet that
1977 * can be transmitted is 8192 - FLTH - burst size.
1978 * If only the transmit fifo was larger...
1979 */
1980 /* Ramit : 1024 DMA is not a good idea, it ends up banging
1981 * some DELL and COMPAQ SMP systems */
1982 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
1983 | ((1600 / 32) * 0x100),
1984 dev->base + TXCFG);
1985
1986 /* Flush the interrupt holdoff timer */
1987 writel(0x000, dev->base + IHR);
1988 writel(0x100, dev->base + IHR);
1989 writel(0x000, dev->base + IHR);
1990
1991 /* Set Rx to full duplex, don't accept runt, errored, long or length
1992 * range errored packets. Use 512 byte DMA.
1993 */
1994 /* Ramit : 1024 DMA is not a good idea, it ends up banging
1995 * some DELL and COMPAQ SMP systems
1996 * Turn on ALP, only we are accpeting Jumbo Packets */
1997 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
1998 | RXCFG_STRIPCRC
1999 //| RXCFG_ALP
2000 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2001
2002 /* Disable priority queueing */
2003 writel(0, dev->base + PQCR);
2004
2005 /* Enable IP checksum validation and detetion of VLAN headers.
2006 * Note: do not set the reject options as at least the 0x102
2007 * revision of the chip does not properly accept IP fragments
2008 * at least for UDP.
2009 */
2010 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2011 * the MAC it calculates the packetsize AFTER stripping the VLAN
2012 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2013 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2014 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2015 * it discrards it!. These guys......
2016 */
2017 writel(VRCR_IPEN | VRCR_VTDEN, dev->base + VRCR);
2018
2019 /* Enable per-packet TCP/UDP/IP checksumming */
2020 writel(VTCR_PPCHK, dev->base + VTCR);
2021
2022 /* Ramit : Enable async and sync pause frames */
2023 /* writel(0, dev->base + PCR); */
2024 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2025 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2026 dev->base + PCR);
2027
2028 /* Disable Wake On Lan */
2029 writel(0, dev->base + WCSR);
2030
2031 ns83820_getmac(dev, ndev->dev_addr);
2032
2033 /* Yes, we support dumb IP checksum on transmit */
2034 ndev->features |= NETIF_F_SG;
2035 ndev->features |= NETIF_F_IP_CSUM;
2036
2037 if (using_dac) {
2038 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2039 ndev->name);
2040 ndev->features |= NETIF_F_HIGHDMA;
2041 }
2042
2043 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2044 ndev->name,
2045 (unsigned)readl(dev->base + SRR) >> 8,
2046 (unsigned)readl(dev->base + SRR) & 0xff,
2047 ndev->dev_addr[0], ndev->dev_addr[1],
2048 ndev->dev_addr[2], ndev->dev_addr[3],
2049 ndev->dev_addr[4], ndev->dev_addr[5],
2050 addr, pci_dev->irq,
2051 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2052 );
2053
2054 #ifdef PHY_CODE_IS_FINISHED
2055 ns83820_probe_phy(ndev);
2056 #endif
2057
2058 err = register_netdevice(ndev);
2059 if (err) {
2060 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2061 goto out_cleanup;
2062 }
2063 rtnl_unlock();
2064
2065 return 0;
2066
2067 out_cleanup:
2068 writel(0, dev->base + IMR); /* paranoia */
2069 writel(0, dev->base + IER);
2070 readl(dev->base + IER);
2071 out_free_irq:
2072 rtnl_unlock();
2073 free_irq(pci_dev->irq, ndev);
2074 out_disable:
2075 if (dev->base)
2076 iounmap(dev->base);
2077 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2078 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2079 pci_disable_device(pci_dev);
2080 out_free:
2081 free_netdev(ndev);
2082 pci_set_drvdata(pci_dev, NULL);
2083 out:
2084 return err;
2085 }
2086
2087 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2088 {
2089 struct net_device *ndev = pci_get_drvdata(pci_dev);
2090 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2091
2092 if (!ndev) /* paranoia */
2093 return;
2094
2095 writel(0, dev->base + IMR); /* paranoia */
2096 writel(0, dev->base + IER);
2097 readl(dev->base + IER);
2098
2099 unregister_netdev(ndev);
2100 free_irq(dev->pci_dev->irq, ndev);
2101 iounmap(dev->base);
2102 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2103 dev->tx_descs, dev->tx_phy_descs);
2104 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2105 dev->rx_info.descs, dev->rx_info.phy_descs);
2106 pci_disable_device(dev->pci_dev);
2107 free_netdev(ndev);
2108 pci_set_drvdata(pci_dev, NULL);
2109 }
2110
2111 static struct pci_device_id ns83820_pci_tbl[] = {
2112 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2113 { 0, },
2114 };
2115
2116 static struct pci_driver driver = {
2117 .name = "ns83820",
2118 .id_table = ns83820_pci_tbl,
2119 .probe = ns83820_init_one,
2120 .remove = __devexit_p(ns83820_remove_one),
2121 #if 0 /* FIXME: implement */
2122 .suspend = ,
2123 .resume = ,
2124 #endif
2125 };
2126
2127
2128 static int __init ns83820_init(void)
2129 {
2130 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2131 return pci_module_init(&driver);
2132 }
2133
2134 static void __exit ns83820_exit(void)
2135 {
2136 pci_unregister_driver(&driver);
2137 }
2138
2139 MODULE_AUTHOR("Benjamin LaHaise <bcrl@redhat.com>");
2140 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2141 MODULE_LICENSE("GPL");
2142
2143 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2144
2145 MODULE_PARM(lnksts, "i");
2146 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2147
2148 MODULE_PARM(ihr, "i");
2149 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2150
2151 MODULE_PARM(reset_phy, "i");
2152 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2153
2154 module_init(ns83820_init);
2155 module_exit(ns83820_exit);
MOXA 2.6.9 from sdlinux-moxaart.tgz