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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / e100.c
bloba39b58c8102e8a135e3bcbc7ae03894269c61b6b
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
135 */
136
137 #include <linux/config.h>
138 #include <linux/module.h>
139 #include <linux/moduleparam.h>
140 #include <linux/kernel.h>
141 #include <linux/types.h>
142 #include <linux/slab.h>
143 #include <linux/delay.h>
144 #include <linux/init.h>
145 #include <linux/pci.h>
146 #include <linux/netdevice.h>
147 #include <linux/etherdevice.h>
148 #include <linux/mii.h>
149 #include <linux/if_vlan.h>
150 #include <linux/skbuff.h>
151 #include <linux/ethtool.h>
152 #include <linux/string.h>
153 #include <asm/unaligned.h>
154
155
156 #define DRV_NAME "e100"
157 #define DRV_EXT "-NAPI"
158 #define DRV_VERSION "3.0.27-k2"DRV_EXT
159 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
160 #define DRV_COPYRIGHT "Copyright(c) 1999-2004 Intel Corporation"
161 #define PFX DRV_NAME ": "
162
163 #define E100_WATCHDOG_PERIOD (2 * HZ)
164 #define E100_NAPI_WEIGHT 16
165
166 MODULE_DESCRIPTION(DRV_DESCRIPTION);
167 MODULE_AUTHOR(DRV_COPYRIGHT);
168 MODULE_LICENSE("GPL");
169
170 static int debug = 3;
171 module_param(debug, int, 0);
172 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
173 #define DPRINTK(nlevel, klevel, fmt, args...) \
174 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
175 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
176 __FUNCTION__ , ## args))
177
178 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
179 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
180 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
181 static struct pci_device_id e100_id_table[] = {
182 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
183 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
184 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
185 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
186 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
190 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
191 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
196 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
197 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
204 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
205 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
206 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
215 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
216 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
217 { 0, }
218 };
219 MODULE_DEVICE_TABLE(pci, e100_id_table);
220
221 enum mac {
222 mac_82557_D100_A = 0,
223 mac_82557_D100_B = 1,
224 mac_82557_D100_C = 2,
225 mac_82558_D101_A4 = 4,
226 mac_82558_D101_B0 = 5,
227 mac_82559_D101M = 8,
228 mac_82559_D101S = 9,
229 mac_82550_D102 = 12,
230 mac_82550_D102_C = 13,
231 mac_82551_E = 14,
232 mac_82551_F = 15,
233 mac_82551_10 = 16,
234 mac_unknown = 0xFF,
235 };
236
237 enum phy {
238 phy_100a = 0x000003E0,
239 phy_100c = 0x035002A8,
240 phy_82555_tx = 0x015002A8,
241 phy_nsc_tx = 0x5C002000,
242 phy_82562_et = 0x033002A8,
243 phy_82562_em = 0x032002A8,
244 phy_82562_ek = 0x031002A8,
245 phy_82562_eh = 0x017002A8,
246 phy_unknown = 0xFFFFFFFF,
247 };
248
249 /* CSR (Control/Status Registers) */
250 struct csr {
251 struct {
252 u8 status;
253 u8 stat_ack;
254 u8 cmd_lo;
255 u8 cmd_hi;
256 u32 gen_ptr;
257 } scb;
258 u32 port;
259 u16 flash_ctrl;
260 u8 eeprom_ctrl_lo;
261 u8 eeprom_ctrl_hi;
262 u32 mdi_ctrl;
263 u32 rx_dma_count;
264 };
265
266 enum scb_status {
267 rus_ready = 0x10,
268 rus_mask = 0x3C,
269 };
270
271 enum scb_stat_ack {
272 stat_ack_not_ours = 0x00,
273 stat_ack_sw_gen = 0x04,
274 stat_ack_rnr = 0x10,
275 stat_ack_cu_idle = 0x20,
276 stat_ack_frame_rx = 0x40,
277 stat_ack_cu_cmd_done = 0x80,
278 stat_ack_not_present = 0xFF,
279 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
280 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
281 };
282
283 enum scb_cmd_hi {
284 irq_mask_none = 0x00,
285 irq_mask_all = 0x01,
286 irq_sw_gen = 0x02,
287 };
288
289 enum scb_cmd_lo {
290 cuc_nop = 0x00,
291 ruc_start = 0x01,
292 ruc_load_base = 0x06,
293 cuc_start = 0x10,
294 cuc_resume = 0x20,
295 cuc_dump_addr = 0x40,
296 cuc_dump_stats = 0x50,
297 cuc_load_base = 0x60,
298 cuc_dump_reset = 0x70,
299 };
300
301 enum cuc_dump {
302 cuc_dump_complete = 0x0000A005,
303 cuc_dump_reset_complete = 0x0000A007,
304 };
305
306 enum port {
307 software_reset = 0x0000,
308 selftest = 0x0001,
309 selective_reset = 0x0002,
310 };
311
312 enum eeprom_ctrl_lo {
313 eesk = 0x01,
314 eecs = 0x02,
315 eedi = 0x04,
316 eedo = 0x08,
317 };
318
319 enum mdi_ctrl {
320 mdi_write = 0x04000000,
321 mdi_read = 0x08000000,
322 mdi_ready = 0x10000000,
323 };
324
325 enum eeprom_op {
326 op_write = 0x05,
327 op_read = 0x06,
328 op_ewds = 0x10,
329 op_ewen = 0x13,
330 };
331
332 enum eeprom_offsets {
333 eeprom_cnfg_mdix = 0x03,
334 eeprom_id = 0x0A,
335 eeprom_config_asf = 0x0D,
336 eeprom_smbus_addr = 0x90,
337 };
338
339 enum eeprom_cnfg_mdix {
340 eeprom_mdix_enabled = 0x0080,
341 };
342
343 enum eeprom_id {
344 eeprom_id_wol = 0x0020,
345 };
346
347 enum eeprom_config_asf {
348 eeprom_asf = 0x8000,
349 eeprom_gcl = 0x4000,
350 };
351
352 enum cb_status {
353 cb_complete = 0x8000,
354 cb_ok = 0x2000,
355 };
356
357 enum cb_command {
358 cb_nop = 0x0000,
359 cb_iaaddr = 0x0001,
360 cb_config = 0x0002,
361 cb_multi = 0x0003,
362 cb_tx = 0x0004,
363 cb_ucode = 0x0005,
364 cb_dump = 0x0006,
365 cb_tx_sf = 0x0008,
366 cb_cid = 0x1f00,
367 cb_i = 0x2000,
368 cb_s = 0x4000,
369 cb_el = 0x8000,
370 };
371
372 struct rfd {
373 u16 status;
374 u16 command;
375 u32 link;
376 u32 rbd;
377 u16 actual_size;
378 u16 size;
379 };
380
381 struct rx {
382 struct rx *next, *prev;
383 struct sk_buff *skb;
384 dma_addr_t dma_addr;
385 };
386
387 #if defined(__BIG_ENDIAN_BITFIELD)
388 #define X(a,b) b,a
389 #else
390 #define X(a,b) a,b
391 #endif
392 struct config {
393 /*0*/ u8 X(byte_count:6, pad0:2);
394 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
395 /*2*/ u8 adaptive_ifs;
396 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
397 term_write_cache_line:1), pad3:4);
398 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
399 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
400 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
401 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
402 rx_discard_overruns:1), rx_save_bad_frames:1);
403 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
404 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
405 tx_dynamic_tbd:1);
406 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
407 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
408 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
409 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
410 loopback:2);
411 /*11*/ u8 X(linear_priority:3, pad11:5);
412 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
413 /*13*/ u8 ip_addr_lo;
414 /*14*/ u8 ip_addr_hi;
415 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
416 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
417 pad15_2:1), crs_or_cdt:1);
418 /*16*/ u8 fc_delay_lo;
419 /*17*/ u8 fc_delay_hi;
420 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
421 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
422 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
423 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
424 full_duplex_force:1), full_duplex_pin:1);
425 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
426 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
427 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
428 u8 pad_d102[9];
429 };
430
431 #define E100_MAX_MULTICAST_ADDRS 64
432 struct multi {
433 u16 count;
434 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
435 };
436
437 /* Important: keep total struct u32-aligned */
438 #define UCODE_SIZE 134
439 struct cb {
440 u16 status;
441 u16 command;
442 u32 link;
443 union {
444 u8 iaaddr[ETH_ALEN];
445 u32 ucode[UCODE_SIZE];
446 struct config config;
447 struct multi multi;
448 struct {
449 u32 tbd_array;
450 u16 tcb_byte_count;
451 u8 threshold;
452 u8 tbd_count;
453 struct {
454 u32 buf_addr;
455 u16 size;
456 u16 eol;
457 } tbd;
458 } tcb;
459 u32 dump_buffer_addr;
460 } u;
461 struct cb *next, *prev;
462 dma_addr_t dma_addr;
463 struct sk_buff *skb;
464 };
465
466 enum loopback {
467 lb_none = 0, lb_mac = 1, lb_phy = 3,
468 };
469
470 struct stats {
471 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
472 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
473 tx_multiple_collisions, tx_total_collisions;
474 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
475 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
476 rx_short_frame_errors;
477 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
478 u16 xmt_tco_frames, rcv_tco_frames;
479 u32 complete;
480 };
481
482 struct mem {
483 struct {
484 u32 signature;
485 u32 result;
486 } selftest;
487 struct stats stats;
488 u8 dump_buf[596];
489 };
490
491 struct param_range {
492 u32 min;
493 u32 max;
494 u32 count;
495 };
496
497 struct params {
498 struct param_range rfds;
499 struct param_range cbs;
500 };
501
502 struct nic {
503 /* Begin: frequently used values: keep adjacent for cache effect */
504 u32 msg_enable ____cacheline_aligned;
505 struct net_device *netdev;
506 struct pci_dev *pdev;
507
508 struct rx *rxs ____cacheline_aligned;
509 struct rx *rx_to_use;
510 struct rx *rx_to_clean;
511 struct rfd blank_rfd;
512 int ru_running;
513
514 spinlock_t cb_lock ____cacheline_aligned;
515 spinlock_t cmd_lock;
516 struct csr *csr;
517 enum scb_cmd_lo cuc_cmd;
518 unsigned int cbs_avail;
519 struct cb *cbs;
520 struct cb *cb_to_use;
521 struct cb *cb_to_send;
522 struct cb *cb_to_clean;
523 u16 tx_command;
524 /* End: frequently used values: keep adjacent for cache effect */
525
526 enum {
527 ich = (1 << 0),
528 promiscuous = (1 << 1),
529 multicast_all = (1 << 2),
530 wol_magic = (1 << 3),
531 ich_10h_workaround = (1 << 4),
532 } flags ____cacheline_aligned;
533
534 enum mac mac;
535 enum phy phy;
536 struct params params;
537 struct net_device_stats net_stats;
538 struct timer_list watchdog;
539 struct timer_list blink_timer;
540 struct mii_if_info mii;
541 enum loopback loopback;
542
543 struct mem *mem;
544 dma_addr_t dma_addr;
545
546 dma_addr_t cbs_dma_addr;
547 u8 adaptive_ifs;
548 u8 tx_threshold;
549 u32 tx_frames;
550 u32 tx_collisions;
551 u32 tx_deferred;
552 u32 tx_single_collisions;
553 u32 tx_multiple_collisions;
554 u32 tx_fc_pause;
555 u32 tx_tco_frames;
556
557 u32 rx_fc_pause;
558 u32 rx_fc_unsupported;
559 u32 rx_tco_frames;
560 u32 rx_over_length_errors;
561
562 u8 rev_id;
563 u16 leds;
564 u16 eeprom_wc;
565 u16 eeprom[256];
566 u32 pm_state[16];
567 };
568
569 static inline void e100_write_flush(struct nic *nic)
570 {
571 /* Flush previous PCI writes through intermediate bridges
572 * by doing a benign read */
573 (void)readb(&nic->csr->scb.status);
574 }
575
576 static inline void e100_enable_irq(struct nic *nic)
577 {
578 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
579 e100_write_flush(nic);
580 }
581
582 static inline void e100_disable_irq(struct nic *nic)
583 {
584 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
585 e100_write_flush(nic);
586 }
587
588 static void e100_hw_reset(struct nic *nic)
589 {
590 /* Put CU and RU into idle with a selective reset to get
591 * device off of PCI bus */
592 writel(selective_reset, &nic->csr->port);
593 e100_write_flush(nic); udelay(20);
594
595 /* Now fully reset device */
596 writel(software_reset, &nic->csr->port);
597 e100_write_flush(nic); udelay(20);
598
599 /* TCO workaround - 82559 and greater */
600 if(nic->mac >= mac_82559_D101M) {
601 /* Issue a redundant CU load base without setting
602 * general pointer, and without waiting for scb to
603 * clear. This gets us into post-driver. Finally,
604 * wait 20 msec for reset to take effect. */
605 writeb(cuc_load_base, &nic->csr->scb.cmd_lo);
606 mdelay(20);
607 }
608
609 /* Mask off our interrupt line - it's unmasked after reset */
610 e100_disable_irq(nic);
611 }
612
613 static int e100_self_test(struct nic *nic)
614 {
615 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
616
617 /* Passing the self-test is a pretty good indication
618 * that the device can DMA to/from host memory */
619
620 nic->mem->selftest.signature = 0;
621 nic->mem->selftest.result = 0xFFFFFFFF;
622
623 writel(selftest | dma_addr, &nic->csr->port);
624 e100_write_flush(nic);
625 /* Wait 10 msec for self-test to complete */
626 set_current_state(TASK_UNINTERRUPTIBLE);
627 schedule_timeout(HZ / 100 + 1);
628
629 /* Interrupts are enabled after self-test */
630 e100_disable_irq(nic);
631
632 /* Check results of self-test */
633 if(nic->mem->selftest.result != 0) {
634 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
635 nic->mem->selftest.result);
636 return -ETIMEDOUT;
637 }
638 if(nic->mem->selftest.signature == 0) {
639 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
640 return -ETIMEDOUT;
641 }
642
643 return 0;
644 }
645
646 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
647 {
648 u32 cmd_addr_data[3];
649 u8 ctrl;
650 int i, j;
651
652 /* Three cmds: write/erase enable, write data, write/erase disable */
653 cmd_addr_data[0] = op_ewen << (addr_len - 2);
654 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
655 cpu_to_le16(data);
656 cmd_addr_data[2] = op_ewds << (addr_len - 2);
657
658 /* Bit-bang cmds to write word to eeprom */
659 for(j = 0; j < 3; j++) {
660
661 /* Chip select */
662 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
663 e100_write_flush(nic); udelay(4);
664
665 for(i = 31; i >= 0; i--) {
666 ctrl = (cmd_addr_data[j] & (1 << i)) ?
667 eecs | eedi : eecs;
668 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
669 e100_write_flush(nic); udelay(4);
670
671 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
672 e100_write_flush(nic); udelay(4);
673 }
674 /* Wait 10 msec for cmd to complete */
675 set_current_state(TASK_UNINTERRUPTIBLE);
676 schedule_timeout(HZ / 100 + 1);
677
678 /* Chip deselect */
679 writeb(0, &nic->csr->eeprom_ctrl_lo);
680 e100_write_flush(nic); udelay(4);
681 }
682 };
683
684 /* General technique stolen from the eepro100 driver - very clever */
685 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
686 {
687 u32 cmd_addr_data;
688 u16 data = 0;
689 u8 ctrl;
690 int i;
691
692 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
693
694 /* Chip select */
695 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
696 e100_write_flush(nic); udelay(4);
697
698 /* Bit-bang to read word from eeprom */
699 for(i = 31; i >= 0; i--) {
700 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
701 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
702 e100_write_flush(nic); udelay(4);
703
704 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
705 e100_write_flush(nic); udelay(4);
706
707 /* Eeprom drives a dummy zero to EEDO after receiving
708 * complete address. Use this to adjust addr_len. */
709 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
710 if(!(ctrl & eedo) && i > 16) {
711 *addr_len -= (i - 16);
712 i = 17;
713 }
714
715 data = (data << 1) | (ctrl & eedo ? 1 : 0);
716 }
717
718 /* Chip deselect */
719 writeb(0, &nic->csr->eeprom_ctrl_lo);
720 e100_write_flush(nic); udelay(4);
721
722 return le16_to_cpu(data);
723 };
724
725 /* Load entire EEPROM image into driver cache and validate checksum */
726 static int e100_eeprom_load(struct nic *nic)
727 {
728 u16 addr, addr_len = 8, checksum = 0;
729
730 /* Try reading with an 8-bit addr len to discover actual addr len */
731 e100_eeprom_read(nic, &addr_len, 0);
732 nic->eeprom_wc = 1 << addr_len;
733
734 for(addr = 0; addr < nic->eeprom_wc; addr++) {
735 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
736 if(addr < nic->eeprom_wc - 1)
737 checksum += cpu_to_le16(nic->eeprom[addr]);
738 }
739
740 /* The checksum, stored in the last word, is calculated such that
741 * the sum of words should be 0xBABA */
742 checksum = le16_to_cpu(0xBABA - checksum);
743 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
744 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
745 return -EAGAIN;
746 }
747
748 return 0;
749 }
750
751 /* Save (portion of) driver EEPROM cache to device and update checksum */
752 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
753 {
754 u16 addr, addr_len = 8, checksum = 0;
755
756 /* Try reading with an 8-bit addr len to discover actual addr len */
757 e100_eeprom_read(nic, &addr_len, 0);
758 nic->eeprom_wc = 1 << addr_len;
759
760 if(start + count >= nic->eeprom_wc)
761 return -EINVAL;
762
763 for(addr = start; addr < start + count; addr++)
764 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
765
766 /* The checksum, stored in the last word, is calculated such that
767 * the sum of words should be 0xBABA */
768 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
769 checksum += cpu_to_le16(nic->eeprom[addr]);
770 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
771 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
772 nic->eeprom[nic->eeprom_wc - 1]);
773
774 return 0;
775 }
776
777 #define E100_WAIT_SCB_TIMEOUT 40
778 static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
779 {
780 unsigned long flags;
781 unsigned int i;
782 int err = 0;
783
784 spin_lock_irqsave(&nic->cmd_lock, flags);
785
786 /* Previous command is accepted when SCB clears */
787 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
788 if(likely(!readb(&nic->csr->scb.cmd_lo)))
789 break;
790 cpu_relax();
791 if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
792 udelay(5);
793 }
794 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
795 err = -EAGAIN;
796 goto err_unlock;
797 }
798
799 if(unlikely(cmd != cuc_resume))
800 writel(dma_addr, &nic->csr->scb.gen_ptr);
801 writeb(cmd, &nic->csr->scb.cmd_lo);
802
803 err_unlock:
804 spin_unlock_irqrestore(&nic->cmd_lock, flags);
805
806 return err;
807 }
808
809 static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
810 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
811 {
812 struct cb *cb;
813 unsigned long flags;
814 int err = 0;
815
816 spin_lock_irqsave(&nic->cb_lock, flags);
817
818 if(unlikely(!nic->cbs_avail)) {
819 err = -ENOMEM;
820 goto err_unlock;
821 }
822
823 cb = nic->cb_to_use;
824 nic->cb_to_use = cb->next;
825 nic->cbs_avail--;
826 cb->skb = skb;
827
828 if(unlikely(!nic->cbs_avail))
829 err = -ENOSPC;
830
831 cb_prepare(nic, cb, skb);
832
833 /* Order is important otherwise we'll be in a race with h/w:
834 * set S-bit in current first, then clear S-bit in previous. */
835 cb->command |= cpu_to_le16(cb_s);
836 wmb();
837 cb->prev->command &= cpu_to_le16(~cb_s);
838
839 while(nic->cb_to_send != nic->cb_to_use) {
840 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
841 nic->cb_to_send->dma_addr))) {
842 /* Ok, here's where things get sticky. It's
843 * possible that we can't schedule the command
844 * because the controller is too busy, so
845 * let's just queue the command and try again
846 * when another command is scheduled. */
847 break;
848 } else {
849 nic->cuc_cmd = cuc_resume;
850 nic->cb_to_send = nic->cb_to_send->next;
851 }
852 }
853
854 err_unlock:
855 spin_unlock_irqrestore(&nic->cb_lock, flags);
856
857 return err;
858 }
859
860 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
861 {
862 u32 data_out = 0;
863 unsigned int i;
864
865 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
866
867 for(i = 0; i < 100; i++) {
868 udelay(20);
869 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
870 break;
871 }
872
873 DPRINTK(HW, DEBUG,
874 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
875 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
876 return (u16)data_out;
877 }
878
879 static int mdio_read(struct net_device *netdev, int addr, int reg)
880 {
881 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
882 }
883
884 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
885 {
886 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
887 }
888
889 static void e100_get_defaults(struct nic *nic)
890 {
891 struct param_range rfds = { .min = 64, .max = 256, .count = 64 };
892 struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
893
894 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
895 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
896 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
897 if(nic->mac == mac_unknown)
898 nic->mac = mac_82557_D100_A;
899
900 nic->params.rfds = rfds;
901 nic->params.cbs = cbs;
902
903 /* Quadwords to DMA into FIFO before starting frame transmit */
904 nic->tx_threshold = 0xE0;
905
906 nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf |
907 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0));
908
909 /* Template for a freshly allocated RFD */
910 nic->blank_rfd.command = cpu_to_le16(cb_el);
911 nic->blank_rfd.rbd = 0xFFFFFFFF;
912 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
913
914 /* MII setup */
915 nic->mii.phy_id_mask = 0x1F;
916 nic->mii.reg_num_mask = 0x1F;
917 nic->mii.dev = nic->netdev;
918 nic->mii.mdio_read = mdio_read;
919 nic->mii.mdio_write = mdio_write;
920 }
921
922 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
923 {
924 struct config *config = &cb->u.config;
925 u8 *c = (u8 *)config;
926
927 cb->command = cpu_to_le16(cb_config);
928
929 memset(config, 0, sizeof(struct config));
930
931 config->byte_count = 0x16; /* bytes in this struct */
932 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
933 config->direct_rx_dma = 0x1; /* reserved */
934 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
935 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
936 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
937 config->tx_underrun_retry = 0x3; /* # of underrun retries */
938 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
939 config->pad10 = 0x6;
940 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
941 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
942 config->ifs = 0x6; /* x16 = inter frame spacing */
943 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
944 config->pad15_1 = 0x1;
945 config->pad15_2 = 0x1;
946 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
947 config->fc_delay_hi = 0x40; /* time delay for fc frame */
948 config->tx_padding = 0x1; /* 1=pad short frames */
949 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
950 config->pad18 = 0x1;
951 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
952 config->pad20_1 = 0x1F;
953 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
954 config->pad21_1 = 0x5;
955
956 config->adaptive_ifs = nic->adaptive_ifs;
957 config->loopback = nic->loopback;
958
959 if(nic->mii.force_media && nic->mii.full_duplex)
960 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
961
962 if(nic->flags & promiscuous || nic->loopback) {
963 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
964 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
965 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
966 }
967
968 if(nic->flags & multicast_all)
969 config->multicast_all = 0x1; /* 1=accept, 0=no */
970
971 if(!(nic->flags & wol_magic))
972 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
973
974 if(nic->mac >= mac_82558_D101_A4) {
975 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
976 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
977 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
978 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
979 if(nic->mac >= mac_82559_D101M)
980 config->tno_intr = 0x1; /* TCO stats enable */
981 else
982 config->standard_stat_counter = 0x0;
983 }
984
985 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
986 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
987 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
988 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
989 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
990 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
991 }
992
993 static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
994 {
995 int i;
996 static const u32 ucode[UCODE_SIZE] = {
997 /* NFS packets are misinterpreted as TCO packets and
998 * incorrectly routed to the BMC over SMBus. This
999 * microcode patch checks the fragmented IP bit in the
1000 * NFS/UDP header to distinguish between NFS and TCO. */
1001 0x0EF70E36, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF,
1002 0x1FFF1FFF, 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000,
1003 0x00906EFD, 0x00900EFD, 0x00E00EF8,
1004 };
1005
1006 if(nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1007 for(i = 0; i < UCODE_SIZE; i++)
1008 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1009 cb->command = cpu_to_le16(cb_ucode);
1010 } else
1011 cb->command = cpu_to_le16(cb_nop);
1012 }
1013
1014 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1015 struct sk_buff *skb)
1016 {
1017 cb->command = cpu_to_le16(cb_iaaddr);
1018 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1019 }
1020
1021 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1022 {
1023 cb->command = cpu_to_le16(cb_dump);
1024 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1025 offsetof(struct mem, dump_buf));
1026 }
1027
1028 #define NCONFIG_AUTO_SWITCH 0x0080
1029 #define MII_NSC_CONG MII_RESV1
1030 #define NSC_CONG_ENABLE 0x0100
1031 #define NSC_CONG_TXREADY 0x0400
1032 #define ADVERTISE_FC_SUPPORTED 0x0400
1033 static int e100_phy_init(struct nic *nic)
1034 {
1035 struct net_device *netdev = nic->netdev;
1036 u32 addr;
1037 u16 bmcr, stat, id_lo, id_hi, cong;
1038
1039 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1040 for(addr = 0; addr < 32; addr++) {
1041 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1042 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1043 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1044 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1045 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1046 break;
1047 }
1048 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1049 if(addr == 32)
1050 return -EAGAIN;
1051
1052 /* Selected the phy and isolate the rest */
1053 for(addr = 0; addr < 32; addr++) {
1054 if(addr != nic->mii.phy_id) {
1055 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1056 } else {
1057 bmcr = mdio_read(netdev, addr, MII_BMCR);
1058 mdio_write(netdev, addr, MII_BMCR,
1059 bmcr & ~BMCR_ISOLATE);
1060 }
1061 }
1062
1063 /* Get phy ID */
1064 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1065 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1066 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1067 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1068
1069 /* Handle National tx phys */
1070 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1071 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1072 /* Disable congestion control */
1073 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1074 cong |= NSC_CONG_TXREADY;
1075 cong &= ~NSC_CONG_ENABLE;
1076 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1077 }
1078
1079 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1080 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1081 (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled)))
1082 /* enable/disable MDI/MDI-X auto-switching */
1083 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1084 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1085
1086 return 0;
1087 }
1088
1089 static int e100_hw_init(struct nic *nic)
1090 {
1091 int err;
1092
1093 e100_hw_reset(nic);
1094
1095 DPRINTK(HW, ERR, "e100_hw_init\n");
1096 if(!in_interrupt() && (err = e100_self_test(nic)))
1097 return err;
1098
1099 if((err = e100_phy_init(nic)))
1100 return err;
1101 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1102 return err;
1103 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1104 return err;
1105 if((err = e100_exec_cb(nic, NULL, e100_load_ucode)))
1106 return err;
1107 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1108 return err;
1109 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1110 return err;
1111 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1112 nic->dma_addr + offsetof(struct mem, stats))))
1113 return err;
1114 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1115 return err;
1116
1117 e100_disable_irq(nic);
1118
1119 return 0;
1120 }
1121
1122 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1123 {
1124 struct net_device *netdev = nic->netdev;
1125 struct dev_mc_list *list = netdev->mc_list;
1126 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1127
1128 cb->command = cpu_to_le16(cb_multi);
1129 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1130 for(i = 0; list && i < count; i++, list = list->next)
1131 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1132 ETH_ALEN);
1133 }
1134
1135 static void e100_set_multicast_list(struct net_device *netdev)
1136 {
1137 struct nic *nic = netdev_priv(netdev);
1138
1139 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1140 netdev->mc_count, netdev->flags);
1141
1142 if(netdev->flags & IFF_PROMISC)
1143 nic->flags |= promiscuous;
1144 else
1145 nic->flags &= ~promiscuous;
1146
1147 if(netdev->flags & IFF_ALLMULTI ||
1148 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1149 nic->flags |= multicast_all;
1150 else
1151 nic->flags &= ~multicast_all;
1152
1153 e100_exec_cb(nic, NULL, e100_configure);
1154 e100_exec_cb(nic, NULL, e100_multi);
1155 }
1156
1157 static void e100_update_stats(struct nic *nic)
1158 {
1159 struct net_device_stats *ns = &nic->net_stats;
1160 struct stats *s = &nic->mem->stats;
1161 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1162 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1163 &s->complete;
1164
1165 /* Device's stats reporting may take several microseconds to
1166 * complete, so where always waiting for results of the
1167 * previous command. */
1168
1169 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1170 *complete = 0;
1171 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1172 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1173 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1174 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1175 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1176 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1177 ns->collisions += nic->tx_collisions;
1178 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1179 le32_to_cpu(s->tx_lost_crs);
1180 ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1181 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1182 nic->rx_over_length_errors;
1183 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1184 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1185 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1186 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1187 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1188 le32_to_cpu(s->rx_alignment_errors) +
1189 le32_to_cpu(s->rx_short_frame_errors) +
1190 le32_to_cpu(s->rx_cdt_errors);
1191 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1192 nic->tx_single_collisions +=
1193 le32_to_cpu(s->tx_single_collisions);
1194 nic->tx_multiple_collisions +=
1195 le32_to_cpu(s->tx_multiple_collisions);
1196 if(nic->mac >= mac_82558_D101_A4) {
1197 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1198 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1199 nic->rx_fc_unsupported +=
1200 le32_to_cpu(s->fc_rcv_unsupported);
1201 if(nic->mac >= mac_82559_D101M) {
1202 nic->tx_tco_frames +=
1203 le16_to_cpu(s->xmt_tco_frames);
1204 nic->rx_tco_frames +=
1205 le16_to_cpu(s->rcv_tco_frames);
1206 }
1207 }
1208 }
1209
1210 e100_exec_cmd(nic, cuc_dump_reset, 0);
1211 }
1212
1213 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1214 {
1215 /* Adjust inter-frame-spacing (IFS) between two transmits if
1216 * we're getting collisions on a half-duplex connection. */
1217
1218 if(duplex == DUPLEX_HALF) {
1219 u32 prev = nic->adaptive_ifs;
1220 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1221
1222 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1223 (nic->tx_frames > min_frames)) {
1224 if(nic->adaptive_ifs < 60)
1225 nic->adaptive_ifs += 5;
1226 } else if (nic->tx_frames < min_frames) {
1227 if(nic->adaptive_ifs >= 5)
1228 nic->adaptive_ifs -= 5;
1229 }
1230 if(nic->adaptive_ifs != prev)
1231 e100_exec_cb(nic, NULL, e100_configure);
1232 }
1233 }
1234
1235 static void e100_watchdog(unsigned long data)
1236 {
1237 struct nic *nic = (struct nic *)data;
1238 struct ethtool_cmd cmd;
1239
1240 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1241
1242 /* mii library handles link maintenance tasks */
1243
1244 mii_ethtool_gset(&nic->mii, &cmd);
1245
1246 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1247 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1248 cmd.speed == SPEED_100 ? "100" : "10",
1249 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1250 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1251 DPRINTK(LINK, INFO, "link down\n");
1252 }
1253
1254 mii_check_link(&nic->mii);
1255
1256 /* Software generated interrupt to recover from (rare) Rx
1257 * allocation failure */
1258 writeb(irq_sw_gen, &nic->csr->scb.cmd_hi);
1259 e100_write_flush(nic);
1260
1261 e100_update_stats(nic);
1262 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1263
1264 if(nic->mac <= mac_82557_D100_C)
1265 /* Issue a multicast command to workaround a 557 lock up */
1266 e100_set_multicast_list(nic->netdev);
1267
1268 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1269 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1270 nic->flags |= ich_10h_workaround;
1271 else
1272 nic->flags &= ~ich_10h_workaround;
1273
1274 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1275 }
1276
1277 static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1278 struct sk_buff *skb)
1279 {
1280 cb->command = nic->tx_command;
1281 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1282 cb->u.tcb.tcb_byte_count = 0;
1283 cb->u.tcb.threshold = nic->tx_threshold;
1284 cb->u.tcb.tbd_count = 1;
1285 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1286 skb->data, skb->len, PCI_DMA_TODEVICE));
1287 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1288 }
1289
1290 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1291 {
1292 struct nic *nic = netdev_priv(netdev);
1293 int err;
1294
1295 if(nic->flags & ich_10h_workaround) {
1296 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1297 Issue a NOP command followed by a 1us delay before
1298 issuing the Tx command. */
1299 e100_exec_cmd(nic, cuc_nop, 0);
1300 udelay(1);
1301 }
1302
1303 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1304
1305 switch(err) {
1306 case -ENOSPC:
1307 /* We queued the skb, but now we're out of space. */
1308 netif_stop_queue(netdev);
1309 break;
1310 case -ENOMEM:
1311 /* This is a hard error - log it. */
1312 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1313 netif_stop_queue(netdev);
1314 return 1;
1315 }
1316
1317 netdev->trans_start = jiffies;
1318 return 0;
1319 }
1320
1321 static inline int e100_tx_clean(struct nic *nic)
1322 {
1323 struct cb *cb;
1324 int tx_cleaned = 0;
1325
1326 spin_lock(&nic->cb_lock);
1327
1328 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1329 nic->cb_to_clean->status);
1330
1331 /* Clean CBs marked complete */
1332 for(cb = nic->cb_to_clean;
1333 cb->status & cpu_to_le16(cb_complete);
1334 cb = nic->cb_to_clean = cb->next) {
1335 if(likely(cb->skb != NULL)) {
1336 nic->net_stats.tx_packets++;
1337 nic->net_stats.tx_bytes += cb->skb->len;
1338
1339 pci_unmap_single(nic->pdev,
1340 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1341 le16_to_cpu(cb->u.tcb.tbd.size),
1342 PCI_DMA_TODEVICE);
1343 dev_kfree_skb_any(cb->skb);
1344 cb->skb = NULL;
1345 tx_cleaned = 1;
1346 }
1347 cb->status = 0;
1348 nic->cbs_avail++;
1349 }
1350
1351 spin_unlock(&nic->cb_lock);
1352
1353 /* Recover from running out of Tx resources in xmit_frame */
1354 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1355 netif_wake_queue(nic->netdev);
1356
1357 return tx_cleaned;
1358 }
1359
1360 static void e100_clean_cbs(struct nic *nic)
1361 {
1362 if(nic->cbs) {
1363 while(nic->cbs_avail != nic->params.cbs.count) {
1364 struct cb *cb = nic->cb_to_clean;
1365 if(cb->skb) {
1366 pci_unmap_single(nic->pdev,
1367 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1368 le16_to_cpu(cb->u.tcb.tbd.size),
1369 PCI_DMA_TODEVICE);
1370 dev_kfree_skb(cb->skb);
1371 }
1372 nic->cb_to_clean = nic->cb_to_clean->next;
1373 nic->cbs_avail++;
1374 }
1375 pci_free_consistent(nic->pdev,
1376 sizeof(struct cb) * nic->params.cbs.count,
1377 nic->cbs, nic->cbs_dma_addr);
1378 nic->cbs = NULL;
1379 nic->cbs_avail = 0;
1380 }
1381 nic->cuc_cmd = cuc_start;
1382 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1383 nic->cbs;
1384 }
1385
1386 static int e100_alloc_cbs(struct nic *nic)
1387 {
1388 struct cb *cb;
1389 unsigned int i, count = nic->params.cbs.count;
1390
1391 nic->cuc_cmd = cuc_start;
1392 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1393 nic->cbs_avail = 0;
1394
1395 nic->cbs = pci_alloc_consistent(nic->pdev,
1396 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1397 if(!nic->cbs)
1398 return -ENOMEM;
1399
1400 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1401 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1402 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1403
1404 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1405 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1406 ((i+1) % count) * sizeof(struct cb));
1407 cb->skb = NULL;
1408 }
1409
1410 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1411 nic->cbs_avail = count;
1412
1413 return 0;
1414 }
1415
1416 static inline void e100_start_receiver(struct nic *nic)
1417 {
1418 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1419 if(!nic->ru_running && nic->rx_to_clean->skb) {
1420 e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr);
1421 nic->ru_running = 1;
1422 }
1423 }
1424
1425 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1426 static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1427 {
1428 unsigned int rx_offset = 2; /* u32 align protocol headers */
1429
1430 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + rx_offset)))
1431 return -ENOMEM;
1432
1433 /* Align, init, and map the RFD. */
1434 rx->skb->dev = nic->netdev;
1435 skb_reserve(rx->skb, rx_offset);
1436 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1437 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1438 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1439
1440 /* Link the RFD to end of RFA by linking previous RFD to
1441 * this one, and clearing EL bit of previous. */
1442 if(rx->prev->skb) {
1443 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1444 put_unaligned(cpu_to_le32(rx->dma_addr),
1445 (u32 *)&prev_rfd->link);
1446 wmb();
1447 prev_rfd->command &= ~cpu_to_le16(cb_el);
1448 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1449 sizeof(struct rfd), PCI_DMA_TODEVICE);
1450 }
1451
1452 return 0;
1453 }
1454
1455 static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1456 unsigned int *work_done, unsigned int work_to_do)
1457 {
1458 struct sk_buff *skb = rx->skb;
1459 struct rfd *rfd = (struct rfd *)skb->data;
1460 u16 rfd_status, actual_size;
1461
1462 if(unlikely(work_done && *work_done >= work_to_do))
1463 return -EAGAIN;
1464
1465 /* Need to sync before taking a peek at cb_complete bit */
1466 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1467 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1468 rfd_status = le16_to_cpu(rfd->status);
1469
1470 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1471
1472 /* If data isn't ready, nothing to indicate */
1473 if(unlikely(!(rfd_status & cb_complete)))
1474 return -EAGAIN;
1475
1476 /* Get actual data size */
1477 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1478 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1479 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1480
1481 /* Get data */
1482 pci_unmap_single(nic->pdev, rx->dma_addr,
1483 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1484
1485 /* Pull off the RFD and put the actual data (minus eth hdr) */
1486 skb_reserve(skb, sizeof(struct rfd));
1487 skb_put(skb, actual_size);
1488 skb->protocol = eth_type_trans(skb, nic->netdev);
1489
1490 if(unlikely(!(rfd_status & cb_ok))) {
1491 /* Don't indicate if hardware indicates errors */
1492 nic->net_stats.rx_dropped++;
1493 dev_kfree_skb_any(skb);
1494 } else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
1495 /* Don't indicate oversized frames */
1496 nic->rx_over_length_errors++;
1497 nic->net_stats.rx_dropped++;
1498 dev_kfree_skb_any(skb);
1499 } else {
1500 nic->net_stats.rx_packets++;
1501 nic->net_stats.rx_bytes += actual_size;
1502 nic->netdev->last_rx = jiffies;
1503 netif_receive_skb(skb);
1504 if(work_done)
1505 (*work_done)++;
1506 }
1507
1508 rx->skb = NULL;
1509
1510 return 0;
1511 }
1512
1513 static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1514 unsigned int work_to_do)
1515 {
1516 struct rx *rx;
1517
1518 /* Indicate newly arrived packets */
1519 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1520 if(e100_rx_indicate(nic, rx, work_done, work_to_do))
1521 break; /* No more to clean */
1522 }
1523
1524 /* Alloc new skbs to refill list */
1525 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1526 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1527 break; /* Better luck next time (see watchdog) */
1528 }
1529
1530 e100_start_receiver(nic);
1531 }
1532
1533 static void e100_rx_clean_list(struct nic *nic)
1534 {
1535 struct rx *rx;
1536 unsigned int i, count = nic->params.rfds.count;
1537
1538 if(nic->rxs) {
1539 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1540 if(rx->skb) {
1541 pci_unmap_single(nic->pdev, rx->dma_addr,
1542 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1543 dev_kfree_skb(rx->skb);
1544 }
1545 }
1546 kfree(nic->rxs);
1547 nic->rxs = NULL;
1548 }
1549
1550 nic->rx_to_use = nic->rx_to_clean = NULL;
1551 nic->ru_running = 0;
1552 }
1553
1554 static int e100_rx_alloc_list(struct nic *nic)
1555 {
1556 struct rx *rx;
1557 unsigned int i, count = nic->params.rfds.count;
1558
1559 nic->rx_to_use = nic->rx_to_clean = NULL;
1560
1561 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1562 return -ENOMEM;
1563 memset(nic->rxs, 0, sizeof(struct rx) * count);
1564
1565 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1566 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1567 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1568 if(e100_rx_alloc_skb(nic, rx)) {
1569 e100_rx_clean_list(nic);
1570 return -ENOMEM;
1571 }
1572 }
1573
1574 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1575
1576 return 0;
1577 }
1578
1579 static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1580 {
1581 struct net_device *netdev = dev_id;
1582 struct nic *nic = netdev_priv(netdev);
1583 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1584
1585 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1586
1587 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1588 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1589 return IRQ_NONE;
1590
1591 /* Ack interrupt(s) */
1592 writeb(stat_ack, &nic->csr->scb.stat_ack);
1593
1594 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1595 if(stat_ack & stat_ack_rnr)
1596 nic->ru_running = 0;
1597
1598 e100_disable_irq(nic);
1599 netif_rx_schedule(netdev);
1600
1601 return IRQ_HANDLED;
1602 }
1603
1604 static int e100_poll(struct net_device *netdev, int *budget)
1605 {
1606 struct nic *nic = netdev_priv(netdev);
1607 unsigned int work_to_do = min(netdev->quota, *budget);
1608 unsigned int work_done = 0;
1609 int tx_cleaned;
1610
1611 e100_rx_clean(nic, &work_done, work_to_do);
1612 tx_cleaned = e100_tx_clean(nic);
1613
1614 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1615 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1616 netif_rx_complete(netdev);
1617 e100_enable_irq(nic);
1618 return 0;
1619 }
1620
1621 *budget -= work_done;
1622 netdev->quota -= work_done;
1623
1624 return 1;
1625 }
1626
1627 #ifdef CONFIG_NET_POLL_CONTROLLER
1628 static void e100_netpoll(struct net_device *netdev)
1629 {
1630 struct nic *nic = netdev_priv(netdev);
1631 e100_disable_irq(nic);
1632 e100_intr(nic->pdev->irq, netdev, NULL);
1633 e100_enable_irq(nic);
1634 }
1635 #endif
1636
1637 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1638 {
1639 struct nic *nic = netdev_priv(netdev);
1640 return &nic->net_stats;
1641 }
1642
1643 static int e100_set_mac_address(struct net_device *netdev, void *p)
1644 {
1645 struct nic *nic = netdev_priv(netdev);
1646 struct sockaddr *addr = p;
1647
1648 if (!is_valid_ether_addr(addr->sa_data))
1649 return -EADDRNOTAVAIL;
1650
1651 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1652 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1653
1654 return 0;
1655 }
1656
1657 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1658 {
1659 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1660 return -EINVAL;
1661 netdev->mtu = new_mtu;
1662 return 0;
1663 }
1664
1665 static int e100_asf(struct nic *nic)
1666 {
1667 /* ASF can be enabled from eeprom */
1668 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1669 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1670 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1671 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1672 }
1673
1674 static int e100_up(struct nic *nic)
1675 {
1676 int err;
1677
1678 if((err = e100_rx_alloc_list(nic)))
1679 return err;
1680 if((err = e100_alloc_cbs(nic)))
1681 goto err_rx_clean_list;
1682 if((err = e100_hw_init(nic)))
1683 goto err_clean_cbs;
1684 e100_set_multicast_list(nic->netdev);
1685 e100_start_receiver(nic);
1686 mod_timer(&nic->watchdog, jiffies);
1687 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1688 nic->netdev->name, nic->netdev)))
1689 goto err_no_irq;
1690 e100_enable_irq(nic);
1691 netif_wake_queue(nic->netdev);
1692 return 0;
1693
1694 err_no_irq:
1695 del_timer_sync(&nic->watchdog);
1696 err_clean_cbs:
1697 e100_clean_cbs(nic);
1698 err_rx_clean_list:
1699 e100_rx_clean_list(nic);
1700 return err;
1701 }
1702
1703 static void e100_down(struct nic *nic)
1704 {
1705 e100_hw_reset(nic);
1706 free_irq(nic->pdev->irq, nic->netdev);
1707 del_timer_sync(&nic->watchdog);
1708 netif_carrier_off(nic->netdev);
1709 netif_stop_queue(nic->netdev);
1710 e100_clean_cbs(nic);
1711 e100_rx_clean_list(nic);
1712 }
1713
1714 static void e100_tx_timeout(struct net_device *netdev)
1715 {
1716 struct nic *nic = netdev_priv(netdev);
1717
1718 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
1719 readb(&nic->csr->scb.status));
1720 e100_down(netdev_priv(netdev));
1721 e100_up(netdev_priv(netdev));
1722 }
1723
1724 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
1725 {
1726 int err;
1727 struct sk_buff *skb;
1728
1729 /* Use driver resources to perform internal MAC or PHY
1730 * loopback test. A single packet is prepared and transmitted
1731 * in loopback mode, and the test passes if the received
1732 * packet compares byte-for-byte to the transmitted packet. */
1733
1734 if((err = e100_rx_alloc_list(nic)))
1735 return err;
1736 if((err = e100_alloc_cbs(nic)))
1737 goto err_clean_rx;
1738
1739 /* ICH PHY loopback is broken so do MAC loopback instead */
1740 if(nic->flags & ich && loopback_mode == lb_phy)
1741 loopback_mode = lb_mac;
1742
1743 nic->loopback = loopback_mode;
1744 if((err = e100_hw_init(nic)))
1745 goto err_loopback_none;
1746
1747 if(loopback_mode == lb_phy)
1748 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
1749 BMCR_LOOPBACK);
1750
1751 e100_start_receiver(nic);
1752
1753 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
1754 err = -ENOMEM;
1755 goto err_loopback_none;
1756 }
1757 skb_put(skb, ETH_DATA_LEN);
1758 memset(skb->data, 0xFF, ETH_DATA_LEN);
1759 e100_xmit_frame(skb, nic->netdev);
1760
1761 set_current_state(TASK_UNINTERRUPTIBLE);
1762 schedule_timeout(HZ / 100 + 1);
1763
1764 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1765 skb->data, ETH_DATA_LEN))
1766 err = -EAGAIN;
1767
1768 err_loopback_none:
1769 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
1770 nic->loopback = lb_none;
1771 e100_hw_init(nic);
1772 e100_clean_cbs(nic);
1773 err_clean_rx:
1774 e100_rx_clean_list(nic);
1775 return err;
1776 }
1777
1778 #define MII_LED_CONTROL 0x1B
1779 static void e100_blink_led(unsigned long data)
1780 {
1781 struct nic *nic = (struct nic *)data;
1782 enum led_state {
1783 led_on = 0x01,
1784 led_off = 0x04,
1785 led_on_559 = 0x05,
1786 led_on_557 = 0x07,
1787 };
1788
1789 nic->leds = (nic->leds & led_on) ? led_off :
1790 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
1791 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
1792 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
1793 }
1794
1795 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1796 {
1797 struct nic *nic = netdev_priv(netdev);
1798 return mii_ethtool_gset(&nic->mii, cmd);
1799 }
1800
1801 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1802 {
1803 struct nic *nic = netdev_priv(netdev);
1804 int err;
1805
1806 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
1807 err = mii_ethtool_sset(&nic->mii, cmd);
1808 e100_exec_cb(nic, NULL, e100_configure);
1809
1810 return err;
1811 }
1812
1813 static void e100_get_drvinfo(struct net_device *netdev,
1814 struct ethtool_drvinfo *info)
1815 {
1816 struct nic *nic = netdev_priv(netdev);
1817 strcpy(info->driver, DRV_NAME);
1818 strcpy(info->version, DRV_VERSION);
1819 strcpy(info->fw_version, "N/A");
1820 strcpy(info->bus_info, pci_name(nic->pdev));
1821 }
1822
1823 static int e100_get_regs_len(struct net_device *netdev)
1824 {
1825 struct nic *nic = netdev_priv(netdev);
1826 #define E100_PHY_REGS 0x1C
1827 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
1828 sizeof(nic->mem->dump_buf) / sizeof(u32)
1829 return E100_REGS_LEN * sizeof(u32);
1830 }
1831
1832 static void e100_get_regs(struct net_device *netdev,
1833 struct ethtool_regs *regs, void *p)
1834 {
1835 struct nic *nic = netdev_priv(netdev);
1836 u32 *buff = p;
1837 int i;
1838
1839 regs->version = (1 << 24) | nic->rev_id;
1840 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
1841 readb(&nic->csr->scb.cmd_lo) << 16 |
1842 readw(&nic->csr->scb.status);
1843 for(i = E100_PHY_REGS; i >= 0; i--)
1844 buff[1 + E100_PHY_REGS - i] =
1845 mdio_read(netdev, nic->mii.phy_id, i);
1846 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
1847 e100_exec_cb(nic, NULL, e100_dump);
1848 set_current_state(TASK_UNINTERRUPTIBLE);
1849 schedule_timeout(HZ / 100 + 1);
1850 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
1851 sizeof(nic->mem->dump_buf));
1852 }
1853
1854 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1855 {
1856 struct nic *nic = netdev_priv(netdev);
1857 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
1858 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
1859 }
1860
1861 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1862 {
1863 struct nic *nic = netdev_priv(netdev);
1864
1865 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
1866 return -EOPNOTSUPP;
1867
1868 if(wol->wolopts)
1869 nic->flags |= wol_magic;
1870 else
1871 nic->flags &= ~wol_magic;
1872
1873 pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
1874 e100_exec_cb(nic, NULL, e100_configure);
1875
1876 return 0;
1877 }
1878
1879 static u32 e100_get_msglevel(struct net_device *netdev)
1880 {
1881 struct nic *nic = netdev_priv(netdev);
1882 return nic->msg_enable;
1883 }
1884
1885 static void e100_set_msglevel(struct net_device *netdev, u32 value)
1886 {
1887 struct nic *nic = netdev_priv(netdev);
1888 nic->msg_enable = value;
1889 }
1890
1891 static int e100_nway_reset(struct net_device *netdev)
1892 {
1893 struct nic *nic = netdev_priv(netdev);
1894 return mii_nway_restart(&nic->mii);
1895 }
1896
1897 static u32 e100_get_link(struct net_device *netdev)
1898 {
1899 struct nic *nic = netdev_priv(netdev);
1900 return mii_link_ok(&nic->mii);
1901 }
1902
1903 static int e100_get_eeprom_len(struct net_device *netdev)
1904 {
1905 struct nic *nic = netdev_priv(netdev);
1906 return nic->eeprom_wc << 1;
1907 }
1908
1909 #define E100_EEPROM_MAGIC 0x1234
1910 static int e100_get_eeprom(struct net_device *netdev,
1911 struct ethtool_eeprom *eeprom, u8 *bytes)
1912 {
1913 struct nic *nic = netdev_priv(netdev);
1914
1915 eeprom->magic = E100_EEPROM_MAGIC;
1916 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
1917
1918 return 0;
1919 }
1920
1921 static int e100_set_eeprom(struct net_device *netdev,
1922 struct ethtool_eeprom *eeprom, u8 *bytes)
1923 {
1924 struct nic *nic = netdev_priv(netdev);
1925
1926 if(eeprom->magic != E100_EEPROM_MAGIC)
1927 return -EINVAL;
1928
1929 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
1930
1931 return e100_eeprom_save(nic, eeprom->offset >> 1,
1932 (eeprom->len >> 1) + 1);
1933 }
1934
1935 static void e100_get_ringparam(struct net_device *netdev,
1936 struct ethtool_ringparam *ring)
1937 {
1938 struct nic *nic = netdev_priv(netdev);
1939 struct param_range *rfds = &nic->params.rfds;
1940 struct param_range *cbs = &nic->params.cbs;
1941
1942 ring->rx_max_pending = rfds->max;
1943 ring->tx_max_pending = cbs->max;
1944 ring->rx_mini_max_pending = 0;
1945 ring->rx_jumbo_max_pending = 0;
1946 ring->rx_pending = rfds->count;
1947 ring->tx_pending = cbs->count;
1948 ring->rx_mini_pending = 0;
1949 ring->rx_jumbo_pending = 0;
1950 }
1951
1952 static int e100_set_ringparam(struct net_device *netdev,
1953 struct ethtool_ringparam *ring)
1954 {
1955 struct nic *nic = netdev_priv(netdev);
1956 struct param_range *rfds = &nic->params.rfds;
1957 struct param_range *cbs = &nic->params.cbs;
1958
1959 if(netif_running(netdev))
1960 e100_down(nic);
1961 rfds->count = max(ring->rx_pending, rfds->min);
1962 rfds->count = min(rfds->count, rfds->max);
1963 cbs->count = max(ring->tx_pending, cbs->min);
1964 cbs->count = min(cbs->count, cbs->max);
1965 if(netif_running(netdev))
1966 e100_up(nic);
1967
1968 return 0;
1969 }
1970
1971 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
1972 "Link test (on/offline)",
1973 "Eeprom test (on/offline)",
1974 "Self test (offline)",
1975 "Mac loopback (offline)",
1976 "Phy loopback (offline)",
1977 };
1978 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
1979
1980 static int e100_diag_test_count(struct net_device *netdev)
1981 {
1982 return E100_TEST_LEN;
1983 }
1984
1985 static void e100_diag_test(struct net_device *netdev,
1986 struct ethtool_test *test, u64 *data)
1987 {
1988 struct ethtool_cmd cmd;
1989 struct nic *nic = netdev_priv(netdev);
1990 int i, err;
1991
1992 memset(data, 0, E100_TEST_LEN * sizeof(u64));
1993 data[0] = !mii_link_ok(&nic->mii);
1994 data[1] = e100_eeprom_load(nic);
1995 if(test->flags & ETH_TEST_FL_OFFLINE) {
1996
1997 /* save speed, duplex & autoneg settings */
1998 err = mii_ethtool_gset(&nic->mii, &cmd);
1999
2000 if(netif_running(netdev))
2001 e100_down(nic);
2002 data[2] = e100_self_test(nic);
2003 data[3] = e100_loopback_test(nic, lb_mac);
2004 data[4] = e100_loopback_test(nic, lb_phy);
2005
2006 /* restore speed, duplex & autoneg settings */
2007 err = mii_ethtool_sset(&nic->mii, &cmd);
2008
2009 if(netif_running(netdev))
2010 e100_up(nic);
2011 }
2012 for(i = 0; i < E100_TEST_LEN; i++)
2013 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2014 }
2015
2016 static int e100_phys_id(struct net_device *netdev, u32 data)
2017 {
2018 struct nic *nic = netdev_priv(netdev);
2019
2020 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2021 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2022 mod_timer(&nic->blink_timer, jiffies);
2023 set_current_state(TASK_INTERRUPTIBLE);
2024 schedule_timeout(data * HZ);
2025 del_timer_sync(&nic->blink_timer);
2026 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2027
2028 return 0;
2029 }
2030
2031 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2032 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2033 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2034 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2035 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2036 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2037 "tx_heartbeat_errors", "tx_window_errors",
2038 /* device-specific stats */
2039 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2040 "tx_flow_control_pause", "rx_flow_control_pause",
2041 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2042 };
2043 #define E100_NET_STATS_LEN 21
2044 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2045
2046 static int e100_get_stats_count(struct net_device *netdev)
2047 {
2048 return E100_STATS_LEN;
2049 }
2050
2051 static void e100_get_ethtool_stats(struct net_device *netdev,
2052 struct ethtool_stats *stats, u64 *data)
2053 {
2054 struct nic *nic = netdev_priv(netdev);
2055 int i;
2056
2057 for(i = 0; i < E100_NET_STATS_LEN; i++)
2058 data[i] = ((unsigned long *)&nic->net_stats)[i];
2059
2060 data[i++] = nic->tx_deferred;
2061 data[i++] = nic->tx_single_collisions;
2062 data[i++] = nic->tx_multiple_collisions;
2063 data[i++] = nic->tx_fc_pause;
2064 data[i++] = nic->rx_fc_pause;
2065 data[i++] = nic->rx_fc_unsupported;
2066 data[i++] = nic->tx_tco_frames;
2067 data[i++] = nic->rx_tco_frames;
2068 }
2069
2070 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2071 {
2072 switch(stringset) {
2073 case ETH_SS_TEST:
2074 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2075 break;
2076 case ETH_SS_STATS:
2077 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2078 break;
2079 }
2080 }
2081
2082 static struct ethtool_ops e100_ethtool_ops = {
2083 .get_settings = e100_get_settings,
2084 .set_settings = e100_set_settings,
2085 .get_drvinfo = e100_get_drvinfo,
2086 .get_regs_len = e100_get_regs_len,
2087 .get_regs = e100_get_regs,
2088 .get_wol = e100_get_wol,
2089 .set_wol = e100_set_wol,
2090 .get_msglevel = e100_get_msglevel,
2091 .set_msglevel = e100_set_msglevel,
2092 .nway_reset = e100_nway_reset,
2093 .get_link = e100_get_link,
2094 .get_eeprom_len = e100_get_eeprom_len,
2095 .get_eeprom = e100_get_eeprom,
2096 .set_eeprom = e100_set_eeprom,
2097 .get_ringparam = e100_get_ringparam,
2098 .set_ringparam = e100_set_ringparam,
2099 .self_test_count = e100_diag_test_count,
2100 .self_test = e100_diag_test,
2101 .get_strings = e100_get_strings,
2102 .phys_id = e100_phys_id,
2103 .get_stats_count = e100_get_stats_count,
2104 .get_ethtool_stats = e100_get_ethtool_stats,
2105 };
2106
2107 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2108 {
2109 struct nic *nic = netdev_priv(netdev);
2110
2111 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2112 }
2113
2114 static int e100_alloc(struct nic *nic)
2115 {
2116 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2117 &nic->dma_addr);
2118 return nic->mem ? 0 : -ENOMEM;
2119 }
2120
2121 static void e100_free(struct nic *nic)
2122 {
2123 if(nic->mem) {
2124 pci_free_consistent(nic->pdev, sizeof(struct mem),
2125 nic->mem, nic->dma_addr);
2126 nic->mem = NULL;
2127 }
2128 }
2129
2130 static int e100_open(struct net_device *netdev)
2131 {
2132 struct nic *nic = netdev_priv(netdev);
2133 int err = 0;
2134
2135 netif_carrier_off(netdev);
2136 if((err = e100_up(nic)))
2137 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2138 return err;
2139 }
2140
2141 static int e100_close(struct net_device *netdev)
2142 {
2143 e100_down(netdev_priv(netdev));
2144 return 0;
2145 }
2146
2147 static int __devinit e100_probe(struct pci_dev *pdev,
2148 const struct pci_device_id *ent)
2149 {
2150 struct net_device *netdev;
2151 struct nic *nic;
2152 int err;
2153
2154 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2155 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2156 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2157 return -ENOMEM;
2158 }
2159
2160 netdev->open = e100_open;
2161 netdev->stop = e100_close;
2162 netdev->hard_start_xmit = e100_xmit_frame;
2163 netdev->get_stats = e100_get_stats;
2164 netdev->set_multicast_list = e100_set_multicast_list;
2165 netdev->set_mac_address = e100_set_mac_address;
2166 netdev->change_mtu = e100_change_mtu;
2167 netdev->do_ioctl = e100_do_ioctl;
2168 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2169 netdev->tx_timeout = e100_tx_timeout;
2170 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2171 netdev->poll = e100_poll;
2172 netdev->weight = E100_NAPI_WEIGHT;
2173 #ifdef CONFIG_NET_POLL_CONTROLLER
2174 netdev->poll_controller = e100_netpoll;
2175 #endif
2176
2177 nic = netdev_priv(netdev);
2178 nic->netdev = netdev;
2179 nic->pdev = pdev;
2180 nic->msg_enable = (1 << debug) - 1;
2181 pci_set_drvdata(pdev, netdev);
2182
2183 if((err = pci_enable_device(pdev))) {
2184 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2185 goto err_out_free_dev;
2186 }
2187
2188 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2189 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2190 "base address, aborting.\n");
2191 err = -ENODEV;
2192 goto err_out_disable_pdev;
2193 }
2194
2195 if((err = pci_request_regions(pdev, DRV_NAME))) {
2196 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2197 goto err_out_disable_pdev;
2198 }
2199
2200 pci_set_master(pdev);
2201
2202 if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
2203 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2204 goto err_out_free_res;
2205 }
2206
2207 SET_MODULE_OWNER(netdev);
2208 SET_NETDEV_DEV(netdev, &pdev->dev);
2209
2210 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2211 if(!nic->csr) {
2212 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2213 err = -ENOMEM;
2214 goto err_out_free_res;
2215 }
2216
2217 if(ent->driver_data)
2218 nic->flags |= ich;
2219 else
2220 nic->flags &= ~ich;
2221
2222 spin_lock_init(&nic->cb_lock);
2223 spin_lock_init(&nic->cmd_lock);
2224
2225 init_timer(&nic->watchdog);
2226 nic->watchdog.function = e100_watchdog;
2227 nic->watchdog.data = (unsigned long)nic;
2228 init_timer(&nic->blink_timer);
2229 nic->blink_timer.function = e100_blink_led;
2230 nic->blink_timer.data = (unsigned long)nic;
2231
2232 if((err = e100_alloc(nic))) {
2233 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2234 goto err_out_iounmap;
2235 }
2236
2237 e100_get_defaults(nic);
2238 e100_hw_reset(nic);
2239 e100_phy_init(nic);
2240
2241 if((err = e100_eeprom_load(nic)))
2242 goto err_out_free;
2243
2244 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2245 if(!is_valid_ether_addr(netdev->dev_addr)) {
2246 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2247 "EEPROM, aborting.\n");
2248 err = -EAGAIN;
2249 goto err_out_free;
2250 }
2251
2252 /* Wol magic packet can be enabled from eeprom */
2253 if((nic->mac >= mac_82558_D101_A4) &&
2254 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2255 nic->flags |= wol_magic;
2256
2257 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2258
2259 if((err = register_netdev(netdev))) {
2260 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2261 goto err_out_free;
2262 }
2263
2264 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2265 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2266 pci_resource_start(pdev, 0), pdev->irq,
2267 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2268 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2269
2270 return 0;
2271
2272 err_out_free:
2273 e100_free(nic);
2274 err_out_iounmap:
2275 iounmap(nic->csr);
2276 err_out_free_res:
2277 pci_release_regions(pdev);
2278 err_out_disable_pdev:
2279 pci_disable_device(pdev);
2280 err_out_free_dev:
2281 pci_set_drvdata(pdev, NULL);
2282 free_netdev(netdev);
2283 return err;
2284 }
2285
2286 static void __devexit e100_remove(struct pci_dev *pdev)
2287 {
2288 struct net_device *netdev = pci_get_drvdata(pdev);
2289
2290 if(netdev) {
2291 struct nic *nic = netdev_priv(netdev);
2292 unregister_netdev(netdev);
2293 e100_free(nic);
2294 iounmap(nic->csr);
2295 free_netdev(netdev);
2296 pci_release_regions(pdev);
2297 pci_disable_device(pdev);
2298 pci_set_drvdata(pdev, NULL);
2299 }
2300 }
2301
2302 #ifdef CONFIG_PM
2303 static int e100_suspend(struct pci_dev *pdev, u32 state)
2304 {
2305 struct net_device *netdev = pci_get_drvdata(pdev);
2306 struct nic *nic = netdev_priv(netdev);
2307
2308 if(netif_running(netdev))
2309 e100_down(nic);
2310 e100_hw_reset(nic);
2311 netif_device_detach(netdev);
2312
2313 pci_save_state(pdev, nic->pm_state);
2314 pci_enable_wake(pdev, state, nic->flags & (wol_magic | e100_asf(nic)));
2315 pci_disable_device(pdev);
2316 pci_set_power_state(pdev, state);
2317
2318 return 0;
2319 }
2320
2321 static int e100_resume(struct pci_dev *pdev)
2322 {
2323 struct net_device *netdev = pci_get_drvdata(pdev);
2324 struct nic *nic = netdev_priv(netdev);
2325
2326 pci_set_power_state(pdev, 0);
2327 pci_restore_state(pdev, nic->pm_state);
2328 e100_hw_init(nic);
2329
2330 netif_device_attach(netdev);
2331 if(netif_running(netdev))
2332 e100_up(nic);
2333
2334 return 0;
2335 }
2336 #endif
2337
2338 static struct pci_driver e100_driver = {
2339 .name = DRV_NAME,
2340 .id_table = e100_id_table,
2341 .probe = e100_probe,
2342 .remove = __devexit_p(e100_remove),
2343 #ifdef CONFIG_PM
2344 .suspend = e100_suspend,
2345 .resume = e100_resume,
2346 #endif
2347 };
2348
2349 static int __init e100_init_module(void)
2350 {
2351 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2352 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2353 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2354 }
2355 return pci_module_init(&e100_driver);
2356 }
2357
2358 static void __exit e100_cleanup_module(void)
2359 {
2360 pci_unregister_driver(&e100_driver);
2361 }
2362
2363 module_init(e100_init_module);
2364 module_exit(e100_cleanup_module);
MOXA 2.6.9 from sdlinux-moxaart.tgz