| blob | 85d1bb3a9865da2581ade75a2c2eebd69890a304 |
1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * The original author:
19 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
20 *
21 * Maintainers:
22 * macro Maciej W. Rozycki <macro@ds2.pg.gda.pl>
23 *
24 * Credits:
25 * I'd like to thank Patricia Cross for helping me get started with
26 * Linux, David Davies for a lot of help upgrading and configuring
27 * my development system and for answering many OS and driver
28 * development questions, and Alan Cox for recommendations and
29 * integration help on getting FDDI support into Linux. LVS
30 *
31 * Driver Architecture:
32 * The driver architecture is largely based on previous driver work
33 * for other operating systems. The upper edge interface and
34 * functions were largely taken from existing Linux device drivers
35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
36 * driver.
37 *
38 * Adapter Probe -
39 * The driver scans for supported EISA adapters by reading the
40 * SLOT ID register for each EISA slot and making a match
41 * against the expected value.
42 *
43 * Bus-Specific Initialization -
44 * This driver currently supports both EISA and PCI controller
45 * families. While the custom DMA chip and FDDI logic is similar
46 * or identical, the bus logic is very different. After
47 * initialization, the only bus-specific differences is in how the
48 * driver enables and disables interrupts. Other than that, the
49 * run-time critical code behaves the same on both families.
50 * It's important to note that both adapter families are configured
51 * to I/O map, rather than memory map, the adapter registers.
52 *
53 * Driver Open/Close -
54 * In the driver open routine, the driver ISR (interrupt service
55 * routine) is registered and the adapter is brought to an
56 * operational state. In the driver close routine, the opposite
57 * occurs; the driver ISR is deregistered and the adapter is
58 * brought to a safe, but closed state. Users may use consecutive
59 * commands to bring the adapter up and down as in the following
60 * example:
61 * ifconfig fddi0 up
62 * ifconfig fddi0 down
63 * ifconfig fddi0 up
64 *
65 * Driver Shutdown -
66 * Apparently, there is no shutdown or halt routine support under
67 * Linux. This routine would be called during "reboot" or
68 * "shutdown" to allow the driver to place the adapter in a safe
69 * state before a warm reboot occurs. To be really safe, the user
70 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
71 * to ensure that the adapter DMA engine is taken off-line. However,
72 * the current driver code anticipates this problem and always issues
73 * a soft reset of the adapter at the beginning of driver initialization.
74 * A future driver enhancement in this area may occur in 2.1.X where
75 * Alan indicated that a shutdown handler may be implemented.
76 *
77 * Interrupt Service Routine -
78 * The driver supports shared interrupts, so the ISR is registered for
79 * each board with the appropriate flag and the pointer to that board's
80 * device structure. This provides the context during interrupt
81 * processing to support shared interrupts and multiple boards.
82 *
83 * Interrupt enabling/disabling can occur at many levels. At the host
84 * end, you can disable system interrupts, or disable interrupts at the
85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
86 * have a bus-logic chip interrupt enable/disable as well as a DMA
87 * controller interrupt enable/disable.
88 *
89 * The driver currently enables and disables adapter interrupts at the
90 * bus-logic chip and assumes that Linux will take care of clearing or
91 * acknowledging any host-based interrupt chips.
92 *
93 * Control Functions -
94 * Control functions are those used to support functions such as adding
95 * or deleting multicast addresses, enabling or disabling packet
96 * reception filters, or other custom/proprietary commands. Presently,
97 * the driver supports the "get statistics", "set multicast list", and
98 * "set mac address" functions defined by Linux. A list of possible
99 * enhancements include:
100 *
101 * - Custom ioctl interface for executing port interface commands
102 * - Custom ioctl interface for adding unicast addresses to
103 * adapter CAM (to support bridge functions).
104 * - Custom ioctl interface for supporting firmware upgrades.
105 *
106 * Hardware (port interface) Support Routines -
107 * The driver function names that start with "dfx_hw_" represent
108 * low-level port interface routines that are called frequently. They
109 * include issuing a DMA or port control command to the adapter,
110 * resetting the adapter, or reading the adapter state. Since the
111 * driver initialization and run-time code must make calls into the
112 * port interface, these routines were written to be as generic and
113 * usable as possible.
114 *
115 * Receive Path -
116 * The adapter DMA engine supports a 256 entry receive descriptor block
117 * of which up to 255 entries can be used at any given time. The
118 * architecture is a standard producer, consumer, completion model in
119 * which the driver "produces" receive buffers to the adapter, the
120 * adapter "consumes" the receive buffers by DMAing incoming packet data,
121 * and the driver "completes" the receive buffers by servicing the
122 * incoming packet, then "produces" a new buffer and starts the cycle
123 * again. Receive buffers can be fragmented in up to 16 fragments
124 * (descriptor entries). For simplicity, this driver posts
125 * single-fragment receive buffers of 4608 bytes, then allocates a
126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
127 * utilization, a better approach would be to pass up the receive
128 * buffer (no extra copy) then allocate and post a replacement buffer.
129 * This is a performance enhancement that should be looked into at
130 * some point.
131 *
132 * Transmit Path -
133 * Like the receive path, the adapter DMA engine supports a 256 entry
134 * transmit descriptor block of which up to 255 entries can be used at
135 * any given time. Transmit buffers can be fragmented in up to 255
136 * fragments (descriptor entries). This driver always posts one
137 * fragment per transmit packet request.
138 *
139 * The fragment contains the entire packet from FC to end of data.
140 * Before posting the buffer to the adapter, the driver sets a three-byte
141 * packet request header (PRH) which is required by the Motorola MAC chip
142 * used on the adapters. The PRH tells the MAC the type of token to
143 * receive/send, whether or not to generate and append the CRC, whether
144 * synchronous or asynchronous framing is used, etc. Since the PRH
145 * definition is not necessarily consistent across all FDDI chipsets,
146 * the driver, rather than the common FDDI packet handler routines,
147 * sets these bytes.
148 *
149 * To reduce the amount of descriptor fetches needed per transmit request,
150 * the driver takes advantage of the fact that there are at least three
151 * bytes available before the skb->data field on the outgoing transmit
152 * request. This is guaranteed by having fddi_setup() in net_init.c set
153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
155 * bytes which we'll use to store the PRH.
156 *
157 * There's a subtle advantage to adding these pad bytes to the
158 * hard_header_len, it ensures that the data portion of the packet for
159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
160 * implementations may not need the extra padding and can start copying
161 * or DMAing directly from the FC byte which starts at skb->data. Should
162 * another driver implementation need ADDITIONAL padding, the net_init.c
163 * module should be updated and dev->hard_header_len should be increased.
164 * NOTE: To maintain the alignment on the data portion of the packet,
165 * dev->hard_header_len should always be evenly divisible by 4 and at
166 * least 24 bytes in size.
167 *
168 * Modification History:
169 * Date Name Description
170 * 16-Aug-96 LVS Created.
171 * 20-Aug-96 LVS Updated dfx_probe so that version information
172 * string is only displayed if 1 or more cards are
173 * found. Changed dfx_rcv_queue_process to copy
174 * 3 NULL bytes before FC to ensure that data is
175 * longword aligned in receive buffer.
176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
177 * LLC group promiscuous mode if multicast list
178 * is too large. LLC individual/group promiscuous
179 * mode is now disabled if IFF_PROMISC flag not set.
180 * dfx_xmt_queue_pkt no longer checks for NULL skb
181 * on Alan Cox recommendation. Added node address
182 * override support.
183 * 12-Sep-96 LVS Reset current address to factory address during
184 * device open. Updated transmit path to post a
185 * single fragment which includes PRH->end of data.
186 * Mar 2000 AC Did various cleanups for 2.3.x
187 * Jun 2000 jgarzik PCI and resource alloc cleanups
188 * Jul 2000 tjeerd Much cleanup and some bug fixes
189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
190 * Feb 2001 Skb allocation fixes
191 * Feb 2001 davej PCI enable cleanups.
192 * 04 Aug 2003 macro Converted to the DMA API.
193 */
195 /* Include files */
197 #include <linux/module.h>
198 #include <linux/kernel.h>
199 #include <linux/string.h>
200 #include <linux/errno.h>
201 #include <linux/ioport.h>
202 #include <linux/slab.h>
203 #include <linux/interrupt.h>
204 #include <linux/pci.h>
205 #include <linux/delay.h>
206 #include <linux/init.h>
207 #include <linux/netdevice.h>
208 #include <linux/fddidevice.h>
209 #include <linux/skbuff.h>
211 #include <asm/byteorder.h>
212 #include <asm/bitops.h>
213 #include <asm/io.h>
217 /* Version information string - should be updated prior to each new release!!! */
224 #define DYNAMIC_BUFFERS 1
226 #define SKBUFF_RX_COPYBREAK 200
227 /*
228 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
229 * alignment for compatibility with old EISA boards.
230 */
231 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
233 /* Define module-wide (static) routines */
256 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
269 /* Define module-wide (static) variables */
273 \f
274 /*
275 * =======================
276 * = dfx_port_write_byte =
277 * = dfx_port_read_byte =
278 * = dfx_port_write_long =
279 * = dfx_port_read_long =
280 * =======================
281 *
282 * Overview:
283 * Routines for reading and writing values from/to adapter
284 *
285 * Returns:
286 * None
287 *
288 * Arguments:
289 * bp - pointer to board information
290 * offset - register offset from base I/O address
291 * data - for dfx_port_write_byte and dfx_port_write_long, this
292 * is a value to write.
293 * for dfx_port_read_byte and dfx_port_read_byte, this
294 * is a pointer to store the read value.
295 *
296 * Functional Description:
297 * These routines perform the correct operation to read or write
298 * the adapter register.
299 *
300 * EISA port block base addresses are based on the slot number in which the
301 * controller is installed. For example, if the EISA controller is installed
302 * in slot 4, the port block base address is 0x4000. If the controller is
303 * installed in slot 2, the port block base address is 0x2000, and so on.
304 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
305 * registers using the register offsets defined in DEFXX.H.
306 *
307 * PCI port block base addresses are assigned by the PCI BIOS or system
308 * firmware. There is one 128 byte port block which can be accessed. It
309 * allows for I/O mapping of both PDQ and PFI registers using the register
310 * offsets defined in DEFXX.H.
311 *
312 * Return Codes:
313 * None
314 *
315 * Assumptions:
316 * bp->base_addr is a valid base I/O address for this adapter.
317 * offset is a valid register offset for this adapter.
318 *
319 * Side Effects:
320 * Rather than produce macros for these functions, these routines
321 * are defined using "inline" to ensure that the compiler will
322 * generate inline code and not waste a procedure call and return.
323 * This provides all the benefits of macros, but with the
324 * advantage of strict data type checking.
325 */
330 u8 data
331 )
333 {
337 }
342 u8 *data
343 )
345 {
349 }
354 u32 data
355 )
357 {
361 }
366 u32 *data
367 )
369 {
373 }
375 \f
376 /*
377 * =============
378 * = dfx_init_one_pci_or_eisa =
379 * =============
380 *
381 * Overview:
382 * Initializes a supported FDDI EISA or PCI controller
383 *
384 * Returns:
385 * Condition code
386 *
387 * Arguments:
388 * pdev - pointer to pci device information (NULL for EISA)
389 * ioaddr - pointer to port (NULL for PCI)
390 *
391 * Functional Description:
392 *
393 * Return Codes:
394 * 0 - This device (fddi0, fddi1, etc) configured successfully
395 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
396 *
397 * Assumptions:
398 * It compiles so it should work :-( (PCI cards do :-)
399 *
400 * Side Effects:
401 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
402 * initialized and the board resources are read and stored in
403 * the device structure.
404 */
406 {
412 #ifndef MODULE
416 {
419 }
420 #endif
426 }
428 /* Enable PCI device. */
433 }
445 }
447 /* Initialize new device structure */
459 /* EISA board */
464 /* PCI board */
469 }
474 }
482 err_out_kfree:
485 #ifndef DYNAMIC_BUFFERS
487 #endif
493 err_out_region:
495 err_out:
498 }
501 {
503 }
506 {
514 /* Scan for FDDI EISA controllers */
517 {
521 {
525 }
526 }
528 }
529 \f
530 /*
531 * ================
532 * = dfx_bus_init =
533 * ================
534 *
535 * Overview:
536 * Initializes EISA and PCI controller bus-specific logic.
537 *
538 * Returns:
539 * None
540 *
541 * Arguments:
542 * dev - pointer to device information
543 *
544 * Functional Description:
545 * Determine and save adapter IRQ in device table,
546 * then perform bus-specific logic initialization.
547 *
548 * Return Codes:
549 * None
550 *
551 * Assumptions:
552 * dev->base_addr has already been set with the proper
553 * base I/O address for this device.
554 *
555 * Side Effects:
556 * Interrupts are enabled at the adapter bus-specific logic.
557 * Note: Interrupts at the DMA engine (PDQ chip) are not
558 * enabled yet.
559 */
562 {
568 /*
569 * Initialize base I/O address field in bp structure
570 *
571 * Note: bp->base_addr is the same as dev->base_addr.
572 * It's useful because often we'll need to read
573 * or write registers where we already have the
574 * bp pointer instead of the dev pointer. Having
575 * the base address in the bp structure will
576 * save a pointer dereference.
577 *
578 * IMPORTANT!! This field must be defined before
579 * any of the dfx_port_* inline functions are
580 * called.
581 */
585 /* And a pointer back to the net_device struct */
588 /* Initialize adapter based on bus type */
591 {
592 /* Get the interrupt level from the ESIC chip */
596 {
612 }
614 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
618 /* Set the I/O decode range of the board */
624 /* Enable access to rest of module (including PDQ and packet memory) */
628 /*
629 * Map PDQ registers into I/O space. This is done by clearing a bit
630 * in Burst Holdoff register.
631 */
636 /* Enable interrupts at EISA bus interface chip (ESIC) */
640 }
641 else
642 {
645 /* Get the interrupt level from the PCI Configuration Table */
649 /* Check Latency Timer and set if less than minimal */
653 {
656 }
658 /* Enable interrupts at PCI bus interface chip (PFI) */
661 }
662 }
664 \f
665 /*
666 * ========================
667 * = dfx_bus_config_check =
668 * ========================
669 *
670 * Overview:
671 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
672 * are illegal, then this routine will set new defaults.
673 *
674 * Returns:
675 * None
676 *
677 * Arguments:
678 * bp - pointer to board information
679 *
680 * Functional Description:
681 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
682 * PDQ, and all FDDI PCI controllers, all values are legal.
683 *
684 * Return Codes:
685 * None
686 *
687 * Assumptions:
688 * dfx_adap_init has NOT been called yet so burst size and other items have
689 * not been set.
690 *
691 * Side Effects:
692 * None
693 */
696 {
703 /* Configuration check only valid for EISA adapter */
706 {
709 /*
710 * First check if revision 2 EISA controller. Rev. 1 cards used
711 * PDQ revision B, so no workaround needed in this case. Rev. 3
712 * cards used PDQ revision E, so no workaround needed in this
713 * case, either. Only Rev. 2 cards used either Rev. D or E
714 * chips, so we must verify the chip revision on Rev. 2 cards.
715 */
718 {
719 /*
720 * Revision 2 FDDI EISA controller found, so let's check PDQ
721 * revision of adapter.
722 */
725 PI_PCTRL_M_SUB_CMD,
726 PI_SUB_CMD_K_PDQ_REV_GET,
730 {
731 /*
732 * Either we couldn't determine the PDQ revision, or
733 * we determined that it is at revision D. In either case,
734 * we need to implement the workaround.
735 */
737 /* Ensure that the burst size is set to 8 longwords or less */
740 {
748 }
750 /* Ensure that full-duplex mode is not enabled */
753 }
754 }
755 }
756 }
758 \f
759 /*
760 * ===================
761 * = dfx_driver_init =
762 * ===================
763 *
764 * Overview:
765 * Initializes remaining adapter board structure information
766 * and makes sure adapter is in a safe state prior to dfx_open().
767 *
768 * Returns:
769 * Condition code
770 *
771 * Arguments:
772 * dev - pointer to device information
773 *
774 * Functional Description:
775 * This function allocates additional resources such as the host memory
776 * blocks needed by the adapter (eg. descriptor and consumer blocks).
777 * Remaining bus initialization steps are also completed. The adapter
778 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
779 * must call dfx_open() to open the adapter and bring it on-line.
780 *
781 * Return Codes:
782 * DFX_K_SUCCESS - initialization succeeded
783 * DFX_K_FAILURE - initialization failed - could not allocate memory
784 * or read adapter MAC address
785 *
786 * Assumptions:
787 * Memory allocated from pci_alloc_consistent() call is physically
788 * contiguous, locked memory.
789 *
790 * Side Effects:
791 * Adapter is reset and should be in DMA_UNAVAILABLE state before
792 * returning from this routine.
793 */
796 {
805 /* Initialize bus-specific hardware registers */
809 /*
810 * Initialize default values for configurable parameters
811 *
812 * Note: All of these parameters are ones that a user may
813 * want to customize. It'd be nice to break these
814 * out into Space.c or someplace else that's more
815 * accessible/understandable than this file.
816 */
823 /*
824 * Ensure that HW configuration is OK
825 *
826 * Note: Depending on the hardware revision, we may need to modify
827 * some of the configurable parameters to workaround hardware
828 * limitations. We'll perform this configuration check AFTER
829 * setting the parameters to their default values.
830 */
834 /* Disable PDQ interrupts first */
838 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
842 /* Read the factory MAC address from the adapter then save it */
845 PI_PCTRL_M_MLA,
846 PI_PDATA_A_MLA_K_LO,
849 {
852 }
856 PI_PCTRL_M_MLA,
857 PI_PDATA_A_MLA_K_HI,
860 {
863 }
866 /*
867 * Set current address to factory address
868 *
869 * Note: Node address override support is handled through
870 * dfx_ctl_set_mac_address.
871 */
875 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
885 else
886 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
897 /*
898 * Get memory for descriptor block, consumer block, and other buffers
899 * that need to be DMA read or written to by the adapter.
900 */
903 PI_CMD_REQ_K_SIZE_MAX +
904 PI_CMD_RSP_K_SIZE_MAX +
905 #ifndef DYNAMIC_BUFFERS
907 #endif
913 {
916 }
920 /*
921 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
922 * plus the amount of memory needed was allocated. The physical address
923 * is now 8K aligned. By carving up the memory in a specific order,
924 * we'll guarantee the alignment requirements for all other structures.
925 *
926 * Note: If the assumptions change regarding the non-paged, non-cached,
927 * physically contiguous nature of the memory block or the address
928 * alignments, then we'll need to implement a different algorithm
929 * for allocating the needed memory.
930 */
935 /* Reserve space for descriptor block */
942 /* Reserve space for command request buffer */
949 /* Reserve space for command response buffer */
956 /* Reserve space for the LLC host receive queue buffers */
961 #ifndef DYNAMIC_BUFFERS
964 #endif
966 /* Reserve space for the consumer block */
971 /* Display virtual and physical addresses if debug driver */
973 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev->name, (long)bp->descr_block_virt, bp->descr_block_phys);
974 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
975 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
976 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
977 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->cons_block_virt, bp->cons_block_phys);
980 }
982 \f
983 /*
984 * =================
985 * = dfx_adap_init =
986 * =================
987 *
988 * Overview:
989 * Brings the adapter to the link avail/link unavailable state.
990 *
991 * Returns:
992 * Condition code
993 *
994 * Arguments:
995 * bp - pointer to board information
996 * get_buffers - non-zero if buffers to be allocated
997 *
998 * Functional Description:
999 * Issues the low-level firmware/hardware calls necessary to bring
1000 * the adapter up, or to properly reset and restore adapter during
1001 * run-time.
1002 *
1003 * Return Codes:
1004 * DFX_K_SUCCESS - Adapter brought up successfully
1005 * DFX_K_FAILURE - Adapter initialization failed
1006 *
1007 * Assumptions:
1008 * bp->reset_type should be set to a valid reset type value before
1009 * calling this routine.
1010 *
1011 * Side Effects:
1012 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1013 * upon a successful return of this routine.
1014 */
1017 {
1020 /* Disable PDQ interrupts first */
1024 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1027 {
1030 }
1032 /*
1033 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1034 * so we'll acknowledge all Type 0 interrupts now before continuing.
1035 */
1039 /*
1040 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1041 *
1042 * Note: We only need to clear host copies of these registers. The PDQ reset
1043 * takes care of the on-board register values.
1044 */
1050 /* Clear consumer block before going to DMA_AVAILABLE state */
1054 /* Initialize the DMA Burst Size */
1057 PI_PCTRL_M_SUB_CMD,
1058 PI_SUB_CMD_K_BURST_SIZE_SET,
1061 {
1064 }
1066 /*
1067 * Set base address of Consumer Block
1068 *
1069 * Assumption: 32-bit physical address of consumer block is 64 byte
1070 * aligned. That is, bits 0-5 of the address must be zero.
1071 */
1074 PI_PCTRL_M_CONS_BLOCK,
1078 {
1081 }
1083 /*
1084 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1085 *
1086 * Note: We also set the literal and data swapping requirements in this
1087 * command. Since this driver presently runs on Intel platforms
1088 * which are Little Endian, we'll tell the adapter to byte swap
1089 * data only. This code will need to change when we support
1090 * Big Endian systems (eg. PowerPC).
1091 *
1092 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1093 * aligned. That is, bits 0-12 of the address must be zero.
1094 */
1097 PI_PCTRL_M_INIT,
1101 {
1104 }
1106 /* Set transmit flush timeout value */
1114 {
1117 }
1119 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1130 {
1133 }
1135 /* Initialize adapter CAM */
1138 {
1141 }
1143 /* Initialize adapter filters */
1146 {
1149 }
1151 /*
1152 * Remove any existing dynamic buffers (i.e. if the adapter is being
1153 * reinitialized)
1154 */
1159 /* Initialize receive descriptor block and produce buffers */
1162 {
1167 }
1169 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1173 {
1178 }
1180 /* Initialization succeeded, reenable PDQ interrupts */
1184 }
1186 \f
1187 /*
1188 * ============
1189 * = dfx_open =
1190 * ============
1191 *
1192 * Overview:
1193 * Opens the adapter
1194 *
1195 * Returns:
1196 * Condition code
1197 *
1198 * Arguments:
1199 * dev - pointer to device information
1200 *
1201 * Functional Description:
1202 * This function brings the adapter to an operational state.
1203 *
1204 * Return Codes:
1205 * 0 - Adapter was successfully opened
1206 * -EAGAIN - Could not register IRQ or adapter initialization failed
1207 *
1208 * Assumptions:
1209 * This routine should only be called for a device that was
1210 * initialized successfully.
1211 *
1212 * Side Effects:
1213 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1214 * if the open is successful.
1215 */
1218 {
1224 /* Register IRQ - support shared interrupts by passing device ptr */
1230 }
1232 /*
1233 * Set current address to factory MAC address
1234 *
1235 * Note: We've already done this step in dfx_driver_init.
1236 * However, it's possible that a user has set a node
1237 * address override, then closed and reopened the
1238 * adapter. Unless we reset the device address field
1239 * now, we'll continue to use the existing modified
1240 * address.
1241 */
1245 /* Clear local unicast/multicast address tables and counts */
1252 /* Disable promiscuous filter settings */
1259 /* Reset and initialize adapter */
1263 {
1267 }
1269 /* Set device structure info */
1272 }
1274 \f
1275 /*
1276 * =============
1277 * = dfx_close =
1278 * =============
1279 *
1280 * Overview:
1281 * Closes the device/module.
1282 *
1283 * Returns:
1284 * Condition code
1285 *
1286 * Arguments:
1287 * dev - pointer to device information
1288 *
1289 * Functional Description:
1290 * This routine closes the adapter and brings it to a safe state.
1291 * The interrupt service routine is deregistered with the OS.
1292 * The adapter can be opened again with another call to dfx_open().
1293 *
1294 * Return Codes:
1295 * Always return 0.
1296 *
1297 * Assumptions:
1298 * No further requests for this adapter are made after this routine is
1299 * called. dfx_open() can be called to reset and reinitialize the
1300 * adapter.
1301 *
1302 * Side Effects:
1303 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1304 * routine.
1305 */
1308 {
1313 /* Disable PDQ interrupts first */
1317 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1321 /*
1322 * Flush any pending transmit buffers
1323 *
1324 * Note: It's important that we flush the transmit buffers
1325 * BEFORE we clear our copy of the Type 2 register.
1326 * Otherwise, we'll have no idea how many buffers
1327 * we need to free.
1328 */
1332 /*
1333 * Clear Type 1 and Type 2 registers after adapter reset
1334 *
1335 * Note: Even though we're closing the adapter, it's
1336 * possible that an interrupt will occur after
1337 * dfx_close is called. Without some assurance to
1338 * the contrary we want to make sure that we don't
1339 * process receive and transmit LLC frames and update
1340 * the Type 2 register with bad information.
1341 */
1347 /* Clear consumer block for the same reason given above */
1351 /* Release all dynamically allocate skb in the receive ring. */
1355 /* Clear device structure flags */
1359 /* Deregister (free) IRQ */
1364 }
1366 \f
1367 /*
1368 * ======================
1369 * = dfx_int_pr_halt_id =
1370 * ======================
1371 *
1372 * Overview:
1373 * Displays halt id's in string form.
1374 *
1375 * Returns:
1376 * None
1377 *
1378 * Arguments:
1379 * bp - pointer to board information
1380 *
1381 * Functional Description:
1382 * Determine current halt id and display appropriate string.
1383 *
1384 * Return Codes:
1385 * None
1386 *
1387 * Assumptions:
1388 * None
1389 *
1390 * Side Effects:
1391 * None
1392 */
1395 {
1399 /* Read the latest port status */
1403 /* Display halt state transition information */
1407 {
1447 }
1448 }
1450 \f
1451 /*
1452 * ==========================
1453 * = dfx_int_type_0_process =
1454 * ==========================
1455 *
1456 * Overview:
1457 * Processes Type 0 interrupts.
1458 *
1459 * Returns:
1460 * None
1461 *
1462 * Arguments:
1463 * bp - pointer to board information
1464 *
1465 * Functional Description:
1466 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1467 * is a serious fault on the adapter, then an error message is displayed
1468 * and the adapter is reset.
1469 *
1470 * One tricky potential timing window is the rapid succession of "link avail"
1471 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1472 * interrupt must be done before reading the state from the Port Status
1473 * register. This is true because a state change could occur after reading
1474 * the data, but before acknowledging the interrupt. If this state change
1475 * does happen, it would be lost because the driver is using the old state,
1476 * and it will never know about the new state because it subsequently
1477 * acknowledges the state change interrupt.
1478 *
1479 * INCORRECT CORRECT
1480 * read type 0 int reasons read type 0 int reasons
1481 * read adapter state ack type 0 interrupts
1482 * ack type 0 interrupts read adapter state
1483 * ... process interrupt ... ... process interrupt ...
1484 *
1485 * Return Codes:
1486 * None
1487 *
1488 * Assumptions:
1489 * None
1490 *
1491 * Side Effects:
1492 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1493 * or if the port status indicates that the adapter is halted. The driver
1494 * is responsible for reinitializing the adapter with the current CAM
1495 * contents and adapter filter settings.
1496 */
1500 {
1504 /*
1505 * Read host interrupt Type 0 register to determine which Type 0
1506 * interrupts are pending. Immediately write it back out to clear
1507 * those interrupts.
1508 */
1513 /* Check for Type 0 error interrupts */
1516 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1517 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1518 {
1519 /* Check for Non-Existent Memory error */
1524 /* Check for Packet Memory Parity error */
1529 /* Check for Host Bus Parity error */
1534 /* Reset adapter and bring it back on-line */
1540 {
1544 }
1547 }
1549 /* Check for transmit flush interrupt */
1552 {
1553 /* Flush any pending xmt's and acknowledge the flush interrupt */
1558 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1561 NULL);
1562 }
1564 /* Check for adapter state change */
1567 {
1568 /* Get latest adapter state */
1572 {
1573 /*
1574 * Adapter has transitioned to HALTED state, try to reset
1575 * adapter to bring it back on-line. If reset fails,
1576 * leave the adapter in the broken state.
1577 */
1582 /* Reset adapter and bring it back on-line */
1588 {
1592 }
1594 }
1596 {
1598 }
1599 }
1600 }
1602 \f
1603 /*
1604 * ==================
1605 * = dfx_int_common =
1606 * ==================
1607 *
1608 * Overview:
1609 * Interrupt service routine (ISR)
1610 *
1611 * Returns:
1612 * None
1613 *
1614 * Arguments:
1615 * bp - pointer to board information
1616 *
1617 * Functional Description:
1618 * This is the ISR which processes incoming adapter interrupts.
1619 *
1620 * Return Codes:
1621 * None
1622 *
1623 * Assumptions:
1624 * This routine assumes PDQ interrupts have not been disabled.
1625 * When interrupts are disabled at the PDQ, the Port Status register
1626 * is automatically cleared. This routine uses the Port Status
1627 * register value to determine whether a Type 0 interrupt occurred,
1628 * so it's important that adapter interrupts are not normally
1629 * enabled/disabled at the PDQ.
1630 *
1631 * It's vital that this routine is NOT reentered for the
1632 * same board and that the OS is not in another section of
1633 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1634 * different thread.
1635 *
1636 * Side Effects:
1637 * Pending interrupts are serviced. Depending on the type of
1638 * interrupt, acknowledging and clearing the interrupt at the
1639 * PDQ involves writing a register to clear the interrupt bit
1640 * or updating completion indices.
1641 */
1644 {
1648 /* Process xmt interrupts - frequent case, so always call this routine */
1653 /* Process rcv interrupts - frequent case, so always call this routine */
1657 /*
1658 * Transmit and receive producer and completion indices are updated on the
1659 * adapter by writing to the Type 2 Producer register. Since the frequent
1660 * case is that we'll be processing either LLC transmit or receive buffers,
1661 * we'll optimize I/O writes by doing a single register write here.
1662 */
1666 /* Read PDQ Port Status register to find out which interrupts need processing */
1670 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1674 }
1676 \f
1677 /*
1678 * =================
1679 * = dfx_interrupt =
1680 * =================
1681 *
1682 * Overview:
1683 * Interrupt processing routine
1684 *
1685 * Returns:
1686 * None
1687 *
1688 * Arguments:
1689 * irq - interrupt vector
1690 * dev_id - pointer to device information
1691 * regs - pointer to registers structure
1692 *
1693 * Functional Description:
1694 * This routine calls the interrupt processing routine for this adapter. It
1695 * disables and reenables adapter interrupts, as appropriate. We can support
1696 * shared interrupts since the incoming dev_id pointer provides our device
1697 * structure context.
1698 *
1699 * Return Codes:
1700 * None
1701 *
1702 * Assumptions:
1703 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1704 * on Intel-based systems) is done by the operating system outside this
1705 * routine.
1706 *
1707 * System interrupts are enabled through this call.
1708 *
1709 * Side Effects:
1710 * Interrupts are disabled, then reenabled at the adapter.
1711 */
1714 {
1719 /* Get board pointer only if device structure is valid */
1725 /* See if we're already servicing an interrupt */
1727 /* Service adapter interrupts */
1730 {
1731 /* Disable PDQ-PFI interrupts at PFI */
1735 /* Call interrupt service routine for this adapter */
1739 /* Clear PDQ interrupt status bit and reenable interrupts */
1744 }
1745 else
1746 {
1747 /* Disable interrupts at the ESIC */
1753 /* Call interrupt service routine for this adapter */
1757 /* Reenable interrupts at the ESIC */
1762 }
1765 }
1767 \f
1768 /*
1769 * =====================
1770 * = dfx_ctl_get_stats =
1771 * =====================
1772 *
1773 * Overview:
1774 * Get statistics for FDDI adapter
1775 *
1776 * Returns:
1777 * Pointer to FDDI statistics structure
1778 *
1779 * Arguments:
1780 * dev - pointer to device information
1781 *
1782 * Functional Description:
1783 * Gets current MIB objects from adapter, then
1784 * returns FDDI statistics structure as defined
1785 * in if_fddi.h.
1786 *
1787 * Note: Since the FDDI statistics structure is
1788 * still new and the device structure doesn't
1789 * have an FDDI-specific get statistics handler,
1790 * we'll return the FDDI statistics structure as
1791 * a pointer to an Ethernet statistics structure.
1792 * That way, at least the first part of the statistics
1793 * structure can be decoded properly, and it allows
1794 * "smart" applications to perform a second cast to
1795 * decode the FDDI-specific statistics.
1796 *
1797 * We'll have to pay attention to this routine as the
1798 * device structure becomes more mature and LAN media
1799 * independent.
1800 *
1801 * Return Codes:
1802 * None
1803 *
1804 * Assumptions:
1805 * None
1806 *
1807 * Side Effects:
1808 * None
1809 */
1812 {
1815 /* Fill the bp->stats structure with driver-maintained counters */
1830 /* Get FDDI SMT MIB objects */
1836 /* Fill the bp->stats structure with the SMT MIB object values */
1838 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1842 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1857 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1861 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1862 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1867 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1868 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1869 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1870 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1874 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1891 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1896 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1897 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1902 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1903 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1910 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1911 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1931 /* Get FDDI counters */
1937 /* Fill the bp->stats structure with the FDDI counter values */
1952 }
1954 \f
1955 /*
1956 * ==============================
1957 * = dfx_ctl_set_multicast_list =
1958 * ==============================
1959 *
1960 * Overview:
1961 * Enable/Disable LLC frame promiscuous mode reception
1962 * on the adapter and/or update multicast address table.
1963 *
1964 * Returns:
1965 * None
1966 *
1967 * Arguments:
1968 * dev - pointer to device information
1969 *
1970 * Functional Description:
1971 * This routine follows a fairly simple algorithm for setting the
1972 * adapter filters and CAM:
1973 *
1974 * if IFF_PROMISC flag is set
1975 * enable LLC individual/group promiscuous mode
1976 * else
1977 * disable LLC individual/group promiscuous mode
1978 * if number of incoming multicast addresses >
1979 * (CAM max size - number of unicast addresses in CAM)
1980 * enable LLC group promiscuous mode
1981 * set driver-maintained multicast address count to zero
1982 * else
1983 * disable LLC group promiscuous mode
1984 * set driver-maintained multicast address count to incoming count
1985 * update adapter CAM
1986 * update adapter filters
1987 *
1988 * Return Codes:
1989 * None
1990 *
1991 * Assumptions:
1992 * Multicast addresses are presented in canonical (LSB) format.
1993 *
1994 * Side Effects:
1995 * On-board adapter CAM and filters are updated.
1996 */
1999 {
2004 /* Enable LLC frame promiscuous mode, if necessary */
2009 /* Else, update multicast address table */
2011 else
2012 {
2014 /*
2015 * Check whether incoming multicast address count exceeds table size
2016 *
2017 * Note: The adapters utilize an on-board 64 entry CAM for
2018 * supporting perfect filtering of multicast packets
2019 * and bridge functions when adding unicast addresses.
2020 * There is no hash function available. To support
2021 * additional multicast addresses, the all multicast
2022 * filter (LLC group promiscuous mode) must be enabled.
2023 *
2024 * The firmware reserves two CAM entries for SMT-related
2025 * multicast addresses, which leaves 62 entries available.
2026 * The following code ensures that we're not being asked
2027 * to add more than 62 addresses to the CAM. If we are,
2028 * the driver will enable the all multicast filter.
2029 * Should the number of multicast addresses drop below
2030 * the high water mark, the filter will be disabled and
2031 * perfect filtering will be used.
2032 */
2035 {
2038 }
2039 else
2040 {
2043 }
2045 /* Copy addresses to multicast address table, then update adapter CAM */
2049 {
2052 }
2054 {
2056 }
2057 else
2058 {
2059 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2060 }
2061 }
2063 /* Update adapter filters */
2066 {
2068 }
2069 else
2070 {
2072 }
2073 }
2075 \f
2076 /*
2077 * ===========================
2078 * = dfx_ctl_set_mac_address =
2079 * ===========================
2080 *
2081 * Overview:
2082 * Add node address override (unicast address) to adapter
2083 * CAM and update dev_addr field in device table.
2084 *
2085 * Returns:
2086 * None
2087 *
2088 * Arguments:
2089 * dev - pointer to device information
2090 * addr - pointer to sockaddr structure containing unicast address to add
2091 *
2092 * Functional Description:
2093 * The adapter supports node address overrides by adding one or more
2094 * unicast addresses to the adapter CAM. This is similar to adding
2095 * multicast addresses. In this routine we'll update the driver and
2096 * device structures with the new address, then update the adapter CAM
2097 * to ensure that the adapter will copy and strip frames destined and
2098 * sourced by that address.
2099 *
2100 * Return Codes:
2101 * Always returns zero.
2102 *
2103 * Assumptions:
2104 * The address pointed to by addr->sa_data is a valid unicast
2105 * address and is presented in canonical (LSB) format.
2106 *
2107 * Side Effects:
2108 * On-board adapter CAM is updated. On-board adapter filters
2109 * may be updated.
2110 */
2113 {
2117 /* Copy unicast address to driver-maintained structs and update count */
2123 /*
2124 * Verify we're not exceeding the CAM size by adding unicast address
2125 *
2126 * Note: It's possible that before entering this routine we've
2127 * already filled the CAM with 62 multicast addresses.
2128 * Since we need to place the node address override into
2129 * the CAM, we have to check to see that we're not
2130 * exceeding the CAM size. If we are, we have to enable
2131 * the LLC group (multicast) promiscuous mode filter as
2132 * in dfx_ctl_set_multicast_list.
2133 */
2136 {
2140 /* Update adapter filters */
2143 {
2145 }
2146 else
2147 {
2149 }
2150 }
2152 /* Update adapter CAM with new unicast address */
2155 {
2157 }
2158 else
2159 {
2161 }
2163 }
2165 \f
2166 /*
2167 * ======================
2168 * = dfx_ctl_update_cam =
2169 * ======================
2170 *
2171 * Overview:
2172 * Procedure to update adapter CAM (Content Addressable Memory)
2173 * with desired unicast and multicast address entries.
2174 *
2175 * Returns:
2176 * Condition code
2177 *
2178 * Arguments:
2179 * bp - pointer to board information
2180 *
2181 * Functional Description:
2182 * Updates adapter CAM with current contents of board structure
2183 * unicast and multicast address tables. Since there are only 62
2184 * free entries in CAM, this routine ensures that the command
2185 * request buffer is not overrun.
2186 *
2187 * Return Codes:
2188 * DFX_K_SUCCESS - Request succeeded
2189 * DFX_K_FAILURE - Request failed
2190 *
2191 * Assumptions:
2192 * All addresses being added (unicast and multicast) are in canonical
2193 * order.
2194 *
2195 * Side Effects:
2196 * On-board adapter CAM is updated.
2197 */
2200 {
2204 /*
2205 * Fill in command request information
2206 *
2207 * Note: Even though both the unicast and multicast address
2208 * table entries are stored as contiguous 6 byte entries,
2209 * the firmware address filter set command expects each
2210 * entry to be two longwords (8 bytes total). We must be
2211 * careful to only copy the six bytes of each unicast and
2212 * multicast table entry into each command entry. This
2213 * is also why we must first clear the entire command
2214 * request buffer.
2215 */
2221 /* Now add unicast addresses to command request buffer, if any */
2224 {
2226 {
2229 }
2230 }
2232 /* Now add multicast addresses to command request buffer, if any */
2235 {
2237 {
2240 }
2241 }
2243 /* Issue command to update adapter CAM, then return */
2248 }
2250 \f
2251 /*
2252 * ==========================
2253 * = dfx_ctl_update_filters =
2254 * ==========================
2255 *
2256 * Overview:
2257 * Procedure to update adapter filters with desired
2258 * filter settings.
2259 *
2260 * Returns:
2261 * Condition code
2262 *
2263 * Arguments:
2264 * bp - pointer to board information
2265 *
2266 * Functional Description:
2267 * Enables or disables filter using current filter settings.
2268 *
2269 * Return Codes:
2270 * DFX_K_SUCCESS - Request succeeded.
2271 * DFX_K_FAILURE - Request failed.
2272 *
2273 * Assumptions:
2274 * We must always pass up packets destined to the broadcast
2275 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2276 * broadcast filter enabled.
2277 *
2278 * Side Effects:
2279 * On-board adapter filters are updated.
2280 */
2283 {
2286 /* Fill in command request information */
2290 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2295 /* Initialize LLC Individual/Group Promiscuous filter */
2300 /* Initialize LLC Group Promiscuous filter */
2305 /* Terminate the item code list */
2309 /* Issue command to update adapter filters, then return */
2314 }
2316 \f
2317 /*
2318 * ======================
2319 * = dfx_hw_dma_cmd_req =
2320 * ======================
2321 *
2322 * Overview:
2323 * Sends PDQ DMA command to adapter firmware
2324 *
2325 * Returns:
2326 * Condition code
2327 *
2328 * Arguments:
2329 * bp - pointer to board information
2330 *
2331 * Functional Description:
2332 * The command request and response buffers are posted to the adapter in the manner
2333 * described in the PDQ Port Specification:
2334 *
2335 * 1. Command Response Buffer is posted to adapter.
2336 * 2. Command Request Buffer is posted to adapter.
2337 * 3. Command Request consumer index is polled until it indicates that request
2338 * buffer has been DMA'd to adapter.
2339 * 4. Command Response consumer index is polled until it indicates that response
2340 * buffer has been DMA'd from adapter.
2341 *
2342 * This ordering ensures that a response buffer is already available for the firmware
2343 * to use once it's done processing the request buffer.
2344 *
2345 * Return Codes:
2346 * DFX_K_SUCCESS - DMA command succeeded
2347 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2348 * DFX_K_HW_TIMEOUT - DMA command timed out
2349 *
2350 * Assumptions:
2351 * Command request buffer has already been filled with desired DMA command.
2352 *
2353 * Side Effects:
2354 * None
2355 */
2358 {
2362 /* Make sure the adapter is in a state that we can issue the DMA command in */
2371 /* Put response buffer on the command response queue */
2377 /* Bump (and wrap) the producer index and write out to register */
2383 /* Put request buffer on the command request queue */
2389 /* Bump (and wrap) the producer index and write out to register */
2395 /*
2396 * Here we wait for the command request consumer index to be equal
2397 * to the producer, indicating that the adapter has DMAed the request.
2398 */
2401 {
2405 }
2409 /* Bump (and wrap) the completion index and write out to register */
2415 /*
2416 * Here we wait for the command response consumer index to be equal
2417 * to the producer, indicating that the adapter has DMAed the response.
2418 */
2421 {
2425 }
2429 /* Bump (and wrap) the completion index and write out to register */
2435 }
2437 \f
2438 /*
2439 * ========================
2440 * = dfx_hw_port_ctrl_req =
2441 * ========================
2442 *
2443 * Overview:
2444 * Sends PDQ port control command to adapter firmware
2445 *
2446 * Returns:
2447 * Host data register value in host_data if ptr is not NULL
2448 *
2449 * Arguments:
2450 * bp - pointer to board information
2451 * command - port control command
2452 * data_a - port data A register value
2453 * data_b - port data B register value
2454 * host_data - ptr to host data register value
2455 *
2456 * Functional Description:
2457 * Send generic port control command to adapter by writing
2458 * to various PDQ port registers, then polling for completion.
2459 *
2460 * Return Codes:
2461 * DFX_K_SUCCESS - port control command succeeded
2462 * DFX_K_HW_TIMEOUT - port control command timed out
2463 *
2464 * Assumptions:
2465 * None
2466 *
2467 * Side Effects:
2468 * None
2469 */
2473 PI_UINT32 command,
2474 PI_UINT32 data_a,
2475 PI_UINT32 data_b,
2476 PI_UINT32 *host_data
2477 )
2479 {
2483 /* Set Command Error bit in command longword */
2487 /* Issue port command to the adapter */
2493 /* Now wait for command to complete */
2497 else
2501 {
2506 }
2510 /*
2511 * If the address of host_data is non-zero, assume caller has supplied a
2512 * non NULL pointer, and return the contents of the HOST_DATA register in
2513 * it.
2514 */
2519 }
2521 \f
2522 /*
2523 * =====================
2524 * = dfx_hw_adap_reset =
2525 * =====================
2526 *
2527 * Overview:
2528 * Resets adapter
2529 *
2530 * Returns:
2531 * None
2532 *
2533 * Arguments:
2534 * bp - pointer to board information
2535 * type - type of reset to perform
2536 *
2537 * Functional Description:
2538 * Issue soft reset to adapter by writing to PDQ Port Reset
2539 * register. Use incoming reset type to tell adapter what
2540 * kind of reset operation to perform.
2541 *
2542 * Return Codes:
2543 * None
2544 *
2545 * Assumptions:
2546 * This routine merely issues a soft reset to the adapter.
2547 * It is expected that after this routine returns, the caller
2548 * will appropriately poll the Port Status register for the
2549 * adapter to enter the proper state.
2550 *
2551 * Side Effects:
2552 * Internal adapter registers are cleared.
2553 */
2557 PI_UINT32 type
2558 )
2560 {
2561 /* Set Reset type and assert reset */
2566 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2570 /* Deassert reset */
2573 }
2575 \f
2576 /*
2577 * ========================
2578 * = dfx_hw_adap_state_rd =
2579 * ========================
2580 *
2581 * Overview:
2582 * Returns current adapter state
2583 *
2584 * Returns:
2585 * Adapter state per PDQ Port Specification
2586 *
2587 * Arguments:
2588 * bp - pointer to board information
2589 *
2590 * Functional Description:
2591 * Reads PDQ Port Status register and returns adapter state.
2592 *
2593 * Return Codes:
2594 * None
2595 *
2596 * Assumptions:
2597 * None
2598 *
2599 * Side Effects:
2600 * None
2601 */
2604 {
2609 }
2611 \f
2612 /*
2613 * =====================
2614 * = dfx_hw_dma_uninit =
2615 * =====================
2616 *
2617 * Overview:
2618 * Brings adapter to DMA_UNAVAILABLE state
2619 *
2620 * Returns:
2621 * Condition code
2622 *
2623 * Arguments:
2624 * bp - pointer to board information
2625 * type - type of reset to perform
2626 *
2627 * Functional Description:
2628 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2629 * 1. Set reset type bit in Port Data A Register then reset adapter.
2630 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2631 *
2632 * Return Codes:
2633 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2634 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2635 *
2636 * Assumptions:
2637 * None
2638 *
2639 * Side Effects:
2640 * Internal adapter registers are cleared.
2641 */
2644 {
2647 /* Set reset type bit and reset adapter */
2651 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2654 {
2658 }
2662 }
2663 \f
2664 /*
2665 * Align an sk_buff to a boundary power of 2
2666 *
2667 */
2670 {
2677 }
2679 \f
2680 /*
2681 * ================
2682 * = dfx_rcv_init =
2683 * ================
2684 *
2685 * Overview:
2686 * Produces buffers to adapter LLC Host receive descriptor block
2687 *
2688 * Returns:
2689 * None
2690 *
2691 * Arguments:
2692 * bp - pointer to board information
2693 * get_buffers - non-zero if buffers to be allocated
2694 *
2695 * Functional Description:
2696 * This routine can be called during dfx_adap_init() or during an adapter
2697 * reset. It initializes the descriptor block and produces all allocated
2698 * LLC Host queue receive buffers.
2699 *
2700 * Return Codes:
2701 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2702 * dynamic buffer allocation). If the buffer allocation failed, the
2703 * already allocated buffers will not be released and the caller should do
2704 * this.
2705 *
2706 * Assumptions:
2707 * The PDQ has been reset and the adapter and driver maintained Type 2
2708 * register indices are cleared.
2709 *
2710 * Side Effects:
2711 * Receive buffers are posted to the adapter LLC queue and the adapter
2712 * is notified.
2713 */
2716 {
2719 /*
2720 * Since each receive buffer is a single fragment of same length, initialize
2721 * first longword in each receive descriptor for entire LLC Host descriptor
2722 * block. Also initialize second longword in each receive descriptor with
2723 * physical address of receive buffer. We'll always allocate receive
2724 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2725 * block and produce new receive buffers by simply updating the receive
2726 * producer index.
2727 *
2728 * Assumptions:
2729 * To support all shipping versions of PDQ, the receive buffer size
2730 * must be mod 128 in length and the physical address must be 128 byte
2731 * aligned. In other words, bits 0-6 of the length and address must
2732 * be zero for the following descriptor field entries to be correct on
2733 * all PDQ-based boards. We guaranteed both requirements during
2734 * driver initialization when we allocated memory for the receive buffers.
2735 */
2738 #ifdef DYNAMIC_BUFFERS
2741 {
2747 /*
2748 * align to 128 bytes for compatibility with
2749 * the old EISA boards.
2750 */
2755 NEW_SKB_SIZE,
2756 PCI_DMA_FROMDEVICE);
2757 /*
2758 * p_rcv_buff_va is only used inside the
2759 * kernel so we put the skb pointer here.
2760 */
2762 }
2763 #else
2766 {
2769 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2771 }
2772 #endif
2773 }
2775 /* Update receive producer and Type 2 register */
2780 }
2782 \f
2783 /*
2784 * =========================
2785 * = dfx_rcv_queue_process =
2786 * =========================
2787 *
2788 * Overview:
2789 * Process received LLC frames.
2790 *
2791 * Returns:
2792 * None
2793 *
2794 * Arguments:
2795 * bp - pointer to board information
2796 *
2797 * Functional Description:
2798 * Received LLC frames are processed until there are no more consumed frames.
2799 * Once all frames are processed, the receive buffers are returned to the
2800 * adapter. Note that this algorithm fixes the length of time that can be spent
2801 * in this routine, because there are a fixed number of receive buffers to
2802 * process and buffers are not produced until this routine exits and returns
2803 * to the ISR.
2804 *
2805 * Return Codes:
2806 * None
2807 *
2808 * Assumptions:
2809 * None
2810 *
2811 * Side Effects:
2812 * None
2813 */
2816 DFX_board_t *bp
2817 )
2819 {
2825 /* Service all consumed LLC receive frames */
2829 {
2830 /* Process any errors */
2835 #ifdef DYNAMIC_BUFFERS
2837 #else
2839 #endif
2843 {
2846 else
2848 }
2849 else
2850 {
2853 /* The frame was received without errors - verify packet length */
2860 #ifdef DYNAMIC_BUFFERS
2872 NEW_SKB_SIZE,
2873 PCI_DMA_FROMDEVICE);
2879 NEW_SKB_SIZE,
2880 PCI_DMA_FROMDEVICE);
2884 #endif
2887 {
2891 }
2893 #ifndef DYNAMIC_BUFFERS
2895 #endif
2896 {
2897 /* Receive buffer allocated, pass receive packet up */
2900 }
2910 /* Update the rcv counters */
2915 }
2916 }
2917 }
2919 /*
2920 * Advance the producer (for recycling) and advance the completion
2921 * (for servicing received frames). Note that it is okay to
2922 * advance the producer without checking that it passes the
2923 * completion index because they are both advanced at the same
2924 * rate.
2925 */
2929 }
2930 }
2932 \f
2933 /*
2934 * =====================
2935 * = dfx_xmt_queue_pkt =
2936 * =====================
2937 *
2938 * Overview:
2939 * Queues packets for transmission
2940 *
2941 * Returns:
2942 * Condition code
2943 *
2944 * Arguments:
2945 * skb - pointer to sk_buff to queue for transmission
2946 * dev - pointer to device information
2947 *
2948 * Functional Description:
2949 * Here we assume that an incoming skb transmit request
2950 * is contained in a single physically contiguous buffer
2951 * in which the virtual address of the start of packet
2952 * (skb->data) can be converted to a physical address
2953 * by using pci_map_single().
2954 *
2955 * Since the adapter architecture requires a three byte
2956 * packet request header to prepend the start of packet,
2957 * we'll write the three byte field immediately prior to
2958 * the FC byte. This assumption is valid because we've
2959 * ensured that dev->hard_header_len includes three pad
2960 * bytes. By posting a single fragment to the adapter,
2961 * we'll reduce the number of descriptor fetches and
2962 * bus traffic needed to send the request.
2963 *
2964 * Also, we can't free the skb until after it's been DMA'd
2965 * out by the adapter, so we'll queue it in the driver and
2966 * return it in dfx_xmt_done.
2967 *
2968 * Return Codes:
2969 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2970 * 1 - caller should requeue the sk_buff for later transmission
2971 *
2972 * Assumptions:
2973 * First and foremost, we assume the incoming skb pointer
2974 * is NOT NULL and is pointing to a valid sk_buff structure.
2975 *
2976 * The outgoing packet is complete, starting with the
2977 * frame control byte including the last byte of data,
2978 * but NOT including the 4 byte CRC. We'll let the
2979 * adapter hardware generate and append the CRC.
2980 *
2981 * The entire packet is stored in one physically
2982 * contiguous buffer which is not cached and whose
2983 * 32-bit physical address can be determined.
2984 *
2985 * It's vital that this routine is NOT reentered for the
2986 * same board and that the OS is not in another section of
2987 * code (eg. dfx_int_common) for the same board on a
2988 * different thread.
2989 *
2990 * Side Effects:
2991 * None
2992 */
2997 )
2999 {
3008 /*
3009 * Verify that incoming transmit request is OK
3010 *
3011 * Note: The packet size check is consistent with other
3012 * Linux device drivers, although the correct packet
3013 * size should be verified before calling the
3014 * transmit routine.
3015 */
3018 {
3025 }
3026 /*
3027 * See if adapter link is available, if not, free buffer
3028 *
3029 * Note: If the link isn't available, free buffer and return 0
3030 * rather than tell the upper layer to requeue the packet.
3031 * The methodology here is that by the time the link
3032 * becomes available, the packet to be sent will be
3033 * fairly stale. By simply dropping the packet, the
3034 * higher layer protocols will eventually time out
3035 * waiting for response packets which it won't receive.
3036 */
3039 {
3042 else
3043 {
3048 }
3049 }
3053 /* Get the current producer and the next free xmt data descriptor */
3058 /*
3059 * Get pointer to auxiliary queue entry to contain information
3060 * for this packet.
3061 *
3062 * Note: The current xmt producer index will become the
3063 * current xmt completion index when we complete this
3064 * packet later on. So, we'll get the pointer to the
3065 * next auxiliary queue entry now before we bump the
3066 * producer index.
3067 */
3071 /* Write the three PRH bytes immediately before the FC byte */
3078 /*
3079 * Write the descriptor with buffer info and bump producer
3080 *
3081 * Note: Since we need to start DMA from the packet request
3082 * header, we'll add 3 bytes to the DMA buffer length,
3083 * and we'll determine the physical address of the
3084 * buffer from the PRH, not skb->data.
3085 *
3086 * Assumptions:
3087 * 1. Packet starts with the frame control (FC) byte
3088 * at skb->data.
3089 * 2. The 4-byte CRC is not appended to the buffer or
3090 * included in the length.
3091 * 3. Packet length (skb->len) is from FC to end of
3092 * data, inclusive.
3093 * 4. The packet length does not exceed the maximum
3094 * FDDI LLC frame length of 4491 bytes.
3095 * 5. The entire packet is contained in a physically
3096 * contiguous, non-cached, locked memory space
3097 * comprised of a single buffer pointed to by
3098 * skb->data.
3099 * 6. The physical address of the start of packet
3100 * can be determined from the virtual address
3101 * by using pci_map_single() and is only 32-bits
3102 * wide.
3103 */
3105 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3109 /*
3110 * Verify that descriptor is actually available
3111 *
3112 * Note: If descriptor isn't available, return 1 which tells
3113 * the upper layer to requeue the packet for later
3114 * transmission.
3115 *
3116 * We need to ensure that the producer never reaches the
3117 * completion, except to indicate that the queue is empty.
3118 */
3121 {
3125 }
3127 /*
3128 * Save info for this packet for xmt done indication routine
3129 *
3130 * Normally, we'd save the producer index in the p_xmt_drv_descr
3131 * structure so that we'd have it handy when we complete this
3132 * packet later (in dfx_xmt_done). However, since the current
3133 * transmit architecture guarantees a single fragment for the
3134 * entire packet, we can simply bump the completion index by
3135 * one (1) for each completed packet.
3136 *
3137 * Note: If this assumption changes and we're presented with
3138 * an inconsistent number of transmit fragments for packet
3139 * data, we'll need to modify this code to save the current
3140 * transmit producer index.
3141 */
3145 /* Update Type 2 register */
3152 }
3154 \f
3155 /*
3156 * ================
3157 * = dfx_xmt_done =
3158 * ================
3159 *
3160 * Overview:
3161 * Processes all frames that have been transmitted.
3162 *
3163 * Returns:
3164 * None
3165 *
3166 * Arguments:
3167 * bp - pointer to board information
3168 *
3169 * Functional Description:
3170 * For all consumed transmit descriptors that have not
3171 * yet been completed, we'll free the skb we were holding
3172 * onto using dev_kfree_skb and bump the appropriate
3173 * counters.
3174 *
3175 * Return Codes:
3176 * None
3177 *
3178 * Assumptions:
3179 * The Type 2 register is not updated in this routine. It is
3180 * assumed that it will be updated in the ISR when dfx_xmt_done
3181 * returns.
3182 *
3183 * Side Effects:
3184 * None
3185 */
3188 {
3194 /* Service all consumed transmit frames */
3198 {
3199 /* Get pointer to the transmit driver descriptor block information */
3203 /* Increment transmit counters */
3208 /* Return skb to operating system */
3213 PCI_DMA_TODEVICE);
3216 /*
3217 * Move to start of next packet by updating completion index
3218 *
3219 * Here we assume that a transmit packet request is always
3220 * serviced by posting one fragment. We can therefore
3221 * simplify the completion code by incrementing the
3222 * completion index by one. This code will need to be
3223 * modified if this assumption changes. See comments
3224 * in dfx_xmt_queue_pkt for more details.
3225 */
3228 freed++;
3229 }
3231 }
3233 \f
3234 /*
3235 * =================
3236 * = dfx_rcv_flush =
3237 * =================
3238 *
3239 * Overview:
3240 * Remove all skb's in the receive ring.
3241 *
3242 * Returns:
3243 * None
3244 *
3245 * Arguments:
3246 * bp - pointer to board information
3247 *
3248 * Functional Description:
3249 * Free's all the dynamically allocated skb's that are
3250 * currently attached to the device receive ring. This
3251 * function is typically only used when the device is
3252 * initialized or reinitialized.
3253 *
3254 * Return Codes:
3255 * None
3256 *
3257 * Side Effects:
3258 * None
3259 */
3260 #ifdef DYNAMIC_BUFFERS
3262 {
3267 {
3273 }
3275 }
3276 #else
3278 {
3279 }
3282 /*
3283 * =================
3284 * = dfx_xmt_flush =
3285 * =================
3286 *
3287 * Overview:
3288 * Processes all frames whether they've been transmitted
3289 * or not.
3290 *
3291 * Returns:
3292 * None
3293 *
3294 * Arguments:
3295 * bp - pointer to board information
3296 *
3297 * Functional Description:
3298 * For all produced transmit descriptors that have not
3299 * yet been completed, we'll free the skb we were holding
3300 * onto using dev_kfree_skb and bump the appropriate
3301 * counters. Of course, it's possible that some of
3302 * these transmit requests actually did go out, but we
3303 * won't make that distinction here. Finally, we'll
3304 * update the consumer index to match the producer.
3305 *
3306 * Return Codes:
3307 * None
3308 *
3309 * Assumptions:
3310 * This routine does NOT update the Type 2 register. It
3311 * is assumed that this routine is being called during a
3312 * transmit flush interrupt, or a shutdown or close routine.
3313 *
3314 * Side Effects:
3315 * None
3316 */
3319 {
3324 /* Flush all outstanding transmit frames */
3327 {
3328 /* Get pointer to the transmit driver descriptor block information */
3332 /* Return skb to operating system */
3337 PCI_DMA_TODEVICE);
3340 /* Increment transmit error counter */
3344 /*
3345 * Move to start of next packet by updating completion index
3346 *
3347 * Here we assume that a transmit packet request is always
3348 * serviced by posting one fragment. We can therefore
3349 * simplify the completion code by incrementing the
3350 * completion index by one. This code will need to be
3351 * modified if this assumption changes. See comments
3352 * in dfx_xmt_queue_pkt for more details.
3353 */
3356 }
3358 /* Update the transmit consumer index in the consumer block */
3363 }
3366 {
3375 #ifndef DYNAMIC_BUFFERS
3377 #endif
3384 }
3387 {
3392 }
3397 };
3405 };
3412 {
3416 {
3424 }
3425 }
3428 {
3431 /* when a module, this is printed whether or not devices are found in probe */
3432 #ifdef MODULE
3434 #endif
3443 }
3446 {
3452 }
3458 \f
3459 /*
3460 * Local variables:
3461 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3462 * End:
3463 */