MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / char / cipher / mxhw_crypto_engine.h
blob7e412174cf8a72b6fb02664101d11a340807e4a6
1 #ifndef _H_MXHW_CRYPTO_ENGINE
2 #define _H_MXHW_CRYPTO_ENGINE
4 #include "mxhw_crypto_driver.h"
5 /* memory offsets of registers */
6 #define _REG_RW_MXCIPHER_CTRL 0x0
7 #define _REG_RO_IOFIFO_INFO 0x8
8 #define _REG_RO_PARITY_INFO 0xC
9 #define _REG_RW_MXCIPHER_KEY0 0x10
10 #define _REG_RW_MXCIPHER_IVIN0 0x30
11 #define _REG_RW_DMA_ADDR_SURC 0x48
12 #define _REG_RW_DMA_ADDR_DEST 0x4C
13 #define _REG_RW_DMA_DATA_SIZE 0x50
14 #define _REG_RW_DMA_ENGN_CTRL 0x54
15 #define _REG_RW_IOFIFO_THRD 0x58
16 #define _REG_RW_INTRPT_ENBL 0x5C
17 #define _REG_RO_INTRPT_PREV 0x60
18 #define _REG_RO_INTRPT_POST 0x64
19 #define _REG_WO_INTRPT_CLEAR 0x68
20 #define _REG_RO_REVISION_NUM 0x70
21 #define _REG_RO_IOFIFO_DEPTH 0x74
22 #define _REG_RO_MXCIPHER_IVOUT0 0x80
24 /* cipher control in bits */
25 #define _BIT_RW_MXCIPHER_PRTY_ENBL 0x0 //0x100
26 #define _BIT_RW_MXCIPHER_IVEC_ENBL 0x80
28 #define _BIT_RW_MXCIPHER_MODE_ECB 0x00
29 #define _BIT_RW_MXCIPHER_MODE_CBC (0x10|_BIT_RW_MXCIPHER_IVEC_ENBL)
30 #define _BIT_RW_MXCIPHER_MODE_CTR (0x20|_BIT_RW_MXCIPHER_IVEC_ENBL)
31 #define _BIT_RW_MXCIPHER_MODE_CFB (0x40|_BIT_RW_MXCIPHER_IVEC_ENBL)
32 #define _BIT_RW_MXCIPHER_MODE_OFB (0x50|_BIT_RW_MXCIPHER_IVEC_ENBL)
33 #define _BIT_RW_MXCIPHER_ALGO_DES 0x0
34 #define _BIT_RW_MXCIPHER_ALGO_3DES 0x2
35 #define _BIT_RW_MXCIPHER_ALGO_AES128 0x8
36 #define _BIT_RW_MXCIPHER_ALGO_AES192 0xa
37 #define _BIT_RW_MXCIPHER_ALGO_AES256 0xc
38 #define _BIT_RW_MXCIPHER_TYPE_ENC 0
39 #define _BIT_RW_MXCIPHER_TYPE_DEC 1
41 #define _BIT_RW_DMA_ENGN_ENBL 0x1
42 #define _BIT_RW_DMA_ENGN_DSBL 0x100
43 #define _BIT_RW_IFIFO_THREHOLD 0x1
44 #define _BIT_RW_OFIFO_THREHOLD 0x100
46 #define _BIT_RW_INTRPT_DONE 0x1
47 #define _BIT_RW_INTRPT_ERR 0x2
48 #define _BIT_RW_INTRPT_STOP 0x4
49 #define _BIT_RO_INTRPT_DONE _BIT_RW_INTRPT_DONE
50 #define _BIT_RO_INTRPT_ERR _BIT_RO_INTRPT_ERR
51 #define _BIT_RO_INTRPT_STOP _BIT_RW_INTRPT_STOP
53 /* FIFO status in bits */
54 #define _RO_FIFO_IN_EMPTY 0x0
55 #define _RO_FIFO_IN_FULL 0x1
56 #define _RO_FIFO_OUT_EMPTY 0x2
57 #define _RO_FIFO_OUT_FULL 0x4
58 #define _RO_FIFO_NASK_COUN_IN 0xff0000
59 #define _RO_FIFO_NASK_COUN_OUT 0xff000000
61 #endif