| blob | 66b7dd74ebafbd186aaf69d3dff48ca4dd86d9c8 |
1 /*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/config.h>
11 #include <linux/linkage.h>
13 /*
14 * Debugging stuff
15 *
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
19 */
20 #ifdef DEBUG
21 #if defined(CONFIG_DEBUG_DC21285_PORT)
22 .macro loadsp, rb
23 mov \rb, #0x42000000
24 .endm
25 .macro writeb, rb
26 str \rb, [r3, #0x160]
27 .endm
28 #elif defined(CONFIG_DEBUG_ICEDCC)
29 .macro loadsp, rb
30 .endm
31 .macro writeb, rb
32 mcr p14, 0, \rb, c0, c1, 0
33 .endm
34 #elif defined(CONFIG_FOOTBRIDGE)
35 .macro loadsp, rb
36 mov \rb, #0x7c000000
37 .endm
38 .macro writeb, rb
39 strb \rb, [r3, #0x3f8]
40 .endm
41 #elif defined(CONFIG_ARCH_RPC)
42 .macro loadsp, rb
43 mov \rb, #0x03000000
44 orr \rb, \rb, #0x00010000
45 .endm
46 .macro writeb, rb
47 strb \rb, [r3, #0x3f8 << 2]
48 .endm
49 #elif defined(CONFIG_ARCH_INTEGRATOR)
50 .macro loadsp, rb
51 mov \rb, #0x16000000
52 .endm
53 .macro writeb, rb
54 strb \rb, [r3, #0]
55 .endm
56 #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
57 .macro loadsp, rb
58 mov \rb, #0x40000000
59 orr \rb, \rb, #0x00100000
60 .endm
61 .macro writeb, rb
62 strb \rb, [r3, #0]
63 .endm
64 #elif defined(CONFIG_ARCH_SA1100)
65 .macro loadsp, rb
66 mov \rb, #0x80000000 @ physical base address
67 # if defined(CONFIG_DEBUG_LL_SER3)
68 add \rb, \rb, #0x00050000 @ Ser3
69 # else
70 add \rb, \rb, #0x00010000 @ Ser1
71 # endif
72 .endm
73 .macro writeb, rb
74 str \rb, [r3, #0x14] @ UTDR
75 .endm
76 #elif defined(CONFIG_ARCH_IXP4XX)
77 .macro loadsp, rb
78 mov \rb, #0xc8000000
79 .endm
80 .macro writeb, rb
81 str \rb, [r3, #0]
82 #elif defined(CONFIG_ARCH_IXP2000)
83 .macro loadsp, rb
84 mov \rb, #0xc0000000
85 orr \rb, \rb, #0x00030000
86 .endm
87 .macro writeb, rb
88 str \rb, [r3, #0]
89 .endm
90 #elif defined(CONFIG_ARCH_LH7A40X)
91 .macro loadsp, rb
92 ldr \rb, =0x80000700 @ UART2 UARTBASE
93 .endm
94 .macro writeb, rb
95 strb \rb, [r3, #0]
96 .endm
97 #elif defined(CONFIG_ARCH_OMAP)
98 .macro loadsp, rb
99 mov \rb, #0xff000000 @ physical base address
100 add \rb, \rb, #0x00fb0000
101 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
102 add \rb, \rb, #0x00000800
103 #endif
104 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
105 add \rb, \rb, #0x00009000
106 #endif
107 .endm
108 .macro writeb, rb
109 strb \rb, [r3]
110 .endm
111 #elif defined(CONFIG_ARCH_IOP331)
112 .macro loadsp, rb
113 mov \rb, #0xff000000
114 orr \rb, \rb, #0x00ff0000
115 orr \rb, \rb, #0x0000f700 @ location of the UART
116 .endm
117 .macro writeb, rb
118 str \rb, [r3, #0]
119 .endm
120 #else
121 #error no serial architecture defined
122 #endif
123 #endif
125 .macro kputc,val
126 mov r0, \val
127 bl putc
128 .endm
130 .macro kphex,val,len
131 mov r0, \val
132 mov r1, #\len
133 bl phex
134 .endm
136 .macro debug_reloc_start
137 #ifdef DEBUG
138 kputc #'\n'
139 kphex r6, 8 /* processor id */
140 kputc #':'
141 kphex r7, 8 /* architecture id */
142 kputc #':'
143 mrc p15, 0, r0, c1, c0
144 kphex r0, 8 /* control reg */
145 kputc #'\n'
146 kphex r5, 8 /* decompressed kernel start */
147 kputc #'-'
148 kphex r8, 8 /* decompressed kernel end */
149 kputc #'>'
150 kphex r4, 8 /* kernel execution address */
151 kputc #'\n'
152 #endif
153 .endm
155 .macro debug_reloc_end
156 #ifdef DEBUG
157 kphex r5, 8 /* end of kernel */
158 kputc #'\n'
159 mov r0, r4
160 bl memdump /* dump 256 bytes at start of kernel */
161 #endif
162 .endm
164 .section ".start", #alloc, #execinstr
165 /*
166 * sort out different calling conventions
167 */
168 .align
169 start:
170 .type start,#function
171 .rept 8
172 mov r0, r0
173 .endr
175 b 1f
176 .word 0x016f2818 @ Magic numbers to help the loader
177 .word start @ absolute load/run zImage address
178 .word _edata @ zImage end address
179 1: mov r7, r1 @ save architecture ID
180 mov r8, #0 @ save r0
181 // following mask by Victor Yu. 06-08-2005
182 #if 0
183 mov r2, #0xc8000000
184 mov r3, #'a'
185 str r3, [r2]
186 #endif
187 // above mask by Victor Yu. 06-08-2005
189 #ifndef __ARM_ARCH_2__
190 /*
191 * Booting from Angel - need to enter SVC mode and disable
192 * FIQs/IRQs (numeric definitions from angel arm.h source).
193 * We only do this if we were in user mode on entry.
194 */
195 mrs r2, cpsr @ get current mode
196 tst r2, #3 @ not user?
197 bne not_angel
198 mov r0, #0x17 @ angel_SWIreason_EnterSVC
199 swi 0x123456 @ angel_SWI_ARM
200 not_angel:
201 mrs r2, cpsr @ turn off interrupts to
202 orr r2, r2, #0xc0 @ prevent angel from running
203 msr cpsr_c, r2
204 #else
205 teqp pc, #0x0c000003 @ turn off interrupts
206 #endif
208 /*
209 * Note that some cache flushing and other stuff may
210 * be needed here - is there an Angel SWI call for this?
211 */
213 /*
214 * some architecture specific code can be inserted
215 * by the linker here, but it should preserve r7 and r8.
216 */
218 .text
219 adr r0, LC0
220 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
221 subs r0, r0, r1 @ calculate the delta offset
223 @ if delta is zero, we are
224 beq not_relocated @ running at the address we
225 @ were linked at.
227 /*
228 * We're running at a different address. We need to fix
229 * up various pointers:
230 * r5 - zImage base address
231 * r6 - GOT start
232 * ip - GOT end
233 */
234 add r5, r5, r0
235 add r6, r6, r0
236 add ip, ip, r0
238 #ifndef CONFIG_ZBOOT_ROM
239 /*
240 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
241 * we need to fix up pointers into the BSS region.
242 * r2 - BSS start
243 * r3 - BSS end
244 * sp - stack pointer
245 */
246 add r2, r2, r0
247 add r3, r3, r0
248 add sp, sp, r0
250 /*
251 * Relocate all entries in the GOT table.
252 */
253 1: ldr r1, [r6, #0] @ relocate entries in the GOT
254 add r1, r1, r0 @ table. This fixes up the
255 str r1, [r6], #4 @ C references.
256 cmp r6, ip
257 blo 1b
258 #else
260 /*
261 * Relocate entries in the GOT table. We only relocate
262 * the entries that are outside the (relocated) BSS region.
263 */
264 1: ldr r1, [r6, #0] @ relocate entries in the GOT
265 cmp r1, r2 @ entry < bss_start ||
266 cmphs r3, r1 @ _end < entry
267 addlo r1, r1, r0 @ table. This fixes up the
268 str r1, [r6], #4 @ C references.
269 cmp r6, ip
270 blo 1b
271 #endif
273 not_relocated: mov r0, #0
274 1: str r0, [r2], #4 @ clear bss
275 str r0, [r2], #4
276 str r0, [r2], #4
277 str r0, [r2], #4
278 cmp r2, r3
279 blo 1b
281 /*
282 * The C runtime environment should now be setup
283 * sufficiently. Turn the cache on, set up some
284 * pointers, and start decompressing.
285 */
286 bl cache_on
288 mov r1, sp @ malloc space above stack
289 add r2, sp, #0x10000 @ 64k max
291 /*
292 * Check to see if we will overwrite ourselves.
293 * r4 = final kernel address
294 * r5 = start of this image
295 * r2 = end of malloc space (and therefore this image)
296 * We basically want:
297 * r4 >= r2 -> OK
298 * r4 + image length <= r5 -> OK
299 */
300 cmp r4, r2
301 bhs wont_overwrite
302 add r0, r4, #4096*1024 @ 4MB largest kernel size
303 cmp r0, r5
304 bls wont_overwrite
306 mov r5, r2 @ decompress after malloc space
307 mov r0, r5
308 mov r3, r7
309 bl decompress_kernel
311 add r0, r0, #127
312 bic r0, r0, #127 @ align the kernel length
313 /*
314 * r0 = decompressed kernel length
315 * r1-r3 = unused
316 * r4 = kernel execution address
317 * r5 = decompressed kernel start
318 * r6 = processor ID
319 * r7 = architecture ID
320 * r8-r14 = unused
321 */
322 add r1, r5, r0 @ end of decompressed kernel
323 adr r2, reloc_start
324 ldr r3, LC1
325 add r3, r2, r3
326 1: ldmia r2!, {r8 - r13} @ copy relocation code
327 stmia r1!, {r8 - r13}
328 ldmia r2!, {r8 - r13}
329 stmia r1!, {r8 - r13}
330 cmp r2, r3
331 blo 1b
333 bl cache_clean_flush
334 add pc, r5, r0 @ call relocation code
336 /*
337 * We're not in danger of overwriting ourselves. Do this the simple way.
338 *
339 * r4 = kernel execution address
340 * r7 = architecture ID
341 */
342 wont_overwrite: mov r0, r4
343 mov r3, r7
344 bl decompress_kernel
345 b call_kernel
347 .type LC0, #object
348 LC0: .word LC0 @ r1
349 .word __bss_start @ r2
350 .word _end @ r3
351 .word zreladdr @ r4
352 .word _start @ r5
353 .word _got_start @ r6
354 .word _got_end @ ip
355 .word user_stack+4096 @ sp
356 LC1: .word reloc_end - reloc_start
357 .size LC0, . - LC0
359 #ifdef CONFIG_ARCH_RPC
360 .globl params
361 params: ldr r0, =params_phys
362 mov pc, lr
363 .ltorg
364 .align
365 #endif
367 /*
368 * Turn on the cache. We need to setup some page tables so that we
369 * can have both the I and D caches on.
370 *
371 * We place the page tables 16k down from the kernel execution address,
372 * and we hope that nothing else is using it. If we're using it, we
373 * will go pop!
374 *
375 * On entry,
376 * r4 = kernel execution address
377 * r6 = processor ID
378 * r7 = architecture number
379 * r8 = run-time address of "start"
380 * On exit,
381 * r1, r2, r3, r8, r9, r12 corrupted
382 * This routine must preserve:
383 * r4, r5, r6, r7
384 */
385 .align 5
386 cache_on: mov r3, #8 @ cache_on function
387 b call_cache_fn
389 __setup_mmu: sub r3, r4, #16384 @ Page directory size
390 bic r3, r3, #0xff @ Align the pointer
391 bic r3, r3, #0x3f00
392 /*
393 * Initialise the page tables, turning on the cacheable and bufferable
394 * bits for the RAM area only.
395 */
396 mov r0, r3
397 mov r8, r0, lsr #18
398 mov r8, r8, lsl #18 @ start of RAM
399 add r9, r8, #0x10000000 @ a reasonable RAM size
400 mov r1, #0x12
401 orr r1, r1, #3 << 10
402 add r2, r3, #16384
403 1: cmp r1, r8 @ if virt > start of RAM
404 orrhs r1, r1, #0x0c @ set cacheable, bufferable
405 cmp r1, r9 @ if virt > end of RAM
406 bichs r1, r1, #0x0c @ clear cacheable, bufferable
407 str r1, [r0], #4 @ 1:1 mapping
408 add r1, r1, #1048576
409 teq r0, r2
410 bne 1b
411 /*
412 * If ever we are running from Flash, then we surely want the cache
413 * to be enabled also for our execution instance... We map 2MB of it
414 * so there is no map overlap problem for up to 1 MB compressed kernel.
415 * If the execution is in RAM then we would only be duplicating the above.
416 */
417 mov r1, #0x1e
418 orr r1, r1, #3 << 10
419 mov r2, pc, lsr #20
420 orr r1, r1, r2, lsl #20
421 add r0, r3, r2, lsl #2
422 str r1, [r0], #4
423 add r1, r1, #1048576
424 str r1, [r0]
425 mov pc, lr
427 __armv4_cache_on:
428 mov r12, lr
429 bl __setup_mmu
430 mov r0, #0
431 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
432 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
433 mrc p15, 0, r0, c1, c0, 0 @ read control reg
434 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
435 orr r0, r0, #0x0030
436 bl __common_cache_on
437 mov r0, #0
438 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
439 mov pc, r12
441 __arm6_cache_on:
442 mov r12, lr
443 bl __setup_mmu
444 mov r0, #0
445 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
446 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
447 mov r0, #0x30
448 bl __common_cache_on
449 mov r0, #0
450 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
451 mov pc, r12
453 __common_cache_on:
454 #ifndef DEBUG
455 orr r0, r0, #0x000d @ Write buffer, mmu
456 #endif
457 mov r1, #-1
458 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
459 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
460 mcr p15, 0, r0, c1, c0, 0 @ load control register
461 // following add by Victor Yu. 06-08-2005
462 #if 1
463 #ifdef CONFIG_ARCH_MOXACPU
464 mov r0, r0
465 mov r0, r0
466 #endif
467 #endif
468 // above add by Victor Yu. 06-08-2005
469 mov pc, lr
471 /*
472 * All code following this line is relocatable. It is relocated by
473 * the above code to the end of the decompressed kernel image and
474 * executed there. During this time, we have no stacks.
475 *
476 * r0 = decompressed kernel length
477 * r1-r3 = unused
478 * r4 = kernel execution address
479 * r5 = decompressed kernel start
480 * r6 = processor ID
481 * r7 = architecture ID
482 * r8-r14 = unused
483 */
484 .align 5
485 reloc_start: add r8, r5, r0
486 debug_reloc_start
487 mov r1, r4
488 1:
489 .rept 4
490 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
491 stmia r1!, {r0, r2, r3, r9 - r13}
492 .endr
494 cmp r5, r8
495 blo 1b
496 debug_reloc_end
498 call_kernel: bl cache_clean_flush
499 bl cache_off
500 mov r0, #0
501 mov r1, r7 @ restore architecture number
502 mov pc, r4 @ call kernel
504 /*
505 * Here follow the relocatable cache support functions for the
506 * various processors. This is a generic hook for locating an
507 * entry and jumping to an instruction at the specified offset
508 * from the start of the block. Please note this is all position
509 * independent code.
510 *
511 * r1 = corrupted
512 * r2 = corrupted
513 * r3 = block offset
514 * r6 = corrupted
515 * r12 = corrupted
516 */
518 call_cache_fn: adr r12, proc_types
519 mrc p15, 0, r6, c0, c0 @ get processor ID
520 1: ldr r1, [r12, #0] @ get value
521 ldr r2, [r12, #4] @ get mask
522 eor r1, r1, r6 @ (real ^ match)
523 tst r1, r2 @ & mask
524 addeq pc, r12, r3 @ call cache function
525 add r12, r12, #4*5
526 b 1b
528 /*
529 * Table for cache operations. This is basically:
530 * - CPU ID match
531 * - CPU ID mask
532 * - 'cache on' method instruction
533 * - 'cache off' method instruction
534 * - 'cache flush' method instruction
535 *
536 * We match an entry using: ((real_id ^ match) & mask) == 0
537 *
538 * Writethrough caches generally only need 'on' and 'off'
539 * methods. Writeback caches _must_ have the flush method
540 * defined.
541 */
542 .type proc_types,#object
543 proc_types:
544 .word 0x41560600 @ ARM6/610
545 .word 0xffffffe0
546 b __arm6_cache_off @ works, but slow
547 b __arm6_cache_off
548 mov pc, lr
549 @ b __arm6_cache_on @ untested
550 @ b __arm6_cache_off
551 @ b __armv3_cache_flush
553 .word 0x00000000 @ old ARM ID
554 .word 0x0000f000
555 mov pc, lr
556 mov pc, lr
557 mov pc, lr
559 .word 0x41007000 @ ARM7/710
560 .word 0xfff8fe00
561 b __arm7_cache_off
562 b __arm7_cache_off
563 mov pc, lr
565 .word 0x41807200 @ ARM720T (writethrough)
566 .word 0xffffff00
567 b __armv4_cache_on
568 b __armv4_cache_off
569 mov pc, lr
571 .word 0x00007000 @ ARM7 IDs
572 .word 0x0000f000
573 mov pc, lr
574 mov pc, lr
575 mov pc, lr
577 @ Everything from here on will be the new ID system.
579 .word 0x4401a100 @ sa110 / sa1100
580 .word 0xffffffe0
581 b __armv4_cache_on
582 b __armv4_cache_off
583 b __armv4_cache_flush
585 .word 0x6901b110 @ sa1110
586 .word 0xfffffff0
587 b __armv4_cache_on
588 b __armv4_cache_off
589 b __armv4_cache_flush
591 @ These match on the architecture ID
593 .word 0x00020000 @ ARMv4T
594 .word 0x000f0000
595 b __armv4_cache_on
596 b __armv4_cache_off
597 b __armv4_cache_flush
599 // following add by Victor Yu. 06-08-2005
600 #if 1
601 #ifdef CONFIG_ARCH_MOXACPU
602 .word 0x66015261
603 .word 0xff01fff1
604 b __armv4_cache_on
605 b __armv4_cache_off
606 b __armv4_cache_flush
607 #endif
608 #endif
609 // above add by Victor Yu. 06-08-2005
611 .word 0x00050000 @ ARMv5TE
612 .word 0x000f0000
613 b __armv4_cache_on
614 b __armv4_cache_off
615 b __armv4_cache_flush
617 .word 0x00060000 @ ARMv5TEJ
618 .word 0x000f0000
619 b __armv4_cache_on
620 b __armv4_cache_off
621 b __armv4_cache_flush
623 .word 0x00070000 @ ARMv6
624 .word 0x000f0000
625 b __armv4_cache_on
626 b __armv4_cache_off
627 b __armv6_cache_flush
629 .word 0 @ unrecognised type
630 .word 0
631 mov pc, lr
632 mov pc, lr
633 mov pc, lr
635 .size proc_types, . - proc_types
637 /*
638 * Turn off the Cache and MMU. ARMv3 does not support
639 * reading the control register, but ARMv4 does.
640 *
641 * On entry, r6 = processor ID
642 * On exit, r0, r1, r2, r3, r12 corrupted
643 * This routine must preserve: r4, r6, r7
644 */
645 .align 5
646 cache_off: mov r3, #12 @ cache_off function
647 b call_cache_fn
649 __armv4_cache_off:
650 mrc p15, 0, r0, c1, c0
651 bic r0, r0, #0x000d
652 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
653 mov r0, #0
654 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
655 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
656 // following add by Victor Yu. 06-08-2005
657 #if 1
658 #ifdef CONFIG_ARCH_MOXACPU
659 mov r0, r0
660 mov r0, r0
661 #endif
662 #endif
663 // above add by Victor Yu. 06-08-2005
664 mov pc, lr
666 __arm6_cache_off:
667 mov r0, #0x00000030 @ ARM6 control reg.
668 b __armv3_cache_off
670 __arm7_cache_off:
671 mov r0, #0x00000070 @ ARM7 control reg.
672 b __armv3_cache_off
674 __armv3_cache_off:
675 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
676 mov r0, #0
677 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
678 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
679 mov pc, lr
681 /*
682 * Clean and flush the cache to maintain consistency.
683 *
684 * On entry,
685 * r6 = processor ID
686 * On exit,
687 * r1, r2, r3, r11, r12 corrupted
688 * This routine must preserve:
689 * r0, r4, r5, r6, r7
690 */
691 .align 5
692 cache_clean_flush:
693 mov r3, #16
694 b call_cache_fn
696 __armv6_cache_flush:
697 mov r1, #0
698 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
699 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
700 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
701 mcr p15, 0, r1, c7, c10, 4 @ drain WB
702 mov pc, lr
704 __armv4_cache_flush:
705 mov r2, #64*1024 @ default: 32K dcache size (*2)
706 mov r11, #32 @ default: 32 byte line size
707 mrc p15, 0, r3, c0, c0, 1 @ read cache type
708 teq r3, r6 @ cache ID register present?
709 beq no_cache_id
710 mov r1, r3, lsr #18
711 and r1, r1, #7
712 mov r2, #1024
713 mov r2, r2, lsl r1 @ base dcache size *2
714 tst r3, #1 << 14 @ test M bit
715 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
716 mov r3, r3, lsr #12
717 and r3, r3, #3
718 mov r11, #8
719 mov r11, r11, lsl r3 @ cache line size in bytes
720 no_cache_id:
721 // following add by Victor Yu. 06-08-2005
722 #if 1
723 #ifdef CONFIG_ARCH_MOXACPU
724 mov r1, #0
725 mcr p15, 0, r1, c7, c10, 0 @ clean D cache
726 #endif
727 #endif
728 // above add by Victor Yu. 06-08-2005
729 bic r1, pc, #63 @ align to longest cache line
730 add r2, r1, r2
731 1: ldr r3, [r1], r11 @ s/w flush D cache
732 teq r1, r2
733 bne 1b
735 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
736 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
737 mcr p15, 0, r1, c7, c10, 4 @ drain WB
738 mov pc, lr
740 __armv3_cache_flush:
741 mov r1, #0
742 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
743 mov pc, lr
745 /*
746 * Various debugging routines for printing hex characters and
747 * memory, which again must be relocatable.
748 */
749 #ifdef DEBUG
750 .type phexbuf,#object
751 phexbuf: .space 12
752 .size phexbuf, . - phexbuf
754 phex: adr r3, phexbuf
755 mov r2, #0
756 strb r2, [r3, r1]
757 1: subs r1, r1, #1
758 movmi r0, r3
759 bmi puts
760 and r2, r0, #15
761 mov r0, r0, lsr #4
762 cmp r2, #10
763 addge r2, r2, #7
764 add r2, r2, #'0'
765 strb r2, [r3, r1]
766 b 1b
768 puts: loadsp r3
769 1: ldrb r2, [r0], #1
770 teq r2, #0
771 moveq pc, lr
772 2: writeb r2
773 mov r1, #0x00020000
774 3: subs r1, r1, #1
775 bne 3b
776 teq r2, #'\n'
777 moveq r2, #'\r'
778 beq 2b
779 teq r0, #0
780 bne 1b
781 mov pc, lr
782 putc:
783 mov r2, r0
784 mov r0, #0
785 loadsp r3
786 b 2b
788 memdump: mov r12, r0
789 mov r10, lr
790 mov r11, #0
791 2: mov r0, r11, lsl #2
792 add r0, r0, r12
793 mov r1, #8
794 bl phex
795 mov r0, #':'
796 bl putc
797 1: mov r0, #' '
798 bl putc
799 ldr r0, [r12, r11, lsl #2]
800 mov r1, #8
801 bl phex
802 and r0, r11, #7
803 teq r0, #3
804 moveq r0, #' '
805 bleq putc
806 and r0, r11, #7
807 add r11, r11, #1
808 teq r0, #7
809 bne 1b
810 mov r0, #'\n'
811 bl putc
812 cmp r11, #64
813 blt 2b
814 mov pc, r10
815 #endif
817 reloc_end:
819 .align
820 .section ".stack", "w"
821 user_stack: .space 4096