include/asm-nios2nommu/spi_struct.h

   1 // SPI Registers
   2 typedef volatile struct
   3   {
   4   int np_spirxdata;       // Read-only, 1-16 bit
   5   int np_spitxdata;       // Write-only, same width as rxdata
   6   int np_spistatus;       // Read-only, 9-bit
   7   int np_spicontrol;      // Read/Write, 9-bit
   8   int np_spireserved;     // reserved
   9   int np_spislaveselect;  // Read/Write, 1-16 bit, master only
  10   int np_spiendofpacket;  // Read/write, same width as txdata, rxdata.
  11   } np_spi;
  12
  13 // SPI Status Register Bits
  14 enum
  15   {
  16   np_spistatus_eop_bit  = 9,
  17   np_spistatus_e_bit    = 8,
  18   np_spistatus_rrdy_bit = 7,
  19   np_spistatus_trdy_bit = 6,
  20   np_spistatus_tmt_bit  = 5,
  21   np_spistatus_toe_bit  = 4,
  22   np_spistatus_roe_bit  = 3,
  23
  24   np_spistatus_eop_mask  = (1 << 9),
  25   np_spistatus_e_mask    = (1 << 8),
  26   np_spistatus_rrdy_mask = (1 << 7),
  27   np_spistatus_trdy_mask = (1 << 6),
  28   np_spistatus_tmt_mask  = (1 << 5),
  29   np_spistatus_toe_mask  = (1 << 4),
  30   np_spistatus_roe_mask  = (1 << 3),
  31   };
  32
  33 // SPI Control Register Bits
  34 enum
  35   {
  36   np_spicontrol_sso_bit   = 10,
  37   np_spicontrol_ieop_bit  = 9,
  38   np_spicontrol_ie_bit    = 8,
  39   np_spicontrol_irrdy_bit = 7,
  40   np_spicontrol_itrdy_bit = 6,
  41   np_spicontrol_itoe_bit  = 4,
  42   np_spicontrol_iroe_bit  = 3,
  43
  44   np_spicontrol_sso_mask   = (1 << 10),
  45   np_spicontrol_ieop_mask  = (1 << 9),
  46   np_spicontrol_ie_mask    = (1 << 8),
  47   np_spicontrol_irrdy_mask = (1 << 7),
  48   np_spicontrol_itrdy_mask = (1 << 6),
  49   np_spicontrol_itoe_mask  = (1 << 4),
  50   np_spicontrol_iroe_mask  = (1 << 3),
  51   };
  52
  53 // SPI Routines.
  54 int nr_spi_rxchar(np_spi *spiBase);
  55 int nr_spi_txchar(int i, np_spi *spiBase);
  56
  57