include/asm-arm/arch-s5c7375/time.h

   1 /*
   2  *  linux/include/asm-arm/arch-s5c7375/time.h
   3  *
   4  *  Copyright (C) SAMSUNG ELECTRONICS
   5  *                      Hyok S. Choi <hyok.choi@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <asm/system.h>
  22 #include <asm/leds.h>
  23 #include <asm/arch/s5c7375.h>
  24 /*
  25  *      Bits    Name    Type    Function
  26  *      15:12   -       Read    Reserved. Read only as zero
  27  *      11:10   M       Read/write      Operating mode :
  28  *                              00 : Free running timer mode(default)   01 : Periodic timer mode.
  29  *                              10 : Free running counter mode.                 11 : Periodic counter mode.
  30  *      9:8     ES      Read/write      External input active edge selection.
  31  *                              00 : Positive edge(default). 01 : Negative edge.
  32  *                              10 : Both positive and negative edge. 11 : unused.
  33  *      7       -       Read    Reserved. Read only as zero
  34  *      6       OM      Read/write      Time output mode. 0 : Toggle mode(default). 1 : Pulse mode.
  35  *      5       UDS     Read/write      Up/down counting control selection.
  36  *                              0 : Up/down is controlled by UD field of TxCTR register(default).
  37  *                              1 : Up/down is controlled by EXTUD[4:0]input register.
  38  *      4       UD      Read/write      Up/down counting selection.
  39  *                              0 : Down counting(default). 1 : Up counting.
  40  *                              This bit affects the counting of timer only when UDS bit is LOW.
  41  *      3       -       Read    Reserved. Read only as zero
  42  *      2       OE      Read/write      Output enable.
  43  *                              0 : Disable timer outputs(default). 1 : Enable timer outputs.
  44  *                              This bit affects the generation of timer interrupt only when TE bit is HIGH.
  45  *      1       IE      Read/write      Interrupt enable. 0 : Toggle mode(default). 1 : Pulse mode.
  46  *                              This bit affects the generation of timer output only when TE bit is HIGH.
  47  *      0       TE      Read/write      Timer enable. 0 : Diable timer(default). 1 : Enable timer.
  48  */
  49
  50 #define TMR_TE_DISABLE                          0x0000
  51 #define TMR_TE_ENABLE                           0x0001
  52
  53 #define TMR_IE_TOGGLE                           0x0000
  54 #define TMR_IE_PULSE                            0x0002
  55
  56 #define TMR_OE_DISABLE                          0x0000
  57 #define TMR_OE_ENABLE                           0x0004
  58
  59 #define TMR_UD_DOWN                             0x0000
  60 #define TMR_UD_UP                                       0x0010
  61
  62 #define TMR_UDS_TxCTR                           0x0000
  63 #define TMR_UDS_EXTUD                           0x0020
  64
  65 #define TMR_OM_TOGGLE                           0x0000
  66 #define TMR_OM_PULSE                            0x0040
  67
  68 #define TMR_ES_POS                                      0x0000
  69 #define TMR_ES_NEG                                      0x0100
  70 #define TMR_ES_BOTH                             0x0200
  71
  72 #define TMR_M_FREE_TIMER                        0x0000
  73 #define TMR_M_PERIODIC_TIMER            0x0400
  74 #define TMR_M_FREE_COUNTER              0x0800
  75 #define TMR_M_PERIODIC_COUNTER  0x0C00
  76
  77
  78
  79
  80 /*
  81  * simpler new version of gettimeoffset
  82  * by Hyok S. Choi
  83  */
  84 #define TICKS_PER_uSEC                  24
  85 #define CLOCKS_PER_USEC (2* ECLK/ (SYS_TIMER03_PRESCALER +1))
  86                                                         //(ECLK/1000000) /* (ARM_CLK/1000000) */
  87                                                         /* this is the newer version */
  88