include/asm-arm/arch-s5c7375/s5c7375.h

   1 /*
   2  *  linux/include/asm-arm/arch-s5c7375/s5c7375.h
   3  *
   4  *  Copyright (C) 2003 SAMSUNG ELECTRONICS
   5  *                         Hyok S. Choi (hyok.choi@samsung.com)
   6  *
   7  */
   8
   9 #ifndef __S5C7375_H
  10 #define __S5C7375_H
  11
  12 /* keywoard : ClockParameter */
  13 #define  FCLK 162000000
  14 #define ECLK 27000000
  15 #define  BUSWIDTH (32)
  16
  17
  18 /* keywoard : Phy2Vir */
  19 #define S5C7375_MEM_SIZE     (CONFIG_DRAM_SIZE)
  20 #define MEM_SIZE            S5C7375_MEM_SIZE
  21
  22 #define PA_SDRAM_BASE         CONFIG_DRAM_BASE/* used in asm/arch/arch.c     */
  23
  24 #ifndef HYOK_ROMFS_BOOT
  25 #define ZIP_RAMDISK_SIZE      (256*1024)  /* used in asm/arch/arch.c  */
  26 #define RAMDISK_DN_ADDR       (PA_SDRAM_BASE + 0x00400000 - ZIP_RAMDISK_SIZE) /* used in asm/arch/arch.c     */
  27 #else
  28 #define ZIP_RAMDISK_SIZE        (0x00040000)  /* used in asm/arch/arch.c  */
  29 #define RAMDISK_DN_ADDR (0x00400000 - ZIP_RAMDISK_SIZE)
  30 #endif
  31
  32 /* if CONFIG_BLK_DEV_RAM_SIZE not defined */
  33 #define BLK_DEV_RAM_SIZE      (256*1024)
  34
  35         #define rSCRBase     0x40000000     /* base of the System Configuration register */
  36         #define rASICBase    0x0C000000     /* base of all I/O module register */
  37         #define rPTEAKBase   0x08F00000     /* preload TeakLite base address */
  38
  39
  40         /* define the base of each I/O devices */
  41         #define rARM920T     rASICBase
  42         #define rMEMBase     (rASICBase+0x10000) /* Memory controller */
  43         #define rDMABase     (rASICBase+0x20000) /* DMA controller */
  44         #define rLCDBase     (rASICBase+0x30000) /* LCD controller */
  45         #define rEMACBase    (rASICBase+0x40000) /* Ethernet MAC controller */
  46         #define rXMEMBase    (rASICBase+0x50000) /* TeakLite X memory(16KB) */
  47         #define rYMEMBase    (rASICBase+0x60000) /* TeakLite Y memory(8KB) */
  48         #define rPMEMBase    (rASICBase+0x70000) /* TeakLite P memory(32KB) */
  49         #define rAPBBase     (rASICBase+0x80000) /* AHB2APB bridge */
  50
  51         /* Preload TeakLite address */
  52         #define rPPDataArea  (rPTEAKBase+0x00)   /* preload TeakLite P data area */
  53         #define rPXDataArea  (rPTEAKBase+0x40000)/* preload TeakLite X data area */
  54         #define rPYDataArea  (rPTEAKBase+0x60000)/* preload TeakLite Y data area */
  55
  56         /************ AHB2APB bridge I/O device register *************/
  57         #define rBRIDGEBase  (rAPBBase+0x000)    /* APB Bridge interface */
  58         #define rSCIBase     (rAPBBase+0x400)    /* Smart card interface */
  59         #define rUSBBase     (rAPBBase+0x5800)    /* USB */
  60         #define rPPIBase     (rAPBBase+0xC00)    /* IEE1284, Parallel port */
  61         #define rIICBase     (rAPBBase+0x1000)   /* IIC */
  62         #define rTIMEBase    (rAPBBase+0x1400)   /* Timer */
  63         #define rRTCBase     (rAPBBase+0x1800)   /* Real time clock */
  64         #define rWDTBase     (rAPBBase+0x1C00)   /* Watch Dog Timer */
  65         #define rIOPBase     (rAPBBase+0x2000)   /* Programmable I/O port */
  66         #define rRPCBase     (rAPBBase+0x2400)   /* Memory remap */
  67         #define rINTBase     (rAPBBase+0x2800)   /* Interrupt controller */
  68         #define rSSPBase     (rAPBBase+0x2C00)   /* SSP interface */
  69         #define rKMI0Base    (rAPBBase+0x3000)   /* KMI0 */
  70         #define rUART0Base   (rAPBBase+0x3400)   /* UART0 */
  71         #define rUART1Base   (rAPBBase+0x3800)   /* UART1 */
  72         #define rPMBase      (rAPBBase+0x3C00)   /* Power manager */
  73         #define rTEAKBase    (rAPBBase+0x4000)   /* Teaklite Z space */
  74         #define rKMI1Base    (rAPBBase+0x4800)   /* KMI1 */
  75         #define rMISCBase    (rAPBBase+0x4C00)   /* Miscellaneous */
  76         #define rEXT0Base    (rAPBBase+0x5000)   /* External 0 */
  77         #define rEXT1Base    (rAPBBase+0x5400)   /* External 1 */
  78         #define rEXT2Base    (rAPBBase+0x5800)   /* External 2 */
  79         #define rEXT3Base    (rAPBBase+0x5C00)   /* External 3 */
  80         #define rPCMCIABase  (rAPBBase+0x9000)   /* Programmable I/O port */
  81
  82         /* Memory Controller(32bit)*/
  83         #define rSDRAMCFG0    (*(volatile unsigned *)(rMEMBase+0x00))   /* SDRAM config0 register */
  84         #define rSDRAMCFG1    (*(volatile unsigned *)(rMEMBase+0x04))   /* SDRAM config1 register */
  85         #define rSDRAMRefresh (*(volatile unsigned *)(rMEMBase+0x08))   /* SDRAM refresh register */
  86         #define rSDRAMWB      (*(volatile unsigned *)(rMEMBase+0x0C))   /* SDRAM WB timeout register */
  87         // new static memory controller version
  88         #define rSMCBANK0     (*(volatile unsigned *)(rMEMBase+0x10))
  89         #define rSMCBANK1     (*(volatile unsigned *)(rMEMBase+0x14))
  90         #define rSMCBANK2     (*(volatile unsigned *)(rMEMBase+0x18))
  91         #define rSMCBANK3     (*(volatile unsigned *)(rMEMBase+0x1C))
  92
  93         /* DMA Controller(32bit)*/
  94         // DMA control register
  95         #define rDMACON0     (*(volatile unsigned *)(rDMABase+0x00))
  96         #define rDMACON1     (*(volatile unsigned *)(rDMABase+0x40))
  97         #define rDMACON2     (*(volatile unsigned *)(rDMABase+0x80))
  98         #define rDMACON3     (*(volatile unsigned *)(rDMABase+0xC0))
  99         #define rDMACON4     (*(volatile unsigned *)(rDMABase+0x100))
 100         #define rDMACON5     (*(volatile unsigned *)(rDMABase+0x140))
 101
 102         // DMA Source Start address register
 103         #define rDMASAR0     (*(volatile unsigned *)(rDMABase+0x04))
 104         #define rDMASAR1     (*(volatile unsigned *)(rDMABase+0x44))
 105         #define rDMASAR2     (*(volatile unsigned *)(rDMABase+0x84))
 106         #define rDMASAR3     (*(volatile unsigned *)(rDMABase+0xC4))
 107         #define rDMASAR4     (*(volatile unsigned *)(rDMABase+0x104))
 108         #define rDMASAR5     (*(volatile unsigned *)(rDMABase+0x144))
 109
 110         // DMA Destination address register
 111         #define rDMADAR0     (*(volatile unsigned *)(rDMABase+0x08))
 112         #define rDMADAR1     (*(volatile unsigned *)(rDMABase+0x48))
 113         #define rDMADAR2     (*(volatile unsigned *)(rDMABase+0x88))
 114         #define rDMADAR3     (*(volatile unsigned *)(rDMABase+0xC8))
 115         #define rDMADAR4     (*(volatile unsigned *)(rDMABase+0x108))
 116         #define rDMADAR5     (*(volatile unsigned *)(rDMABase+0x148))
 117
 118         // DMA Terminal Counter register
 119         #define rDMATCR0     (*(volatile unsigned *)(rDMABase+0x0C))
 120         #define rDMATCR1     (*(volatile unsigned *)(rDMABase+0x4C))
 121         #define rDMATCR2     (*(volatile unsigned *)(rDMABase+0x8C))
 122         #define rDMATCR3     (*(volatile unsigned *)(rDMABase+0xCC))
 123         #define rDMATCR4     (*(volatile unsigned *)(rDMABase+0x10C))
 124         #define rDMATCR5     (*(volatile unsigned *)(rDMABase+0x14C))
 125
 126         // DMA pending & priority register
 127         #define rDMAPRI      (*(volatile unsigned *)(rDMABase+0x1F8))
 128         #define rDMAPND      (*(volatile unsigned *)(rDMABase+0x1FC))
 129
 130         /* LCD(primecell) Controller(32bit)*/
 131
 132         /* APB Base register map */
 133         /* 1.APB pulse width control register */
 134         #define rAPBCON0     (*(volatile unsigned *)(rBRIDGEBase+0x00))
 135         #define rAPBCON1     (*(volatile unsigned *)(rBRIDGEBase+0x04))
 136         #define rAPBCON2     (*(volatile unsigned *)(rBRIDGEBase+0x08))
 137         #define rAPBCON3     (*(volatile unsigned *)(rBRIDGEBase+0x0C))
 138
 139         /* 2.Smart card interface */
 140
 141
 142         /* 3.USB register(8bit)*/
 143
 144
 145         // Non indexed registers
 146         #define USB_R0       (volatile unsigned *)(rUSBBase+0x00)    // 0x00 - Function address register
 147         #define USB_R1       (volatile unsigned *)(rUSBBase+0x04)    // 0x01 - Power management register
 148
 149         #define USB_R2       (volatile unsigned *)(rUSBBase+0x08)    // 0x02 - Endpoint interrupt1 register (EP0-EP7)
 150         #define USB_R3       (volatile unsigned *)(rUSBBase+0x0c)    // 0x03 - Endpoint interrupt2 register (EP8-EP15)
 151         #define USB_R4       (volatile unsigned *)(rUSBBase+0x10)    //- Out interrupt register bank1
 152         #define USB_R5       (volatile unsigned *)(rUSBBase+0x14)    //- Out interrupt register bank2
 153         #define USB_R6       (volatile unsigned *)(rUSBBase+0x18)    // 0x06 - USB interrpt register
 154
 155         #define USB_R7       (volatile unsigned *)(rUSBBase+0x1C)    // 0x07 - Endpoint interrupt enable1 register (EP0-EP7)
 156         #define USB_R8       (volatile unsigned *)(rUSBBase+0x20)    // 0x08 - Endpoint interrupt enable2 register (EP8-EP15)
 157         #define USB_R9       (volatile unsigned *)(rUSBBase+0x24)    //- Out interrupt enable register bank1
 158         #define USB_R10      (volatile unsigned *)(rUSBBase+0x28)    //- Out interrupt enable register bank2
 159         #define USB_R11      (volatile unsigned *)(rUSBBase+0x2C)    // 0x0B - USB interrupt enable register
 160
 161         #define USB_R12      (volatile unsigned *)(rUSBBase+0x30)    // 0x0C - Frame number1 register
 162         #define USB_R13      (volatile unsigned *)(rUSBBase+0x34)    // 0x0D - Frame number2 register
 163         #define USB_R14      (volatile unsigned *)(rUSBBase+0x38)    // 0x0E - Index register
 164
 165         // Common indexed registers
 166         #define USB_IR1      (volatile unsigned *)(rUSBBase+0x40)    // 0x10 - Max packet register
 167
 168         // In indexed registers
 169         #define USB_IR2      (volatile unsigned *)(rUSBBase+0x44)    // 0x11 - IN CSR1 register (EP0 CSR register)
 170         #define USB_IR3      (volatile unsigned *)(rUSBBase+0x48)    // 0x12 - IN CSR2 register
 171
 172         // Out indexed registers
 173         #define USB_OR1      (volatile unsigned *)(rUSBBase+0x4C)    //- OUT max packet register
 174         #define USB_OR2      (volatile unsigned *)(rUSBBase+0x50)    // 0x14 - OUT CSR1 register
 175         #define USB_OR3      (volatile unsigned *)(rUSBBase+0x54)    // 0x15 - OUT CSR2 register
 176         #define USB_OR4      (volatile unsigned *)(rUSBBase+0x58)    // 0x16 - OUT FIFO write Count1 register
 177         #define USB_OR5      (volatile unsigned *)(rUSBBase+0x5c)    // 0x17 - OUT FIFO write Count2 register
 178
 179         // FIFO registers
 180         #define EP0_FIFO     (volatile unsigned *)(rUSBBase+0x80)    // 0x20 - EP0 FIFO
 181         #define EP1_FIFO     (volatile unsigned *)(rUSBBase+0x84)        // 0x21 - EP1 FIFO
 182         #define EP2_FIFO     (volatile unsigned *)(rUSBBase+0x88)        // 0x22 - EP2 FIFO
 183         #define EP3_FIFO     (volatile unsigned *)(rUSBBase+0x8C)        // 0x23 - EP3 FIFO
 184
 185
 186         /* 4.IEEE 1284(PPI)(8bit)*/
 187
 188         /* 5.IIC register(8bit)*/
 189         /* 6.TIMER register(16bit)*/
 190         #define rT0CTR       (*(volatile int *)(rTIMEBase+0x00))
 191         #define rT0PSR       (*(volatile int *)(rTIMEBase+0x04))
 192         #define rT0LDR       (*(volatile int *)(rTIMEBase+0x08))
 193         #define rT0ISR       (*(volatile int *)(rTIMEBase+0x0C))
 194
 195         #define rT1CTR       (*(volatile int *)(rTIMEBase+0x10))
 196         #define rT1PSR       (*(volatile int *)(rTIMEBase+0x14))
 197         #define rT1LDR       (*(volatile int *)(rTIMEBase+0x18))
 198         #define rT1ISR       (*(volatile int *)(rTIMEBase+0x1C))
 199
 200         #define rT2CTR       (*(volatile int *)(rTIMEBase+0x20))
 201         #define rT2PSR       (*(volatile int *)(rTIMEBase+0x24))
 202         #define rT2LDR       (*(volatile int *)(rTIMEBase+0x28))
 203         #define rT2ISR       (*(volatile int *)(rTIMEBase+0x2C))
 204
 205         #define rT3CTR       (*(volatile int *)(rTIMEBase+0x30))
 206         #define rT3PSR       (*(volatile int *)(rTIMEBase+0x34))
 207         #define rT3LDR       (*(volatile int *)(rTIMEBase+0x38))
 208         #define rT3ISR       (*(volatile int *)(rTIMEBase+0x3C))
 209
 210         #define rT4CTR       (*(volatile int *)(rTIMEBase+0x40))
 211         #define rT4PSR       (*(volatile int *)(rTIMEBase+0x44))
 212         #define rT4LDR       (*(volatile int *)(rTIMEBase+0x48))
 213         #define rT4ISR       (*(volatile int *)(rTIMEBase+0x4C))
 214
 215         #define rTTMR       (*(volatile int *)(rTIMEBase+0x80))
 216         #define rTTIR       (*(volatile int *)(rTIMEBase+0x84))
 217         #define rTTCR       (*(volatile int *)(rTIMEBase+0x88))
 218
 219
 220         /* 7.RTC register(8bit)*/
 221         #define rRTCCON      (*(volatile unsigned *)(rRTCBase+0x00)) /* RTC control register */
 222         #define rRTCRST      (*(volatile unsigned *)(rRTCBase+0x04)) /* RTC round reset register */
 223         #define rRTCALM      (*(volatile unsigned *)(rRTCBase+0x08)) /* RTC alarm register */
 224         #define rALMSEC      (*(volatile unsigned *)(rRTCBase+0x0C)) /* Alarm second data register */
 225         #define rALMMIN      (*(volatile unsigned *)(rRTCBase+0x10))
 226         #define rALMHOUR     (*(volatile unsigned *)(rRTCBase+0x14)) /* Alarm hour data register */
 227         #define rALMDATE     (*(volatile unsigned *)(rRTCBase+0x18)) /* Alarm date data register */
 228         #define rALMDAY      (*(volatile unsigned *)(rRTCBase+0x1C)) /* Alarm day data register */
 229         #define rALMMON      (*(volatile unsigned *)(rRTCBase+0x20)) /* Alarm mon data register */
 230         #define rALMYEAR     (*(volatile unsigned *)(rRTCBase+0x24)) /* Alarm year data register */
 231         #define rBCDSEC      (*(volatile unsigned *)(rRTCBase+0x28)) /* BCD second data register */
 232         #define rBCDMIN      (*(volatile unsigned *)(rRTCBase+0x2C)) /* BCD minute data register */
 233         #define rBCDHOUR     (*(volatile unsigned *)(rRTCBase+0x30)) /* BCD hour data register */
 234         #define rBCDDATE     (*(volatile unsigned *)(rRTCBase+0x34)) /* BCD day data register */
 235         #define rBCDDAY      (*(volatile unsigned *)(rRTCBase+0x38)) /* BCD day data register */
 236         #define rBCDMON      (*(volatile unsigned *)(rRTCBase+0x3C)) /* BCD month data register */
 237         #define rBCDYEAR     (*(volatile unsigned *)(rRTCBase+0x40)) /* BCD year  data register */
 238         #define rRTCIM       (*(volatile unsigned *)(rRTCBase+0x44)) /* BCD year  data register */
 239         #define rRTCPEND     (*(volatile unsigned *)(rRTCBase+0x48)) /* BCD year  data register */
 240
 241
 242         /* 8.Watch Dog Timer register(8bit)*/
 243
 244         /* 9.Programmable I/O port */
 245         #define rGIOPCON     (*(volatile unsigned *)(rIOPBase+0x00)) /* Port direction register */
 246         #define rGIOPDATA    (*(volatile unsigned *)(rIOPBase+0x04)) /* Data register */
 247         #define rGIOPINTEN   (*(volatile unsigned *)(rIOPBase+0x08)) /* Interrupt enable register */
 248         #define rGIOPLEVEL   (*(volatile unsigned *)(rIOPBase+0x0C)) /* Ative level indication register */
 249         #define rGIOPPEND    (*(volatile unsigned *)(rIOPBase+0x10)) /* Interrupt pending register */
 250
 251
 252         /* 10.Interrupt controller */           //0xc082800
 253         #define rINTCON      (*(volatile unsigned *)(rINTBase+0x00)) /* interrupt control register */
 254         #define rINTPND      (*(volatile unsigned *)(rINTBase+0x04)) /* interrupt pending register */
 255         #define rINTMOD      (*(volatile unsigned *)(rINTBase+0x08)) /* interrupt mode register */
 256         #define rINTMSK      (*(volatile unsigned *)(rINTBase+0x0C)) /* interrupt mask register */
 257         #define rINTLEVEL    (*(volatile unsigned *)(rINTBase+0x10))
 258         #define rIRQPSLV0    (*(volatile unsigned *)(rINTBase+0x14)) /* IRQ priority of slave register0 */
 259         #define rIRQPSLV1    (*(volatile unsigned *)(rINTBase+0x18)) /* IRQ priority of slave register1 */
 260         #define rIRQPSLV2    (*(volatile unsigned *)(rINTBase+0x1C)) /* IRQ priority of slave register2 */
 261         #define rIRQPSLV3    (*(volatile unsigned *)(rINTBase+0x20)) /* IRQ priority of slave register3 */
 262         #define rIRQPMST     (*(volatile unsigned *)(rINTBase+0x24)) /* IRQ priority of master register */
 263         #define rIRQCSLV0    (*(volatile unsigned *)(rINTBase+0x28)) /* current IRQ priority of slave register0 */
 264         #define rIRQCSLV1    (*(volatile unsigned *)(rINTBase+0x2C)) /* current IRQ priority of slave register1 */
 265         #define rIRQCSLV2    (*(volatile unsigned *)(rINTBase+0x30)) /* current IRQ priority of slave register2 */
 266         #define rIRQCSLV3    (*(volatile unsigned *)(rINTBase+0x34)) /* current IRQ priority of slave register3 */
 267         #define rIRQCMST     (*(volatile unsigned *)(rINTBase+0x38)) /* current IRQ priority of master register */
 268         #define rIRQISPR     (*(volatile unsigned *)(rINTBase+0x3C)) /* IRQ service pending register */
 269         #define rIRQISPC     (*(volatile unsigned *)(rINTBase+0x40)) /* IRQ service clear register */
 270         #define rFIQPSLV0    (*(volatile unsigned *)(rINTBase+0x44)) /* FIQ priority of slave register0 */
 271         #define rFIQPSLV1    (*(volatile unsigned *)(rINTBase+0x48)) /* FIQ priority of slave register1 */
 272         #define rFIQPSLV2    (*(volatile unsigned *)(rINTBase+0x4C)) /* FIQ priority of slave register2 */
 273         #define rFIQPSLV3    (*(volatile unsigned *)(rINTBase+0x50)) /* FIQ priority of slave register3 */
 274         #define rFIQPMST     (*(volatile unsigned *)(rINTBase+0x54)) /* FIQ priority of master register */
 275         #define rFIQCSLV0    (*(volatile unsigned *)(rINTBase+0x58)) /* current FIQ priority of slave register0 */
 276         #define rFIQCSLV1    (*(volatile unsigned *)(rINTBase+0x5C)) /* current FIQ priority of slave register1 */
 277         #define rFIQCSLV2    (*(volatile unsigned *)(rINTBase+0x60)) /* current FIQ priority of slave register2 */
 278         #define rFIQCSLV3    (*(volatile unsigned *)(rINTBase+0x64)) /* current FIQ priority of slave register3 */
 279         #define rFIQCMST     (*(volatile unsigned *)(rINTBase+0x68)) /* current FIQ priority of master register */
 280         #define rFIQISPR     (*(volatile unsigned *)(rINTBase+0x6C)) /* FIQ service pending register */
 281         #define rFIQISPC     (*(volatile unsigned *)(rINTBase+0x70)) /* FIQ service clear register */
 282         #define rPOLARITY    (*(volatile unsigned *)(rINTBase+0x74))
 283         #define rIVEC_ADDR   (*(volatile unsigned *)(rINTBase+0x78))
 284         #define rFVEC_ADDR   (*(volatile unsigned *)(rINTBase+0x7C))
 285
 286         /* 11.SSP(prime cell) Synchronous serial port register(16bit) */
 287
 288
 289         /* 12.KMI0(prime cell) Keyboard/Mouse interface register(8bit) */
 290
 291         /* 13.KMI1(prime cell) Keyboard/Mouse interface register(8bit) */
 292
 293
 294         /* 14.UART0(prime cell) register(8bit)*/
 295
 296
 297         /* 15.UART1(prime cell) register(8bit)*/
 298
 299
 300         /* 16.Power manager register */
 301         #define rPLLCON      (*(volatile unsigned *)(rPMBase+0x00)) /* pll configuration register */
 302         #define rMODCON      (*(volatile unsigned *)(rPMBase+0x04)) /* mode control register */
 303         #define rLOCKCON     (*(volatile unsigned *)(rPMBase+0x08)) /* Lock-up timer */
 304         #define rHCLKCON     (*(volatile unsigned *)(rPMBase+0x0C)) /* Normal system clock control register */
 305
 306
 307         /* 17.Teak base register */
 308
 309         //-    timer register
 310         /*
 311          *      Bits    Name    Type    Function
 312          *      15:12   -       Read    Reserved. Read only as zero
 313          *      11:10   M       Read/write      Operating mode :
 314          *                              00 : Free running timer mode(default)   01 : Periodic timer mode.
 315          *                              10 : Free running counter mode.                 11 : Periodic counter mode.
 316          *      9:8     ES      Read/write      External input active edge selection.
 317          *                              00 : Positive edge(default). 01 : Negative edge.
 318          *                              10 : Both positive and negative edge. 11 : unused.
 319          *      7       -       Read    Reserved. Read only as zero
 320          *      6       OM      Read/write      Time output mode. 0 : Toggle mode(default). 1 : Pulse mode.
 321          *      5       UDS     Read/write      Up/down counting control selection.
 322          *                              0 : Up/down is controlled by UD field of TxCTR register(default).
 323          *                              1 : Up/down is controlled by EXTUD[4:0]input register.
 324          *      4       UD      Read/write      Up/down counting selection.
 325          *                              0 : Down counting(default). 1 : Up counting.
 326          *                              This bit affects the counting of timer only when UDS bit is LOW.
 327          *      3       -       Read    Reserved. Read only as zero
 328          *      2       OE      Read/write      Output enable.
 329          *                              0 : Disable timer outputs(default). 1 : Enable timer outputs.
 330          *                              This bit affects the generation of timer interrupt only when TE bit is HIGH.
 331          *      1       IE      Read/write      Interrupt enable. 0 : Toggle mode(default). 1 : Pulse mode.
 332          *                              This bit affects the generation of timer output only when TE bit is HIGH.
 333          *      0       TE      Read/write      Timer enable. 0 : Diable timer(default). 1 : Enable timer.
 334          */
 335         #define TMR_TE_DISABLE                          0x0000
 336         #define TMR_TE_ENABLE                           0x0001
 337
 338         #define TMR_IE_TOGGLE                           0x0000
 339         #define TMR_IE_PULSE                            0x0002
 340
 341         #define TMR_OE_DISABLE                          0x0000
 342         #define TMR_OE_ENABLE                           0x0004
 343
 344         #define TMR_UD_DOWN                             0x0000
 345         #define TMR_UD_UP                                       0x0010
 346
 347         #define TMR_UDS_TxCTR                           0x0000
 348         #define TMR_UDS_EXTUD                           0x0020
 349
 350         #define TMR_OM_TOGGLE                           0x0000
 351         #define TMR_OM_PULSE                            0x0040
 352
 353         #define TMR_ES_POS                                      0x0000
 354         #define TMR_ES_NEG                                      0x0100
 355         #define TMR_ES_BOTH                             0x0200
 356
 357         #define TMR_M_FREE_TIMER                        0x0000
 358         #define TMR_M_PERIODIC_TIMER            0x0400
 359         #define TMR_M_FREE_COUNTER              0x0800
 360         #define TMR_M_PERIODIC_COUNTER  0x0C00
 361
 362
 363         /* 18.memory stick Host controller-External Device 1*/
 364         #define COMD_REG  (*(volatile unsigned short *)(rEXT1Base+0x0))     /* Command Register */
 365         #define STAT_REG  (*(volatile unsigned short *)(rEXT1Base+0x4))  /* Status Register */
 366         #define CONT_REG  (*(volatile unsigned short *)(rEXT1Base+0x4))  /* Control Register */
 367         #define RECV_REG  (*(volatile unsigned short *)(rEXT1Base+0x8))  /* Receive Data Register */
 368         #define SEND_REG  (*(volatile unsigned short *)(rEXT1Base+0x8))  /* Send Data Register */
 369         #define INTD_REG  (*(volatile unsigned short *)(rEXT1Base+0xc))  /* Interrupt Data Register */
 370         #define INTC_REG  (*(volatile unsigned short *)(rEXT1Base+0xc))  /* Interrupt Control Register */
 371         #define PARD_REG  (*(volatile unsigned short *)(rEXT1Base+0x10)) /* Parallel Data Register */
 372         #define PARC_REG  (*(volatile unsigned short *)(rEXT1Base+0x10)) /* Parallel Control Register */
 373         #define CONT2_REG  (*(volatile unsigned short *)(rEXT1Base+0x14))
 374         #define ACD_REG  (*(volatile unsigned short *)(rEXT1Base+0x18))
 375
 376
 377         /* Searching Keyword: OS_Timer */
 378         #define SYS_TIMER03_PRESCALER   0x6B      /* for System Timer, 4usec(3.996)  */
 379         #define SYS_TIMER03_DIVIDER     0x01
 380
 381         #define RESCHED_PERIOD          10      /* 10 ms */
 382         #define __KERNEL_HZ                     100
 383
 384 #endif /* __S5C7375_H */