include/asm-arm/arch-moxart/moxa-uart.h

   1 /* for MOXA CPU embedded UART */
   2 #define MOXA_EMBEDDED_UART_IRQ                          31
   3 #define MOXA_EMBEDDED_UART_BASE_REG                     0x98200000L
   4 #define MOXA_EMBEDDED_UART_BASE_INT                     0x982000C0L
   5 #define MOXA_EMBEDDED_UART_BASE_MODE                    0x982000E0L
   6 /*
   7 #define MOXA_EMBEDDED_UART_IRQ                          31
   8 #define MOXA_EMBEDDED_UART_BASE_REG                     0xB0900000L
   9 #define MOXA_EMBEDDED_UART_BASE_INT                     0xB09000C0L
  10 #define MOXA_EMBEDDED_UART_BASE_MODE                    0xB09000E0L
  11 */
  12
  13 #define MOXA_EMBEDDED_UART_CLK                          14745600
  14 /* for register offset */
  15 #define MOXA_EMBEDDED_UART_TX                           (UART_TX*4)
  16 #define MOXA_EMBEDDED_UART_RX                           (UART_RX*4)
  17 #define MOXA_EMBEDDED_UART_LCR                          (UART_LCR*4)
  18 #define MOXA_EMBEDDED_UART_FCR                          (UART_FCR*4)
  19 #define MOXA_EMBEDDED_UART_IIR                          (UART_IIR*4)
  20 #define MOXA_EMBEDDED_UART_IER                          (UART_IER*4)
  21 #define MOXA_EMBEDDED_UART_MCR                          (UART_MCR*4)
  22 #define MOXA_EMBEDDED_UART_LSR                          (UART_LSR*4)
  23 #define MOXA_EMBEDDED_UART_MSR                          (UART_MSR*4)
  24 #define MOXA_EMBEDDED_UART_DLL                          (UART_DLL*4)
  25 #define MOXA_EMBEDDED_UART_DLM                          (UART_DLM*4)
  26
  27 /* for register mask */
  28 #define MOXA_EMBEDDED_MASK_IIR                          0x3E
  29
  30 /* Enhance mode */
  31 /* good data mode enable*/
  32 #define MOXA_FCR_GDA_MODE_ENABLE        0x20
  33 /* only good data put into RxFIFO */
  34 #define MOXA_FCR_GDA_ONLY_ENABLE        0x10
  35 /* enable CTS interrupt */
  36 #define MOXA_IER_ECTSI          0x80
  37 /* eanble RTS interrupt */
  38 #define MOXA_IER_ERTSI          0x40
  39 /* enable Xon/Xoff interrupt */
  40 #define MOXA_IER_XINT           0x20
  41 /* enable GDA interrupt */
  42 #define MOXA_IER_EGDAI          0x10
  43
  44 #define MOXA_RECV_ISR           (UART_IER_RDI | MOXA_IER_EGDAI)
  45
  46 /* GDA interrupt pending */
  47 #define MOXA_IIR_GDA            0x1C
  48 #define MOXA_IIR_RDA            0x04
  49 #define MOXA_IIR_RTO            0x0C
  50 #define MOXA_IIR_LSR            0x06
  51
  52 /* recieved Xon/Xoff or specical interrupt pending */
  53 #define MOXA_IIR_XSC            0x10
  54
  55 /* RTS/CTS change state interrupt pending */
  56 #define MOXA_IIR_RTSCTS         0x20
  57 #define MOXA_IIR_MASK           0x3E
  58 #define MOXA_MCR_XON_FLAG       0x40
  59 #define MOXA_MCR_XON_ANY        0x80
  60 #define MOXA_MCR_TX_XON         0x08
  61
  62
  63 /* software flow control on chip mask value */
  64 #define MOXA_EFR_SF_MASK        0x0F
  65 /* send Xon1/Xoff1 */
  66 #define MOXA_EFR_SF_TX2         0x04
  67 /* send Xon1,Xon2/Xoff1,Xoff2 */
  68 #define MOXA_EFR_SF_TX12        0x0C
  69 /* don't send Xon/Xoff */
  70 #define MOXA_EFR_SF_TX_NO       0x00
  71 /* Tx software flow control mask */
  72 #define MOXA_EFR_SF_TX_MASK     0x0C
  73 /* don't receive Xon/Xoff */
  74 #define MOXA_EFR_SF_RX_NO       0x00
  75 /* receive Xon1/Xoff1 */
  76 #define MOXA_EFR_SF_RX1         0x02
  77 /* receive Xon2/Xoff2 */
  78 #define MOXA_EFR_SF_RX2         0x01
  79 /* receive Xon1,Xon2/Xoff1,Xoff2 */
  80 #define MOXA_EFR_SF_RX12        0x03
  81 /* Rx software flow control mask */
  82 #define MOXA_EFR_SF_RX_MASK     0x03
  83