2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/smp_lock.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/reboot.h>
34 #include <linux/usb.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
38 #include "../core/hcd.h"
40 #include <asm/byteorder.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
47 /*-------------------------------------------------------------------------*/
50 * EHCI hc_driver implementation ... experimental, incomplete.
51 * Based on the final 1.0 register interface specification.
53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 * Next comes "CardBay", using USB 2.0 signals.
57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 * Special thanks to Intel and VIA for providing host controllers to
59 * test this driver on, and Cypress (including In-System Design) for
60 * providing early devices for those host controllers to talk to!
64 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
65 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
66 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
67 * <sojkam@centrum.cz>, updates by DB).
69 * 2002-11-29 Correct handling for hw async_next register.
70 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
71 * only scheduling is different, no arbitrary limitations.
72 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
73 * clean up HC run state handshaking.
74 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
75 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
76 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
77 * 2002-05-07 Some error path cleanups to report better errors; wmb();
78 * use non-CVS version id; better iso bandwidth claim.
79 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
80 * errors in submit path. Bugfixes to interrupt scheduling/processing.
81 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
82 * more checking to generic hcd framework (db). Make it work with
83 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
84 * 2002-01-14 Minor cleanup; version synch.
85 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
86 * 2002-01-04 Control/Bulk queuing behaves.
88 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
89 * 2001-June Works with usb-storage and NEC EHCI on 2.4
92 #define DRIVER_VERSION "10 Dec 2004"
93 #define DRIVER_AUTHOR "David Brownell"
94 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
96 static const char hcd_name
[] = "ehci_hcd";
99 #undef EHCI_VERBOSE_DEBUG
100 #undef EHCI_URB_TRACE
106 /* magic numbers that can affect system performance */
107 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
108 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
109 #define EHCI_TUNE_RL_TT 0
110 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
111 #define EHCI_TUNE_MULT_TT 1
112 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
114 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
115 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
116 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
117 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
119 /* Initial IRQ latency: faster than hw default */
120 static int log2_irq_thresh
= 0; // 0 to 6
121 module_param (log2_irq_thresh
, int, S_IRUGO
);
122 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
124 /* initial park setting: slower than hw default */
125 static unsigned park
= 0;
126 module_param (park
, uint
, S_IRUGO
);
127 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
129 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
131 /*-------------------------------------------------------------------------*/
134 #include "ehci-dbg.c"
136 /*-------------------------------------------------------------------------*/
139 * handshake - spin reading hc until handshake completes or fails
140 * @ptr: address of hc register to be read
141 * @mask: bits to look at in result of read
142 * @done: value of those bits when handshake succeeds
143 * @usec: timeout in microseconds
145 * Returns negative errno, or zero on success
147 * Success happens when the "mask" bits have the specified value (hardware
148 * handshake done). There are two failure modes: "usec" have passed (major
149 * hardware flakeout), or the register reads as all-ones (hardware removed).
151 * That last failure should_only happen in cases like physical cardbus eject
152 * before driver shutdown. But it also seems to be caused by bugs in cardbus
153 * bridge shutdown: shutting down the bridge before the devices using it.
155 static int handshake (void __iomem
*ptr
, u32 mask
, u32 done
, int usec
)
160 result
= readl (ptr
);
161 if (result
== ~(u32
)0) /* card removed */
172 /* force HC to halt state from unknown (EHCI spec section 2.3) */
173 static int ehci_halt (struct ehci_hcd
*ehci
)
175 u32 temp
= readl (&ehci
->regs
->status
);
177 /* disable any irqs left enabled by previous code */
178 writel (0, &ehci
->regs
->intr_enable
);
180 if ((temp
& STS_HALT
) != 0)
183 temp
= readl (&ehci
->regs
->command
);
185 writel (temp
, &ehci
->regs
->command
);
186 return handshake (&ehci
->regs
->status
, STS_HALT
, STS_HALT
, 16 * 125);
189 /* put TDI/ARC silicon into EHCI mode */
190 static void tdi_reset (struct ehci_hcd
*ehci
)
192 u32 __iomem
*reg_ptr
;
195 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + 0x68);
196 tmp
= readl (reg_ptr
);
198 writel (tmp
, reg_ptr
);
201 /* reset a non-running (STS_HALT == 1) controller */
202 static int ehci_reset (struct ehci_hcd
*ehci
)
205 u32 command
= readl (&ehci
->regs
->command
);
207 command
|= CMD_RESET
;
208 dbg_cmd (ehci
, "reset", command
);
209 writel (command
, &ehci
->regs
->command
);
210 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
211 ehci
->next_statechange
= jiffies
;
212 retval
= handshake (&ehci
->regs
->command
, CMD_RESET
, 0, 250 * 1000);
217 if (ehci_is_TDI(ehci
))
223 /* idle the controller (from running) */
224 static void ehci_quiesce (struct ehci_hcd
*ehci
)
229 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
233 /* wait for any schedule enables/disables to take effect */
234 temp
= readl (&ehci
->regs
->command
) << 10;
235 temp
&= STS_ASS
| STS_PSS
;
236 if (handshake (&ehci
->regs
->status
, STS_ASS
| STS_PSS
,
237 temp
, 16 * 125) != 0) {
238 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
242 /* then disable anything that's still active */
243 temp
= readl (&ehci
->regs
->command
);
244 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
245 writel (temp
, &ehci
->regs
->command
);
247 /* hardware can take 16 microframes to turn off ... */
248 if (handshake (&ehci
->regs
->status
, STS_ASS
| STS_PSS
,
250 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
255 /*-------------------------------------------------------------------------*/
257 static void ehci_work(struct ehci_hcd
*ehci
);
259 #include "ehci-hub.c"
260 #include "ehci-mem.c"
262 #include "ehci-sched.c"
264 /*-------------------------------------------------------------------------*/
266 static void ehci_watchdog (unsigned long param
)
268 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
271 spin_lock_irqsave (&ehci
->lock
, flags
);
273 /* lost IAA irqs wedge things badly; seen with a vt8235 */
275 u32 status
= readl (&ehci
->regs
->status
);
276 if (status
& STS_IAA
) {
277 ehci_vdbg (ehci
, "lost IAA\n");
278 COUNT (ehci
->stats
.lost_iaa
);
279 writel (STS_IAA
, &ehci
->regs
->status
);
280 ehci
->reclaim_ready
= 1;
284 /* stop async processing after it's idled a bit */
285 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
286 start_unlink_async (ehci
, ehci
->async
);
288 /* ehci could run by timer, without IRQs ... */
291 spin_unlock_irqrestore (&ehci
->lock
, flags
);
294 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
295 * This forcibly disables dma and IRQs, helping kexec and other cases
296 * where the next system software may expect clean state.
299 ehci_shutdown (struct usb_hcd
*hcd
)
301 struct ehci_hcd
*ehci
;
303 ehci
= hcd_to_ehci (hcd
);
304 (void) ehci_halt (ehci
);
306 /* make BIOS/etc use companion controller during reboot */
307 #ifndef CONFIG_ARCH_MOXART // add by Victor Yu. 07-24-2007
308 writel (0, &ehci
->regs
->configured_flag
);
312 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
316 if (!HCS_PPC (ehci
->hcs_params
))
319 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
320 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
321 (void) ehci_hub_control(ehci_to_hcd(ehci
),
322 is_on
? SetPortFeature
: ClearPortFeature
,
328 /*-------------------------------------------------------------------------*/
331 * ehci_work is called from some interrupts, timers, and so on.
332 * it calls driver completion functions, after dropping ehci->lock.
334 static void ehci_work (struct ehci_hcd
*ehci
)
336 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
337 if (ehci
->reclaim_ready
)
338 end_unlink_async (ehci
);
340 /* another CPU may drop ehci->lock during a schedule scan while
341 * it reports urb completions. this flag guards against bogus
342 * attempts at re-entrant schedule scanning.
348 if (ehci
->next_uframe
!= -1)
349 scan_periodic (ehci
);
352 /* the IO watchdog guards against hardware or driver bugs that
353 * misplace IRQs, and should let us run completely without IRQs.
354 * such lossage has been observed on both VT6202 and VT8235.
356 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
357 (ehci
->async
->qh_next
.ptr
!= NULL
||
358 ehci
->periodic_sched
!= 0))
359 timer_action (ehci
, TIMER_IO_WATCHDOG
);
362 static void ehci_stop (struct usb_hcd
*hcd
)
364 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
366 ehci_dbg (ehci
, "stop\n");
368 /* Turn off port power on all root hub ports. */
369 ehci_port_power (ehci
, 0);
371 /* no more interrupts ... */
372 del_timer_sync (&ehci
->watchdog
);
374 spin_lock_irq(&ehci
->lock
);
375 if (HC_IS_RUNNING (hcd
->state
))
379 writel (0, &ehci
->regs
->intr_enable
);
380 spin_unlock_irq(&ehci
->lock
);
382 /* let companion controllers work when we aren't */
383 #ifndef CONFIG_ARCH_MOXART // add by Victor Yu. 07-24-2007
384 writel (0, &ehci
->regs
->configured_flag
);
387 remove_debug_files (ehci
);
389 /* root hub is shut down separately (first, when possible) */
390 spin_lock_irq (&ehci
->lock
);
393 spin_unlock_irq (&ehci
->lock
);
394 ehci_mem_cleanup (ehci
);
397 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
398 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
399 ehci
->stats
.lost_iaa
);
400 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
401 ehci
->stats
.complete
, ehci
->stats
.unlink
);
404 dbg_status (ehci
, "ehci_stop completed", readl (&ehci
->regs
->status
));
407 /* one-time init, only for memory state */
408 static int ehci_init(struct usb_hcd
*hcd
)
410 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
415 spin_lock_init(&ehci
->lock
);
417 init_timer(&ehci
->watchdog
);
418 ehci
->watchdog
.function
= ehci_watchdog
;
419 ehci
->watchdog
.data
= (unsigned long) ehci
;
422 * hw default: 1K periodic list heads, one per frame.
423 * periodic_size can shrink by USBCMD update if hcc_params allows.
425 ehci
->periodic_size
= DEFAULT_I_TDPS
;
426 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
429 /* controllers may cache some of the periodic schedule ... */
430 hcc_params
= readl(&ehci
->caps
->hcc_params
);
431 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
433 else // N microframes cached
434 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
436 ehci
->reclaim
= NULL
;
437 ehci
->reclaim_ready
= 0;
438 ehci
->next_uframe
= -1;
441 * dedicate a qh for the async ring head, since we couldn't unlink
442 * a 'real' qh without stopping the async schedule [4.8]. use it
443 * as the 'reclamation list head' too.
444 * its dummy is used in hw_alt_next of many tds, to prevent the qh
445 * from automatically advancing to the next td after short reads.
447 ehci
->async
->qh_next
.qh
= NULL
;
448 ehci
->async
->hw_next
= QH_NEXT(ehci
->async
->qh_dma
);
449 ehci
->async
->hw_info1
= cpu_to_le32(QH_HEAD
);
450 ehci
->async
->hw_token
= cpu_to_le32(QTD_STS_HALT
);
451 ehci
->async
->hw_qtd_next
= EHCI_LIST_END
;
452 ehci
->async
->qh_state
= QH_STATE_LINKED
;
453 ehci
->async
->hw_alt_next
= QTD_NEXT(ehci
->async
->dummy
->qtd_dma
);
455 /* clear interrupt enables, set irq latency */
456 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
458 temp
= 1 << (16 + log2_irq_thresh
);
459 if (HCC_CANPARK(hcc_params
)) {
460 /* HW default park == 3, on hardware that supports it (like
461 * NVidia and ALI silicon), maximizes throughput on the async
462 * schedule by avoiding QH fetches between transfers.
464 * With fast usb storage devices and NForce2, "park" seems to
465 * make problems: throughput reduction (!), data errors...
468 park
= min(park
, (unsigned) 3);
472 ehci_dbg(ehci
, "park %d\n", park
);
474 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
475 /* periodic schedule size can be smaller than default */
477 temp
|= (EHCI_TUNE_FLS
<< 2);
478 switch (EHCI_TUNE_FLS
) {
479 case 0: ehci
->periodic_size
= 1024; break;
480 case 1: ehci
->periodic_size
= 512; break;
481 case 2: ehci
->periodic_size
= 256; break;
485 ehci
->command
= temp
;
490 /* start HC running; it's halted, ehci_init() has been run (once) */
491 static int ehci_run (struct usb_hcd
*hcd
)
493 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
498 /* EHCI spec section 4.1 */
499 if ((retval
= ehci_reset(ehci
)) != 0) {
500 ehci_mem_cleanup(ehci
);
503 writel(ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
504 writel((u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
507 * hcc_params controls whether ehci->regs->segment must (!!!)
508 * be used; it constrains QH/ITD/SITD and QTD locations.
509 * pci_pool consistent memory always uses segment zero.
510 * streaming mappings for I/O buffers, like pci_map_single(),
511 * can return segments above 4GB, if the device allows.
513 * NOTE: the dma mask is visible through dma_supported(), so
514 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
515 * Scsi_Host.highmem_io, and so forth. It's readonly to all
516 * host side drivers though.
518 hcc_params
= readl(&ehci
->caps
->hcc_params
);
519 if (HCC_64BIT_ADDR(hcc_params
)) {
520 writel(0, &ehci
->regs
->segment
);
522 // this is deeply broken on almost all architectures
523 if (!dma_set_mask(hcd
->self
.controller
, DMA_64BIT_MASK
))
524 ehci_info(ehci
, "enabled 64bit DMA\n");
529 // Philips, Intel, and maybe others need CMD_RUN before the
530 // root hub will detect new devices (why?); NEC doesn't
531 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
532 ehci
->command
|= CMD_RUN
;
533 writel (ehci
->command
, &ehci
->regs
->command
);
534 dbg_cmd (ehci
, "init", ehci
->command
);
537 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
538 * are explicitly handed to companion controller(s), so no TT is
539 * involved with the root hub. (Except where one is integrated,
540 * and there's no companion controller unless maybe for USB OTG.)
542 hcd
->state
= HC_STATE_RUNNING
;
543 #ifndef CONFIG_ARCH_MOXART // add by Victor Yu. 07-24-2007
544 writel (FLAG_CF
, &ehci
->regs
->configured_flag
);
546 readl (&ehci
->regs
->command
); /* unblock posted writes */
548 temp
= HC_VERSION(readl (&ehci
->caps
->hc_capbase
));
550 "USB %x.%x started, EHCI %x.%02x, driver %s\n",
551 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
552 temp
>> 8, temp
& 0xff, DRIVER_VERSION
);
554 writel (INTR_MASK
, &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
556 /* GRR this is run-once init(), being done every time the HC starts.
557 * So long as they're part of class devices, we can't do it init()
558 * since the class device isn't created that early.
560 create_debug_files(ehci
);
565 /*-------------------------------------------------------------------------*/
567 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
569 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
573 spin_lock (&ehci
->lock
);
575 status
= readl (&ehci
->regs
->status
);
577 /* e.g. cardbus physical eject */
578 if (status
== ~(u32
) 0) {
579 ehci_dbg (ehci
, "device removed\n");
584 if (!status
) { /* irq sharing? */
585 spin_unlock(&ehci
->lock
);
589 /* clear (just) interrupts */
590 writel (status
, &ehci
->regs
->status
);
591 readl (&ehci
->regs
->command
); /* unblock posted write */
594 #ifdef EHCI_VERBOSE_DEBUG
595 /* unrequested/ignored: Frame List Rollover */
596 dbg_status (ehci
, "irq", status
);
599 /* INT, ERR, and IAA interrupt rates can be throttled */
601 /* normal [4.15.1.2] or error [4.15.1.1] completion */
602 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
603 if (likely ((status
& STS_ERR
) == 0))
604 COUNT (ehci
->stats
.normal
);
606 COUNT (ehci
->stats
.error
);
610 /* complete the unlinking of some qh [4.15.2.3] */
611 if (status
& STS_IAA
) {
612 COUNT (ehci
->stats
.reclaim
);
613 ehci
->reclaim_ready
= 1;
617 /* remote wakeup [4.3.1] */
618 if (status
& STS_PCD
) {
619 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
621 /* resume root hub? */
622 status
= readl (&ehci
->regs
->command
);
623 if (!(status
& CMD_RUN
))
624 writel (status
| CMD_RUN
, &ehci
->regs
->command
);
627 int pstatus
= readl (&ehci
->regs
->port_status
[i
]);
629 if (pstatus
& PORT_OWNER
)
631 if (!(pstatus
& PORT_RESUME
)
632 || ehci
->reset_done
[i
] != 0)
635 /* start 20 msec resume signaling from this port,
636 * and make khubd collect PORT_STAT_C_SUSPEND to
637 * stop that signaling.
639 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
640 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
641 usb_hcd_resume_root_hub(hcd
);
645 /* PCI errors [4.15.2.4] */
646 if (unlikely ((status
& STS_FATAL
) != 0)) {
647 /* bogus "fatal" IRQs appear on some chips... why? */
648 status
= readl (&ehci
->regs
->status
);
649 dbg_cmd (ehci
, "fatal", readl (&ehci
->regs
->command
));
650 dbg_status (ehci
, "fatal", status
);
651 if (status
& STS_HALT
) {
652 ehci_err (ehci
, "fatal error\n");
655 #ifndef CONFIG_ARCH_MOXART // add by Victor Yu. 07-24-2007
656 writel (0, &ehci
->regs
->configured_flag
);
658 /* generic layer kills/unlinks all urbs, then
659 * uses ehci_stop to clean up the rest
667 spin_unlock (&ehci
->lock
);
671 /*-------------------------------------------------------------------------*/
674 * non-error returns are a promise to giveback() the urb later
675 * we drop ownership so next owner (or urb unlink) can get it
677 * urb + dev is in hcd.self.controller.urb_list
678 * we're queueing TDs onto software and hardware lists
680 * hcd-specific init for hcpriv hasn't been done yet
682 * NOTE: control, bulk, and interrupt share the same code to append TDs
683 * to a (possibly active) QH, and the same QH scanning code.
685 static int ehci_urb_enqueue (
687 struct usb_host_endpoint
*ep
,
691 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
692 struct list_head qtd_list
;
694 INIT_LIST_HEAD (&qtd_list
);
696 switch (usb_pipetype (urb
->pipe
)) {
697 // case PIPE_CONTROL:
700 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
702 return submit_async (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
705 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
707 return intr_submit (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
709 case PIPE_ISOCHRONOUS
:
710 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
711 return itd_submit (ehci
, urb
, mem_flags
);
713 return sitd_submit (ehci
, urb
, mem_flags
);
717 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
719 /* if we need to use IAA and it's busy, defer */
720 if (qh
->qh_state
== QH_STATE_LINKED
722 && HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)) {
723 struct ehci_qh
*last
;
725 for (last
= ehci
->reclaim
;
727 last
= last
->reclaim
)
729 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
732 /* bypass IAA if the hc can't care */
733 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
734 end_unlink_async (ehci
);
736 /* something else might have unlinked the qh by now */
737 if (qh
->qh_state
== QH_STATE_LINKED
)
738 start_unlink_async (ehci
, qh
);
741 /* remove from hardware lists
742 * completions normally happen asynchronously
745 static int ehci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
747 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
751 spin_lock_irqsave (&ehci
->lock
, flags
);
752 switch (usb_pipetype (urb
->pipe
)) {
753 // case PIPE_CONTROL:
756 qh
= (struct ehci_qh
*) urb
->hcpriv
;
759 unlink_async (ehci
, qh
);
763 qh
= (struct ehci_qh
*) urb
->hcpriv
;
766 switch (qh
->qh_state
) {
767 case QH_STATE_LINKED
:
768 intr_deschedule (ehci
, qh
);
771 qh_completions (ehci
, qh
);
774 ehci_dbg (ehci
, "bogus qh %p state %d\n",
779 /* reschedule QH iff another request is queued */
780 if (!list_empty (&qh
->qtd_list
)
781 && HC_IS_RUNNING (hcd
->state
)) {
784 status
= qh_schedule (ehci
, qh
);
785 spin_unlock_irqrestore (&ehci
->lock
, flags
);
788 // shouldn't happen often, but ...
789 // FIXME kill those tds' urbs
790 err ("can't reschedule qh %p, err %d",
797 case PIPE_ISOCHRONOUS
:
800 // wait till next completion, do it then.
801 // completion irqs can wait up to 1024 msec,
805 spin_unlock_irqrestore (&ehci
->lock
, flags
);
809 /*-------------------------------------------------------------------------*/
811 // bulk qh holds the data toggle
814 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
816 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
818 struct ehci_qh
*qh
, *tmp
;
820 /* ASSERT: any requests/urbs are being unlinked */
821 /* ASSERT: nobody can be submitting urbs for this any more */
824 spin_lock_irqsave (&ehci
->lock
, flags
);
829 /* endpoints can be iso streams. for now, we don't
830 * accelerate iso completions ... so spin a while.
832 if (qh
->hw_info1
== 0) {
833 ehci_vdbg (ehci
, "iso delay\n");
837 if (!HC_IS_RUNNING (hcd
->state
))
838 qh
->qh_state
= QH_STATE_IDLE
;
839 switch (qh
->qh_state
) {
840 case QH_STATE_LINKED
:
841 for (tmp
= ehci
->async
->qh_next
.qh
;
843 tmp
= tmp
->qh_next
.qh
)
845 /* periodic qh self-unlinks on empty */
848 unlink_async (ehci
, qh
);
850 case QH_STATE_UNLINK
: /* wait for hw to finish? */
852 spin_unlock_irqrestore (&ehci
->lock
, flags
);
853 schedule_timeout_uninterruptible(1);
855 case QH_STATE_IDLE
: /* fully unlinked */
856 if (list_empty (&qh
->qtd_list
)) {
860 /* else FALL THROUGH */
863 /* caller was supposed to have unlinked any requests;
864 * that's not our job. just leak this memory.
866 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
867 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
868 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
873 spin_unlock_irqrestore (&ehci
->lock
, flags
);
877 static int ehci_get_frame (struct usb_hcd
*hcd
)
879 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
880 return (readl (&ehci
->regs
->frame_index
) >> 3) % ehci
->periodic_size
;
883 /*-------------------------------------------------------------------------*/
885 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
887 MODULE_DESCRIPTION (DRIVER_INFO
);
888 MODULE_AUTHOR (DRIVER_AUTHOR
);
889 MODULE_LICENSE ("GPL");
892 #include "ehci-pci.c"
893 #define PCI_DRIVER ehci_pci_driver
896 #ifdef CONFIG_MPC834x
897 #include "ehci-fsl.c"
898 #define PLATFORM_DRIVER ehci_fsl_driver
901 #ifdef CONFIG_SOC_AU1200
902 #include "ehci-au1xxx.c"
903 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
906 #ifdef CONFIG_ARCH_MOXART
907 #include "ehci-moxaart.c"
908 #define PLATFORM_DRIVER ehci_hcd_moxaart_driver
911 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
912 #error "missing bus glue for ehci-hcd"
915 static int __init
ehci_hcd_init(void)
919 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
921 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
922 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
924 #ifdef PLATFORM_DRIVER
925 retval
= platform_driver_register(&PLATFORM_DRIVER
);
931 retval
= pci_register_driver(&PCI_DRIVER
);
933 #ifdef PLATFORM_DRIVER
934 platform_driver_unregister(&PLATFORM_DRIVER
);
941 module_init(ehci_hcd_init
);
943 static void __exit
ehci_hcd_cleanup(void)
945 #ifdef PLATFORM_DRIVER
946 platform_driver_unregister(&PLATFORM_DRIVER
);
949 pci_unregister_driver(&PCI_DRIVER
);
952 module_exit(ehci_hcd_cleanup
);