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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / serial / sh-sci.c
blob36956ed27c2257b51cf7bf1c9d3593aa81a145b1
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20
21 #undef DEBUG
22
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/timer.h>
26 #include <linux/interrupt.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/serial.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/sysrq.h>
33 #include <linux/ioport.h>
34 #include <linux/mm.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/console.h>
38 #include <linux/platform_device.h>
39
40 #ifdef CONFIG_CPU_FREQ
41 #include <linux/notifier.h>
42 #include <linux/cpufreq.h>
43 #endif
44
45 #ifdef CONFIG_LEDMAN
46 #include <linux/ledman.h>
47 #endif
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/irq.h>
52 #include <asm/uaccess.h>
53
54 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
55 #include <asm/clock.h>
56 #include <asm/sh_bios.h>
57 #include <asm/kgdb.h>
58 #endif
59
60 #include <asm/sci.h>
61
62 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
63 #define SUPPORT_SYSRQ
64 #endif
65
66 #include "sh-sci.h"
67
68 struct sci_port {
69 struct uart_port port;
70
71 /* Port type */
72 unsigned int type;
73
74 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
75 unsigned int irqs[SCIx_NR_IRQS];
76
77 /* Port pin configuration */
78 void (*init_pins)(struct uart_port *port,
79 unsigned int cflag);
80
81 /* Port enable callback */
82 void (*enable)(struct uart_port *port);
83
84 /* Port disable callback */
85 void (*disable)(struct uart_port *port);
86
87 /* Break timer */
88 struct timer_list break_timer;
89 int break_flag;
90
91 #if defined(CONFIG_SH_SECUREEDGE5410)
92 int open;
93 #endif
94 };
95
96 #ifdef CONFIG_SH_KGDB
97 static struct sci_port *kgdb_sci_port;
98 #endif
99
100 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
101 static struct sci_port *serial_console_port;
102 #endif
103
104 /* Function prototypes */
105 static void sci_stop_tx(struct uart_port *port);
106
107 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
108
109 static struct sci_port sci_ports[SCI_NPORTS];
110 static struct uart_driver sci_uart_driver;
111
112 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
113 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
114 static inline void handle_error(struct uart_port *port)
115 {
116 /* Clear error flags */
117 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
118 }
119
120 static int get_char(struct uart_port *port)
121 {
122 unsigned long flags;
123 unsigned short status;
124 int c;
125
126 spin_lock_irqsave(&port->lock, flags);
127 do {
128 status = sci_in(port, SCxSR);
129 if (status & SCxSR_ERRORS(port)) {
130 handle_error(port);
131 continue;
132 }
133 } while (!(status & SCxSR_RDxF(port)));
134 c = sci_in(port, SCxRDR);
135 sci_in(port, SCxSR); /* Dummy read */
136 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
137 spin_unlock_irqrestore(&port->lock, flags);
138
139 return c;
140 }
141 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
142
143 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
144 static void put_char(struct uart_port *port, char c)
145 {
146 unsigned long flags;
147 unsigned short status;
148
149 spin_lock_irqsave(&port->lock, flags);
150
151 do {
152 status = sci_in(port, SCxSR);
153 } while (!(status & SCxSR_TDxE(port)));
154
155 sci_out(port, SCxTDR, c);
156 sci_in(port, SCxSR); /* Dummy read */
157 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
158
159 spin_unlock_irqrestore(&port->lock, flags);
160 }
161 #endif
162
163 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
164 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
165 {
166 struct uart_port *port = &sci_port->port;
167 const unsigned char *p = buffer;
168 int i;
169
170 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
171 int checksum;
172 int usegdb=0;
173
174 #ifdef CONFIG_SH_STANDARD_BIOS
175 /* This call only does a trap the first time it is
176 * called, and so is safe to do here unconditionally
177 */
178 usegdb |= sh_bios_in_gdb_mode();
179 #endif
180 #ifdef CONFIG_SH_KGDB
181 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
182 #endif
183
184 if (usegdb) {
185 /* $<packet info>#<checksum>. */
186 do {
187 unsigned char c;
188 put_char(port, '$');
189 put_char(port, 'O'); /* 'O'utput to console */
190 checksum = 'O';
191
192 for (i=0; i<count; i++) { /* Don't use run length encoding */
193 int h, l;
194
195 c = *p++;
196 h = highhex(c);
197 l = lowhex(c);
198 put_char(port, h);
199 put_char(port, l);
200 checksum += h + l;
201 }
202 put_char(port, '#');
203 put_char(port, highhex(checksum));
204 put_char(port, lowhex(checksum));
205 } while (get_char(port) != '+');
206 } else
207 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
208 for (i=0; i<count; i++) {
209 if (*p == 10)
210 put_char(port, '\r');
211 put_char(port, *p++);
212 }
213 }
214 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
215
216 #if defined(CONFIG_SH_SECUREEDGE5410)
217 #include <asm/snapgear.h>
218 struct timer_list sci_timer_struct;
219 static unsigned char sci_dcdstatus[2];
220
221 /*
222 * This subroutine is called when the RS_TIMER goes off. It is used
223 * to monitor the state of the DCD lines - since they have no edge
224 * sensors and interrupt generators.
225 */
226 static void sci_timer(unsigned long data)
227 {
228 unsigned short s, i;
229 unsigned char dcdstatus[2];
230
231 s = SECUREEDGE_READ_IOPORT();
232 dcdstatus[0] = !(s & 0x10);
233 dcdstatus[1] = !(s & 0x1);
234
235 for (i = 0; i < 2; i++) {
236 if (dcdstatus[i] != sci_dcdstatus[i]) {
237 if (sci_ports[i].open != 0) {
238 uart_handle_dcd_change(&sci_ports[i].port, dcdstatus[i]);
239 }
240 }
241 sci_dcdstatus[i] = dcdstatus[i];
242 }
243
244 sci_timer_struct.expires = jiffies + HZ/25;
245 add_timer(&sci_timer_struct);
246 }
247
248 #endif
249
250
251 #ifdef CONFIG_SH_KGDB
252 static int kgdb_sci_getchar(void)
253 {
254 int c;
255
256 /* Keep trying to read a character, this could be neater */
257 while ((c = get_char(kgdb_sci_port)) < 0)
258 cpu_relax();
259
260 return c;
261 }
262
263 static inline void kgdb_sci_putchar(int c)
264 {
265 put_char(kgdb_sci_port, c);
266 }
267 #endif /* CONFIG_SH_KGDB */
268
269 #if defined(__H8300S__)
270 enum { sci_disable, sci_enable };
271
272 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
273 {
274 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
275 int ch = (port->mapbase - SMR0) >> 3;
276 unsigned char mask = 1 << (ch+1);
277
278 if (ctrl == sci_disable) {
279 *mstpcrl |= mask;
280 } else {
281 *mstpcrl &= ~mask;
282 }
283 }
284
285 static inline void h8300_sci_enable(struct uart_port *port)
286 {
287 h8300_sci_config(port, sci_enable);
288 }
289
290 static inline void h8300_sci_disable(struct uart_port *port)
291 {
292 h8300_sci_config(port, sci_disable);
293 }
294 #endif
295
296 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
297 defined(__H8300H__) || defined(__H8300S__)
298 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
299 {
300 int ch = (port->mapbase - SMR0) >> 3;
301
302 /* set DDR regs */
303 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
304 h8300_sci_pins[ch].rx,
305 H8300_GPIO_INPUT);
306 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
307 h8300_sci_pins[ch].tx,
308 H8300_GPIO_OUTPUT);
309
310 /* tx mark output*/
311 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
312 }
313 #else
314 #define sci_init_pins_sci NULL
315 #endif
316
317 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
318 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
319 {
320 unsigned int fcr_val = 0;
321
322 if (cflag & CRTSCTS)
323 fcr_val |= SCFCR_MCE;
324
325 sci_out(port, SCFCR, fcr_val);
326 }
327 #else
328 #define sci_init_pins_irda NULL
329 #endif
330
331 #ifdef SCI_ONLY
332 #define sci_init_pins_scif NULL
333 #endif
334
335 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
336 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
337 /* SH7300 doesn't use RTS/CTS */
338 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
339 {
340 sci_out(port, SCFCR, 0);
341 }
342 #elif defined(CONFIG_CPU_SH3)
343 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
344 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
345 {
346 unsigned int fcr_val = 0;
347 unsigned short data;
348
349 /* We need to set SCPCR to enable RTS/CTS */
350 data = ctrl_inw(SCPCR);
351 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
352 ctrl_outw(data & 0x0fcf, SCPCR);
353
354 if (cflag & CRTSCTS)
355 fcr_val |= SCFCR_MCE;
356 else {
357 /* We need to set SCPCR to enable RTS/CTS */
358 data = ctrl_inw(SCPCR);
359 /* Clear out SCP7MD1,0, SCP4MD1,0,
360 Set SCP6MD1,0 = {01} (output) */
361 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
362
363 data = ctrl_inb(SCPDR);
364 /* Set /RTS2 (bit6) = 0 */
365 ctrl_outb(data & 0xbf, SCPDR);
366 }
367
368 sci_out(port, SCFCR, fcr_val);
369 }
370 #else
371 /* For SH7750 */
372 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
373 {
374 unsigned int fcr_val = 0;
375
376 if (cflag & CRTSCTS) {
377 fcr_val |= SCFCR_MCE;
378 } else {
379 #ifdef CONFIG_CPU_SUBTYPE_SH7343
380 /* Nothing */
381 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
382 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
383 #else
384 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
385 #endif
386 }
387 sci_out(port, SCFCR, fcr_val);
388 }
389 #endif
390
391 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
392 static inline int scif_txroom(struct uart_port *port)
393 {
394 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
395 }
396
397 static inline int scif_rxroom(struct uart_port *port)
398 {
399 return sci_in(port, SCRFDR) & 0x7f;
400 }
401 #else
402 static inline int scif_txroom(struct uart_port *port)
403 {
404 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
405 }
406
407 static inline int scif_rxroom(struct uart_port *port)
408 {
409 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
410 }
411 #endif
412 #endif /* SCIF_ONLY || SCI_AND_SCIF */
413
414 static inline int sci_txroom(struct uart_port *port)
415 {
416 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
417 }
418
419 static inline int sci_rxroom(struct uart_port *port)
420 {
421 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
422 }
423
424 /* ********************************************************************** *
425 * the interrupt related routines *
426 * ********************************************************************** */
427
428 static void sci_transmit_chars(struct uart_port *port)
429 {
430 struct circ_buf *xmit = &port->info->xmit;
431 unsigned int stopped = uart_tx_stopped(port);
432 unsigned short status;
433 unsigned short ctrl;
434 int count;
435
436 #ifdef CONFIG_LEDMAN
437 ledman_cmd(LEDMAN_CMD_SET,
438 port == &sci_ports[0].port ? LEDMAN_COM1_TX : LEDMAN_COM2_TX);
439 #endif
440
441 status = sci_in(port, SCxSR);
442 if (!(status & SCxSR_TDxE(port))) {
443 ctrl = sci_in(port, SCSCR);
444 if (uart_circ_empty(xmit)) {
445 ctrl &= ~SCI_CTRL_FLAGS_TIE;
446 } else {
447 ctrl |= SCI_CTRL_FLAGS_TIE;
448 }
449 sci_out(port, SCSCR, ctrl);
450 return;
451 }
452
453 #ifndef SCI_ONLY
454 if (port->type == PORT_SCIF)
455 count = scif_txroom(port);
456 else
457 #endif
458 count = sci_txroom(port);
459
460 do {
461 unsigned char c;
462
463 if (port->x_char) {
464 c = port->x_char;
465 port->x_char = 0;
466 } else if (!uart_circ_empty(xmit) && !stopped) {
467 c = xmit->buf[xmit->tail];
468 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
469 } else {
470 break;
471 }
472
473 sci_out(port, SCxTDR, c);
474
475 port->icount.tx++;
476 } while (--count > 0);
477
478 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
479
480 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
481 uart_write_wakeup(port);
482 if (uart_circ_empty(xmit)) {
483 sci_stop_tx(port);
484 } else {
485 ctrl = sci_in(port, SCSCR);
486
487 #if !defined(SCI_ONLY)
488 if (port->type == PORT_SCIF) {
489 sci_in(port, SCxSR); /* Dummy read */
490 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
491 }
492 #endif
493
494 ctrl |= SCI_CTRL_FLAGS_TIE;
495 sci_out(port, SCSCR, ctrl);
496 }
497 }
498
499 /* On SH3, SCIF may read end-of-break as a space->mark char */
500 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
501
502 static inline void sci_receive_chars(struct uart_port *port)
503 {
504 struct sci_port *sci_port = (struct sci_port *)port;
505 struct tty_struct *tty = port->info->tty;
506 int i, count, copied = 0;
507 unsigned short status;
508 unsigned char flag;
509
510 status = sci_in(port, SCxSR);
511 if (!(status & SCxSR_RDxF(port)))
512 return;
513
514 #ifdef CONFIG_LEDMAN
515 ledman_cmd(LEDMAN_CMD_SET,
516 port == &sci_ports[0].port ? LEDMAN_COM1_RX : LEDMAN_COM2_RX);
517 #endif
518
519 while (1) {
520 #if !defined(SCI_ONLY)
521 if (port->type == PORT_SCIF)
522 count = scif_rxroom(port);
523 else
524 #endif
525 count = sci_rxroom(port);
526
527 /* Don't copy more bytes than there is room for in the buffer */
528 count = tty_buffer_request_room(tty, count);
529
530 /* If for any reason we can't copy more data, we're done! */
531 if (count == 0)
532 break;
533
534 if (port->type == PORT_SCI) {
535 char c = sci_in(port, SCxRDR);
536 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
537 count = 0;
538 else {
539 tty_insert_flip_char(tty, c, TTY_NORMAL);
540 }
541 } else {
542 for (i=0; i<count; i++) {
543 char c = sci_in(port, SCxRDR);
544 status = sci_in(port, SCxSR);
545 #if defined(CONFIG_CPU_SH3)
546 /* Skip "chars" during break */
547 if (sci_port->break_flag) {
548 if ((c == 0) &&
549 (status & SCxSR_FER(port))) {
550 count--; i--;
551 continue;
552 }
553
554 /* Nonzero => end-of-break */
555 pr_debug("scif: debounce<%02x>\n", c);
556 sci_port->break_flag = 0;
557
558 if (STEPFN(c)) {
559 count--; i--;
560 continue;
561 }
562 }
563 #endif /* CONFIG_CPU_SH3 */
564 if (uart_handle_sysrq_char(port, c)) {
565 count--; i--;
566 continue;
567 }
568
569 /* Store data and status */
570 if (status&SCxSR_FER(port)) {
571 flag = TTY_FRAME;
572 pr_debug("sci: frame error\n");
573 } else if (status&SCxSR_PER(port)) {
574 flag = TTY_PARITY;
575 pr_debug("sci: parity error\n");
576 } else
577 flag = TTY_NORMAL;
578 tty_insert_flip_char(tty, c, flag);
579 }
580 }
581
582 sci_in(port, SCxSR); /* dummy read */
583 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
584
585 copied += count;
586 port->icount.rx += count;
587 }
588
589 if (copied) {
590 /* Tell the rest of the system the news. New characters! */
591 tty_flip_buffer_push(tty);
592 } else {
593 sci_in(port, SCxSR); /* dummy read */
594 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
595 }
596 }
597
598 #define SCI_BREAK_JIFFIES (HZ/20)
599 /* The sci generates interrupts during the break,
600 * 1 per millisecond or so during the break period, for 9600 baud.
601 * So dont bother disabling interrupts.
602 * But dont want more than 1 break event.
603 * Use a kernel timer to periodically poll the rx line until
604 * the break is finished.
605 */
606 static void sci_schedule_break_timer(struct sci_port *port)
607 {
608 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
609 add_timer(&port->break_timer);
610 }
611 /* Ensure that two consecutive samples find the break over. */
612 static void sci_break_timer(unsigned long data)
613 {
614 struct sci_port *port = (struct sci_port *)data;
615
616 if (sci_rxd_in(&port->port) == 0) {
617 port->break_flag = 1;
618 sci_schedule_break_timer(port);
619 } else if (port->break_flag == 1) {
620 /* break is over. */
621 port->break_flag = 2;
622 sci_schedule_break_timer(port);
623 } else
624 port->break_flag = 0;
625 }
626
627 static inline int sci_handle_errors(struct uart_port *port)
628 {
629 int copied = 0;
630 unsigned short status = sci_in(port, SCxSR);
631 struct tty_struct *tty = port->info->tty;
632
633 if (status & SCxSR_ORER(port)) {
634 /* overrun error */
635 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
636 copied++;
637 pr_debug("sci: overrun error\n");
638 }
639
640 if (status & SCxSR_FER(port)) {
641 if (sci_rxd_in(port) == 0) {
642 /* Notify of BREAK */
643 struct sci_port *sci_port = (struct sci_port *)port;
644
645 if (!sci_port->break_flag) {
646 sci_port->break_flag = 1;
647 sci_schedule_break_timer(sci_port);
648
649 /* Do sysrq handling. */
650 if (uart_handle_break(port))
651 return 0;
652 pr_debug("sci: BREAK detected\n");
653 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
654 copied++;
655 }
656 } else {
657 /* frame error */
658 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
659 copied++;
660 pr_debug("sci: frame error\n");
661 }
662 }
663
664 if (status & SCxSR_PER(port)) {
665 /* parity error */
666 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
667 copied++;
668 pr_debug("sci: parity error\n");
669 }
670
671 if (copied)
672 tty_flip_buffer_push(tty);
673
674 return copied;
675 }
676
677 static inline int sci_handle_breaks(struct uart_port *port)
678 {
679 int copied = 0;
680 unsigned short status = sci_in(port, SCxSR);
681 struct tty_struct *tty = port->info->tty;
682 struct sci_port *s = &sci_ports[port->line];
683
684 if (!s->break_flag && status & SCxSR_BRK(port)) {
685 #if defined(CONFIG_CPU_SH3)
686 /* Debounce break */
687 s->break_flag = 1;
688 #endif
689 /* Notify of BREAK */
690 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
691 copied++;
692 pr_debug("sci: BREAK detected\n");
693 }
694
695 #if defined(SCIF_ORER)
696 /* XXX: Handle SCIF overrun error */
697 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
698 sci_out(port, SCLSR, 0);
699 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
700 copied++;
701 pr_debug("sci: overrun error\n");
702 }
703 }
704 #endif
705
706 if (copied)
707 tty_flip_buffer_push(tty);
708
709 return copied;
710 }
711
712 static irqreturn_t sci_rx_interrupt(int irq, void *port)
713 {
714 /* I think sci_receive_chars has to be called irrespective
715 * of whether the I_IXOFF is set, otherwise, how is the interrupt
716 * to be disabled?
717 */
718 sci_receive_chars(port);
719
720 return IRQ_HANDLED;
721 }
722
723 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
724 {
725 struct uart_port *port = ptr;
726
727 spin_lock_irq(&port->lock);
728 sci_transmit_chars(port);
729 spin_unlock_irq(&port->lock);
730
731 return IRQ_HANDLED;
732 }
733
734 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
735 {
736 struct uart_port *port = ptr;
737
738 /* Handle errors */
739 if (port->type == PORT_SCI) {
740 if (sci_handle_errors(port)) {
741 /* discard character in rx buffer */
742 sci_in(port, SCxSR);
743 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
744 }
745 } else {
746 #if defined(SCIF_ORER)
747 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
748 struct tty_struct *tty = port->info->tty;
749
750 sci_out(port, SCLSR, 0);
751 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
752 tty_flip_buffer_push(tty);
753 pr_debug("scif: overrun error\n");
754 }
755 #endif
756 sci_rx_interrupt(irq, ptr);
757 }
758
759 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
760
761 /* Kick the transmission */
762 sci_tx_interrupt(irq, ptr);
763
764 return IRQ_HANDLED;
765 }
766
767 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
768 {
769 struct uart_port *port = ptr;
770
771 /* Handle BREAKs */
772 sci_handle_breaks(port);
773
774 #ifdef CONFIG_SH_KGDB
775 /* Break into the debugger if a break is detected */
776 BREAKPOINT();
777 #endif
778
779 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
780
781 return IRQ_HANDLED;
782 }
783
784 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
785 {
786 unsigned short ssr_status, scr_status;
787 struct uart_port *port = ptr;
788
789 ssr_status = sci_in(port,SCxSR);
790 scr_status = sci_in(port,SCSCR);
791
792 /* Tx Interrupt */
793 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
794 sci_tx_interrupt(irq, ptr);
795 /* Rx Interrupt */
796 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
797 sci_rx_interrupt(irq, ptr);
798 /* Error Interrupt */
799 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
800 sci_er_interrupt(irq, ptr);
801 /* Break Interrupt */
802 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
803 sci_br_interrupt(irq, ptr);
804
805 return IRQ_HANDLED;
806 }
807
808 #ifdef CONFIG_CPU_FREQ
809 /*
810 * Here we define a transistion notifier so that we can update all of our
811 * ports' baud rate when the peripheral clock changes.
812 */
813 static int sci_notifier(struct notifier_block *self,
814 unsigned long phase, void *p)
815 {
816 struct cpufreq_freqs *freqs = p;
817 int i;
818
819 if ((phase == CPUFREQ_POSTCHANGE) ||
820 (phase == CPUFREQ_RESUMECHANGE)){
821 for (i = 0; i < SCI_NPORTS; i++) {
822 struct uart_port *port = &sci_ports[i].port;
823 struct clk *clk;
824
825 /*
826 * Update the uartclk per-port if frequency has
827 * changed, since it will no longer necessarily be
828 * consistent with the old frequency.
829 *
830 * Really we want to be able to do something like
831 * uart_change_speed() or something along those lines
832 * here to implicitly reset the per-port baud rate..
833 *
834 * Clean this up later..
835 */
836 clk = clk_get("module_clk");
837 port->uartclk = clk_get_rate(clk) * 16;
838 clk_put(clk);
839 }
840
841 printk(KERN_INFO "%s: got a postchange notification "
842 "for cpu %d (old %d, new %d)\n",
843 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
844 }
845
846 return NOTIFY_OK;
847 }
848
849 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
850 #endif /* CONFIG_CPU_FREQ */
851
852 static int sci_request_irq(struct sci_port *port)
853 {
854 int i;
855 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
856 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
857 sci_br_interrupt,
858 };
859 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
860 "SCI Transmit Data Empty", "SCI Break" };
861
862 if (port->irqs[0] == port->irqs[1]) {
863 if (!port->irqs[0]) {
864 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
865 return -ENODEV;
866 }
867
868 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
869 IRQF_DISABLED, "sci", port)) {
870 printk(KERN_ERR "sci: Cannot allocate irq.\n");
871 return -ENODEV;
872 }
873 } else {
874 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
875 if (!port->irqs[i])
876 continue;
877 if (request_irq(port->irqs[i], handlers[i],
878 IRQF_DISABLED, desc[i], port)) {
879 printk(KERN_ERR "sci: Cannot allocate irq.\n");
880 return -ENODEV;
881 }
882 }
883 }
884
885 return 0;
886 }
887
888 static void sci_free_irq(struct sci_port *port)
889 {
890 int i;
891
892 if (port->irqs[0] == port->irqs[1]) {
893 if (!port->irqs[0])
894 printk("sci: sci_free_irq error\n");
895 else
896 free_irq(port->irqs[0], port);
897 } else {
898 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
899 if (!port->irqs[i])
900 continue;
901
902 free_irq(port->irqs[i], port);
903 }
904 }
905 }
906
907 static unsigned int sci_tx_empty(struct uart_port *port)
908 {
909 /* Can't detect */
910 return TIOCSER_TEMT;
911 }
912
913 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
914 {
915 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
916 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
917 /* If you have signals for DTR and DCD, please implement here. */
918 #if defined(CONFIG_SH_SECUREEDGE5410)
919 int flags;
920
921 local_irq_save(flags);
922 switch (port->line) {
923 case 1: /* port 1 only */
924 if (mctrl & TIOCM_DTR)
925 SECUREEDGE_WRITE_IOPORT(0x0000, 0x0080);
926 else
927 SECUREEDGE_WRITE_IOPORT(0x0080, 0x0080);
928 if ((sci_in(port, SCFCR) & SCFCR_MCE) == 0) {
929 if (mctrl & TIOCM_RTS)
930 sci_out(port, SCSPTR, sci_in(port, SCSPTR) & ~0x40);
931 else
932 sci_out(port, SCSPTR, sci_in(port, SCSPTR) | 0x40);
933 }
934 break;
935 case 0: /* port 0 only */
936 if (mctrl & TIOCM_DTR)
937 SECUREEDGE_WRITE_IOPORT(0x0000, 0x0200);
938 else
939 SECUREEDGE_WRITE_IOPORT(0x0200, 0x0200);
940 if (mctrl & TIOCM_RTS)
941 SECUREEDGE_WRITE_IOPORT(0x0000, 0x0100);
942 else
943 SECUREEDGE_WRITE_IOPORT(0x0100, 0x0100);
944 break;
945 }
946 local_irq_restore(flags);
947 #endif
948 }
949
950 static unsigned int sci_get_mctrl(struct uart_port *port)
951 {
952 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
953 and CTS/RTS */
954
955 #if defined(CONFIG_SH_SECUREEDGE5410)
956 int rc = TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
957
958 switch (port->line) {
959 case 1: /* port 1 only */
960 {
961 unsigned short s = SECUREEDGE_READ_IOPORT();
962 rc = TIOCM_RTS|TIOCM_DSR|TIOCM_CTS;
963
964 if ((sci_in(port, SCFCR) & SCFCR_MCE) == 0) {
965 if (sci_in(port, SCSPTR) & 0x0040)
966 rc &= ~TIOCM_RTS;
967 if (sci_in(port, SCSPTR) & 0x0010)
968 rc &= ~TIOCM_CTS;
969 }
970
971 if ((s & 0x0001) == 0)
972 rc |= TIOCM_CAR;
973 if ((SECUREEDGE_READ_IOPORT() & 0x0080) == 0)
974 rc |= TIOCM_DTR;
975 }
976 break;
977 case 0: /* port 0 only */
978 {
979 unsigned short s = SECUREEDGE_READ_IOPORT();
980 rc = TIOCM_DSR;
981
982 if ((s & 0x0010) == 0)
983 rc |= TIOCM_CAR;
984 if ((s & 0x0004) == 0)
985 rc |= TIOCM_CTS;
986 if ((SECUREEDGE_READ_IOPORT() & 0x0200) == 0)
987 rc |= TIOCM_DTR;
988 if ((SECUREEDGE_READ_IOPORT() & 0x0100) == 0)
989 rc |= TIOCM_RTS;
990 }
991 break;
992 }
993 return(rc);
994 #endif
995 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
996 }
997
998 static void sci_start_tx(struct uart_port *port)
999 {
1000 unsigned short ctrl;
1001
1002 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1003 ctrl = sci_in(port, SCSCR);
1004 ctrl |= SCI_CTRL_FLAGS_TIE;
1005 sci_out(port, SCSCR, ctrl);
1006 }
1007
1008 static void sci_stop_tx(struct uart_port *port)
1009 {
1010 unsigned short ctrl;
1011
1012 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1013 ctrl = sci_in(port, SCSCR);
1014 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1015 sci_out(port, SCSCR, ctrl);
1016 }
1017
1018 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
1019 {
1020 unsigned short ctrl;
1021
1022 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1023 ctrl = sci_in(port, SCSCR);
1024 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1025 sci_out(port, SCSCR, ctrl);
1026 }
1027
1028 static void sci_stop_rx(struct uart_port *port)
1029 {
1030 unsigned short ctrl;
1031
1032 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1033 ctrl = sci_in(port, SCSCR);
1034 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1035 sci_out(port, SCSCR, ctrl);
1036 }
1037
1038 static void sci_enable_ms(struct uart_port *port)
1039 {
1040 /* Nothing here yet .. */
1041 }
1042
1043 static void sci_break_ctl(struct uart_port *port, int break_state)
1044 {
1045 /* Nothing here yet .. */
1046 }
1047
1048 static int sci_startup(struct uart_port *port)
1049 {
1050 struct sci_port *s = &sci_ports[port->line];
1051
1052 #if defined(CONFIG_SH_SECUREEDGE5410)
1053 sci_ports[port->line].open++;
1054 #endif
1055 #if defined(__H8300S__)
1056 h8300_sci_enable(port, sci_enable);
1057 #endif
1058 if (s->enable)
1059 s->enable(port);
1060
1061 sci_request_irq(s);
1062 sci_start_tx(port);
1063 sci_start_rx(port, 1);
1064
1065 return 0;
1066 }
1067
1068 static void sci_shutdown(struct uart_port *port)
1069 {
1070 struct sci_port *s = &sci_ports[port->line];
1071
1072 sci_stop_rx(port);
1073 sci_stop_tx(port);
1074 sci_free_irq(s);
1075
1076 #if defined(__H8300S__)
1077 h8300_sci_enable(port, sci_disable);
1078 #endif
1079 #if defined(CONFIG_SH_SECUREEDGE5410)
1080 sci_ports[port->line].open--;
1081 #endif
1082 if (s->disable)
1083 s->disable(port);
1084 }
1085
1086 static void sci_set_termios(struct uart_port *port, struct termios *termios,
1087 struct termios *old)
1088 {
1089 struct sci_port *s = &sci_ports[port->line];
1090 unsigned int status, baud, smr_val;
1091 unsigned long flags;
1092 int t;
1093
1094 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1095
1096 switch (baud) {
1097 case 0:
1098 t = -1;
1099 break;
1100 default:
1101 {
1102 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1103 struct clk *clk = clk_get("module_clk");
1104 t = SCBRR_VALUE(baud, clk_get_rate(clk));
1105 clk_put(clk);
1106 #else
1107 t = SCBRR_VALUE(baud);
1108 #endif
1109 }
1110 break;
1111 }
1112
1113 spin_lock_irqsave(&port->lock, flags);
1114
1115 do {
1116 status = sci_in(port, SCxSR);
1117 } while (!(status & SCxSR_TEND(port)));
1118
1119 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1120
1121 #if !defined(SCI_ONLY)
1122 if (port->type == PORT_SCIF)
1123 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1124 #endif
1125
1126 smr_val = sci_in(port, SCSMR) & 3;
1127 if ((termios->c_cflag & CSIZE) == CS7)
1128 smr_val |= 0x40;
1129 if (termios->c_cflag & PARENB)
1130 smr_val |= 0x20;
1131 if (termios->c_cflag & PARODD)
1132 smr_val |= 0x30;
1133 if (termios->c_cflag & CSTOPB)
1134 smr_val |= 0x08;
1135
1136 uart_update_timeout(port, termios->c_cflag, baud);
1137
1138 sci_out(port, SCSMR, smr_val);
1139
1140 if (t > 0) {
1141 if(t >= 256) {
1142 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1143 t >>= 2;
1144 } else {
1145 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1146 }
1147 sci_out(port, SCBRR, t);
1148 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1149 }
1150
1151 if (likely(s->init_pins))
1152 s->init_pins(port, termios->c_cflag);
1153
1154 sci_out(port, SCSCR, SCSCR_INIT(port));
1155
1156 if ((termios->c_cflag & CREAD) != 0)
1157 sci_start_rx(port,0);
1158
1159 spin_unlock_irqrestore(&port->lock, flags);
1160 }
1161
1162 static const char *sci_type(struct uart_port *port)
1163 {
1164 switch (port->type) {
1165 case PORT_SCI: return "sci";
1166 case PORT_SCIF: return "scif";
1167 case PORT_IRDA: return "irda";
1168 }
1169
1170 return 0;
1171 }
1172
1173 static void sci_release_port(struct uart_port *port)
1174 {
1175 /* Nothing here yet .. */
1176 }
1177
1178 static int sci_request_port(struct uart_port *port)
1179 {
1180 /* Nothing here yet .. */
1181 return 0;
1182 }
1183
1184 static void sci_config_port(struct uart_port *port, int flags)
1185 {
1186 struct sci_port *s = &sci_ports[port->line];
1187
1188 port->type = s->type;
1189
1190 switch (port->type) {
1191 case PORT_SCI:
1192 s->init_pins = sci_init_pins_sci;
1193 break;
1194 case PORT_SCIF:
1195 s->init_pins = sci_init_pins_scif;
1196 break;
1197 case PORT_IRDA:
1198 s->init_pins = sci_init_pins_irda;
1199 break;
1200 }
1201
1202 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1203 if (port->mapbase == 0)
1204 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1205
1206 port->membase = (void __iomem *)port->mapbase;
1207 #endif
1208 }
1209
1210 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1211 {
1212 struct sci_port *s = &sci_ports[port->line];
1213
1214 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1215 return -EINVAL;
1216 if (ser->baud_base < 2400)
1217 /* No paper tape reader for Mitch.. */
1218 return -EINVAL;
1219
1220 return 0;
1221 }
1222
1223 static struct uart_ops sci_uart_ops = {
1224 .tx_empty = sci_tx_empty,
1225 .set_mctrl = sci_set_mctrl,
1226 .get_mctrl = sci_get_mctrl,
1227 .start_tx = sci_start_tx,
1228 .stop_tx = sci_stop_tx,
1229 .stop_rx = sci_stop_rx,
1230 .enable_ms = sci_enable_ms,
1231 .break_ctl = sci_break_ctl,
1232 .startup = sci_startup,
1233 .shutdown = sci_shutdown,
1234 .set_termios = sci_set_termios,
1235 .type = sci_type,
1236 .release_port = sci_release_port,
1237 .request_port = sci_request_port,
1238 .config_port = sci_config_port,
1239 .verify_port = sci_verify_port,
1240 };
1241
1242 static void __init sci_init_ports(void)
1243 {
1244 static int first = 1;
1245 int i;
1246
1247 if (!first)
1248 return;
1249
1250 first = 0;
1251
1252 for (i = 0; i < SCI_NPORTS; i++) {
1253 sci_ports[i].port.ops = &sci_uart_ops;
1254 sci_ports[i].port.iotype = UPIO_MEM;
1255 sci_ports[i].port.line = i;
1256 sci_ports[i].port.fifosize = 1;
1257
1258 #if defined(__H8300H__) || defined(__H8300S__)
1259 #ifdef __H8300S__
1260 sci_ports[i].enable = h8300_sci_enable;
1261 sci_ports[i].disable = h8300_sci_disable;
1262 #endif
1263 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1264 #elif defined(CONFIG_SUPERH64)
1265 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1266 #else
1267 /*
1268 * XXX: We should use a proper SCI/SCIF clock
1269 */
1270 {
1271 struct clk *clk = clk_get("module_clk");
1272 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1273 clk_put(clk);
1274 }
1275 #endif
1276
1277 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1278 sci_ports[i].break_timer.function = sci_break_timer;
1279
1280 init_timer(&sci_ports[i].break_timer);
1281 }
1282 }
1283
1284 int __init early_sci_setup(struct uart_port *port)
1285 {
1286 if (unlikely(port->line > SCI_NPORTS))
1287 return -ENODEV;
1288
1289 sci_init_ports();
1290
1291 sci_ports[port->line].port.membase = port->membase;
1292 sci_ports[port->line].port.mapbase = port->mapbase;
1293 sci_ports[port->line].port.type = port->type;
1294
1295 return 0;
1296 }
1297
1298 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1299 /*
1300 * Print a string to the serial port trying not to disturb
1301 * any possible real use of the port...
1302 */
1303 static void serial_console_write(struct console *co, const char *s,
1304 unsigned count)
1305 {
1306 put_string(serial_console_port, s, count);
1307 }
1308
1309 static int __init serial_console_setup(struct console *co, char *options)
1310 {
1311 struct uart_port *port;
1312 int baud = 115200;
1313 int bits = 8;
1314 int parity = 'n';
1315 int flow = 'n';
1316 int ret;
1317
1318 /*
1319 * Check whether an invalid uart number has been specified, and
1320 * if so, search for the first available port that does have
1321 * console support.
1322 */
1323 if (co->index >= SCI_NPORTS)
1324 co->index = 0;
1325
1326 serial_console_port = &sci_ports[co->index];
1327 port = &serial_console_port->port;
1328
1329 /*
1330 * Also need to check port->type, we don't actually have any
1331 * UPIO_PORT ports, but uart_report_port() handily misreports
1332 * it anyways if we don't have a port available by the time this is
1333 * called.
1334 */
1335 if (!port->type)
1336 return -ENODEV;
1337 if (!port->membase || !port->mapbase)
1338 return -ENODEV;
1339
1340 spin_lock_init(&port->lock);
1341
1342 port->type = serial_console_port->type;
1343
1344 if (port->flags & UPF_IOREMAP)
1345 sci_config_port(port, 0);
1346
1347 if (serial_console_port->enable)
1348 serial_console_port->enable(port);
1349
1350 if (options)
1351 uart_parse_options(options, &baud, &parity, &bits, &flow);
1352
1353 ret = uart_set_options(port, co, baud, parity, bits, flow);
1354 #if defined(__H8300H__) || defined(__H8300S__)
1355 /* disable rx interrupt */
1356 if (ret == 0)
1357 sci_stop_rx(port);
1358 #endif
1359 return ret;
1360 }
1361
1362 static struct console serial_console = {
1363 .name = "ttySC",
1364 .device = uart_console_device,
1365 .write = serial_console_write,
1366 .setup = serial_console_setup,
1367 .flags = CON_PRINTBUFFER,
1368 .index = -1,
1369 .data = &sci_uart_driver,
1370 };
1371
1372 static int __init sci_console_init(void)
1373 {
1374 sci_init_ports();
1375 register_console(&serial_console);
1376 return 0;
1377 }
1378 console_initcall(sci_console_init);
1379 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1380
1381 #ifdef CONFIG_SH_KGDB
1382 /*
1383 * FIXME: Most of this can go away.. at the moment, we rely on
1384 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1385 * most of that can easily be done here instead.
1386 *
1387 * For the time being, just accept the values that were parsed earlier..
1388 */
1389 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1390 int *parity, int *bits)
1391 {
1392 *baud = kgdb_baud;
1393 *parity = tolower(kgdb_parity);
1394 *bits = kgdb_bits - '0';
1395 }
1396
1397 /*
1398 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1399 * care of the early-on initialization for kgdb, regardless of whether we
1400 * actually use kgdb as a console or not.
1401 *
1402 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1403 */
1404 int __init kgdb_console_setup(struct console *co, char *options)
1405 {
1406 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1407 int baud = 38400;
1408 int bits = 8;
1409 int parity = 'n';
1410 int flow = 'n';
1411
1412 spin_lock_init(&port->lock);
1413
1414 if (co->index != kgdb_portnum)
1415 co->index = kgdb_portnum;
1416
1417 if (options)
1418 uart_parse_options(options, &baud, &parity, &bits, &flow);
1419 else
1420 kgdb_console_get_options(port, &baud, &parity, &bits);
1421
1422 kgdb_getchar = kgdb_sci_getchar;
1423 kgdb_putchar = kgdb_sci_putchar;
1424
1425 return uart_set_options(port, co, baud, parity, bits, flow);
1426 }
1427 #endif /* CONFIG_SH_KGDB */
1428
1429 #ifdef CONFIG_SH_KGDB_CONSOLE
1430 static struct console kgdb_console = {
1431 .name = "ttySC",
1432 .write = kgdb_console_write,
1433 .setup = kgdb_console_setup,
1434 .flags = CON_PRINTBUFFER | CON_ENABLED,
1435 .index = -1,
1436 .data = &sci_uart_driver,
1437 };
1438
1439 /* Register the KGDB console so we get messages (d'oh!) */
1440 static int __init kgdb_console_init(void)
1441 {
1442 sci_init_ports();
1443 register_console(&kgdb_console);
1444 return 0;
1445 }
1446 console_initcall(kgdb_console_init);
1447 #endif /* CONFIG_SH_KGDB_CONSOLE */
1448
1449 #if defined(CONFIG_SH_KGDB_CONSOLE)
1450 #define SCI_CONSOLE &kgdb_console
1451 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1452 #define SCI_CONSOLE &serial_console
1453 #else
1454 #define SCI_CONSOLE 0
1455 #endif
1456
1457 static char banner[] __initdata =
1458 KERN_INFO "SuperH SCI(F) driver initialized\n";
1459
1460 static struct uart_driver sci_uart_driver = {
1461 .owner = THIS_MODULE,
1462 .driver_name = "sci",
1463 .dev_name = "ttySC",
1464 .major = SCI_MAJOR,
1465 .minor = SCI_MINOR_START,
1466 .nr = SCI_NPORTS,
1467 .cons = SCI_CONSOLE,
1468 };
1469
1470 /*
1471 * Register a set of serial devices attached to a platform device. The
1472 * list is terminated with a zero flags entry, which means we expect
1473 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1474 * remapping (such as sh64) should also set UPF_IOREMAP.
1475 */
1476 static int __devinit sci_probe(struct platform_device *dev)
1477 {
1478 struct plat_sci_port *p = dev->dev.platform_data;
1479 int i;
1480
1481 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
1482 struct sci_port *sciport = &sci_ports[i];
1483
1484 sciport->port.mapbase = p->mapbase;
1485
1486 /*
1487 * For the simple (and majority of) cases where we don't need
1488 * to do any remapping, just cast the cookie directly.
1489 */
1490 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1491 p->membase = (void __iomem *)p->mapbase;
1492
1493 sciport->port.membase = p->membase;
1494
1495 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1496 sciport->port.flags = p->flags;
1497 sciport->port.dev = &dev->dev;
1498
1499 sciport->type = sciport->port.type = p->type;
1500
1501 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1502
1503 uart_add_one_port(&sci_uart_driver, &sciport->port);
1504 }
1505
1506 #ifdef CONFIG_CPU_FREQ
1507 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1508 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1509 #endif
1510
1511 #ifdef CONFIG_SH_STANDARD_BIOS
1512 sh_bios_gdb_detach();
1513 #endif
1514
1515 return 0;
1516 }
1517
1518 static int __devexit sci_remove(struct platform_device *dev)
1519 {
1520 int i;
1521
1522 for (i = 0; i < SCI_NPORTS; i++)
1523 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1524
1525 return 0;
1526 }
1527
1528 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1529 {
1530 int i;
1531
1532 for (i = 0; i < SCI_NPORTS; i++) {
1533 struct sci_port *p = &sci_ports[i];
1534
1535 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1536 uart_suspend_port(&sci_uart_driver, &p->port);
1537 }
1538
1539 return 0;
1540 }
1541
1542 static int sci_resume(struct platform_device *dev)
1543 {
1544 int i;
1545
1546 for (i = 0; i < SCI_NPORTS; i++) {
1547 struct sci_port *p = &sci_ports[i];
1548
1549 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1550 uart_resume_port(&sci_uart_driver, &p->port);
1551 }
1552
1553 return 0;
1554 }
1555
1556 static struct platform_driver sci_driver = {
1557 .probe = sci_probe,
1558 .remove = __devexit_p(sci_remove),
1559 .suspend = sci_suspend,
1560 .resume = sci_resume,
1561 .driver = {
1562 .name = "sh-sci",
1563 .owner = THIS_MODULE,
1564 },
1565 };
1566
1567 static int __init sci_init(void)
1568 {
1569 int ret;
1570
1571 printk(banner);
1572
1573 sci_init_ports();
1574
1575 ret = uart_register_driver(&sci_uart_driver);
1576 if (likely(ret == 0)) {
1577
1578 #if defined(CONFIG_SH_SECUREEDGE5410)
1579 unsigned short s;
1580
1581 init_timer(&sci_timer_struct);
1582 sci_timer_struct.function = sci_timer;
1583 sci_timer_struct.data = 0;
1584 sci_timer_struct.expires = jiffies + HZ/25;
1585 add_timer(&sci_timer_struct);
1586
1587 s = SECUREEDGE_READ_IOPORT();
1588 sci_dcdstatus[0] = !(s & 0x10);
1589 sci_dcdstatus[1] = !(s & 0x1);
1590 #endif
1591
1592 ret = platform_driver_register(&sci_driver);
1593 if (unlikely(ret))
1594 uart_unregister_driver(&sci_uart_driver);
1595 }
1596
1597 return ret;
1598 }
1599
1600 static void __exit sci_exit(void)
1601 {
1602 #if defined(CONFIG_SH_SECUREEDGE5410)
1603 del_timer(&sci_timer_struct);
1604 #endif
1605 platform_driver_unregister(&sci_driver);
1606 uart_unregister_driver(&sci_uart_driver);
1607 }
1608
1609 module_init(sci_init);
1610 module_exit(sci_exit);
1611
1612 MODULE_LICENSE("GPL");
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz