drivers/net/open_eth.h

   1 /*--------------------------------------------------------------------
   2  * open_eth.c
   3  *
   4  * Ethernet driver for Open Ethernet Controller (www.opencores.org).
   5  *
   6  * Copyright (c) 2002 Simon Srot (simons@opencores.org)
   7  * Copyright (C) 2004 Microtronix Datacom Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  *
  20  * History:
  21  *    Jun/20/2004   DGT Microtronix Datacom NiosII
  22  *
  23  ---------------------------------------------------------------------*/
  24
  25
  26 /* Ethernet configuration registers */
  27 typedef struct _oeth_regs {
  28         uint    moder;          /* Mode Register */
  29         uint    int_src;        /* Interrupt Source Register */
  30         uint    int_mask;       /* Interrupt Mask Register */
  31         uint    ipgt;           /* Back to Bak Inter Packet Gap Register */
  32         uint    ipgr1;          /* Non Back to Back Inter Packet Gap Register 1 */
  33         uint    ipgr2;          /* Non Back to Back Inter Packet Gap Register 2 */
  34         uint    packet_len;     /* Packet Length Register (min. and max.) */
  35         uint    collconf;       /* Collision and Retry Configuration Register */
  36         uint    tx_bd_num;      /* Transmit Buffer Descriptor Number Register */
  37         uint    ctrlmoder;      /* Control Module Mode Register */
  38         uint    miimoder;       /* MII Mode Register */
  39         uint    miicommand;     /* MII Command Register */
  40         uint    miiaddress;     /* MII Address Register */
  41         uint    miitx_data;     /* MII Transmit Data Register */
  42         uint    miirx_data;     /* MII Receive Data Register */
  43         uint    miistatus;      /* MII Status Register */
  44         uint    mac_addr0;      /* MAC Individual Address Register 0 */
  45         uint    mac_addr1;      /* MAC Individual Address Register 1 */
  46         uint    hash_addr0;     /* Hash Register 0 */
  47         uint    hash_addr1;     /* Hash Register 1 */
  48 } oeth_regs;
  49
  50 /* Ethernet buffer descriptor */
  51 typedef struct _oeth_bd {
  52 #if 0
  53         ushort  len;            /* Buffer length */
  54         ushort  status;         /* Buffer status */
  55 #else
  56         uint    len_status;
  57 #endif
  58         uint    addr;           /* Buffer address */
  59 } oeth_bd;
  60
  61 #define OETH_REG_BASE           ETH_BASE_ADD
  62 #define OETH_BD_BASE            (ETH_BASE_ADD + 0x400)
  63 #define OETH_TOTAL_BD           128
  64 #define OETH_MAXBUF_LEN         0x600
  65
  66 /* Tx BD */
  67 #define OETH_TX_BD_READY        0x8000 /* Tx BD Ready */
  68 #define OETH_TX_BD_IRQ          0x4000 /* Tx BD IRQ Enable */
  69 #define OETH_TX_BD_WRAP         0x2000 /* Tx BD Wrap (last BD) */
  70 #define OETH_TX_BD_PAD          0x1000 /* Tx BD Pad Enable */
  71 #define OETH_TX_BD_CRC          0x0800 /* Tx BD CRC Enable */
  72
  73 #define OETH_TX_BD_UNDERRUN     0x0100 /* Tx BD Underrun Status */
  74 #define OETH_TX_BD_RETRY        0x00F0 /* Tx BD Retry Status */
  75 #define OETH_TX_BD_RETLIM       0x0008 /* Tx BD Retransmission Limit Status */
  76 #define OETH_TX_BD_LATECOL      0x0004 /* Tx BD Late Collision Status */
  77 #define OETH_TX_BD_DEFER        0x0002 /* Tx BD Defer Status */
  78 #define OETH_TX_BD_CARRIER      0x0001 /* Tx BD Carrier Sense Lost Status */
  79 #define OETH_TX_BD_STATS        (OETH_TX_BD_UNDERRUN            | \
  80                                 OETH_TX_BD_RETRY                | \
  81                                 OETH_TX_BD_RETLIM               | \
  82                                 OETH_TX_BD_LATECOL              | \
  83                                 OETH_TX_BD_DEFER                | \
  84                                 OETH_TX_BD_CARRIER)
  85
  86 /* Rx BD */
  87 #define OETH_RX_BD_EMPTY        0x8000 /* Rx BD Empty */
  88 #define OETH_RX_BD_IRQ          0x4000 /* Rx BD IRQ Enable */
  89 #define OETH_RX_BD_WRAP         0x2000 /* Rx BD Wrap (last BD) */
  90
  91 #define OETH_RX_BD_MISS         0x0080 /* Rx BD Miss Status */
  92 #define OETH_RX_BD_OVERRUN      0x0040 /* Rx BD Overrun Status */
  93 #define OETH_RX_BD_INVSIMB      0x0020 /* Rx BD Invalid Symbol Status */
  94 #define OETH_RX_BD_DRIBBLE      0x0010 /* Rx BD Dribble Nibble Status */
  95 #define OETH_RX_BD_TOOLONG      0x0008 /* Rx BD Too Long Status */
  96 #define OETH_RX_BD_SHORT        0x0004 /* Rx BD Too Short Frame Status */
  97 #define OETH_RX_BD_CRCERR       0x0002 /* Rx BD CRC Error Status */
  98 #define OETH_RX_BD_LATECOL      0x0001 /* Rx BD Late Collision Status */
  99 #define OETH_RX_BD_STATS        (OETH_RX_BD_MISS                | \
 100                                 OETH_RX_BD_OVERRUN              | \
 101                                 OETH_RX_BD_INVSIMB              | \
 102                                 OETH_RX_BD_DRIBBLE              | \
 103                                 OETH_RX_BD_TOOLONG              | \
 104                                 OETH_RX_BD_SHORT                | \
 105                                 OETH_RX_BD_CRCERR               | \
 106                                 OETH_RX_BD_LATECOL)
 107
 108 /* MODER Register */
 109 #define OETH_MODER_RXEN         0x00000001 /* Receive Enable  */
 110 #define OETH_MODER_TXEN         0x00000002 /* Transmit Enable */
 111 #define OETH_MODER_NOPRE        0x00000004 /* No Preamble  */
 112 #define OETH_MODER_BRO          0x00000008 /* Reject Broadcast */
 113 #define OETH_MODER_IAM          0x00000010 /* Use Individual Hash */
 114 #define OETH_MODER_PRO          0x00000020 /* Promiscuous (receive all) */
 115 #define OETH_MODER_IFG          0x00000040 /* Min. IFG not required */
 116 #define OETH_MODER_LOOPBCK      0x00000080 /* Loop Back */
 117 #define OETH_MODER_NOBCKOF      0x00000100 /* No Backoff */
 118 #define OETH_MODER_EXDFREN      0x00000200 /* Excess Defer */
 119 #define OETH_MODER_FULLD        0x00000400 /* Full Duplex */
 120 #define OETH_MODER_RST          0x00000800 /* Reset MAC */
 121 #define OETH_MODER_DLYCRCEN     0x00001000 /* Delayed CRC Enable */
 122 #define OETH_MODER_CRCEN        0x00002000 /* CRC Enable */
 123 #define OETH_MODER_HUGEN        0x00004000 /* Huge Enable */
 124 #define OETH_MODER_PAD          0x00008000 /* Pad Enable */
 125 #define OETH_MODER_RECSMALL     0x00010000 /* Receive Small */
 126
 127 /* Interrupt Source Register */
 128 #define OETH_INT_TXB            0x00000001 /* Transmit Buffer IRQ */
 129 #define OETH_INT_TXE            0x00000002 /* Transmit Error IRQ */
 130 #define OETH_INT_RXF            0x00000004 /* Receive Frame IRQ */
 131 #define OETH_INT_RXE            0x00000008 /* Receive Error IRQ */
 132 #define OETH_INT_BUSY           0x00000010 /* Busy IRQ */
 133 #define OETH_INT_TXC            0x00000020 /* Transmit Control Frame IRQ */
 134 #define OETH_INT_RXC            0x00000040 /* Received Control Frame IRQ */
 135
 136 /* Interrupt Mask Register */
 137 #define OETH_INT_MASK_TXB       0x00000001 /* Transmit Buffer IRQ Mask */
 138 #define OETH_INT_MASK_TXE       0x00000002 /* Transmit Error IRQ Mask */
 139 #define OETH_INT_MASK_RXF       0x00000004 /* Receive Frame IRQ Mask */
 140 #define OETH_INT_MASK_RXE       0x00000008 /* Receive Error IRQ Mask */
 141 #define OETH_INT_MASK_BUSY      0x00000010 /* Busy IRQ Mask */
 142 #define OETH_INT_MASK_TXC       0x00000020 /* Transmit Control Frame IRQ Mask */
 143 #define OETH_INT_MASK_RXC       0x00000040 /* Received Control Frame IRQ Mask */
 144
 145 /* Control Module Mode Register */
 146 #define OETH_CTRLMODER_PASSALL  0x00000001 /* Pass Control Frames */
 147 #define OETH_CTRLMODER_RXFLOW   0x00000002 /* Receive Control Flow Enable */
 148 #define OETH_CTRLMODER_TXFLOW   0x00000004 /* Transmit Control Flow Enable */
 149
 150 /* MII Mode Register */
 151 #define OETH_MIIMODER_CLKDIV    0x000000FF /* Clock Divider */
 152 #define OETH_MIIMODER_NOPRE     0x00000100 /* No Preamble */
 153 #define OETH_MIIMODER_RST       0x00000200 /* MIIM Reset */
 154
 155 /* MII Command Register */
 156 #define OETH_MIICOMMAND_SCANSTAT  0x00000001 /* Scan Status */
 157 #define OETH_MIICOMMAND_RSTAT     0x00000002 /* Read Status */
 158 #define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
 159
 160 /* MII Address Register */
 161 #define OETH_MIIADDRESS_FIAD    0x0000001F /* PHY Address */
 162   //;dgt;May2005-note Mx Altera Nios (CONFIG_EXCALIBUR) with
 163   //; a TDK78Q2120 phy does NOT use OETH_MIIADDRESS_FIAD, but
 164   //; instead uses its own PHY_ADDRESS (0x00 = "broadcast"
 165   //; phy address) invention
 166   //;dgt:IIRC, Mx Tdk's USED to use address 0x1F but changed some
 167   //; undocumented time ago...
 168 #define OETH_MIIADDRESS_RGAD    0x00001F00 /* RGAD Address */
 169
 170 /* MII Status Register */
 171 #define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
 172 #define OETH_MIISTATUS_BUSY     0x00000002 /* MII Busy */
 173 #define OETH_MIISTATUS_NVALID   0x00000004 /* Data in MII Status Register is invalid */
 174
 175 /*----------------------------------------------------------------------*/
 176
 177     #define OETH_IO_EXTENT      (sizeof(oeth_regs))
 178
 179 /*----------------------------------------------------------------------*/