1 /*----------------------------------------------------------------------
4 . Driver: MoreThanIP 10/100/1000Mbps Emac IP
13 . o MoreThanIP 10/100/1000Mbps Reference Guide V3.2 - May 2003
14 . o MoreThanIP Altera Plugs sources
15 . o Smc9111 uClinux port(s)
18 . o Apr2004 DGT Microtronix Datacom
20 -----------------------------------------------------------------------*/
25 /*----------------------------------------------------------------------*/
27 #ifndef na_mtip_mac_control_port
28 #if defined (na_mip_mac_control_port)
29 #define na_mtip_mac_control_port na_mip_mac_control_port
32 #ifndef na_mtip_mac_rxFIFO
33 #if defined (na_mip_mac_rxFIFO)
34 #define na_mtip_mac_rxFIFO na_mip_mac_rxFIFO
37 #ifndef na_mtip_mac_rxFIFO_irq
38 #if defined (na_mip_mac_rxFIFO_irq)
39 #define na_mtip_mac_rxFIFO_irq na_mip_mac_rxFIFO_irq
42 #ifndef na_mtip_mac_txFIFO
43 #if defined (na_mip_mac_txFIFO)
44 #define na_mtip_mac_txFIFO na_mip_mac_txFIFO
47 #ifndef na_mtip_mac_txFIFO_irq
48 #if defined (na_mip_mac_txFIFO_irq)
49 #define na_mtip_mac_txFIFO_irq na_mip_mac_txFIFO_irq
53 /*----------------------------------------------------------------------*/
55 // Number of bytes the largest frame can have.
56 // For receive, should be at least the MAC's FRAME_LENGTH
57 // programmed value + 8.
58 #define MTIP_MAC_MAX_FRAME_SIZE 1524
60 // Receive buffer must be at least 'maximum possible frame size'+16.
61 #define MTIP_MI_XBUF_BYTS 24
62 #define MTIP_SKB_XBUF_BYTS MTIP_MI_XBUF_BYTS
64 // MDIO registers within MAC register Space
65 // memory mapped access
67 typedef volatile struct
105 // MAC Registers - 32 Bit
107 typedef volatile struct
110 unsigned int SCRATCH
;
111 unsigned int COMMAND_CONFIG
;
114 unsigned int FRM_LENGTH
;
115 unsigned int PAUSE_QUANT
;
116 unsigned int RX_SECTION_EMPTY
;
117 unsigned int RX_SECTION_FULL
;
118 unsigned int TX_SECTION_EMPTY
;
119 unsigned int TX_SECTION_FULL
;
120 unsigned int RX_ALMOST_EMPTY
;
121 unsigned int RX_ALMOST_FULL
;
122 unsigned int TX_ALMOST_EMPTY
;
123 unsigned int TX_ALMOST_FULL
;
124 unsigned int MDIO_ADDR0
;
125 unsigned int MDIO_ADDR1
;
127 unsigned int AUTONEG_CNTL
;
128 // only if 100/1000 BaseX PCS, reserved otherwise
130 unsigned int AN_ABILITY_INT
;
131 unsigned int LP_ABILITY_INT
;
132 unsigned int LINK_TIMER_INT
;
134 unsigned int reservedx54
;
135 unsigned int reservedx58
;
136 unsigned int reservedx5C
;
138 unsigned int aMACID_1
;
139 unsigned int aMACID_2
;
140 unsigned int aFramesTransmittedOK
;
141 unsigned int aFramesReceivedOK
;
142 unsigned int aFramesCheckSequenceErrors
;
143 unsigned int aAlignmentErrors
;
144 unsigned int aOctetsTransmittedOK
;
145 unsigned int aOctetsReceivedOK
;
146 unsigned int aTxPAUSEMACCtrlFrames
;
147 unsigned int aRxPAUSEMACCtrlFrames
;
148 unsigned int ifInErrors
;
149 unsigned int ifOutErrors
;
150 unsigned int ifInUcastPkts
;
151 unsigned int ifInBroadcastPkts
;
152 unsigned int ifInMulticastPkts
;
153 unsigned int ifOutDiscards
;
154 unsigned int ifOutUcastPkts
;
155 unsigned int ifOutBroadcastPkts
;
156 unsigned int ifOutMulticastPkts
;
157 unsigned int etherStatsDropEvent
;
158 unsigned int etherStatsOctets
;
159 unsigned int etherStatsPkts
;
160 unsigned int etherStatsUndersizePkts
;
161 unsigned int etherStatsOversizePkts
;
162 unsigned int etherStatsPkts64Octets
;
163 unsigned int etherStatsPkts65to127Octets
;
164 unsigned int etherStatsPkts128to255Octets
;
165 unsigned int etherStatsPkts256to511Octets
;
166 unsigned int etherStatsPkts512to1023Octets
;
167 unsigned int etherStatsPkts1024to1518Octets
;
169 unsigned int reservedxD8
;
170 unsigned int reservedxDC
;
172 unsigned int AVL_STATUS
;
173 unsigned int IRQ_CONFIG
;
177 unsigned int reservedxF0
;
178 unsigned int reservedxF4
;
179 unsigned int reservedxF8
;
180 unsigned int reservedxFC
;
182 unsigned int hashtable
[64];
190 // Base-Structure for all library functions
202 volatile unsigned int *rxFIFO
;
203 volatile unsigned int *txFIFO
;
205 unsigned int cfgflags
;
206 // flags or'ed during initialization of COMMAND_CONFIG
208 int *rxbuf
; // receive buffer to use
210 } mtip_mac_trans_info
;
212 // COMMAND_CONFIG Register Bits
216 mmac_cc_TX_ENA_bit
= 0,
217 mmac_cc_RX_ENA_bit
= 1,
218 mmac_cc_XOFF_GEN_bit
= 2,
219 mmac_cc_ETH_SPEED_bit
= 3,
220 mmac_cc_PROMIS_EN_bit
= 4,
221 mmac_cc_PAD_EN_bit
= 5,
222 mmac_cc_CRC_FWD_bit
= 6,
223 mmac_cc_PAUSE_FWD_bit
= 7,
224 mmac_cc_PAUSE_IGNORE_bit
= 8,
225 mmac_cc_TX_ADDR__INS_bit
= 9,
226 mmac_cc_HD_ENA_bit
= 10,
227 mmac_cc_EXCESS_COL_bit
= 11,
228 mmac_cc_LATE_COL_bit
= 12,
229 mmac_cc_SW_RESET_bit
= 13,
230 //;dgt2; mmac_cc_MHASH_SEL_bit = 13,
231 mmac_cc_MHASH_SEL_bit
= 14, //;dgt2;
232 mmac_cc_LOOPBACK_bit
= 15,
233 mmac_cc_TX_ADDR_SEL_bit
= 16, // bits 18:16 = address select
234 mmac_cc_MAGIC_ENA_bit
= 19,
235 mmac_cc_SLEEP_ENA_bit
= 20,
237 mmac_cc_TX_ENA_mask
= (1 << 0), // enable TX
238 mmac_cc_RX_ENA_mask
= (1 << 1), // enable RX
239 mmac_cc_XOFF_GEN_mask
= (1 << 2), // generate Pause frame with Quanta
240 mmac_cc_ETH_SPEED_mask
= (1 << 3), // Select Gigabit
241 mmac_cc_PROMIS_EN_mask
= (1 << 4), // enable Promiscuous mode
242 mmac_cc_PAD_EN_mask
= (1 << 5), // enable padding remove on RX
243 mmac_cc_CRC_FWD_mask
= (1 << 6), // forward CRC to application on RX (as opposed to stripping it off)
244 mmac_cc_PAUSE_FWD_mask
= (1 << 7), // forward Pause frames to application
245 mmac_cc_PAUSE_IGNORE_mask
= (1 << 8), // ignore Pause frames
246 mmac_cc_TX_ADDR_INS_mask
= (1 << 9), // MAC overwrites bytes 6 to 12 of frame with address on all transmitted frames
247 mmac_cc_HD_ENA_mask
= (1 << 10),// enable half-duplex operation
248 mmac_cc_EXCESS_COL_mask
= (1 << 11),// indicator
249 mmac_cc_LATE_COL_mask
= (1 << 12),// indicator
250 mmac_cc_SW_RESET_mask
= (1 << 13),// issue register and counter reset
251 mmac_cc_MHASH_SEL_mask
= (1 << 14),// select multicast hash method
252 mmac_cc_LOOPBACK_mask
= (1 << 15),// enable GMII loopback
253 mmac_cc_MAGIC_ENA_mask
= (1 << 19),// enable magic packet detect
254 mmac_cc_SLEEP_ENA_mask
= (1 << 20) // enter sleep mode
257 // AVL_STATUS Register Bits
261 mmac_as_RX_FRAME_AVAILABLE_mask
= (1 << 0),
262 mmac_as_TX_FIFO_EMPTY_mask
= (1 << 1),
263 mmac_as_TX_FIFO_SEPTY_mask
= (1 << 2)
267 // IRQ_CONFIG Register Bits
271 mmac_ic_EN_RX_FRAME_AVAILABLE_mask
= (1 << 0), // rx frame available (status FIFO)
272 mmac_ic_EN_TX_FIFO_EMPTY_mask
= (1 << 1), // tx section empty
273 mmac_ic_EN_RX_MAGIC_FRAME_mask
= (1 << 2), // magic frame received interrupt when in sleep mode
274 mmac_ic_OR_WRITE
= (1 << 30), // if set, write data is OR'ed with current register bits
275 mmac_ic_AND_WRITE
= (1 << 31) // if set, write data is AND'ed with current register bits
279 // TX_CMD_STAT Register bits
282 mmac_tcs_LENGTH_mask
= 0x3fff, // length portion
283 mmac_tcs_FRAME_COMPLETE_mask
= (1 << 31), // negative as long as frame is not complete
284 mmac_tcs_SET_ERROR_mask
= (1 << 16),
285 mmac_tcs_OMIT_CRC_mask
= (1 << 17)
289 // RX_CMD_STAT Register bits
292 mmac_rcs_FRAME_LENGTH_mask
= 0x0000ffff,
293 mmac_rcs_ERROR_mask
= (1 << 16),
294 //mmac_rcs_FIFO_OVERFLOW_mask = (1 << xx), //;dgt2; ???
295 mmac_rcs_VLAN_mask
= (1 << 17),
296 mmac_rcs_MCAST_mask
= (1 << 18),
297 mmac_rcs_BCAST_mask
= (1 << 19),
298 mmac_rcs_UNICAST_mask
= (1 << 20), //;dgt2; 20 or 23 ?...
299 mmac_rcs_READ_CMD_mask
= (1 << 24),
300 mmac_rcs_VALID_mask
= (1 << 31)
304 /** extracts AVL_STATUS' VALID bit to detect if there is a frame in the RX fifo. */
310 //;dgt2; available...?...;
311 //;dgt2; #define mtip_mac_isFrameAvail( pmtip_mac ) ( pmtip_mac->RX_CMD_STAT & mmac_rcs_VALID_mask )
313 /** extracts length of frame currently available in the FIFO. */
315 #define mtip_mac_getFrameLength( pmtip_mac) ( pmtip_mac->RX_CMD_STAT & mmac_rcs_FRAME_LENGTH_mask )
317 /** set promiscous bit. */
319 #define mtip_mac_setPromiscuous( pmtip_mac) ( pmtip_mac->COMMAND_CONFIG |= mmac_cc_PROMIS_EN_mask )
321 /** clear promiscuous bit. */
323 #define mtip_mac_clearPromiscuous(pmtip_mac) ( pmtip_mac->COMMAND_CONFIG &= ~mmac_cc_PROMIS_EN_mask )
326 /** switch MAC into MII (10/100) mode. */
328 #define mtip_mac_setMIImode( pmtip_mac ) ( pmtip_mac->COMMAND_CONFIG &= ~mmac_cc_ETH_SPEED_mask )
330 /** switch MAC into GMII (Gigabit) mode. */
331 #define mtip_mac_setGMIImode( pmtip_mac ) ( pmtip_mac->COMMAND_CONFIG |= mmac_cc_ETH_SPEED_mask )
334 // PCS --------------
336 /** PCS Control Register Bits. IEEE 802.3 Clause 22.2.4.1
339 PCS_CTL_speed1
= 1<<6, // speed select
340 PCS_CTL_speed0
= 1<<13,
341 PCS_CTL_fullduplex
= 1<<8, // fullduplex mode select
342 PCS_CTL_an_restart
= 1<<9, // Autonegotiation restart command
343 PCS_CTL_isolate
= 1<<10, // isolate command
344 PCS_CTL_powerdown
= 1<<11, // powerdown command
345 PCS_CTL_an_enable
= 1<<12, // Autonegotiation enable
346 PCS_CTL_rx_slpbk
= 1<<14, // Serial Loopback enable
347 PCS_CTL_sw_reset
= 1<<15 // perform soft reset
351 /** PCS Status Register Bits. IEEE 801.2 Clause 22.2.4.2
354 PCS_ST_has_extcap
= 1<<0, // PHY has extended capabilities registers
355 PCS_ST_rx_sync
= 1<<2, // RX is in sync (8B/10B codes o.k.)
356 PCS_ST_an_ability
= 1<<3, // PHY supports autonegotiation
357 PCS_ST_rem_fault
= 1<<4, // Autonegotiation completed
358 PCS_ST_an_done
= 1<<5
362 /** Autonegotiation Capabilities Register Bits. IEEE 802.3 Clause 37.2.1 */
365 ANCAP_NEXTPAGE
= 1 << 15,
373 // all others are reserved
376 /*----------------------------------------------------------------------*/
378 #define MTIP1000_IO_EXTENT (sizeof(np_mtip_mac))
380 /*----------------------------------------------------------------------*/
385 * Declarations for the sysctl interface, which allows users to
386 * control the finer aspects of the Emac. Since the
387 * module registers its sysctl table dynamically, the sysctl path
388 * for module FOO is /proc/sys/dev/ethX/FOO
390 #define CTL_MTIP1000 (CTL_BUS+1389)
391 // arbitrary and hopefully unused
395 CTL_MTIP_INFO
= 1, // Sysctl files information
396 CTL_MTIP_SWVER
, // Driver Software Version Info
399 // Register access for debugging
402 // ---------------------------------------------------
403 CTL_MTIP_LAST_ENTRY
// Add new entries above the line
406 #endif // CONFIG_SYSCTL
408 #endif /* _MTIP1000_H_ */