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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / net / 8139too.c
blobb2e2ed43ada5507c82d99943cb885c7f473f85a2
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #ifdef CONFIG_LEDMAN
115 #include <linux/ledman.h>
116 #endif
117
118 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
119 #define PFX DRV_NAME ": "
120
121 /* Default Message level */
122 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
123 NETIF_MSG_PROBE | \
124 NETIF_MSG_LINK)
125
126
127 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
128 #ifdef CONFIG_8139TOO_PIO
129 #define USE_IO_OPS 1
130 #endif
131
132 /* define to 1, 2 or 3 to enable copious debugging info */
133 #define RTL8139_DEBUG 0
134
135 /* define to 1 to disable lightweight runtime debugging checks */
136 #undef RTL8139_NDEBUG
137
138
139 #if RTL8139_DEBUG
140 /* note: prints function name for you */
141 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
142 #else
143 # define DPRINTK(fmt, args...)
144 #endif
145
146 #ifdef RTL8139_NDEBUG
147 # define assert(expr) do {} while (0)
148 #else
149 # define assert(expr) \
150 if(unlikely(!(expr))) { \
151 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
152 #expr,__FILE__,__FUNCTION__,__LINE__); \
153 }
154 #endif
155
156
157 /* A few user-configurable values. */
158 /* media options */
159 #define MAX_UNITS 8
160 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
161 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
162
163 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
164 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
165 static int multicast_filter_limit = 32;
166
167 /* bitmapped message enable number */
168 static int debug = -1;
169
170 /*
171 * Receive ring size
172 * Warning: 64K ring has hardware issues and may lock up.
173 */
174 #if defined(CONFIG_SH_DREAMCAST)
175 #define RX_BUF_IDX 1 /* 16K ring */
176 #else
177 #define RX_BUF_IDX 2 /* 32K ring */
178 #endif
179 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
180 #define RX_BUF_PAD 16
181 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
182
183 #if RX_BUF_LEN == 65536
184 #define RX_BUF_TOT_LEN RX_BUF_LEN
185 #else
186 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
187 #endif
188
189 /* Number of Tx descriptor registers. */
190 #define NUM_TX_DESC 4
191
192 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
193 #define MAX_ETH_FRAME_SIZE 1536
194
195 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
196 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
197 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
198
199 /* PCI Tuning Parameters
200 Threshold is bytes transferred to chip before transmission starts. */
201 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
202
203 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
204 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
205 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
206 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
207 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
208
209 /* Operational parameters that usually are not changed. */
210 /* Time in jiffies before concluding the transmitter is hung. */
211 #define TX_TIMEOUT (6*HZ)
212
213
214 enum {
215 HAS_MII_XCVR = 0x010000,
216 HAS_CHIP_XCVR = 0x020000,
217 HAS_LNK_CHNG = 0x040000,
218 };
219
220 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
221 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
222 #define RTL_MIN_IO_SIZE 0x80
223 #define RTL8139B_IO_SIZE 256
224
225 #define RTL8129_CAPS HAS_MII_XCVR
226 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
227
228 typedef enum {
229 RTL8139 = 0,
230 RTL8129,
231 } board_t;
232
233
234 /* indexed by board_t, above */
235 static const struct {
236 const char *name;
237 u32 hw_flags;
238 } board_info[] __devinitdata = {
239 { "RealTek RTL8139", RTL8139_CAPS },
240 { "RealTek RTL8129", RTL8129_CAPS },
241 };
242
243
244 static struct pci_device_id rtl8139_pci_tbl[] = {
245 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
262 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
263 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264
265 #if defined(CONFIG_MTD_NETtel) || defined(CONFIG_SH_SECUREEDGE5410)
266 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
268 #endif
269 #ifdef CONFIG_8139TOO_8129
270 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
271 #endif
272
273 /* some crazy cards report invalid vendor ids like
274 * 0x0001 here. The other ids are valid and constant,
275 * so we simply don't match on the main vendor id.
276 */
277 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
278 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
279 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
280
281 {0,}
282 };
283 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
284
285 static struct {
286 const char str[ETH_GSTRING_LEN];
287 } ethtool_stats_keys[] = {
288 { "early_rx" },
289 { "tx_buf_mapped" },
290 { "tx_timeouts" },
291 { "rx_lost_in_ring" },
292 };
293
294 /* The rest of these values should never change. */
295
296 /* Symbolic offsets to registers. */
297 enum RTL8139_registers {
298 MAC0 = 0, /* Ethernet hardware address. */
299 MAR0 = 8, /* Multicast filter. */
300 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
301 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
302 RxBuf = 0x30,
303 ChipCmd = 0x37,
304 RxBufPtr = 0x38,
305 RxBufAddr = 0x3A,
306 IntrMask = 0x3C,
307 IntrStatus = 0x3E,
308 TxConfig = 0x40,
309 RxConfig = 0x44,
310 Timer = 0x48, /* A general-purpose counter. */
311 RxMissed = 0x4C, /* 24 bits valid, write clears. */
312 Cfg9346 = 0x50,
313 Config0 = 0x51,
314 Config1 = 0x52,
315 FlashReg = 0x54,
316 MediaStatus = 0x58,
317 Config3 = 0x59,
318 Config4 = 0x5A, /* absent on RTL-8139A */
319 HltClk = 0x5B,
320 MultiIntr = 0x5C,
321 TxSummary = 0x60,
322 BasicModeCtrl = 0x62,
323 BasicModeStatus = 0x64,
324 NWayAdvert = 0x66,
325 NWayLPAR = 0x68,
326 NWayExpansion = 0x6A,
327 /* Undocumented registers, but required for proper operation. */
328 FIFOTMS = 0x70, /* FIFO Control and test. */
329 CSCR = 0x74, /* Chip Status and Configuration Register. */
330 PARA78 = 0x78,
331 PARA7c = 0x7c, /* Magic transceiver parameter register. */
332 Config5 = 0xD8, /* absent on RTL-8139A */
333 };
334
335 enum ClearBitMasks {
336 MultiIntrClear = 0xF000,
337 ChipCmdClear = 0xE2,
338 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
339 };
340
341 enum ChipCmdBits {
342 CmdReset = 0x10,
343 CmdRxEnb = 0x08,
344 CmdTxEnb = 0x04,
345 RxBufEmpty = 0x01,
346 };
347
348 /* Interrupt register bits, using my own meaningful names. */
349 enum IntrStatusBits {
350 PCIErr = 0x8000,
351 PCSTimeout = 0x4000,
352 RxFIFOOver = 0x40,
353 RxUnderrun = 0x20,
354 RxOverflow = 0x10,
355 TxErr = 0x08,
356 TxOK = 0x04,
357 RxErr = 0x02,
358 RxOK = 0x01,
359
360 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
361 };
362
363 enum TxStatusBits {
364 TxHostOwns = 0x2000,
365 TxUnderrun = 0x4000,
366 TxStatOK = 0x8000,
367 TxOutOfWindow = 0x20000000,
368 TxAborted = 0x40000000,
369 TxCarrierLost = 0x80000000,
370 };
371 enum RxStatusBits {
372 RxMulticast = 0x8000,
373 RxPhysical = 0x4000,
374 RxBroadcast = 0x2000,
375 RxBadSymbol = 0x0020,
376 RxRunt = 0x0010,
377 RxTooLong = 0x0008,
378 RxCRCErr = 0x0004,
379 RxBadAlign = 0x0002,
380 RxStatusOK = 0x0001,
381 };
382
383 /* Bits in RxConfig. */
384 enum rx_mode_bits {
385 AcceptErr = 0x20,
386 AcceptRunt = 0x10,
387 AcceptBroadcast = 0x08,
388 AcceptMulticast = 0x04,
389 AcceptMyPhys = 0x02,
390 AcceptAllPhys = 0x01,
391 };
392
393 /* Bits in TxConfig. */
394 enum tx_config_bits {
395
396 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
397 TxIFGShift = 24,
398 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
399 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
400 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
401 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
402
403 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
404 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
405 TxClearAbt = (1 << 0), /* Clear abort (WO) */
406 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
407 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
408
409 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
410 };
411
412 /* Bits in Config1 */
413 enum Config1Bits {
414 Cfg1_PM_Enable = 0x01,
415 Cfg1_VPD_Enable = 0x02,
416 Cfg1_PIO = 0x04,
417 Cfg1_MMIO = 0x08,
418 LWAKE = 0x10, /* not on 8139, 8139A */
419 Cfg1_Driver_Load = 0x20,
420 Cfg1_LED0 = 0x40,
421 Cfg1_LED1 = 0x80,
422 SLEEP = (1 << 1), /* only on 8139, 8139A */
423 PWRDN = (1 << 0), /* only on 8139, 8139A */
424 };
425
426 /* Bits in Config3 */
427 enum Config3Bits {
428 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
429 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
430 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
431 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
432 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
433 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
434 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
435 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
436 };
437
438 /* Bits in Config4 */
439 enum Config4Bits {
440 LWPTN = (1 << 2), /* not on 8139, 8139A */
441 };
442
443 /* Bits in Config5 */
444 enum Config5Bits {
445 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
446 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
447 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
448 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
449 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
450 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
451 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
452 };
453
454 enum RxConfigBits {
455 /* rx fifo threshold */
456 RxCfgFIFOShift = 13,
457 RxCfgFIFONone = (7 << RxCfgFIFOShift),
458
459 /* Max DMA burst */
460 RxCfgDMAShift = 8,
461 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
462
463 /* rx ring buffer length */
464 RxCfgRcv8K = 0,
465 RxCfgRcv16K = (1 << 11),
466 RxCfgRcv32K = (1 << 12),
467 RxCfgRcv64K = (1 << 11) | (1 << 12),
468
469 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
470 RxNoWrap = (1 << 7),
471 };
472
473 /* Twister tuning parameters from RealTek.
474 Completely undocumented, but required to tune bad links on some boards. */
475 enum CSCRBits {
476 CSCR_LinkOKBit = 0x0400,
477 CSCR_LinkChangeBit = 0x0800,
478 CSCR_LinkStatusBits = 0x0f000,
479 CSCR_LinkDownOffCmd = 0x003c0,
480 CSCR_LinkDownCmd = 0x0f3c0,
481 };
482
483 enum Cfg9346Bits {
484 Cfg9346_Lock = 0x00,
485 Cfg9346_Unlock = 0xC0,
486 };
487
488 typedef enum {
489 CH_8139 = 0,
490 CH_8139_K,
491 CH_8139A,
492 CH_8139A_G,
493 CH_8139B,
494 CH_8130,
495 CH_8139C,
496 CH_8100,
497 CH_8100B_8139D,
498 CH_8101,
499 } chip_t;
500
501 enum chip_flags {
502 HasHltClk = (1 << 0),
503 HasLWake = (1 << 1),
504 };
505
506 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
507 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
508 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
509
510 /* directly indexed by chip_t, above */
511 static const struct {
512 const char *name;
513 u32 version; /* from RTL8139C/RTL8139D docs */
514 u32 flags;
515 } rtl_chip_info[] = {
516 { "RTL-8139",
517 HW_REVID(1, 0, 0, 0, 0, 0, 0),
518 HasHltClk,
519 },
520
521 { "RTL-8139 rev K",
522 HW_REVID(1, 1, 0, 0, 0, 0, 0),
523 HasHltClk,
524 },
525
526 { "RTL-8139A",
527 HW_REVID(1, 1, 1, 0, 0, 0, 0),
528 HasHltClk, /* XXX undocumented? */
529 },
530
531 { "RTL-8139A rev G",
532 HW_REVID(1, 1, 1, 0, 0, 1, 0),
533 HasHltClk, /* XXX undocumented? */
534 },
535
536 { "RTL-8139B",
537 HW_REVID(1, 1, 1, 1, 0, 0, 0),
538 HasLWake,
539 },
540
541 { "RTL-8130",
542 HW_REVID(1, 1, 1, 1, 1, 0, 0),
543 HasLWake,
544 },
545
546 { "RTL-8139C",
547 HW_REVID(1, 1, 1, 0, 1, 0, 0),
548 HasLWake,
549 },
550
551 { "RTL-8100",
552 HW_REVID(1, 1, 1, 1, 0, 1, 0),
553 HasLWake,
554 },
555
556 { "RTL-8100B/8139D",
557 HW_REVID(1, 1, 1, 0, 1, 0, 1),
558 HasHltClk /* XXX undocumented? */
559 | HasLWake,
560 },
561
562 { "RTL-8101",
563 HW_REVID(1, 1, 1, 0, 1, 1, 1),
564 HasLWake,
565 },
566 };
567
568 struct rtl_extra_stats {
569 unsigned long early_rx;
570 unsigned long tx_buf_mapped;
571 unsigned long tx_timeouts;
572 unsigned long rx_lost_in_ring;
573 };
574
575 struct rtl8139_private {
576 void __iomem *mmio_addr;
577 int drv_flags;
578 struct pci_dev *pci_dev;
579 u32 msg_enable;
580 struct net_device_stats stats;
581 unsigned char *rx_ring;
582 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
583 unsigned int tx_flag;
584 unsigned long cur_tx;
585 unsigned long dirty_tx;
586 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
587 unsigned char *tx_bufs; /* Tx bounce buffer region. */
588 dma_addr_t rx_ring_dma;
589 dma_addr_t tx_bufs_dma;
590 signed char phys[4]; /* MII device addresses. */
591 char twistie, twist_row, twist_col; /* Twister tune state. */
592 unsigned int watchdog_fired : 1;
593 unsigned int default_port : 4; /* Last dev->if_port value. */
594 unsigned int have_thread : 1;
595 spinlock_t lock;
596 spinlock_t rx_lock;
597 chip_t chipset;
598 u32 rx_config;
599 struct rtl_extra_stats xstats;
600
601 struct work_struct thread;
602
603 struct mii_if_info mii;
604 unsigned int regs_len;
605 unsigned long fifo_copy_timeout;
606 };
607
608 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
609 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
610 MODULE_LICENSE("GPL");
611 MODULE_VERSION(DRV_VERSION);
612
613 module_param(multicast_filter_limit, int, 0);
614 module_param_array(media, int, NULL, 0);
615 module_param_array(full_duplex, int, NULL, 0);
616 module_param(debug, int, 0);
617 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
618 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
619 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
620 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
621
622 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
623 static int rtl8139_open (struct net_device *dev);
624 static int mdio_read (struct net_device *dev, int phy_id, int location);
625 static void mdio_write (struct net_device *dev, int phy_id, int location,
626 int val);
627 static void rtl8139_start_thread(struct rtl8139_private *tp);
628 static void rtl8139_tx_timeout (struct net_device *dev);
629 static void rtl8139_init_ring (struct net_device *dev);
630 static int rtl8139_start_xmit (struct sk_buff *skb,
631 struct net_device *dev);
632 static int rtl8139_poll(struct net_device *dev, int *budget);
633 #ifdef CONFIG_NET_POLL_CONTROLLER
634 static void rtl8139_poll_controller(struct net_device *dev);
635 #endif
636 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
637 static int rtl8139_close (struct net_device *dev);
638 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
639 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
640 static void rtl8139_set_rx_mode (struct net_device *dev);
641 static void __set_rx_mode (struct net_device *dev);
642 static void rtl8139_hw_start (struct net_device *dev);
643 static void rtl8139_thread (void *_data);
644 static void rtl8139_tx_timeout_task(void *_data);
645 static const struct ethtool_ops rtl8139_ethtool_ops;
646
647 /* write MMIO register, with flush */
648 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
649 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
650 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
651 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
652
653
654 #define MMIO_FLUSH_AUDIT_COMPLETE 1
655 #if MMIO_FLUSH_AUDIT_COMPLETE
656
657 /* write MMIO register */
658 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
659 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
660 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
661
662 #else
663
664 /* write MMIO register, then flush */
665 #define RTL_W8 RTL_W8_F
666 #define RTL_W16 RTL_W16_F
667 #define RTL_W32 RTL_W32_F
668
669 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
670
671 /* read MMIO register */
672 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
673 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
674 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
675
676
677 static const u16 rtl8139_intr_mask =
678 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
679 TxErr | TxOK | RxErr | RxOK;
680
681 static const u16 rtl8139_norx_intr_mask =
682 PCIErr | PCSTimeout | RxUnderrun |
683 TxErr | TxOK | RxErr ;
684
685 #if RX_BUF_IDX == 0
686 static const unsigned int rtl8139_rx_config =
687 RxCfgRcv8K | RxNoWrap |
688 (RX_FIFO_THRESH << RxCfgFIFOShift) |
689 (RX_DMA_BURST << RxCfgDMAShift);
690 #elif RX_BUF_IDX == 1
691 static const unsigned int rtl8139_rx_config =
692 RxCfgRcv16K | RxNoWrap |
693 (RX_FIFO_THRESH << RxCfgFIFOShift) |
694 (RX_DMA_BURST << RxCfgDMAShift);
695 #elif RX_BUF_IDX == 2
696 static const unsigned int rtl8139_rx_config =
697 RxCfgRcv32K | RxNoWrap |
698 (RX_FIFO_THRESH << RxCfgFIFOShift) |
699 (RX_DMA_BURST << RxCfgDMAShift);
700 #elif RX_BUF_IDX == 3
701 static const unsigned int rtl8139_rx_config =
702 RxCfgRcv64K |
703 (RX_FIFO_THRESH << RxCfgFIFOShift) |
704 (RX_DMA_BURST << RxCfgDMAShift);
705 #else
706 #error "Invalid configuration for 8139_RXBUF_IDX"
707 #endif
708
709 static const unsigned int rtl8139_tx_config =
710 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
711
712 static void __rtl8139_cleanup_dev (struct net_device *dev)
713 {
714 struct rtl8139_private *tp = netdev_priv(dev);
715 struct pci_dev *pdev;
716
717 assert (dev != NULL);
718 assert (tp->pci_dev != NULL);
719 pdev = tp->pci_dev;
720
721 #ifdef USE_IO_OPS
722 if (tp->mmio_addr)
723 ioport_unmap (tp->mmio_addr);
724 #else
725 if (tp->mmio_addr)
726 pci_iounmap (pdev, tp->mmio_addr);
727 #endif /* USE_IO_OPS */
728
729 /* it's ok to call this even if we have no regions to free */
730 pci_release_regions (pdev);
731
732 free_netdev(dev);
733 pci_set_drvdata (pdev, NULL);
734 }
735
736
737 static void rtl8139_chip_reset (void __iomem *ioaddr)
738 {
739 int i;
740
741 /* Soft reset the chip. */
742 RTL_W8 (ChipCmd, CmdReset);
743
744 /* Check that the chip has finished the reset. */
745 for (i = 1000; i > 0; i--) {
746 barrier();
747 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
748 break;
749 udelay (10);
750 }
751 }
752
753
754 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
755 struct net_device **dev_out)
756 {
757 void __iomem *ioaddr;
758 struct net_device *dev;
759 struct rtl8139_private *tp;
760 u8 tmp8;
761 int rc, disable_dev_on_err = 0;
762 unsigned int i;
763 unsigned long pio_start, pio_end, pio_flags, pio_len;
764 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
765 u32 version;
766
767 assert (pdev != NULL);
768
769 *dev_out = NULL;
770
771 /* dev and priv zeroed in alloc_etherdev */
772 dev = alloc_etherdev (sizeof (*tp));
773 if (dev == NULL) {
774 dev_err(&pdev->dev, "Unable to alloc new net device\n");
775 return -ENOMEM;
776 }
777 SET_MODULE_OWNER(dev);
778 SET_NETDEV_DEV(dev, &pdev->dev);
779
780 tp = netdev_priv(dev);
781 tp->pci_dev = pdev;
782
783 /* enable device (incl. PCI PM wakeup and hotplug setup) */
784 rc = pci_enable_device (pdev);
785 if (rc)
786 goto err_out;
787
788 pio_start = pci_resource_start (pdev, 0);
789 pio_end = pci_resource_end (pdev, 0);
790 pio_flags = pci_resource_flags (pdev, 0);
791 pio_len = pci_resource_len (pdev, 0);
792
793 mmio_start = pci_resource_start (pdev, 1);
794 mmio_end = pci_resource_end (pdev, 1);
795 mmio_flags = pci_resource_flags (pdev, 1);
796 mmio_len = pci_resource_len (pdev, 1);
797
798 /* set this immediately, we need to know before
799 * we talk to the chip directly */
800 DPRINTK("PIO region size == 0x%02X\n", pio_len);
801 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
802
803 #ifdef USE_IO_OPS
804 /* make sure PCI base addr 0 is PIO */
805 if (!(pio_flags & IORESOURCE_IO)) {
806 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
807 rc = -ENODEV;
808 goto err_out;
809 }
810 /* check for weird/broken PCI region reporting */
811 if (pio_len < RTL_MIN_IO_SIZE) {
812 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
813 rc = -ENODEV;
814 goto err_out;
815 }
816 #else
817 /* make sure PCI base addr 1 is MMIO */
818 if (!(mmio_flags & IORESOURCE_MEM)) {
819 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
820 rc = -ENODEV;
821 goto err_out;
822 }
823 if (mmio_len < RTL_MIN_IO_SIZE) {
824 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
825 rc = -ENODEV;
826 goto err_out;
827 }
828 #endif
829
830 rc = pci_request_regions (pdev, DRV_NAME);
831 if (rc)
832 goto err_out;
833 disable_dev_on_err = 1;
834
835 /* enable PCI bus-mastering */
836 pci_set_master (pdev);
837
838 #ifdef USE_IO_OPS
839 ioaddr = ioport_map(pio_start, pio_len);
840 if (!ioaddr) {
841 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
842 rc = -EIO;
843 goto err_out;
844 }
845 dev->base_addr = pio_start;
846 tp->mmio_addr = ioaddr;
847 tp->regs_len = pio_len;
848 #else
849 /* ioremap MMIO region */
850 ioaddr = pci_iomap(pdev, 1, 0);
851 if (ioaddr == NULL) {
852 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
853 rc = -EIO;
854 goto err_out;
855 }
856 dev->base_addr = (long) ioaddr;
857 tp->mmio_addr = ioaddr;
858 tp->regs_len = mmio_len;
859 #endif /* USE_IO_OPS */
860
861 /* Bring old chips out of low-power mode. */
862 RTL_W8 (HltClk, 'R');
863
864 /* check for missing/broken hardware */
865 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
866 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
867 rc = -EIO;
868 goto err_out;
869 }
870
871 /* identify chip attached to board */
872 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
873 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
874 if (version == rtl_chip_info[i].version) {
875 tp->chipset = i;
876 goto match;
877 }
878
879 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
880 dev_printk (KERN_DEBUG, &pdev->dev,
881 "unknown chip version, assuming RTL-8139\n");
882 dev_printk (KERN_DEBUG, &pdev->dev,
883 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
884 tp->chipset = 0;
885
886 match:
887 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
888 version, i, rtl_chip_info[i].name);
889
890 if (tp->chipset >= CH_8139B) {
891 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
892 DPRINTK("PCI PM wakeup\n");
893 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
894 (tmp8 & LWAKE))
895 new_tmp8 &= ~LWAKE;
896 new_tmp8 |= Cfg1_PM_Enable;
897 if (new_tmp8 != tmp8) {
898 RTL_W8 (Cfg9346, Cfg9346_Unlock);
899 RTL_W8 (Config1, tmp8);
900 RTL_W8 (Cfg9346, Cfg9346_Lock);
901 }
902 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
903 tmp8 = RTL_R8 (Config4);
904 if (tmp8 & LWPTN) {
905 RTL_W8 (Cfg9346, Cfg9346_Unlock);
906 RTL_W8 (Config4, tmp8 & ~LWPTN);
907 RTL_W8 (Cfg9346, Cfg9346_Lock);
908 }
909 }
910 } else {
911 DPRINTK("Old chip wakeup\n");
912 tmp8 = RTL_R8 (Config1);
913 tmp8 &= ~(SLEEP | PWRDN);
914 RTL_W8 (Config1, tmp8);
915 }
916
917 rtl8139_chip_reset (ioaddr);
918
919 *dev_out = dev;
920 return 0;
921
922 err_out:
923 __rtl8139_cleanup_dev (dev);
924 if (disable_dev_on_err)
925 pci_disable_device (pdev);
926 return rc;
927 }
928
929
930 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
931 const struct pci_device_id *ent)
932 {
933 struct net_device *dev = NULL;
934 struct rtl8139_private *tp;
935 int i, addr_len, option;
936 void __iomem *ioaddr;
937 static int board_idx = -1;
938 u8 pci_rev;
939
940 assert (pdev != NULL);
941 assert (ent != NULL);
942
943 board_idx++;
944
945 /* when we're built into the kernel, the driver version message
946 * is only printed if at least one 8139 board has been found
947 */
948 #ifndef MODULE
949 {
950 static int printed_version;
951 if (!printed_version++)
952 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
953 }
954 #endif
955
956 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
957
958 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
959 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
960 dev_info(&pdev->dev,
961 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
962 pdev->vendor, pdev->device, pci_rev);
963 dev_info(&pdev->dev,
964 "Use the \"8139cp\" driver for improved performance and stability.\n");
965 }
966
967 i = rtl8139_init_board (pdev, &dev);
968 if (i < 0)
969 return i;
970
971 assert (dev != NULL);
972 tp = netdev_priv(dev);
973
974 ioaddr = tp->mmio_addr;
975 assert (ioaddr != NULL);
976
977 #if defined(CONFIG_MTD_NETtel) || defined(CONFIG_SH_SECUREEDGE5410)
978 /* Don't rely on the eeprom, get MAC from chip. */
979 for (i = 0; i < 6; i++)
980 dev->dev_addr[i] = readb(ioaddr + MAC0 + i);
981 #else
982 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
983 for (i = 0; i < 3; i++)
984 ((u16 *) (dev->dev_addr))[i] =
985 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
986 #endif
987 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
988
989 /* The Rtl8139-specific entries in the device structure. */
990 dev->open = rtl8139_open;
991 dev->hard_start_xmit = rtl8139_start_xmit;
992 dev->poll = rtl8139_poll;
993 dev->weight = 64;
994 dev->stop = rtl8139_close;
995 dev->get_stats = rtl8139_get_stats;
996 dev->set_multicast_list = rtl8139_set_rx_mode;
997 dev->do_ioctl = netdev_ioctl;
998 dev->ethtool_ops = &rtl8139_ethtool_ops;
999 dev->tx_timeout = rtl8139_tx_timeout;
1000 dev->watchdog_timeo = TX_TIMEOUT;
1001 #ifdef CONFIG_NET_POLL_CONTROLLER
1002 dev->poll_controller = rtl8139_poll_controller;
1003 #endif
1004
1005 /* note: the hardware is not capable of sg/csum/highdma, however
1006 * through the use of skb_copy_and_csum_dev we enable these
1007 * features
1008 */
1009 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1010
1011 dev->irq = pdev->irq;
1012
1013 /* tp zeroed and aligned in alloc_etherdev */
1014 tp = netdev_priv(dev);
1015
1016 /* note: tp->chipset set in rtl8139_init_board */
1017 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1018 tp->mmio_addr = ioaddr;
1019 tp->msg_enable =
1020 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1021 spin_lock_init (&tp->lock);
1022 spin_lock_init (&tp->rx_lock);
1023 INIT_WORK(&tp->thread, rtl8139_thread, dev);
1024 tp->mii.dev = dev;
1025 tp->mii.mdio_read = mdio_read;
1026 tp->mii.mdio_write = mdio_write;
1027 tp->mii.phy_id_mask = 0x3f;
1028 tp->mii.reg_num_mask = 0x1f;
1029
1030 /* dev is fully set up and ready to use now */
1031 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1032 i = register_netdev (dev);
1033 if (i) goto err_out;
1034
1035 pci_set_drvdata (pdev, dev);
1036
1037 printk (KERN_INFO "%s: %s at 0x%lx, "
1038 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1039 "IRQ %d\n",
1040 dev->name,
1041 board_info[ent->driver_data].name,
1042 dev->base_addr,
1043 dev->dev_addr[0], dev->dev_addr[1],
1044 dev->dev_addr[2], dev->dev_addr[3],
1045 dev->dev_addr[4], dev->dev_addr[5],
1046 dev->irq);
1047
1048 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1049 dev->name, rtl_chip_info[tp->chipset].name);
1050
1051 /* Find the connected MII xcvrs.
1052 Doing this in open() would allow detecting external xcvrs later, but
1053 takes too much time. */
1054 #ifdef CONFIG_8139TOO_8129
1055 if (tp->drv_flags & HAS_MII_XCVR) {
1056 int phy, phy_idx = 0;
1057 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1058 int mii_status = mdio_read(dev, phy, 1);
1059 if (mii_status != 0xffff && mii_status != 0x0000) {
1060 u16 advertising = mdio_read(dev, phy, 4);
1061 tp->phys[phy_idx++] = phy;
1062 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1063 "advertising %4.4x.\n",
1064 dev->name, phy, mii_status, advertising);
1065 }
1066 }
1067 if (phy_idx == 0) {
1068 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1069 "transceiver.\n",
1070 dev->name);
1071 tp->phys[0] = 32;
1072 }
1073 } else
1074 #endif
1075 tp->phys[0] = 32;
1076 tp->mii.phy_id = tp->phys[0];
1077
1078 /* The lower four bits are the media type. */
1079 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1080 if (option > 0) {
1081 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1082 tp->default_port = option & 0xFF;
1083 if (tp->default_port)
1084 tp->mii.force_media = 1;
1085 }
1086 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1087 tp->mii.full_duplex = full_duplex[board_idx];
1088 if (tp->mii.full_duplex) {
1089 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1090 /* Changing the MII-advertised media because might prevent
1091 re-connection. */
1092 tp->mii.force_media = 1;
1093 }
1094 if (tp->default_port) {
1095 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1096 (option & 0x20 ? 100 : 10),
1097 (option & 0x10 ? "full" : "half"));
1098 mdio_write(dev, tp->phys[0], 0,
1099 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1100 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1101 }
1102
1103 /* Put the chip into low-power mode. */
1104 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1105 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1106
1107 return 0;
1108
1109 err_out:
1110 __rtl8139_cleanup_dev (dev);
1111 pci_disable_device (pdev);
1112 return i;
1113 }
1114
1115
1116 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1117 {
1118 struct net_device *dev = pci_get_drvdata (pdev);
1119
1120 assert (dev != NULL);
1121
1122 unregister_netdev (dev);
1123
1124 __rtl8139_cleanup_dev (dev);
1125 pci_disable_device (pdev);
1126 }
1127
1128
1129 /* Serial EEPROM section. */
1130
1131 /* EEPROM_Ctrl bits. */
1132 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1133 #define EE_CS 0x08 /* EEPROM chip select. */
1134 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1135 #define EE_WRITE_0 0x00
1136 #define EE_WRITE_1 0x02
1137 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1138 #define EE_ENB (0x80 | EE_CS)
1139
1140 /* Delay between EEPROM clock transitions.
1141 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1142 */
1143
1144 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1145
1146 /* The EEPROM commands include the alway-set leading bit. */
1147 #define EE_WRITE_CMD (5)
1148 #define EE_READ_CMD (6)
1149 #define EE_ERASE_CMD (7)
1150
1151 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1152 {
1153 int i;
1154 unsigned retval = 0;
1155 int read_cmd = location | (EE_READ_CMD << addr_len);
1156
1157 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1158 RTL_W8 (Cfg9346, EE_ENB);
1159 eeprom_delay ();
1160
1161 /* Shift the read command bits out. */
1162 for (i = 4 + addr_len; i >= 0; i--) {
1163 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1164 RTL_W8 (Cfg9346, EE_ENB | dataval);
1165 eeprom_delay ();
1166 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1167 eeprom_delay ();
1168 }
1169 RTL_W8 (Cfg9346, EE_ENB);
1170 eeprom_delay ();
1171
1172 for (i = 16; i > 0; i--) {
1173 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1174 eeprom_delay ();
1175 retval =
1176 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1177 0);
1178 RTL_W8 (Cfg9346, EE_ENB);
1179 eeprom_delay ();
1180 }
1181
1182 /* Terminate the EEPROM access. */
1183 RTL_W8 (Cfg9346, ~EE_CS);
1184 eeprom_delay ();
1185
1186 return retval;
1187 }
1188
1189 /* MII serial management: mostly bogus for now. */
1190 /* Read and write the MII management registers using software-generated
1191 serial MDIO protocol.
1192 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1193 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1194 "overclocking" issues. */
1195 #define MDIO_DIR 0x80
1196 #define MDIO_DATA_OUT 0x04
1197 #define MDIO_DATA_IN 0x02
1198 #define MDIO_CLK 0x01
1199 #define MDIO_WRITE0 (MDIO_DIR)
1200 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1201
1202 #define mdio_delay() RTL_R8(Config4)
1203
1204
1205 static const char mii_2_8139_map[8] = {
1206 BasicModeCtrl,
1207 BasicModeStatus,
1208 0,
1209 0,
1210 NWayAdvert,
1211 NWayLPAR,
1212 NWayExpansion,
1213 0
1214 };
1215
1216
1217 #ifdef CONFIG_8139TOO_8129
1218 /* Syncronize the MII management interface by shifting 32 one bits out. */
1219 static void mdio_sync (void __iomem *ioaddr)
1220 {
1221 int i;
1222
1223 for (i = 32; i >= 0; i--) {
1224 RTL_W8 (Config4, MDIO_WRITE1);
1225 mdio_delay ();
1226 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1227 mdio_delay ();
1228 }
1229 }
1230 #endif
1231
1232 static int mdio_read (struct net_device *dev, int phy_id, int location)
1233 {
1234 struct rtl8139_private *tp = netdev_priv(dev);
1235 int retval = 0;
1236 #ifdef CONFIG_8139TOO_8129
1237 void __iomem *ioaddr = tp->mmio_addr;
1238 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1239 int i;
1240 #endif
1241
1242 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1243 void __iomem *ioaddr = tp->mmio_addr;
1244 return location < 8 && mii_2_8139_map[location] ?
1245 RTL_R16 (mii_2_8139_map[location]) : 0;
1246 }
1247
1248 #ifdef CONFIG_8139TOO_8129
1249 mdio_sync (ioaddr);
1250 /* Shift the read command bits out. */
1251 for (i = 15; i >= 0; i--) {
1252 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1253
1254 RTL_W8 (Config4, MDIO_DIR | dataval);
1255 mdio_delay ();
1256 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1257 mdio_delay ();
1258 }
1259
1260 /* Read the two transition, 16 data, and wire-idle bits. */
1261 for (i = 19; i > 0; i--) {
1262 RTL_W8 (Config4, 0);
1263 mdio_delay ();
1264 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1265 RTL_W8 (Config4, MDIO_CLK);
1266 mdio_delay ();
1267 }
1268 #endif
1269
1270 return (retval >> 1) & 0xffff;
1271 }
1272
1273
1274 static void mdio_write (struct net_device *dev, int phy_id, int location,
1275 int value)
1276 {
1277 struct rtl8139_private *tp = netdev_priv(dev);
1278 #ifdef CONFIG_8139TOO_8129
1279 void __iomem *ioaddr = tp->mmio_addr;
1280 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1281 int i;
1282 #endif
1283
1284 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1285 void __iomem *ioaddr = tp->mmio_addr;
1286 if (location == 0) {
1287 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1288 RTL_W16 (BasicModeCtrl, value);
1289 RTL_W8 (Cfg9346, Cfg9346_Lock);
1290 } else if (location < 8 && mii_2_8139_map[location])
1291 RTL_W16 (mii_2_8139_map[location], value);
1292 return;
1293 }
1294
1295 #ifdef CONFIG_8139TOO_8129
1296 mdio_sync (ioaddr);
1297
1298 /* Shift the command bits out. */
1299 for (i = 31; i >= 0; i--) {
1300 int dataval =
1301 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1302 RTL_W8 (Config4, dataval);
1303 mdio_delay ();
1304 RTL_W8 (Config4, dataval | MDIO_CLK);
1305 mdio_delay ();
1306 }
1307 /* Clear out extra bits. */
1308 for (i = 2; i > 0; i--) {
1309 RTL_W8 (Config4, 0);
1310 mdio_delay ();
1311 RTL_W8 (Config4, MDIO_CLK);
1312 mdio_delay ();
1313 }
1314 #endif
1315 }
1316
1317
1318 static int rtl8139_open (struct net_device *dev)
1319 {
1320 struct rtl8139_private *tp = netdev_priv(dev);
1321 int retval;
1322 void __iomem *ioaddr = tp->mmio_addr;
1323
1324 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1325 if (retval)
1326 return retval;
1327
1328 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1329 &tp->tx_bufs_dma);
1330 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1331 &tp->rx_ring_dma);
1332 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1333 free_irq(dev->irq, dev);
1334
1335 if (tp->tx_bufs)
1336 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1337 tp->tx_bufs, tp->tx_bufs_dma);
1338 if (tp->rx_ring)
1339 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1340 tp->rx_ring, tp->rx_ring_dma);
1341
1342 return -ENOMEM;
1343
1344 }
1345
1346 tp->mii.full_duplex = tp->mii.force_media;
1347 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1348
1349 rtl8139_init_ring (dev);
1350 rtl8139_hw_start (dev);
1351 netif_start_queue (dev);
1352
1353 if (netif_msg_ifup(tp))
1354 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1355 " GP Pins %2.2x %s-duplex.\n", dev->name,
1356 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1357 dev->irq, RTL_R8 (MediaStatus),
1358 tp->mii.full_duplex ? "full" : "half");
1359
1360 rtl8139_start_thread(tp);
1361
1362 return 0;
1363 }
1364
1365
1366 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1367 {
1368 struct rtl8139_private *tp = netdev_priv(dev);
1369
1370 if (tp->phys[0] >= 0) {
1371 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1372 }
1373 }
1374
1375 /* Start the hardware at open or resume. */
1376 static void rtl8139_hw_start (struct net_device *dev)
1377 {
1378 struct rtl8139_private *tp = netdev_priv(dev);
1379 void __iomem *ioaddr = tp->mmio_addr;
1380 u32 i;
1381 u8 tmp;
1382
1383 /* Bring old chips out of low-power mode. */
1384 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1385 RTL_W8 (HltClk, 'R');
1386
1387 rtl8139_chip_reset (ioaddr);
1388
1389 /* unlock Config[01234] and BMCR register writes */
1390 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1391 /* Restore our idea of the MAC address. */
1392 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1393 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1394
1395 /* Must enable Tx/Rx before setting transfer thresholds! */
1396 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1397
1398 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1399 RTL_W32 (RxConfig, tp->rx_config);
1400 RTL_W32 (TxConfig, rtl8139_tx_config);
1401
1402 tp->cur_rx = 0;
1403
1404 rtl_check_media (dev, 1);
1405
1406 if (tp->chipset >= CH_8139B) {
1407 /* Disable magic packet scanning, which is enabled
1408 * when PM is enabled in Config1. It can be reenabled
1409 * via ETHTOOL_SWOL if desired. */
1410 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1411 }
1412
1413 DPRINTK("init buffer addresses\n");
1414
1415 /* Lock Config[01234] and BMCR register writes */
1416 RTL_W8 (Cfg9346, Cfg9346_Lock);
1417
1418 /* init Rx ring buffer DMA address */
1419 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1420
1421 /* init Tx buffer DMA addresses */
1422 for (i = 0; i < NUM_TX_DESC; i++)
1423 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1424
1425 RTL_W32 (RxMissed, 0);
1426
1427 rtl8139_set_rx_mode (dev);
1428
1429 /* no early-rx interrupts */
1430 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1431
1432 /* make sure RxTx has started */
1433 tmp = RTL_R8 (ChipCmd);
1434 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1435 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1436
1437 /* Enable all known interrupts by setting the interrupt mask. */
1438 RTL_W16 (IntrMask, rtl8139_intr_mask);
1439 }
1440
1441
1442 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1443 static void rtl8139_init_ring (struct net_device *dev)
1444 {
1445 struct rtl8139_private *tp = netdev_priv(dev);
1446 int i;
1447
1448 tp->cur_rx = 0;
1449 tp->cur_tx = 0;
1450 tp->dirty_tx = 0;
1451
1452 for (i = 0; i < NUM_TX_DESC; i++)
1453 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1454 }
1455
1456
1457 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1458 static int next_tick = 3 * HZ;
1459
1460 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1461 static inline void rtl8139_tune_twister (struct net_device *dev,
1462 struct rtl8139_private *tp) {}
1463 #else
1464 enum TwisterParamVals {
1465 PARA78_default = 0x78fa8388,
1466 PARA7c_default = 0xcb38de43, /* param[0][3] */
1467 PARA7c_xxx = 0xcb38de43,
1468 };
1469
1470 static const unsigned long param[4][4] = {
1471 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1472 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1473 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1474 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1475 };
1476
1477 static void rtl8139_tune_twister (struct net_device *dev,
1478 struct rtl8139_private *tp)
1479 {
1480 int linkcase;
1481 void __iomem *ioaddr = tp->mmio_addr;
1482
1483 /* This is a complicated state machine to configure the "twister" for
1484 impedance/echos based on the cable length.
1485 All of this is magic and undocumented.
1486 */
1487 switch (tp->twistie) {
1488 case 1:
1489 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1490 /* We have link beat, let us tune the twister. */
1491 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1492 tp->twistie = 2; /* Change to state 2. */
1493 next_tick = HZ / 10;
1494 } else {
1495 /* Just put in some reasonable defaults for when beat returns. */
1496 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1497 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1498 RTL_W32 (PARA78, PARA78_default);
1499 RTL_W32 (PARA7c, PARA7c_default);
1500 tp->twistie = 0; /* Bail from future actions. */
1501 }
1502 break;
1503 case 2:
1504 /* Read how long it took to hear the echo. */
1505 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1506 if (linkcase == 0x7000)
1507 tp->twist_row = 3;
1508 else if (linkcase == 0x3000)
1509 tp->twist_row = 2;
1510 else if (linkcase == 0x1000)
1511 tp->twist_row = 1;
1512 else
1513 tp->twist_row = 0;
1514 tp->twist_col = 0;
1515 tp->twistie = 3; /* Change to state 2. */
1516 next_tick = HZ / 10;
1517 break;
1518 case 3:
1519 /* Put out four tuning parameters, one per 100msec. */
1520 if (tp->twist_col == 0)
1521 RTL_W16 (FIFOTMS, 0);
1522 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1523 [(int) tp->twist_col]);
1524 next_tick = HZ / 10;
1525 if (++tp->twist_col >= 4) {
1526 /* For short cables we are done.
1527 For long cables (row == 3) check for mistune. */
1528 tp->twistie =
1529 (tp->twist_row == 3) ? 4 : 0;
1530 }
1531 break;
1532 case 4:
1533 /* Special case for long cables: check for mistune. */
1534 if ((RTL_R16 (CSCR) &
1535 CSCR_LinkStatusBits) == 0x7000) {
1536 tp->twistie = 0;
1537 break;
1538 } else {
1539 RTL_W32 (PARA7c, 0xfb38de03);
1540 tp->twistie = 5;
1541 next_tick = HZ / 10;
1542 }
1543 break;
1544 case 5:
1545 /* Retune for shorter cable (column 2). */
1546 RTL_W32 (FIFOTMS, 0x20);
1547 RTL_W32 (PARA78, PARA78_default);
1548 RTL_W32 (PARA7c, PARA7c_default);
1549 RTL_W32 (FIFOTMS, 0x00);
1550 tp->twist_row = 2;
1551 tp->twist_col = 0;
1552 tp->twistie = 3;
1553 next_tick = HZ / 10;
1554 break;
1555
1556 default:
1557 /* do nothing */
1558 break;
1559 }
1560 }
1561 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1562
1563 static inline void rtl8139_thread_iter (struct net_device *dev,
1564 struct rtl8139_private *tp,
1565 void __iomem *ioaddr)
1566 {
1567 int mii_lpa;
1568
1569 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1570
1571 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1572 int duplex = (mii_lpa & LPA_100FULL)
1573 || (mii_lpa & 0x01C0) == 0x0040;
1574 if (tp->mii.full_duplex != duplex) {
1575 tp->mii.full_duplex = duplex;
1576
1577 if (mii_lpa) {
1578 printk (KERN_INFO
1579 "%s: Setting %s-duplex based on MII #%d link"
1580 " partner ability of %4.4x.\n",
1581 dev->name,
1582 tp->mii.full_duplex ? "full" : "half",
1583 tp->phys[0], mii_lpa);
1584 } else {
1585 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1586 dev->name);
1587 }
1588 #if 0
1589 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1590 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1591 RTL_W8 (Cfg9346, Cfg9346_Lock);
1592 #endif
1593 }
1594 }
1595
1596 next_tick = HZ * 60;
1597
1598 rtl8139_tune_twister (dev, tp);
1599
1600 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1601 dev->name, RTL_R16 (NWayLPAR));
1602 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1603 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1604 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1605 dev->name, RTL_R8 (Config0),
1606 RTL_R8 (Config1));
1607 }
1608
1609 static void rtl8139_thread (void *_data)
1610 {
1611 struct net_device *dev = _data;
1612 struct rtl8139_private *tp = netdev_priv(dev);
1613 unsigned long thr_delay = next_tick;
1614
1615 if (tp->watchdog_fired) {
1616 tp->watchdog_fired = 0;
1617 rtl8139_tx_timeout_task(_data);
1618 } else if (rtnl_trylock()) {
1619 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1620 rtnl_unlock ();
1621 } else {
1622 /* unlikely race. mitigate with fast poll. */
1623 thr_delay = HZ / 2;
1624 }
1625
1626 schedule_delayed_work(&tp->thread, thr_delay);
1627 }
1628
1629 static void rtl8139_start_thread(struct rtl8139_private *tp)
1630 {
1631 tp->twistie = 0;
1632 if (tp->chipset == CH_8139_K)
1633 tp->twistie = 1;
1634 else if (tp->drv_flags & HAS_LNK_CHNG)
1635 return;
1636
1637 tp->have_thread = 1;
1638
1639 schedule_delayed_work(&tp->thread, next_tick);
1640 }
1641
1642 static void rtl8139_stop_thread(struct rtl8139_private *tp)
1643 {
1644 if (tp->have_thread) {
1645 cancel_rearming_delayed_work(&tp->thread);
1646 tp->have_thread = 0;
1647 } else
1648 flush_scheduled_work();
1649 }
1650
1651 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1652 {
1653 tp->cur_tx = 0;
1654 tp->dirty_tx = 0;
1655
1656 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1657 }
1658
1659 static void rtl8139_tx_timeout_task (void *_data)
1660 {
1661 struct net_device *dev = _data;
1662 struct rtl8139_private *tp = netdev_priv(dev);
1663 void __iomem *ioaddr = tp->mmio_addr;
1664 int i;
1665 u8 tmp8;
1666
1667 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1668 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1669 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1670 /* Emit info to figure out what went wrong. */
1671 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1672 dev->name, tp->cur_tx, tp->dirty_tx);
1673 for (i = 0; i < NUM_TX_DESC; i++)
1674 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1675 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1676 i == tp->dirty_tx % NUM_TX_DESC ?
1677 " (queue head)" : "");
1678
1679 tp->xstats.tx_timeouts++;
1680
1681 /* disable Tx ASAP, if not already */
1682 tmp8 = RTL_R8 (ChipCmd);
1683 if (tmp8 & CmdTxEnb)
1684 RTL_W8 (ChipCmd, CmdRxEnb);
1685
1686 spin_lock_bh(&tp->rx_lock);
1687 /* Disable interrupts by clearing the interrupt mask. */
1688 RTL_W16 (IntrMask, 0x0000);
1689
1690 /* Stop a shared interrupt from scavenging while we are. */
1691 spin_lock_irq(&tp->lock);
1692 rtl8139_tx_clear (tp);
1693 spin_unlock_irq(&tp->lock);
1694
1695 /* ...and finally, reset everything */
1696 if (netif_running(dev)) {
1697 rtl8139_hw_start (dev);
1698 netif_wake_queue (dev);
1699 }
1700 spin_unlock_bh(&tp->rx_lock);
1701 }
1702
1703 static void rtl8139_tx_timeout (struct net_device *dev)
1704 {
1705 struct rtl8139_private *tp = netdev_priv(dev);
1706
1707 if (!tp->have_thread) {
1708 INIT_WORK(&tp->thread, rtl8139_tx_timeout_task, dev);
1709 schedule_delayed_work(&tp->thread, next_tick);
1710 } else
1711 tp->watchdog_fired = 1;
1712
1713 }
1714
1715 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1716 {
1717 struct rtl8139_private *tp = netdev_priv(dev);
1718 void __iomem *ioaddr = tp->mmio_addr;
1719 unsigned int entry;
1720 unsigned int len = skb->len;
1721 unsigned long flags;
1722
1723 #ifdef CONFIG_LEDMAN
1724 ledman_cmd(LEDMAN_CMD_SET,
1725 (dev->name[3] == '0') ? LEDMAN_LAN1_TX : LEDMAN_LAN2_TX);
1726 #endif
1727
1728 /* Calculate the next Tx descriptor entry. */
1729 entry = tp->cur_tx % NUM_TX_DESC;
1730
1731 /* Note: the chip doesn't have auto-pad! */
1732 if (likely(len < TX_BUF_SIZE)) {
1733 if (len < ETH_ZLEN)
1734 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1735 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1736 dev_kfree_skb(skb);
1737 } else {
1738 dev_kfree_skb(skb);
1739 tp->stats.tx_dropped++;
1740 return 0;
1741 }
1742
1743 spin_lock_irqsave(&tp->lock, flags);
1744 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1745 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1746
1747 dev->trans_start = jiffies;
1748
1749 tp->cur_tx++;
1750 wmb();
1751
1752 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1753 netif_stop_queue (dev);
1754 spin_unlock_irqrestore(&tp->lock, flags);
1755
1756 if (netif_msg_tx_queued(tp))
1757 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1758 dev->name, len, entry);
1759
1760 return 0;
1761 }
1762
1763
1764 static void rtl8139_tx_interrupt (struct net_device *dev,
1765 struct rtl8139_private *tp,
1766 void __iomem *ioaddr)
1767 {
1768 unsigned long dirty_tx, tx_left;
1769
1770 assert (dev != NULL);
1771 assert (ioaddr != NULL);
1772
1773 dirty_tx = tp->dirty_tx;
1774 tx_left = tp->cur_tx - dirty_tx;
1775 while (tx_left > 0) {
1776 int entry = dirty_tx % NUM_TX_DESC;
1777 int txstatus;
1778
1779 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1780
1781 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1782 break; /* It still hasn't been Txed */
1783
1784 /* Note: TxCarrierLost is always asserted at 100mbps. */
1785 if (txstatus & (TxOutOfWindow | TxAborted)) {
1786 /* There was an major error, log it. */
1787 if (netif_msg_tx_err(tp))
1788 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1789 dev->name, txstatus);
1790 tp->stats.tx_errors++;
1791 if (txstatus & TxAborted) {
1792 tp->stats.tx_aborted_errors++;
1793 RTL_W32 (TxConfig, TxClearAbt);
1794 RTL_W16 (IntrStatus, TxErr);
1795 wmb();
1796 }
1797 if (txstatus & TxCarrierLost)
1798 tp->stats.tx_carrier_errors++;
1799 if (txstatus & TxOutOfWindow)
1800 tp->stats.tx_window_errors++;
1801 } else {
1802 if (txstatus & TxUnderrun) {
1803 /* Add 64 to the Tx FIFO threshold. */
1804 if (tp->tx_flag < 0x00300000)
1805 tp->tx_flag += 0x00020000;
1806 tp->stats.tx_fifo_errors++;
1807 }
1808 tp->stats.collisions += (txstatus >> 24) & 15;
1809 tp->stats.tx_bytes += txstatus & 0x7ff;
1810 tp->stats.tx_packets++;
1811 }
1812
1813 dirty_tx++;
1814 tx_left--;
1815 }
1816
1817 #ifndef RTL8139_NDEBUG
1818 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1819 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1820 dev->name, dirty_tx, tp->cur_tx);
1821 dirty_tx += NUM_TX_DESC;
1822 }
1823 #endif /* RTL8139_NDEBUG */
1824
1825 /* only wake the queue if we did work, and the queue is stopped */
1826 if (tp->dirty_tx != dirty_tx) {
1827 tp->dirty_tx = dirty_tx;
1828 mb();
1829 netif_wake_queue (dev);
1830 }
1831 }
1832
1833
1834 /* TODO: clean this up! Rx reset need not be this intensive */
1835 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1836 struct rtl8139_private *tp, void __iomem *ioaddr)
1837 {
1838 u8 tmp8;
1839 #ifdef CONFIG_8139_OLD_RX_RESET
1840 int tmp_work;
1841 #endif
1842
1843 if (netif_msg_rx_err (tp))
1844 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1845 dev->name, rx_status);
1846 tp->stats.rx_errors++;
1847 if (!(rx_status & RxStatusOK)) {
1848 if (rx_status & RxTooLong) {
1849 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1850 dev->name, rx_status);
1851 /* A.C.: The chip hangs here. */
1852 }
1853 if (rx_status & (RxBadSymbol | RxBadAlign))
1854 tp->stats.rx_frame_errors++;
1855 if (rx_status & (RxRunt | RxTooLong))
1856 tp->stats.rx_length_errors++;
1857 if (rx_status & RxCRCErr)
1858 tp->stats.rx_crc_errors++;
1859 } else {
1860 tp->xstats.rx_lost_in_ring++;
1861 }
1862
1863 #ifndef CONFIG_8139_OLD_RX_RESET
1864 tmp8 = RTL_R8 (ChipCmd);
1865 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1866 RTL_W8 (ChipCmd, tmp8);
1867 RTL_W32 (RxConfig, tp->rx_config);
1868 tp->cur_rx = 0;
1869 #else
1870 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1871
1872 /* disable receive */
1873 RTL_W8_F (ChipCmd, CmdTxEnb);
1874 tmp_work = 200;
1875 while (--tmp_work > 0) {
1876 udelay(1);
1877 tmp8 = RTL_R8 (ChipCmd);
1878 if (!(tmp8 & CmdRxEnb))
1879 break;
1880 }
1881 if (tmp_work <= 0)
1882 printk (KERN_WARNING PFX "rx stop wait too long\n");
1883 /* restart receive */
1884 tmp_work = 200;
1885 while (--tmp_work > 0) {
1886 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1887 udelay(1);
1888 tmp8 = RTL_R8 (ChipCmd);
1889 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1890 break;
1891 }
1892 if (tmp_work <= 0)
1893 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1894
1895 /* and reinitialize all rx related registers */
1896 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1897 /* Must enable Tx/Rx before setting transfer thresholds! */
1898 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1899
1900 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1901 RTL_W32 (RxConfig, tp->rx_config);
1902 tp->cur_rx = 0;
1903
1904 DPRINTK("init buffer addresses\n");
1905
1906 /* Lock Config[01234] and BMCR register writes */
1907 RTL_W8 (Cfg9346, Cfg9346_Lock);
1908
1909 /* init Rx ring buffer DMA address */
1910 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1911
1912 /* A.C.: Reset the multicast list. */
1913 __set_rx_mode (dev);
1914 #endif
1915 }
1916
1917 #if RX_BUF_IDX == 3
1918 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1919 u32 offset, unsigned int size)
1920 {
1921 u32 left = RX_BUF_LEN - offset;
1922
1923 if (size > left) {
1924 memcpy(skb->data, ring + offset, left);
1925 memcpy(skb->data+left, ring, size - left);
1926 } else
1927 memcpy(skb->data, ring + offset, size);
1928 }
1929 #endif
1930
1931 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1932 {
1933 void __iomem *ioaddr = tp->mmio_addr;
1934 u16 status;
1935
1936 status = RTL_R16 (IntrStatus) & RxAckBits;
1937
1938 /* Clear out errors and receive interrupts */
1939 if (likely(status != 0)) {
1940 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1941 tp->stats.rx_errors++;
1942 if (status & RxFIFOOver)
1943 tp->stats.rx_fifo_errors++;
1944 }
1945 RTL_W16_F (IntrStatus, RxAckBits);
1946 }
1947 }
1948
1949 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1950 int budget)
1951 {
1952 void __iomem *ioaddr = tp->mmio_addr;
1953 int received = 0;
1954 unsigned char *rx_ring = tp->rx_ring;
1955 unsigned int cur_rx = tp->cur_rx;
1956 unsigned int rx_size = 0;
1957
1958 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1959 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1960 RTL_R16 (RxBufAddr),
1961 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1962
1963 while (netif_running(dev) && received < budget
1964 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1965 u32 ring_offset = cur_rx % RX_BUF_LEN;
1966 u32 rx_status;
1967 unsigned int pkt_size;
1968 struct sk_buff *skb;
1969
1970 rmb();
1971
1972 /* read size+status of next frame from DMA ring buffer */
1973 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1974 rx_size = rx_status >> 16;
1975 pkt_size = rx_size - 4;
1976
1977 if (netif_msg_rx_status(tp))
1978 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1979 " cur %4.4x.\n", dev->name, rx_status,
1980 rx_size, cur_rx);
1981 #if RTL8139_DEBUG > 2
1982 {
1983 int i;
1984 DPRINTK ("%s: Frame contents ", dev->name);
1985 for (i = 0; i < 70; i++)
1986 printk (" %2.2x",
1987 rx_ring[ring_offset + i]);
1988 printk (".\n");
1989 }
1990 #endif
1991
1992 #ifdef CONFIG_LEDMAN
1993 ledman_cmd(LEDMAN_CMD_SET, (dev->name[3] == '0') ?
1994 LEDMAN_LAN1_RX : LEDMAN_LAN2_RX);
1995 #endif
1996
1997 /* Packet copy from FIFO still in progress.
1998 * Theoretically, this should never happen
1999 * since EarlyRx is disabled.
2000 */
2001 if (unlikely(rx_size == 0xfff0)) {
2002 if (!tp->fifo_copy_timeout)
2003 tp->fifo_copy_timeout = jiffies + 2;
2004 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
2005 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
2006 rx_size = 0;
2007 goto no_early_rx;
2008 }
2009 if (netif_msg_intr(tp)) {
2010 printk(KERN_DEBUG "%s: fifo copy in progress.",
2011 dev->name);
2012 }
2013 tp->xstats.early_rx++;
2014 break;
2015 }
2016
2017 no_early_rx:
2018 tp->fifo_copy_timeout = 0;
2019
2020 /* If Rx err or invalid rx_size/rx_status received
2021 * (which happens if we get lost in the ring),
2022 * Rx process gets reset, so we abort any further
2023 * Rx processing.
2024 */
2025 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2026 (rx_size < 8) ||
2027 (!(rx_status & RxStatusOK)))) {
2028 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2029 received = -1;
2030 goto out;
2031 }
2032
2033 /* Malloc up new buffer, compatible with net-2e. */
2034 /* Omit the four octet CRC from the length. */
2035
2036 skb = dev_alloc_skb (pkt_size + 2);
2037 if (likely(skb)) {
2038 skb->dev = dev;
2039 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2040 #if RX_BUF_IDX == 3
2041 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2042 #else
2043 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2044 #endif
2045 skb_put (skb, pkt_size);
2046
2047 skb->protocol = eth_type_trans (skb, dev);
2048
2049 dev->last_rx = jiffies;
2050 tp->stats.rx_bytes += pkt_size;
2051 tp->stats.rx_packets++;
2052
2053 netif_receive_skb (skb);
2054 } else {
2055 if (net_ratelimit())
2056 printk (KERN_WARNING
2057 "%s: Memory squeeze, dropping packet.\n",
2058 dev->name);
2059 tp->stats.rx_dropped++;
2060 }
2061 received++;
2062
2063 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2064 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2065
2066 rtl8139_isr_ack(tp);
2067 }
2068
2069 if (unlikely(!received || rx_size == 0xfff0))
2070 rtl8139_isr_ack(tp);
2071
2072 #if RTL8139_DEBUG > 1
2073 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2074 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2075 RTL_R16 (RxBufAddr),
2076 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2077 #endif
2078
2079 tp->cur_rx = cur_rx;
2080
2081 /*
2082 * The receive buffer should be mostly empty.
2083 * Tell NAPI to reenable the Rx irq.
2084 */
2085 if (tp->fifo_copy_timeout)
2086 received = budget;
2087
2088 out:
2089 return received;
2090 }
2091
2092
2093 static void rtl8139_weird_interrupt (struct net_device *dev,
2094 struct rtl8139_private *tp,
2095 void __iomem *ioaddr,
2096 int status, int link_changed)
2097 {
2098 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2099 dev->name, status);
2100
2101 assert (dev != NULL);
2102 assert (tp != NULL);
2103 assert (ioaddr != NULL);
2104
2105 /* Update the error count. */
2106 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2107 RTL_W32 (RxMissed, 0);
2108
2109 if ((status & RxUnderrun) && link_changed &&
2110 (tp->drv_flags & HAS_LNK_CHNG)) {
2111 rtl_check_media(dev, 0);
2112 status &= ~RxUnderrun;
2113 }
2114
2115 if (status & (RxUnderrun | RxErr))
2116 tp->stats.rx_errors++;
2117
2118 if (status & PCSTimeout)
2119 tp->stats.rx_length_errors++;
2120 if (status & RxUnderrun)
2121 tp->stats.rx_fifo_errors++;
2122 if (status & PCIErr) {
2123 u16 pci_cmd_status;
2124 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2125 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2126
2127 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2128 dev->name, pci_cmd_status);
2129 }
2130 }
2131
2132 static int rtl8139_poll(struct net_device *dev, int *budget)
2133 {
2134 struct rtl8139_private *tp = netdev_priv(dev);
2135 void __iomem *ioaddr = tp->mmio_addr;
2136 int orig_budget = min(*budget, dev->quota);
2137 int done = 1;
2138
2139 spin_lock(&tp->rx_lock);
2140 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2141 int work_done;
2142
2143 work_done = rtl8139_rx(dev, tp, orig_budget);
2144 if (likely(work_done > 0)) {
2145 *budget -= work_done;
2146 dev->quota -= work_done;
2147 done = (work_done < orig_budget);
2148 }
2149 }
2150
2151 if (done) {
2152 /*
2153 * Order is important since data can get interrupted
2154 * again when we think we are done.
2155 */
2156 local_irq_disable();
2157 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2158 __netif_rx_complete(dev);
2159 local_irq_enable();
2160 }
2161 spin_unlock(&tp->rx_lock);
2162
2163 return !done;
2164 }
2165
2166 /* The interrupt handler does all of the Rx thread work and cleans up
2167 after the Tx thread. */
2168 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2169 {
2170 struct net_device *dev = (struct net_device *) dev_instance;
2171 struct rtl8139_private *tp = netdev_priv(dev);
2172 void __iomem *ioaddr = tp->mmio_addr;
2173 u16 status, ackstat;
2174 int link_changed = 0; /* avoid bogus "uninit" warning */
2175 int handled = 0;
2176
2177 spin_lock (&tp->lock);
2178 status = RTL_R16 (IntrStatus);
2179
2180 /* shared irq? */
2181 if (unlikely((status & rtl8139_intr_mask) == 0))
2182 goto out;
2183
2184 handled = 1;
2185
2186 /* h/w no longer present (hotplug?) or major error, bail */
2187 if (unlikely(status == 0xFFFF))
2188 goto out;
2189
2190 /* close possible race's with dev_close */
2191 if (unlikely(!netif_running(dev))) {
2192 RTL_W16 (IntrMask, 0);
2193 goto out;
2194 }
2195
2196 /* Acknowledge all of the current interrupt sources ASAP, but
2197 an first get an additional status bit from CSCR. */
2198 if (unlikely(status & RxUnderrun))
2199 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2200
2201 ackstat = status & ~(RxAckBits | TxErr);
2202 if (ackstat)
2203 RTL_W16 (IntrStatus, ackstat);
2204
2205 /* Receive packets are processed by poll routine.
2206 If not running start it now. */
2207 if (status & RxAckBits){
2208 if (netif_rx_schedule_prep(dev)) {
2209 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2210 __netif_rx_schedule (dev);
2211 }
2212 }
2213
2214 /* Check uncommon events with one test. */
2215 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2216 rtl8139_weird_interrupt (dev, tp, ioaddr,
2217 status, link_changed);
2218
2219 if (status & (TxOK | TxErr)) {
2220 rtl8139_tx_interrupt (dev, tp, ioaddr);
2221 if (status & TxErr)
2222 RTL_W16 (IntrStatus, TxErr);
2223 }
2224 out:
2225 spin_unlock (&tp->lock);
2226
2227 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2228 dev->name, RTL_R16 (IntrStatus));
2229 return IRQ_RETVAL(handled);
2230 }
2231
2232 #ifdef CONFIG_NET_POLL_CONTROLLER
2233 /*
2234 * Polling receive - used by netconsole and other diagnostic tools
2235 * to allow network i/o with interrupts disabled.
2236 */
2237 static void rtl8139_poll_controller(struct net_device *dev)
2238 {
2239 disable_irq(dev->irq);
2240 rtl8139_interrupt(dev->irq, dev);
2241 enable_irq(dev->irq);
2242 }
2243 #endif
2244
2245 static int rtl8139_close (struct net_device *dev)
2246 {
2247 struct rtl8139_private *tp = netdev_priv(dev);
2248 void __iomem *ioaddr = tp->mmio_addr;
2249 unsigned long flags;
2250
2251 netif_stop_queue (dev);
2252
2253 rtl8139_stop_thread(tp);
2254
2255 if (netif_msg_ifdown(tp))
2256 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2257 dev->name, RTL_R16 (IntrStatus));
2258
2259 spin_lock_irqsave (&tp->lock, flags);
2260
2261 /* Stop the chip's Tx and Rx DMA processes. */
2262 RTL_W8 (ChipCmd, 0);
2263
2264 /* Disable interrupts by clearing the interrupt mask. */
2265 RTL_W16 (IntrMask, 0);
2266
2267 /* Update the error counts. */
2268 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2269 RTL_W32 (RxMissed, 0);
2270
2271 spin_unlock_irqrestore (&tp->lock, flags);
2272
2273 synchronize_irq (dev->irq); /* racy, but that's ok here */
2274 free_irq (dev->irq, dev);
2275
2276 rtl8139_tx_clear (tp);
2277
2278 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2279 tp->rx_ring, tp->rx_ring_dma);
2280 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2281 tp->tx_bufs, tp->tx_bufs_dma);
2282 tp->rx_ring = NULL;
2283 tp->tx_bufs = NULL;
2284
2285 /* Green! Put the chip in low-power mode. */
2286 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2287
2288 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2289 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2290
2291 return 0;
2292 }
2293
2294
2295 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2296 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2297 other threads or interrupts aren't messing with the 8139. */
2298 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2299 {
2300 struct rtl8139_private *np = netdev_priv(dev);
2301 void __iomem *ioaddr = np->mmio_addr;
2302
2303 spin_lock_irq(&np->lock);
2304 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2305 u8 cfg3 = RTL_R8 (Config3);
2306 u8 cfg5 = RTL_R8 (Config5);
2307
2308 wol->supported = WAKE_PHY | WAKE_MAGIC
2309 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2310
2311 wol->wolopts = 0;
2312 if (cfg3 & Cfg3_LinkUp)
2313 wol->wolopts |= WAKE_PHY;
2314 if (cfg3 & Cfg3_Magic)
2315 wol->wolopts |= WAKE_MAGIC;
2316 /* (KON)FIXME: See how netdev_set_wol() handles the
2317 following constants. */
2318 if (cfg5 & Cfg5_UWF)
2319 wol->wolopts |= WAKE_UCAST;
2320 if (cfg5 & Cfg5_MWF)
2321 wol->wolopts |= WAKE_MCAST;
2322 if (cfg5 & Cfg5_BWF)
2323 wol->wolopts |= WAKE_BCAST;
2324 }
2325 spin_unlock_irq(&np->lock);
2326 }
2327
2328
2329 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2330 that wol points to kernel memory and other threads or interrupts
2331 aren't messing with the 8139. */
2332 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2333 {
2334 struct rtl8139_private *np = netdev_priv(dev);
2335 void __iomem *ioaddr = np->mmio_addr;
2336 u32 support;
2337 u8 cfg3, cfg5;
2338
2339 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2340 ? (WAKE_PHY | WAKE_MAGIC
2341 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2342 : 0);
2343 if (wol->wolopts & ~support)
2344 return -EINVAL;
2345
2346 spin_lock_irq(&np->lock);
2347 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2348 if (wol->wolopts & WAKE_PHY)
2349 cfg3 |= Cfg3_LinkUp;
2350 if (wol->wolopts & WAKE_MAGIC)
2351 cfg3 |= Cfg3_Magic;
2352 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2353 RTL_W8 (Config3, cfg3);
2354 RTL_W8 (Cfg9346, Cfg9346_Lock);
2355
2356 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2357 /* (KON)FIXME: These are untested. We may have to set the
2358 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2359 documentation. */
2360 if (wol->wolopts & WAKE_UCAST)
2361 cfg5 |= Cfg5_UWF;
2362 if (wol->wolopts & WAKE_MCAST)
2363 cfg5 |= Cfg5_MWF;
2364 if (wol->wolopts & WAKE_BCAST)
2365 cfg5 |= Cfg5_BWF;
2366 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2367 spin_unlock_irq(&np->lock);
2368
2369 return 0;
2370 }
2371
2372 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2373 {
2374 struct rtl8139_private *np = netdev_priv(dev);
2375 strcpy(info->driver, DRV_NAME);
2376 strcpy(info->version, DRV_VERSION);
2377 strcpy(info->bus_info, pci_name(np->pci_dev));
2378 info->regdump_len = np->regs_len;
2379 }
2380
2381 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2382 {
2383 struct rtl8139_private *np = netdev_priv(dev);
2384 spin_lock_irq(&np->lock);
2385 mii_ethtool_gset(&np->mii, cmd);
2386 spin_unlock_irq(&np->lock);
2387 return 0;
2388 }
2389
2390 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2391 {
2392 struct rtl8139_private *np = netdev_priv(dev);
2393 int rc;
2394 spin_lock_irq(&np->lock);
2395 rc = mii_ethtool_sset(&np->mii, cmd);
2396 spin_unlock_irq(&np->lock);
2397 return rc;
2398 }
2399
2400 static int rtl8139_nway_reset(struct net_device *dev)
2401 {
2402 struct rtl8139_private *np = netdev_priv(dev);
2403 return mii_nway_restart(&np->mii);
2404 }
2405
2406 static u32 rtl8139_get_link(struct net_device *dev)
2407 {
2408 struct rtl8139_private *np = netdev_priv(dev);
2409 return mii_link_ok(&np->mii);
2410 }
2411
2412 static u32 rtl8139_get_msglevel(struct net_device *dev)
2413 {
2414 struct rtl8139_private *np = netdev_priv(dev);
2415 return np->msg_enable;
2416 }
2417
2418 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2419 {
2420 struct rtl8139_private *np = netdev_priv(dev);
2421 np->msg_enable = datum;
2422 }
2423
2424 /* TODO: we are too slack to do reg dumping for pio, for now */
2425 #ifdef CONFIG_8139TOO_PIO
2426 #define rtl8139_get_regs_len NULL
2427 #define rtl8139_get_regs NULL
2428 #else
2429 static int rtl8139_get_regs_len(struct net_device *dev)
2430 {
2431 struct rtl8139_private *np = netdev_priv(dev);
2432 return np->regs_len;
2433 }
2434
2435 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2436 {
2437 struct rtl8139_private *np = netdev_priv(dev);
2438
2439 regs->version = RTL_REGS_VER;
2440
2441 spin_lock_irq(&np->lock);
2442 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2443 spin_unlock_irq(&np->lock);
2444 }
2445 #endif /* CONFIG_8139TOO_MMIO */
2446
2447 static int rtl8139_get_stats_count(struct net_device *dev)
2448 {
2449 return RTL_NUM_STATS;
2450 }
2451
2452 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2453 {
2454 struct rtl8139_private *np = netdev_priv(dev);
2455
2456 data[0] = np->xstats.early_rx;
2457 data[1] = np->xstats.tx_buf_mapped;
2458 data[2] = np->xstats.tx_timeouts;
2459 data[3] = np->xstats.rx_lost_in_ring;
2460 }
2461
2462 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2463 {
2464 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2465 }
2466
2467 static const struct ethtool_ops rtl8139_ethtool_ops = {
2468 .get_drvinfo = rtl8139_get_drvinfo,
2469 .get_settings = rtl8139_get_settings,
2470 .set_settings = rtl8139_set_settings,
2471 .get_regs_len = rtl8139_get_regs_len,
2472 .get_regs = rtl8139_get_regs,
2473 .nway_reset = rtl8139_nway_reset,
2474 .get_link = rtl8139_get_link,
2475 .get_msglevel = rtl8139_get_msglevel,
2476 .set_msglevel = rtl8139_set_msglevel,
2477 .get_wol = rtl8139_get_wol,
2478 .set_wol = rtl8139_set_wol,
2479 .get_strings = rtl8139_get_strings,
2480 .get_stats_count = rtl8139_get_stats_count,
2481 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2482 .get_perm_addr = ethtool_op_get_perm_addr,
2483 };
2484
2485 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2486 {
2487 struct rtl8139_private *np = netdev_priv(dev);
2488 int rc;
2489
2490 if (!netif_running(dev))
2491 return -EINVAL;
2492
2493 spin_lock_irq(&np->lock);
2494 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2495 spin_unlock_irq(&np->lock);
2496
2497 return rc;
2498 }
2499
2500
2501 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2502 {
2503 struct rtl8139_private *tp = netdev_priv(dev);
2504 void __iomem *ioaddr = tp->mmio_addr;
2505 unsigned long flags;
2506
2507 if (netif_running(dev)) {
2508 spin_lock_irqsave (&tp->lock, flags);
2509 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2510 RTL_W32 (RxMissed, 0);
2511 spin_unlock_irqrestore (&tp->lock, flags);
2512 }
2513
2514 return &tp->stats;
2515 }
2516
2517 /* Set or clear the multicast filter for this adaptor.
2518 This routine is not state sensitive and need not be SMP locked. */
2519
2520 static void __set_rx_mode (struct net_device *dev)
2521 {
2522 struct rtl8139_private *tp = netdev_priv(dev);
2523 void __iomem *ioaddr = tp->mmio_addr;
2524 u32 mc_filter[2]; /* Multicast hash filter */
2525 int i, rx_mode;
2526 u32 tmp;
2527
2528 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2529 dev->name, dev->flags, RTL_R32 (RxConfig));
2530
2531 /* Note: do not reorder, GCC is clever about common statements. */
2532 if (dev->flags & IFF_PROMISC) {
2533 rx_mode =
2534 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2535 AcceptAllPhys;
2536 mc_filter[1] = mc_filter[0] = 0xffffffff;
2537 } else if ((dev->mc_count > multicast_filter_limit)
2538 || (dev->flags & IFF_ALLMULTI)) {
2539 /* Too many to filter perfectly -- accept all multicasts. */
2540 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2541 mc_filter[1] = mc_filter[0] = 0xffffffff;
2542 } else {
2543 struct dev_mc_list *mclist;
2544 rx_mode = AcceptBroadcast | AcceptMyPhys;
2545 mc_filter[1] = mc_filter[0] = 0;
2546 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2547 i++, mclist = mclist->next) {
2548 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2549
2550 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2551 rx_mode |= AcceptMulticast;
2552 }
2553 }
2554
2555 /* We can safely update without stopping the chip. */
2556 tmp = rtl8139_rx_config | rx_mode;
2557 if (tp->rx_config != tmp) {
2558 RTL_W32_F (RxConfig, tmp);
2559 tp->rx_config = tmp;
2560 }
2561 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2562 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2563 }
2564
2565 static void rtl8139_set_rx_mode (struct net_device *dev)
2566 {
2567 unsigned long flags;
2568 struct rtl8139_private *tp = netdev_priv(dev);
2569
2570 spin_lock_irqsave (&tp->lock, flags);
2571 __set_rx_mode(dev);
2572 spin_unlock_irqrestore (&tp->lock, flags);
2573 }
2574
2575 #ifdef CONFIG_PM
2576
2577 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2578 {
2579 struct net_device *dev = pci_get_drvdata (pdev);
2580 struct rtl8139_private *tp = netdev_priv(dev);
2581 void __iomem *ioaddr = tp->mmio_addr;
2582 unsigned long flags;
2583
2584 pci_save_state (pdev);
2585
2586 if (!netif_running (dev))
2587 return 0;
2588
2589 netif_device_detach (dev);
2590
2591 spin_lock_irqsave (&tp->lock, flags);
2592
2593 /* Disable interrupts, stop Tx and Rx. */
2594 RTL_W16 (IntrMask, 0);
2595 RTL_W8 (ChipCmd, 0);
2596
2597 /* Update the error counts. */
2598 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2599 RTL_W32 (RxMissed, 0);
2600
2601 spin_unlock_irqrestore (&tp->lock, flags);
2602
2603 pci_set_power_state (pdev, PCI_D3hot);
2604
2605 return 0;
2606 }
2607
2608
2609 static int rtl8139_resume (struct pci_dev *pdev)
2610 {
2611 struct net_device *dev = pci_get_drvdata (pdev);
2612
2613 pci_restore_state (pdev);
2614 if (!netif_running (dev))
2615 return 0;
2616 pci_set_power_state (pdev, PCI_D0);
2617 rtl8139_init_ring (dev);
2618 rtl8139_hw_start (dev);
2619 netif_device_attach (dev);
2620 return 0;
2621 }
2622
2623 #endif /* CONFIG_PM */
2624
2625
2626 static struct pci_driver rtl8139_pci_driver = {
2627 .name = DRV_NAME,
2628 .id_table = rtl8139_pci_tbl,
2629 .probe = rtl8139_init_one,
2630 .remove = __devexit_p(rtl8139_remove_one),
2631 #ifdef CONFIG_PM
2632 .suspend = rtl8139_suspend,
2633 .resume = rtl8139_resume,
2634 #endif /* CONFIG_PM */
2635 };
2636
2637
2638 static int __init rtl8139_init_module (void)
2639 {
2640 /* when we're a module, we always print a version message,
2641 * even if no 8139 board is found.
2642 */
2643 #ifdef MODULE
2644 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2645 #endif
2646
2647 return pci_register_driver(&rtl8139_pci_driver);
2648 }
2649
2650
2651 static void __exit rtl8139_cleanup_module (void)
2652 {
2653 pci_unregister_driver (&rtl8139_pci_driver);
2654 }
2655
2656
2657 module_init(rtl8139_init_module);
2658 module_exit(rtl8139_cleanup_module);
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz