?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / mmc / omap.c
blob762fa28958918fbd21770a574f035a725bb14bd5
1 /*
2 * linux/drivers/media/mmc/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/protocol.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28
29 #include <asm/io.h>
30 #include <asm/irq.h>
31 #include <asm/scatterlist.h>
32 #include <asm/mach-types.h>
33
34 #include <asm/arch/board.h>
35 #include <asm/arch/gpio.h>
36 #include <asm/arch/dma.h>
37 #include <asm/arch/mux.h>
38 #include <asm/arch/fpga.h>
39 #include <asm/arch/tps65010.h>
40
41 #include "omap.h"
42
43 #define DRIVER_NAME "mmci-omap"
44 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
45
46 /* Specifies how often in millisecs to poll for card status changes
47 * when the cover switch is open */
48 #define OMAP_MMC_SWITCH_POLL_DELAY 500
49
50 static int mmc_omap_enable_poll = 1;
51
52 struct mmc_omap_host {
53 int initialized;
54 int suspended;
55 struct mmc_request * mrq;
56 struct mmc_command * cmd;
57 struct mmc_data * data;
58 struct mmc_host * mmc;
59 struct device * dev;
60 unsigned char id; /* 16xx chips have 2 MMC blocks */
61 struct clk * iclk;
62 struct clk * fclk;
63 struct resource *res;
64 void __iomem *base;
65 int irq;
66 unsigned char bus_mode;
67 unsigned char hw_bus_mode;
68
69 unsigned int sg_len;
70 int sg_idx;
71 u16 * buffer;
72 u32 buffer_bytes_left;
73 u32 total_bytes_left;
74
75 unsigned use_dma:1;
76 unsigned brs_received:1, dma_done:1;
77 unsigned dma_is_read:1;
78 unsigned dma_in_use:1;
79 int dma_ch;
80 spinlock_t dma_lock;
81 struct timer_list dma_timer;
82 unsigned dma_len;
83
84 short power_pin;
85 short wp_pin;
86
87 int switch_pin;
88 struct work_struct switch_work;
89 struct timer_list switch_timer;
90 int switch_last_state;
91 };
92
93 static inline int
94 mmc_omap_cover_is_open(struct mmc_omap_host *host)
95 {
96 if (host->switch_pin < 0)
97 return 0;
98 return omap_get_gpio_datain(host->switch_pin);
99 }
100
101 static ssize_t
102 mmc_omap_show_cover_switch(struct device *dev,
103 struct device_attribute *attr, char *buf)
104 {
105 struct mmc_omap_host *host = dev_get_drvdata(dev);
106
107 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
108 "closed");
109 }
110
111 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
112
113 static ssize_t
114 mmc_omap_show_enable_poll(struct device *dev,
115 struct device_attribute *attr, char *buf)
116 {
117 return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
118 }
119
120 static ssize_t
121 mmc_omap_store_enable_poll(struct device *dev,
122 struct device_attribute *attr, const char *buf,
123 size_t size)
124 {
125 int enable_poll;
126
127 if (sscanf(buf, "%10d", &enable_poll) != 1)
128 return -EINVAL;
129
130 if (enable_poll != mmc_omap_enable_poll) {
131 struct mmc_omap_host *host = dev_get_drvdata(dev);
132
133 mmc_omap_enable_poll = enable_poll;
134 if (enable_poll && host->switch_pin >= 0)
135 schedule_work(&host->switch_work);
136 }
137 return size;
138 }
139
140 static DEVICE_ATTR(enable_poll, 0664,
141 mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
142
143 static void
144 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
145 {
146 u32 cmdreg;
147 u32 resptype;
148 u32 cmdtype;
149
150 host->cmd = cmd;
151
152 resptype = 0;
153 cmdtype = 0;
154
155 /* Our hardware needs to know exact type */
156 switch (RSP_TYPE(mmc_resp_type(cmd))) {
157 case RSP_TYPE(MMC_RSP_R1):
158 /* resp 1, resp 1b */
159 resptype = 1;
160 break;
161 case RSP_TYPE(MMC_RSP_R2):
162 resptype = 2;
163 break;
164 case RSP_TYPE(MMC_RSP_R3):
165 resptype = 3;
166 break;
167 default:
168 break;
169 }
170
171 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
172 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
173 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
174 cmdtype = OMAP_MMC_CMDTYPE_BC;
175 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
176 cmdtype = OMAP_MMC_CMDTYPE_BCR;
177 } else {
178 cmdtype = OMAP_MMC_CMDTYPE_AC;
179 }
180
181 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
182
183 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
184 cmdreg |= 1 << 6;
185
186 if (cmd->flags & MMC_RSP_BUSY)
187 cmdreg |= 1 << 11;
188
189 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
190 cmdreg |= 1 << 15;
191
192 clk_enable(host->fclk);
193
194 OMAP_MMC_WRITE(host->base, CTO, 200);
195 OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff);
196 OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16);
197 OMAP_MMC_WRITE(host->base, IE,
198 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
199 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
200 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
201 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
202 OMAP_MMC_STAT_END_OF_DATA);
203 OMAP_MMC_WRITE(host->base, CMD, cmdreg);
204 }
205
206 static void
207 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
208 {
209 if (host->dma_in_use) {
210 enum dma_data_direction dma_data_dir;
211
212 BUG_ON(host->dma_ch < 0);
213 if (data->error != MMC_ERR_NONE)
214 omap_stop_dma(host->dma_ch);
215 /* Release DMA channel lazily */
216 mod_timer(&host->dma_timer, jiffies + HZ);
217 if (data->flags & MMC_DATA_WRITE)
218 dma_data_dir = DMA_TO_DEVICE;
219 else
220 dma_data_dir = DMA_FROM_DEVICE;
221 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
222 dma_data_dir);
223 }
224 host->data = NULL;
225 host->sg_len = 0;
226 clk_disable(host->fclk);
227
228 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
229 * dozens of requests until the card finishes writing data.
230 * It'd be cheaper to just wait till an EOFB interrupt arrives...
231 */
232
233 if (!data->stop) {
234 host->mrq = NULL;
235 mmc_request_done(host->mmc, data->mrq);
236 return;
237 }
238
239 mmc_omap_start_command(host, data->stop);
240 }
241
242 static void
243 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
244 {
245 unsigned long flags;
246 int done;
247
248 if (!host->dma_in_use) {
249 mmc_omap_xfer_done(host, data);
250 return;
251 }
252 done = 0;
253 spin_lock_irqsave(&host->dma_lock, flags);
254 if (host->dma_done)
255 done = 1;
256 else
257 host->brs_received = 1;
258 spin_unlock_irqrestore(&host->dma_lock, flags);
259 if (done)
260 mmc_omap_xfer_done(host, data);
261 }
262
263 static void
264 mmc_omap_dma_timer(unsigned long data)
265 {
266 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
267
268 BUG_ON(host->dma_ch < 0);
269 omap_free_dma(host->dma_ch);
270 host->dma_ch = -1;
271 }
272
273 static void
274 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
275 {
276 unsigned long flags;
277 int done;
278
279 done = 0;
280 spin_lock_irqsave(&host->dma_lock, flags);
281 if (host->brs_received)
282 done = 1;
283 else
284 host->dma_done = 1;
285 spin_unlock_irqrestore(&host->dma_lock, flags);
286 if (done)
287 mmc_omap_xfer_done(host, data);
288 }
289
290 static void
291 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
292 {
293 host->cmd = NULL;
294
295 if (cmd->flags & MMC_RSP_PRESENT) {
296 if (cmd->flags & MMC_RSP_136) {
297 /* response type 2 */
298 cmd->resp[3] =
299 OMAP_MMC_READ(host->base, RSP0) |
300 (OMAP_MMC_READ(host->base, RSP1) << 16);
301 cmd->resp[2] =
302 OMAP_MMC_READ(host->base, RSP2) |
303 (OMAP_MMC_READ(host->base, RSP3) << 16);
304 cmd->resp[1] =
305 OMAP_MMC_READ(host->base, RSP4) |
306 (OMAP_MMC_READ(host->base, RSP5) << 16);
307 cmd->resp[0] =
308 OMAP_MMC_READ(host->base, RSP6) |
309 (OMAP_MMC_READ(host->base, RSP7) << 16);
310 } else {
311 /* response types 1, 1b, 3, 4, 5, 6 */
312 cmd->resp[0] =
313 OMAP_MMC_READ(host->base, RSP6) |
314 (OMAP_MMC_READ(host->base, RSP7) << 16);
315 }
316 }
317
318 if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
319 host->mrq = NULL;
320 clk_disable(host->fclk);
321 mmc_request_done(host->mmc, cmd->mrq);
322 }
323 }
324
325 /* PIO only */
326 static void
327 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
328 {
329 struct scatterlist *sg;
330
331 sg = host->data->sg + host->sg_idx;
332 host->buffer_bytes_left = sg->length;
333 host->buffer = page_address(sg->page) + sg->offset;
334 if (host->buffer_bytes_left > host->total_bytes_left)
335 host->buffer_bytes_left = host->total_bytes_left;
336 }
337
338 /* PIO only */
339 static void
340 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
341 {
342 int n;
343
344 if (host->buffer_bytes_left == 0) {
345 host->sg_idx++;
346 BUG_ON(host->sg_idx == host->sg_len);
347 mmc_omap_sg_to_buf(host);
348 }
349 n = 64;
350 if (n > host->buffer_bytes_left)
351 n = host->buffer_bytes_left;
352 host->buffer_bytes_left -= n;
353 host->total_bytes_left -= n;
354 host->data->bytes_xfered += n;
355
356 if (write) {
357 __raw_writesw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
358 } else {
359 __raw_readsw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
360 }
361 }
362
363 static inline void mmc_omap_report_irq(u16 status)
364 {
365 static const char *mmc_omap_status_bits[] = {
366 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
367 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
368 };
369 int i, c = 0;
370
371 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
372 if (status & (1 << i)) {
373 if (c)
374 printk(" ");
375 printk("%s", mmc_omap_status_bits[i]);
376 c++;
377 }
378 }
379
380 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
381 {
382 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
383 u16 status;
384 int end_command;
385 int end_transfer;
386 int transfer_error;
387
388 if (host->cmd == NULL && host->data == NULL) {
389 status = OMAP_MMC_READ(host->base, STAT);
390 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
391 if (status != 0) {
392 OMAP_MMC_WRITE(host->base, STAT, status);
393 OMAP_MMC_WRITE(host->base, IE, 0);
394 }
395 return IRQ_HANDLED;
396 }
397
398 end_command = 0;
399 end_transfer = 0;
400 transfer_error = 0;
401
402 while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) {
403 OMAP_MMC_WRITE(host->base, STAT, status);
404 #ifdef CONFIG_MMC_DEBUG
405 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
406 status, host->cmd != NULL ? host->cmd->opcode : -1);
407 mmc_omap_report_irq(status);
408 printk("\n");
409 #endif
410 if (host->total_bytes_left) {
411 if ((status & OMAP_MMC_STAT_A_FULL) ||
412 (status & OMAP_MMC_STAT_END_OF_DATA))
413 mmc_omap_xfer_data(host, 0);
414 if (status & OMAP_MMC_STAT_A_EMPTY)
415 mmc_omap_xfer_data(host, 1);
416 }
417
418 if (status & OMAP_MMC_STAT_END_OF_DATA) {
419 end_transfer = 1;
420 }
421
422 if (status & OMAP_MMC_STAT_DATA_TOUT) {
423 dev_dbg(mmc_dev(host->mmc), "data timeout\n");
424 if (host->data) {
425 host->data->error |= MMC_ERR_TIMEOUT;
426 transfer_error = 1;
427 }
428 }
429
430 if (status & OMAP_MMC_STAT_DATA_CRC) {
431 if (host->data) {
432 host->data->error |= MMC_ERR_BADCRC;
433 dev_dbg(mmc_dev(host->mmc),
434 "data CRC error, bytes left %d\n",
435 host->total_bytes_left);
436 transfer_error = 1;
437 } else {
438 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
439 }
440 }
441
442 if (status & OMAP_MMC_STAT_CMD_TOUT) {
443 /* Timeouts are routine with some commands */
444 if (host->cmd) {
445 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
446 host->cmd->opcode !=
447 MMC_SEND_OP_COND &&
448 host->cmd->opcode !=
449 MMC_APP_CMD &&
450 !mmc_omap_cover_is_open(host))
451 dev_err(mmc_dev(host->mmc),
452 "command timeout, CMD %d\n",
453 host->cmd->opcode);
454 host->cmd->error = MMC_ERR_TIMEOUT;
455 end_command = 1;
456 }
457 }
458
459 if (status & OMAP_MMC_STAT_CMD_CRC) {
460 if (host->cmd) {
461 dev_err(mmc_dev(host->mmc),
462 "command CRC error (CMD%d, arg 0x%08x)\n",
463 host->cmd->opcode, host->cmd->arg);
464 host->cmd->error = MMC_ERR_BADCRC;
465 end_command = 1;
466 } else
467 dev_err(mmc_dev(host->mmc),
468 "command CRC error without cmd?\n");
469 }
470
471 if (status & OMAP_MMC_STAT_CARD_ERR) {
472 if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
473 u32 response = OMAP_MMC_READ(host->base, RSP6)
474 | (OMAP_MMC_READ(host->base, RSP7) << 16);
475 /* STOP sometimes sets must-ignore bits */
476 if (!(response & (R1_CC_ERROR
477 | R1_ILLEGAL_COMMAND
478 | R1_COM_CRC_ERROR))) {
479 end_command = 1;
480 continue;
481 }
482 }
483
484 dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
485 host->cmd->opcode);
486 if (host->cmd) {
487 host->cmd->error = MMC_ERR_FAILED;
488 end_command = 1;
489 }
490 if (host->data) {
491 host->data->error = MMC_ERR_FAILED;
492 transfer_error = 1;
493 }
494 }
495
496 /*
497 * NOTE: On 1610 the END_OF_CMD may come too early when
498 * starting a write
499 */
500 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
501 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
502 end_command = 1;
503 }
504 }
505
506 if (end_command) {
507 mmc_omap_cmd_done(host, host->cmd);
508 }
509 if (transfer_error)
510 mmc_omap_xfer_done(host, host->data);
511 else if (end_transfer)
512 mmc_omap_end_of_data(host, host->data);
513
514 return IRQ_HANDLED;
515 }
516
517 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
518 {
519 struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
520
521 schedule_work(&host->switch_work);
522
523 return IRQ_HANDLED;
524 }
525
526 static void mmc_omap_switch_timer(unsigned long arg)
527 {
528 struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
529
530 schedule_work(&host->switch_work);
531 }
532
533 /* FIXME: Handle card insertion and removal properly. Maybe use a mask
534 * for MMC state? */
535 static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
536 {
537 }
538
539 static void mmc_omap_switch_handler(void *data)
540 {
541 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
542 struct mmc_card *card;
543 static int complained = 0;
544 int cards = 0, cover_open;
545
546 if (host->switch_pin == -1)
547 return;
548 cover_open = mmc_omap_cover_is_open(host);
549 if (cover_open != host->switch_last_state) {
550 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
551 host->switch_last_state = cover_open;
552 }
553 mmc_detect_change(host->mmc, 0);
554 list_for_each_entry(card, &host->mmc->cards, node) {
555 if (mmc_card_present(card))
556 cards++;
557 }
558 if (mmc_omap_cover_is_open(host)) {
559 if (!complained) {
560 dev_info(mmc_dev(host->mmc), "cover is open");
561 complained = 1;
562 }
563 if (mmc_omap_enable_poll)
564 mod_timer(&host->switch_timer, jiffies +
565 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
566 } else {
567 complained = 0;
568 }
569 }
570
571 /* Prepare to transfer the next segment of a scatterlist */
572 static void
573 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
574 {
575 int dma_ch = host->dma_ch;
576 unsigned long data_addr;
577 u16 buf, frame;
578 u32 count;
579 struct scatterlist *sg = &data->sg[host->sg_idx];
580 int src_port = 0;
581 int dst_port = 0;
582 int sync_dev = 0;
583
584 data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA;
585 frame = data->blksz;
586 count = sg_dma_len(sg);
587
588 if ((data->blocks == 1) && (count > data->blksz))
589 count = frame;
590
591 host->dma_len = count;
592
593 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
594 * Use 16 or 32 word frames when the blocksize is at least that large.
595 * Blocksize is usually 512 bytes; but not for some SD reads.
596 */
597 if (cpu_is_omap15xx() && frame > 32)
598 frame = 32;
599 else if (frame > 64)
600 frame = 64;
601 count /= frame;
602 frame >>= 1;
603
604 if (!(data->flags & MMC_DATA_WRITE)) {
605 buf = 0x800f | ((frame - 1) << 8);
606
607 if (cpu_class_is_omap1()) {
608 src_port = OMAP_DMA_PORT_TIPB;
609 dst_port = OMAP_DMA_PORT_EMIFF;
610 }
611 if (cpu_is_omap24xx())
612 sync_dev = OMAP24XX_DMA_MMC1_RX;
613
614 omap_set_dma_src_params(dma_ch, src_port,
615 OMAP_DMA_AMODE_CONSTANT,
616 data_addr, 0, 0);
617 omap_set_dma_dest_params(dma_ch, dst_port,
618 OMAP_DMA_AMODE_POST_INC,
619 sg_dma_address(sg), 0, 0);
620 omap_set_dma_dest_data_pack(dma_ch, 1);
621 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
622 } else {
623 buf = 0x0f80 | ((frame - 1) << 0);
624
625 if (cpu_class_is_omap1()) {
626 src_port = OMAP_DMA_PORT_EMIFF;
627 dst_port = OMAP_DMA_PORT_TIPB;
628 }
629 if (cpu_is_omap24xx())
630 sync_dev = OMAP24XX_DMA_MMC1_TX;
631
632 omap_set_dma_dest_params(dma_ch, dst_port,
633 OMAP_DMA_AMODE_CONSTANT,
634 data_addr, 0, 0);
635 omap_set_dma_src_params(dma_ch, src_port,
636 OMAP_DMA_AMODE_POST_INC,
637 sg_dma_address(sg), 0, 0);
638 omap_set_dma_src_data_pack(dma_ch, 1);
639 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
640 }
641
642 /* Max limit for DMA frame count is 0xffff */
643 if (unlikely(count > 0xffff))
644 BUG();
645
646 OMAP_MMC_WRITE(host->base, BUF, buf);
647 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
648 frame, count, OMAP_DMA_SYNC_FRAME,
649 sync_dev, 0);
650 }
651
652 /* A scatterlist segment completed */
653 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
654 {
655 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
656 struct mmc_data *mmcdat = host->data;
657
658 if (unlikely(host->dma_ch < 0)) {
659 dev_err(mmc_dev(host->mmc),
660 "DMA callback while DMA not enabled\n");
661 return;
662 }
663 /* FIXME: We really should do something to _handle_ the errors */
664 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
665 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
666 return;
667 }
668 if (ch_status & OMAP_DMA_DROP_IRQ) {
669 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
670 return;
671 }
672 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
673 return;
674 }
675 mmcdat->bytes_xfered += host->dma_len;
676 host->sg_idx++;
677 if (host->sg_idx < host->sg_len) {
678 mmc_omap_prepare_dma(host, host->data);
679 omap_start_dma(host->dma_ch);
680 } else
681 mmc_omap_dma_done(host, host->data);
682 }
683
684 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
685 {
686 const char *dev_name;
687 int sync_dev, dma_ch, is_read, r;
688
689 is_read = !(data->flags & MMC_DATA_WRITE);
690 del_timer_sync(&host->dma_timer);
691 if (host->dma_ch >= 0) {
692 if (is_read == host->dma_is_read)
693 return 0;
694 omap_free_dma(host->dma_ch);
695 host->dma_ch = -1;
696 }
697
698 if (is_read) {
699 if (host->id == 1) {
700 sync_dev = OMAP_DMA_MMC_RX;
701 dev_name = "MMC1 read";
702 } else {
703 sync_dev = OMAP_DMA_MMC2_RX;
704 dev_name = "MMC2 read";
705 }
706 } else {
707 if (host->id == 1) {
708 sync_dev = OMAP_DMA_MMC_TX;
709 dev_name = "MMC1 write";
710 } else {
711 sync_dev = OMAP_DMA_MMC2_TX;
712 dev_name = "MMC2 write";
713 }
714 }
715 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
716 host, &dma_ch);
717 if (r != 0) {
718 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
719 return r;
720 }
721 host->dma_ch = dma_ch;
722 host->dma_is_read = is_read;
723
724 return 0;
725 }
726
727 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
728 {
729 u16 reg;
730
731 reg = OMAP_MMC_READ(host->base, SDIO);
732 reg &= ~(1 << 5);
733 OMAP_MMC_WRITE(host->base, SDIO, reg);
734 /* Set maximum timeout */
735 OMAP_MMC_WRITE(host->base, CTO, 0xff);
736 }
737
738 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
739 {
740 int timeout;
741 u16 reg;
742
743 /* Convert ns to clock cycles by assuming 20MHz frequency
744 * 1 cycle at 20MHz = 500 ns
745 */
746 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
747
748 /* Check if we need to use timeout multiplier register */
749 reg = OMAP_MMC_READ(host->base, SDIO);
750 if (timeout > 0xffff) {
751 reg |= (1 << 5);
752 timeout /= 1024;
753 } else
754 reg &= ~(1 << 5);
755 OMAP_MMC_WRITE(host->base, SDIO, reg);
756 OMAP_MMC_WRITE(host->base, DTO, timeout);
757 }
758
759 static void
760 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
761 {
762 struct mmc_data *data = req->data;
763 int i, use_dma, block_size;
764 unsigned sg_len;
765
766 host->data = data;
767 if (data == NULL) {
768 OMAP_MMC_WRITE(host->base, BLEN, 0);
769 OMAP_MMC_WRITE(host->base, NBLK, 0);
770 OMAP_MMC_WRITE(host->base, BUF, 0);
771 host->dma_in_use = 0;
772 set_cmd_timeout(host, req);
773 return;
774 }
775
776
777 block_size = data->blksz;
778
779 OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1);
780 OMAP_MMC_WRITE(host->base, BLEN, block_size - 1);
781 set_data_timeout(host, req);
782
783 /* cope with calling layer confusion; it issues "single
784 * block" writes using multi-block scatterlists.
785 */
786 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
787
788 /* Only do DMA for entire blocks */
789 use_dma = host->use_dma;
790 if (use_dma) {
791 for (i = 0; i < sg_len; i++) {
792 if ((data->sg[i].length % block_size) != 0) {
793 use_dma = 0;
794 break;
795 }
796 }
797 }
798
799 host->sg_idx = 0;
800 if (use_dma) {
801 if (mmc_omap_get_dma_channel(host, data) == 0) {
802 enum dma_data_direction dma_data_dir;
803
804 if (data->flags & MMC_DATA_WRITE)
805 dma_data_dir = DMA_TO_DEVICE;
806 else
807 dma_data_dir = DMA_FROM_DEVICE;
808
809 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
810 sg_len, dma_data_dir);
811 host->total_bytes_left = 0;
812 mmc_omap_prepare_dma(host, req->data);
813 host->brs_received = 0;
814 host->dma_done = 0;
815 host->dma_in_use = 1;
816 } else
817 use_dma = 0;
818 }
819
820 /* Revert to PIO? */
821 if (!use_dma) {
822 OMAP_MMC_WRITE(host->base, BUF, 0x1f1f);
823 host->total_bytes_left = data->blocks * block_size;
824 host->sg_len = sg_len;
825 mmc_omap_sg_to_buf(host);
826 host->dma_in_use = 0;
827 }
828 }
829
830 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
831 {
832 struct mmc_omap_host *host = mmc_priv(mmc);
833
834 WARN_ON(host->mrq != NULL);
835
836 host->mrq = req;
837
838 /* only touch fifo AFTER the controller readies it */
839 mmc_omap_prepare_data(host, req);
840 mmc_omap_start_command(host, req->cmd);
841 if (host->dma_in_use)
842 omap_start_dma(host->dma_ch);
843 }
844
845 static void innovator_fpga_socket_power(int on)
846 {
847 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
848
849 if (on) {
850 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
851 OMAP1510_FPGA_POWER);
852 } else {
853 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
854 OMAP1510_FPGA_POWER);
855 }
856 #endif
857 }
858
859 /*
860 * Turn the socket power on/off. Innovator uses FPGA, most boards
861 * probably use GPIO.
862 */
863 static void mmc_omap_power(struct mmc_omap_host *host, int on)
864 {
865 if (on) {
866 if (machine_is_omap_innovator())
867 innovator_fpga_socket_power(1);
868 else if (machine_is_omap_h2())
869 tps65010_set_gpio_out_value(GPIO3, HIGH);
870 else if (machine_is_omap_h3())
871 /* GPIO 4 of TPS65010 sends SD_EN signal */
872 tps65010_set_gpio_out_value(GPIO4, HIGH);
873 else if (cpu_is_omap24xx()) {
874 u16 reg = OMAP_MMC_READ(host->base, CON);
875 OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11));
876 } else
877 if (host->power_pin >= 0)
878 omap_set_gpio_dataout(host->power_pin, 1);
879 } else {
880 if (machine_is_omap_innovator())
881 innovator_fpga_socket_power(0);
882 else if (machine_is_omap_h2())
883 tps65010_set_gpio_out_value(GPIO3, LOW);
884 else if (machine_is_omap_h3())
885 tps65010_set_gpio_out_value(GPIO4, LOW);
886 else if (cpu_is_omap24xx()) {
887 u16 reg = OMAP_MMC_READ(host->base, CON);
888 OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11));
889 } else
890 if (host->power_pin >= 0)
891 omap_set_gpio_dataout(host->power_pin, 0);
892 }
893 }
894
895 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
896 {
897 struct mmc_omap_host *host = mmc_priv(mmc);
898 int dsor;
899 int realclock, i;
900
901 realclock = ios->clock;
902
903 if (ios->clock == 0)
904 dsor = 0;
905 else {
906 int func_clk_rate = clk_get_rate(host->fclk);
907
908 dsor = func_clk_rate / realclock;
909 if (dsor < 1)
910 dsor = 1;
911
912 if (func_clk_rate / dsor > realclock)
913 dsor++;
914
915 if (dsor > 250)
916 dsor = 250;
917 dsor++;
918
919 if (ios->bus_width == MMC_BUS_WIDTH_4)
920 dsor |= 1 << 15;
921 }
922
923 switch (ios->power_mode) {
924 case MMC_POWER_OFF:
925 mmc_omap_power(host, 0);
926 break;
927 case MMC_POWER_UP:
928 case MMC_POWER_ON:
929 mmc_omap_power(host, 1);
930 dsor |= 1<<11;
931 break;
932 }
933
934 host->bus_mode = ios->bus_mode;
935 host->hw_bus_mode = host->bus_mode;
936
937 clk_enable(host->fclk);
938
939 /* On insanely high arm_per frequencies something sometimes
940 * goes somehow out of sync, and the POW bit is not being set,
941 * which results in the while loop below getting stuck.
942 * Writing to the CON register twice seems to do the trick. */
943 for (i = 0; i < 2; i++)
944 OMAP_MMC_WRITE(host->base, CON, dsor);
945 if (ios->power_mode == MMC_POWER_UP) {
946 /* Send clock cycles, poll completion */
947 OMAP_MMC_WRITE(host->base, IE, 0);
948 OMAP_MMC_WRITE(host->base, STAT, 0xffff);
949 OMAP_MMC_WRITE(host->base, CMD, 1<<7);
950 while (0 == (OMAP_MMC_READ(host->base, STAT) & 1));
951 OMAP_MMC_WRITE(host->base, STAT, 1);
952 }
953 clk_disable(host->fclk);
954 }
955
956 static int mmc_omap_get_ro(struct mmc_host *mmc)
957 {
958 struct mmc_omap_host *host = mmc_priv(mmc);
959
960 return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
961 }
962
963 static struct mmc_host_ops mmc_omap_ops = {
964 .request = mmc_omap_request,
965 .set_ios = mmc_omap_set_ios,
966 .get_ro = mmc_omap_get_ro,
967 };
968
969 static int __init mmc_omap_probe(struct platform_device *pdev)
970 {
971 struct omap_mmc_conf *minfo = pdev->dev.platform_data;
972 struct mmc_host *mmc;
973 struct mmc_omap_host *host = NULL;
974 struct resource *r;
975 int ret = 0;
976 int irq;
977
978 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
979 irq = platform_get_irq(pdev, 0);
980 if (!r || irq < 0)
981 return -ENXIO;
982
983 r = request_mem_region(pdev->resource[0].start,
984 pdev->resource[0].end - pdev->resource[0].start + 1,
985 pdev->name);
986 if (!r)
987 return -EBUSY;
988
989 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
990 if (!mmc) {
991 ret = -ENOMEM;
992 goto out;
993 }
994
995 host = mmc_priv(mmc);
996 host->mmc = mmc;
997
998 spin_lock_init(&host->dma_lock);
999 init_timer(&host->dma_timer);
1000 host->dma_timer.function = mmc_omap_dma_timer;
1001 host->dma_timer.data = (unsigned long) host;
1002
1003 host->id = pdev->id;
1004 host->res = r;
1005 host->irq = irq;
1006
1007 if (cpu_is_omap24xx()) {
1008 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1009 if (IS_ERR(host->iclk))
1010 goto out;
1011 clk_enable(host->iclk);
1012 }
1013
1014 if (!cpu_is_omap24xx())
1015 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1016 else
1017 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1018
1019 if (IS_ERR(host->fclk)) {
1020 ret = PTR_ERR(host->fclk);
1021 goto out;
1022 }
1023
1024 /* REVISIT:
1025 * Also, use minfo->cover to decide how to manage
1026 * the card detect sensing.
1027 */
1028 host->power_pin = minfo->power_pin;
1029 host->switch_pin = minfo->switch_pin;
1030 host->wp_pin = minfo->wp_pin;
1031 host->use_dma = 1;
1032 host->dma_ch = -1;
1033
1034 host->irq = pdev->resource[1].start;
1035 host->base = (void __iomem*)IO_ADDRESS(r->start);
1036
1037 mmc->ops = &mmc_omap_ops;
1038 mmc->f_min = 400000;
1039 mmc->f_max = 24000000;
1040 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1041 mmc->caps = MMC_CAP_BYTEBLOCK;
1042
1043 if (minfo->wire4)
1044 mmc->caps |= MMC_CAP_4_BIT_DATA;
1045
1046 /* Use scatterlist DMA to reduce per-transfer costs.
1047 * NOTE max_seg_size assumption that small blocks aren't
1048 * normally used (except e.g. for reading SD registers).
1049 */
1050 mmc->max_phys_segs = 32;
1051 mmc->max_hw_segs = 32;
1052 mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
1053 mmc->max_seg_size = mmc->max_sectors * 512;
1054
1055 if (host->power_pin >= 0) {
1056 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1057 dev_err(mmc_dev(host->mmc),
1058 "Unable to get GPIO pin for MMC power\n");
1059 goto out;
1060 }
1061 omap_set_gpio_direction(host->power_pin, 0);
1062 }
1063
1064 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1065 if (ret)
1066 goto out;
1067
1068 host->dev = &pdev->dev;
1069 platform_set_drvdata(pdev, host);
1070
1071 mmc_add_host(mmc);
1072
1073 if (host->switch_pin >= 0) {
1074 INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
1075 init_timer(&host->switch_timer);
1076 host->switch_timer.function = mmc_omap_switch_timer;
1077 host->switch_timer.data = (unsigned long) host;
1078 if (omap_request_gpio(host->switch_pin) != 0) {
1079 dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1080 host->switch_pin = -1;
1081 goto no_switch;
1082 }
1083
1084 omap_set_gpio_direction(host->switch_pin, 1);
1085 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1086 mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1087 if (ret) {
1088 dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1089 omap_free_gpio(host->switch_pin);
1090 host->switch_pin = -1;
1091 goto no_switch;
1092 }
1093 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1094 if (ret == 0) {
1095 ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1096 if (ret != 0)
1097 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1098 }
1099 if (ret) {
1100 dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1101 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1102 omap_free_gpio(host->switch_pin);
1103 host->switch_pin = -1;
1104 goto no_switch;
1105 }
1106 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1107 schedule_work(&host->switch_work);
1108 }
1109
1110 no_switch:
1111 return 0;
1112
1113 out:
1114 /* FIXME: Free other resources too. */
1115 if (host) {
1116 if (host->iclk && !IS_ERR(host->iclk))
1117 clk_put(host->iclk);
1118 if (host->fclk && !IS_ERR(host->fclk))
1119 clk_put(host->fclk);
1120 mmc_free_host(host->mmc);
1121 }
1122 return ret;
1123 }
1124
1125 static int mmc_omap_remove(struct platform_device *pdev)
1126 {
1127 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1128
1129 platform_set_drvdata(pdev, NULL);
1130
1131 if (host) {
1132 mmc_remove_host(host->mmc);
1133 free_irq(host->irq, host);
1134
1135 if (host->power_pin >= 0)
1136 omap_free_gpio(host->power_pin);
1137 if (host->switch_pin >= 0) {
1138 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1139 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1140 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1141 omap_free_gpio(host->switch_pin);
1142 host->switch_pin = -1;
1143 del_timer_sync(&host->switch_timer);
1144 flush_scheduled_work();
1145 }
1146 if (host->iclk && !IS_ERR(host->iclk))
1147 clk_put(host->iclk);
1148 if (host->fclk && !IS_ERR(host->fclk))
1149 clk_put(host->fclk);
1150 mmc_free_host(host->mmc);
1151 }
1152
1153 release_mem_region(pdev->resource[0].start,
1154 pdev->resource[0].end - pdev->resource[0].start + 1);
1155
1156 return 0;
1157 }
1158
1159 #ifdef CONFIG_PM
1160 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1161 {
1162 int ret = 0;
1163 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1164
1165 if (host && host->suspended)
1166 return 0;
1167
1168 if (host) {
1169 ret = mmc_suspend_host(host->mmc, mesg);
1170 if (ret == 0)
1171 host->suspended = 1;
1172 }
1173 return ret;
1174 }
1175
1176 static int mmc_omap_resume(struct platform_device *pdev)
1177 {
1178 int ret = 0;
1179 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1180
1181 if (host && !host->suspended)
1182 return 0;
1183
1184 if (host) {
1185 ret = mmc_resume_host(host->mmc);
1186 if (ret == 0)
1187 host->suspended = 0;
1188 }
1189
1190 return ret;
1191 }
1192 #else
1193 #define mmc_omap_suspend NULL
1194 #define mmc_omap_resume NULL
1195 #endif
1196
1197 static struct platform_driver mmc_omap_driver = {
1198 .probe = mmc_omap_probe,
1199 .remove = mmc_omap_remove,
1200 .suspend = mmc_omap_suspend,
1201 .resume = mmc_omap_resume,
1202 .driver = {
1203 .name = DRIVER_NAME,
1204 },
1205 };
1206
1207 static int __init mmc_omap_init(void)
1208 {
1209 return platform_driver_register(&mmc_omap_driver);
1210 }
1211
1212 static void __exit mmc_omap_exit(void)
1213 {
1214 platform_driver_unregister(&mmc_omap_driver);
1215 }
1216
1217 module_init(mmc_omap_init);
1218 module_exit(mmc_omap_exit);
1219
1220 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1221 MODULE_LICENSE("GPL");
1222 MODULE_ALIAS(DRIVER_NAME);
1223 MODULE_AUTHOR("Juha Yrjölä");
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz