drivers/mmc/at91_mci.c

   1 /*
   2  *  linux/drivers/mmc/at91_mci.c - ATMEL AT91RM9200 MCI Driver
   3  *
   4  *  Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
   5  *
   6  *  Copyright (C) 2006 Malcolm Noyes
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 /*
  14    This is the AT91RM9200 MCI driver that has been tested with both MMC cards
  15    and SD-cards.  Boards that support write protect are now supported.
  16    The CCAT91SBC001 board does not support SD cards.
  17
  18    The three entry points are at91_mci_request, at91_mci_set_ios
  19    and at91_mci_get_ro.
  20
  21    SET IOS
  22      This configures the device to put it into the correct mode and clock speed
  23      required.
  24
  25    MCI REQUEST
  26      MCI request processes the commands sent in the mmc_request structure. This
  27      can consist of a processing command and a stop command in the case of
  28      multiple block transfers.
  29
  30      There are three main types of request, commands, reads and writes.
  31
  32      Commands are straight forward. The command is submitted to the controller and
  33      the request function returns. When the controller generates an interrupt to indicate
  34      the command is finished, the response to the command are read and the mmc_request_done
  35      function called to end the request.
  36
  37      Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
  38      controller to manage the transfers.
  39
  40      A read is done from the controller directly to the scatterlist passed in from the request.
  41      Due to a bug in the controller, when a read is completed, all the words are byte
  42      swapped in the scatterlist buffers.
  43
  44      The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
  45
  46      A write is slightly different in that the bytes to write are read from the scatterlist
  47      into a dma memory buffer (this is in case the source buffer should be read only). The
  48      entire write buffer is then done from this single dma memory buffer.
  49
  50      The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
  51
  52    GET RO
  53      Gets the status of the write protect pin, if available.
  54 */
  55
  56 #include <linux/module.h>
  57 #include <linux/moduleparam.h>
  58 #include <linux/init.h>
  59 #include <linux/ioport.h>
  60 #include <linux/platform_device.h>
  61 #include <linux/interrupt.h>
  62 #include <linux/blkdev.h>
  63 #include <linux/delay.h>
  64 #include <linux/err.h>
  65 #include <linux/dma-mapping.h>
  66 #include <linux/clk.h>
  67
  68 #include <linux/mmc/host.h>
  69 #include <linux/mmc/protocol.h>
  70
  71 #include <asm/io.h>
  72 #include <asm/irq.h>
  73 #include <asm/mach/mmc.h>
  74 #include <asm/arch/board.h>
  75 #include <asm/arch/gpio.h>
  76 #include <asm/arch/at91rm9200_mci.h>
  77 #include <asm/arch/at91rm9200_pdc.h>
  78
  79 #define DRIVER_NAME "at91_mci"
  80
  81 #undef  SUPPORT_4WIRE
  82
  83 static struct clk *mci_clk;
  84
  85 #define FL_SENT_COMMAND (1 << 0)
  86 #define FL_SENT_STOP (1 << 1)
  87
  88
  89
  90 /*
  91  * Read from a MCI register.
  92  */
  93 static inline unsigned long at91_mci_read(unsigned int reg)
  94 {
  95         void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
  96
  97         return __raw_readl(mci_base + reg);
  98 }
  99
 100 /*
 101  * Write to a MCI register.
 102  */
 103 static inline void at91_mci_write(unsigned int reg, unsigned long value)
 104 {
 105         void __iomem *mci_base = (void __iomem *)AT91_VA_BASE_MCI;
 106
 107         __raw_writel(value, mci_base + reg);
 108 }
 109
 110 /*
 111  * Low level type for this driver
 112  */
 113 struct at91mci_host
 114 {
 115         struct mmc_host *mmc;
 116         struct mmc_command *cmd;
 117         struct mmc_request *request;
 118
 119         struct at91_mmc_data *board;
 120         int present;
 121
 122         /*
 123          * Flag indicating when the command has been sent. This is used to
 124          * work out whether or not to send the stop
 125          */
 126         unsigned int flags;
 127         /* flag for current bus settings */
 128         u32 bus_mode;
 129
 130         /* DMA buffer used for transmitting */
 131         unsigned int* buffer;
 132         dma_addr_t physical_address;
 133         unsigned int total_length;
 134
 135         /* Latest in the scatterlist that has been enabled for transfer, but not freed */
 136         int in_use_index;
 137
 138         /* Latest in the scatterlist that has been enabled for transfer */
 139         int transfer_index;
 140 };
 141
 142 /*
 143  * Copy from sg to a dma block - used for transfers
 144  */
 145 static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
 146 {
 147         unsigned int len, i, size;
 148         unsigned *dmabuf = host->buffer;
 149
 150         size = host->total_length;
 151         len = data->sg_len;
 152
 153         /*
 154          * Just loop through all entries. Size might not
 155          * be the entire list though so make sure that
 156          * we do not transfer too much.
 157          */
 158         for (i = 0; i < len; i++) {
 159                 struct scatterlist *sg;
 160                 int amount;
 161                 int index;
 162                 unsigned int *sgbuffer;
 163
 164                 sg = &data->sg[i];
 165
 166                 sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
 167                 amount = min(size, sg->length);
 168                 size -= amount;
 169                 amount /= 4;
 170
 171                 for (index = 0; index < amount; index++)
 172                         *dmabuf++ = swab32(sgbuffer[index]);
 173
 174                 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
 175
 176                 if (size == 0)
 177                         break;
 178         }
 179
 180         /*
 181          * Check that we didn't get a request to transfer
 182          * more data than can fit into the SG list.
 183          */
 184         BUG_ON(size != 0);
 185 }
 186
 187 /*
 188  * Prepare a dma read
 189  */
 190 static void at91mci_pre_dma_read(struct at91mci_host *host)
 191 {
 192         int i;
 193         struct scatterlist *sg;
 194         struct mmc_command *cmd;
 195         struct mmc_data *data;
 196
 197         pr_debug("pre dma read\n");
 198
 199         cmd = host->cmd;
 200         if (!cmd) {
 201                 pr_debug("no command\n");
 202                 return;
 203         }
 204
 205         data = cmd->data;
 206         if (!data) {
 207                 pr_debug("no data\n");
 208                 return;
 209         }
 210
 211         for (i = 0; i < 2; i++) {
 212                 /* nothing left to transfer */
 213                 if (host->transfer_index >= data->sg_len) {
 214                         pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index);
 215                         break;
 216                 }
 217
 218                 /* Check to see if this needs filling */
 219                 if (i == 0) {
 220                         if (at91_mci_read(AT91_PDC_RCR) != 0) {
 221                                 pr_debug("Transfer active in current\n");
 222                                 continue;
 223                         }
 224                 }
 225                 else {
 226                         if (at91_mci_read(AT91_PDC_RNCR) != 0) {
 227                                 pr_debug("Transfer active in next\n");
 228                                 continue;
 229                         }
 230                 }
 231
 232                 /* Setup the next transfer */
 233                 pr_debug("Using transfer index %d\n", host->transfer_index);
 234
 235                 sg = &data->sg[host->transfer_index++];
 236                 pr_debug("sg = %p\n", sg);
 237
 238                 sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE);
 239
 240                 pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
 241
 242                 if (i == 0) {
 243                         at91_mci_write(AT91_PDC_RPR, sg->dma_address);
 244                         at91_mci_write(AT91_PDC_RCR, sg->length / 4);
 245                 }
 246                 else {
 247                         at91_mci_write(AT91_PDC_RNPR, sg->dma_address);
 248                         at91_mci_write(AT91_PDC_RNCR, sg->length / 4);
 249                 }
 250         }
 251
 252         pr_debug("pre dma read done\n");
 253 }
 254
 255 /*
 256  * Handle after a dma read
 257  */
 258 static void at91mci_post_dma_read(struct at91mci_host *host)
 259 {
 260         struct mmc_command *cmd;
 261         struct mmc_data *data;
 262
 263         pr_debug("post dma read\n");
 264
 265         cmd = host->cmd;
 266         if (!cmd) {
 267                 pr_debug("no command\n");
 268                 return;
 269         }
 270
 271         data = cmd->data;
 272         if (!data) {
 273                 pr_debug("no data\n");
 274                 return;
 275         }
 276
 277         while (host->in_use_index < host->transfer_index) {
 278                 unsigned int *buffer;
 279                 int index;
 280                 int len;
 281
 282                 struct scatterlist *sg;
 283
 284                 pr_debug("finishing index %d\n", host->in_use_index);
 285
 286                 sg = &data->sg[host->in_use_index++];
 287
 288                 pr_debug("Unmapping page %08X\n", sg->dma_address);
 289
 290                 dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
 291
 292                 /* Swap the contents of the buffer */
 293                 buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
 294                 pr_debug("buffer = %p, length = %d\n", buffer, sg->length);
 295
 296                 data->bytes_xfered += sg->length;
 297
 298                 len = sg->length / 4;
 299
 300                 for (index = 0; index < len; index++) {
 301                         buffer[index] = swab32(buffer[index]);
 302                 }
 303                 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 304                 flush_dcache_page(sg->page);
 305         }
 306
 307         /* Is there another transfer to trigger? */
 308         if (host->transfer_index < data->sg_len)
 309                 at91mci_pre_dma_read(host);
 310         else {
 311                 at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
 312                 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
 313         }
 314
 315         pr_debug("post dma read done\n");
 316 }
 317
 318 /*
 319  * Handle transmitted data
 320  */
 321 static void at91_mci_handle_transmitted(struct at91mci_host *host)
 322 {
 323         struct mmc_command *cmd;
 324         struct mmc_data *data;
 325
 326         pr_debug("Handling the transmit\n");
 327
 328         /* Disable the transfer */
 329         at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
 330
 331         /* Now wait for cmd ready */
 332         at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
 333         at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
 334
 335         cmd = host->cmd;
 336         if (!cmd) return;
 337
 338         data = cmd->data;
 339         if (!data) return;
 340
 341         data->bytes_xfered = host->total_length;
 342 }
 343
 344 /*
 345  * Enable the controller
 346  */
 347 static void at91_mci_enable(void)
 348 {
 349         at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
 350         at91_mci_write(AT91_MCI_IDR, 0xFFFFFFFF);
 351         at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
 352         at91_mci_write(AT91_MCI_MR, 0x834A);
 353         at91_mci_write(AT91_MCI_SDCR, 0x0);
 354 }
 355
 356 /*
 357  * Disable the controller
 358  */
 359 static void at91_mci_disable(void)
 360 {
 361         at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
 362 }
 363
 364 /*
 365  * Send a command
 366  * return the interrupts to enable
 367  */
 368 static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
 369 {
 370         unsigned int cmdr, mr;
 371         unsigned int block_length;
 372         struct mmc_data *data = cmd->data;
 373
 374         unsigned int blocks;
 375         unsigned int ier = 0;
 376
 377         host->cmd = cmd;
 378
 379         /* Not sure if this is needed */
 380 #if 0
 381         if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
 382                 pr_debug("Clearing timeout\n");
 383                 at91_mci_write(AT91_MCI_ARGR, 0);
 384                 at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
 385                 while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
 386                         /* spin */
 387                         pr_debug("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
 388                 }
 389         }
 390 #endif
 391         cmdr = cmd->opcode;
 392
 393         if (mmc_resp_type(cmd) == MMC_RSP_NONE)
 394                 cmdr |= AT91_MCI_RSPTYP_NONE;
 395         else {
 396                 /* if a response is expected then allow maximum response latancy */
 397                 cmdr |= AT91_MCI_MAXLAT;
 398                 /* set 136 bit response for R2, 48 bit response otherwise */
 399                 if (mmc_resp_type(cmd) == MMC_RSP_R2)
 400                         cmdr |= AT91_MCI_RSPTYP_136;
 401                 else
 402                         cmdr |= AT91_MCI_RSPTYP_48;
 403         }
 404
 405         if (data) {
 406                 block_length = data->blksz;
 407                 blocks = data->blocks;
 408
 409                 /* always set data start - also set direction flag for read */
 410                 if (data->flags & MMC_DATA_READ)
 411                         cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
 412                 else if (data->flags & MMC_DATA_WRITE)
 413                         cmdr |= AT91_MCI_TRCMD_START;
 414
 415                 if (data->flags & MMC_DATA_STREAM)
 416                         cmdr |= AT91_MCI_TRTYP_STREAM;
 417                 if (data->flags & MMC_DATA_MULTI)
 418                         cmdr |= AT91_MCI_TRTYP_MULTIPLE;
 419         }
 420         else {
 421                 block_length = 0;
 422                 blocks = 0;
 423         }
 424
 425         if (cmd->opcode == MMC_STOP_TRANSMISSION)
 426                 cmdr |= AT91_MCI_TRCMD_STOP;
 427
 428         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 429                 cmdr |= AT91_MCI_OPDCMD;
 430
 431         /*
 432          * Set the arguments and send the command
 433          */
 434         pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n",
 435                 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
 436
 437         if (!data) {
 438                 at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
 439                 at91_mci_write(AT91_PDC_RPR, 0);
 440                 at91_mci_write(AT91_PDC_RCR, 0);
 441                 at91_mci_write(AT91_PDC_RNPR, 0);
 442                 at91_mci_write(AT91_PDC_RNCR, 0);
 443                 at91_mci_write(AT91_PDC_TPR, 0);
 444                 at91_mci_write(AT91_PDC_TCR, 0);
 445                 at91_mci_write(AT91_PDC_TNPR, 0);
 446                 at91_mci_write(AT91_PDC_TNCR, 0);
 447
 448                 at91_mci_write(AT91_MCI_ARGR, cmd->arg);
 449                 at91_mci_write(AT91_MCI_CMDR, cmdr);
 450                 return AT91_MCI_CMDRDY;
 451         }
 452
 453         mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;       /* zero block length and PDC mode */
 454         at91_mci_write(AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
 455
 456         /*
 457          * Disable the PDC controller
 458          */
 459         at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
 460
 461         if (cmdr & AT91_MCI_TRCMD_START) {
 462                 data->bytes_xfered = 0;
 463                 host->transfer_index = 0;
 464                 host->in_use_index = 0;
 465                 if (cmdr & AT91_MCI_TRDIR) {
 466                         /*
 467                          * Handle a read
 468                          */
 469                         host->buffer = NULL;
 470                         host->total_length = 0;
 471
 472                         at91mci_pre_dma_read(host);
 473                         ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
 474                 }
 475                 else {
 476                         /*
 477                          * Handle a write
 478                          */
 479                         host->total_length = block_length * blocks;
 480                         host->buffer = dma_alloc_coherent(NULL,
 481                                                   host->total_length,
 482                                                   &host->physical_address, GFP_KERNEL);
 483
 484                         at91mci_sg_to_dma(host, data);
 485
 486                         pr_debug("Transmitting %d bytes\n", host->total_length);
 487
 488                         at91_mci_write(AT91_PDC_TPR, host->physical_address);
 489                         at91_mci_write(AT91_PDC_TCR, host->total_length / 4);
 490                         ier = AT91_MCI_TXBUFE;
 491                 }
 492         }
 493
 494         /*
 495          * Send the command and then enable the PDC - not the other way round as
 496          * the data sheet says
 497          */
 498
 499         at91_mci_write(AT91_MCI_ARGR, cmd->arg);
 500         at91_mci_write(AT91_MCI_CMDR, cmdr);
 501
 502         if (cmdr & AT91_MCI_TRCMD_START) {
 503                 if (cmdr & AT91_MCI_TRDIR)
 504                         at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
 505                 else
 506                         at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
 507         }
 508         return ier;
 509 }
 510
 511 /*
 512  * Wait for a command to complete
 513  */
 514 static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd)
 515 {
 516         unsigned int ier;
 517
 518         ier = at91_mci_send_command(host, cmd);
 519
 520         pr_debug("setting ier to %08X\n", ier);
 521
 522         /* Stop on errors or the required value */
 523         at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier);
 524 }
 525
 526 /*
 527  * Process the next step in the request
 528  */
 529 static void at91mci_process_next(struct at91mci_host *host)
 530 {
 531         if (!(host->flags & FL_SENT_COMMAND)) {
 532                 host->flags |= FL_SENT_COMMAND;
 533                 at91mci_process_command(host, host->request->cmd);
 534         }
 535         else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
 536                 host->flags |= FL_SENT_STOP;
 537                 at91mci_process_command(host, host->request->stop);
 538         }
 539         else
 540                 mmc_request_done(host->mmc, host->request);
 541 }
 542
 543 /*
 544  * Handle a command that has been completed
 545  */
 546 static void at91mci_completed_command(struct at91mci_host *host)
 547 {
 548         struct mmc_command *cmd = host->cmd;
 549         unsigned int status;
 550
 551         at91_mci_write(AT91_MCI_IDR, 0xffffffff);
 552
 553         cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
 554         cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
 555         cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
 556         cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
 557
 558         if (host->buffer) {
 559                 dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
 560                 host->buffer = NULL;
 561         }
 562
 563         status = at91_mci_read(AT91_MCI_SR);
 564
 565         pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
 566                  status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
 567
 568         if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
 569                         AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
 570                         AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
 571                 if ((status & AT91_MCI_RCRCE) &&
 572                         ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
 573                         cmd->error = MMC_ERR_NONE;
 574                 }
 575                 else {
 576                         if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE))
 577                                 cmd->error = MMC_ERR_TIMEOUT;
 578                         else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE))
 579                                 cmd->error = MMC_ERR_BADCRC;
 580                         else if (status & (AT91_MCI_OVRE | AT91_MCI_UNRE))
 581                                 cmd->error = MMC_ERR_FIFO;
 582                         else
 583                                 cmd->error = MMC_ERR_FAILED;
 584
 585                         pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n",
 586                                  cmd->error, cmd->opcode, cmd->retries);
 587                 }
 588         }
 589         else
 590                 cmd->error = MMC_ERR_NONE;
 591
 592         at91mci_process_next(host);
 593 }
 594
 595 /*
 596  * Handle an MMC request
 597  */
 598 static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 599 {
 600         struct at91mci_host *host = mmc_priv(mmc);
 601         host->request = mrq;
 602         host->flags = 0;
 603
 604         at91mci_process_next(host);
 605 }
 606
 607 /*
 608  * Set the IOS
 609  */
 610 static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 611 {
 612         int clkdiv;
 613         struct at91mci_host *host = mmc_priv(mmc);
 614         unsigned long at91_master_clock = clk_get_rate(mci_clk);
 615
 616         host->bus_mode = ios->bus_mode;
 617
 618         if (ios->clock == 0) {
 619                 /* Disable the MCI controller */
 620                 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
 621                 clkdiv = 0;
 622         }
 623         else {
 624                 /* Enable the MCI controller */
 625                 at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
 626
 627                 if ((at91_master_clock % (ios->clock * 2)) == 0)
 628                         clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
 629                 else
 630                         clkdiv = (at91_master_clock / ios->clock) / 2;
 631
 632                 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
 633                         at91_master_clock / (2 * (clkdiv + 1)));
 634         }
 635         if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
 636                 pr_debug("MMC: Setting controller bus width to 4\n");
 637                 at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
 638         }
 639         else {
 640                 pr_debug("MMC: Setting controller bus width to 1\n");
 641                 at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
 642         }
 643
 644         /* Set the clock divider */
 645         at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
 646
 647         /* maybe switch power to the card */
 648         if (host->board->vcc_pin) {
 649                 switch (ios->power_mode) {
 650                         case MMC_POWER_OFF:
 651                                 at91_set_gpio_output(host->board->vcc_pin, 0);
 652                                 break;
 653                         case MMC_POWER_UP:
 654                         case MMC_POWER_ON:
 655                                 at91_set_gpio_output(host->board->vcc_pin, 1);
 656                                 break;
 657                 }
 658         }
 659 }
 660
 661 /*
 662  * Handle an interrupt
 663  */
 664 static irqreturn_t at91_mci_irq(int irq, void *devid)
 665 {
 666         struct at91mci_host *host = devid;
 667         int completed = 0;
 668
 669         unsigned int int_status;
 670
 671         int_status = at91_mci_read(AT91_MCI_SR);
 672         pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR),
 673                 int_status & at91_mci_read(AT91_MCI_IMR));
 674
 675         if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000)
 676                 completed = 1;
 677
 678         int_status &= at91_mci_read(AT91_MCI_IMR);
 679
 680         if (int_status & AT91_MCI_UNRE)
 681                 pr_debug("MMC: Underrun error\n");
 682         if (int_status & AT91_MCI_OVRE)
 683                 pr_debug("MMC: Overrun error\n");
 684         if (int_status & AT91_MCI_DTOE)
 685                 pr_debug("MMC: Data timeout\n");
 686         if (int_status & AT91_MCI_DCRCE)
 687                 pr_debug("MMC: CRC error in data\n");
 688         if (int_status & AT91_MCI_RTOE)
 689                 pr_debug("MMC: Response timeout\n");
 690         if (int_status & AT91_MCI_RENDE)
 691                 pr_debug("MMC: Response end bit error\n");
 692         if (int_status & AT91_MCI_RCRCE)
 693                 pr_debug("MMC: Response CRC error\n");
 694         if (int_status & AT91_MCI_RDIRE)
 695                 pr_debug("MMC: Response direction error\n");
 696         if (int_status & AT91_MCI_RINDE)
 697                 pr_debug("MMC: Response index error\n");
 698
 699         /* Only continue processing if no errors */
 700         if (!completed) {
 701                 if (int_status & AT91_MCI_TXBUFE) {
 702                         pr_debug("TX buffer empty\n");
 703                         at91_mci_handle_transmitted(host);
 704                 }
 705
 706                 if (int_status & AT91_MCI_RXBUFF) {
 707                         pr_debug("RX buffer full\n");
 708                         at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
 709                 }
 710
 711                 if (int_status & AT91_MCI_ENDTX) {
 712                         pr_debug("Transmit has ended\n");
 713                 }
 714
 715                 if (int_status & AT91_MCI_ENDRX) {
 716                         pr_debug("Receive has ended\n");
 717                         at91mci_post_dma_read(host);
 718                 }
 719
 720                 if (int_status & AT91_MCI_NOTBUSY) {
 721                         pr_debug("Card is ready\n");
 722                         at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY);
 723                 }
 724
 725                 if (int_status & AT91_MCI_DTIP) {
 726                         pr_debug("Data transfer in progress\n");
 727                 }
 728
 729                 if (int_status & AT91_MCI_BLKE) {
 730                         pr_debug("Block transfer has ended\n");
 731                 }
 732
 733                 if (int_status & AT91_MCI_TXRDY) {
 734                         pr_debug("Ready to transmit\n");
 735                 }
 736
 737                 if (int_status & AT91_MCI_RXRDY) {
 738                         pr_debug("Ready to receive\n");
 739                 }
 740
 741                 if (int_status & AT91_MCI_CMDRDY) {
 742                         pr_debug("Command ready\n");
 743                         completed = 1;
 744                 }
 745         }
 746         at91_mci_write(AT91_MCI_IDR, int_status);
 747
 748         if (completed) {
 749                 pr_debug("Completed command\n");
 750                 at91_mci_write(AT91_MCI_IDR, 0xffffffff);
 751                 at91mci_completed_command(host);
 752         }
 753
 754         return IRQ_HANDLED;
 755 }
 756
 757 static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
 758 {
 759         struct at91mci_host *host = _host;
 760         int present = !at91_get_gpio_value(irq);
 761
 762         /*
 763          * we expect this irq on both insert and remove,
 764          * and use a short delay to debounce.
 765          */
 766         if (present != host->present) {
 767                 host->present = present;
 768                 pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
 769                         present ? "insert" : "remove");
 770                 if (!present) {
 771                         pr_debug("****** Resetting SD-card bus width ******\n");
 772                         at91_mci_write(AT91_MCI_SDCR, 0);
 773                 }
 774                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
 775         }
 776         return IRQ_HANDLED;
 777 }
 778
 779 int at91_mci_get_ro(struct mmc_host *mmc)
 780 {
 781         int read_only = 0;
 782         struct at91mci_host *host = mmc_priv(mmc);
 783
 784         if (host->board->wp_pin) {
 785                 read_only = at91_get_gpio_value(host->board->wp_pin);
 786                 printk(KERN_WARNING "%s: card is %s\n", mmc_hostname(mmc),
 787                                 (read_only ? "read-only" : "read-write") );
 788         }
 789         else {
 790                 printk(KERN_WARNING "%s: host does not support reading read-only "
 791                                 "switch.  Assuming write-enable.\n", mmc_hostname(mmc));
 792         }
 793         return read_only;
 794 }
 795
 796 static struct mmc_host_ops at91_mci_ops = {
 797         .request        = at91_mci_request,
 798         .set_ios        = at91_mci_set_ios,
 799         .get_ro         = at91_mci_get_ro,
 800 };
 801
 802 /*
 803  * Probe for the device
 804  */
 805 static int at91_mci_probe(struct platform_device *pdev)
 806 {
 807         struct mmc_host *mmc;
 808         struct at91mci_host *host;
 809         int ret;
 810
 811         pr_debug("Probe MCI devices\n");
 812         at91_mci_disable();
 813         at91_mci_enable();
 814
 815         mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
 816         if (!mmc) {
 817                 pr_debug("Failed to allocate mmc host\n");
 818                 return -ENOMEM;
 819         }
 820
 821         mmc->ops = &at91_mci_ops;
 822         mmc->f_min = 375000;
 823         mmc->f_max = 25000000;
 824         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 825         mmc->caps = MMC_CAP_BYTEBLOCK;
 826
 827         host = mmc_priv(mmc);
 828         host->mmc = mmc;
 829         host->buffer = NULL;
 830         host->bus_mode = 0;
 831         host->board = pdev->dev.platform_data;
 832         if (host->board->wire4) {
 833 #ifdef SUPPORT_4WIRE
 834                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 835 #else
 836                 printk("MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
 837 #endif
 838         }
 839
 840         /*
 841          * Get Clock
 842          */
 843         mci_clk = clk_get(&pdev->dev, "mci_clk");
 844         if (IS_ERR(mci_clk)) {
 845                 printk(KERN_ERR "AT91 MMC: no clock defined.\n");
 846                 mmc_free_host(mmc);
 847                 return -ENODEV;
 848         }
 849         clk_enable(mci_clk);                    /* Enable the peripheral clock */
 850
 851         /*
 852          * Allocate the MCI interrupt
 853          */
 854         ret = request_irq(AT91RM9200_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
 855         if (ret) {
 856                 printk(KERN_ERR "Failed to request MCI interrupt\n");
 857                 clk_disable(mci_clk);
 858                 clk_put(mci_clk);
 859                 mmc_free_host(mmc);
 860                 return ret;
 861         }
 862
 863         platform_set_drvdata(pdev, mmc);
 864
 865         /*
 866          * Add host to MMC layer
 867          */
 868         if (host->board->det_pin)
 869                 host->present = !at91_get_gpio_value(host->board->det_pin);
 870         else
 871                 host->present = -1;
 872
 873         mmc_add_host(mmc);
 874
 875         /*
 876          * monitor card insertion/removal if we can
 877          */
 878         if (host->board->det_pin) {
 879                 ret = request_irq(host->board->det_pin, at91_mmc_det_irq,
 880                                 0, DRIVER_NAME, host);
 881                 if (ret)
 882                         printk(KERN_ERR "couldn't allocate MMC detect irq\n");
 883         }
 884
 885         pr_debug(KERN_INFO "Added MCI driver\n");
 886
 887         return 0;
 888 }
 889
 890 /*
 891  * Remove a device
 892  */
 893 static int at91_mci_remove(struct platform_device *pdev)
 894 {
 895         struct mmc_host *mmc = platform_get_drvdata(pdev);
 896         struct at91mci_host *host;
 897
 898         if (!mmc)
 899                 return -1;
 900
 901         host = mmc_priv(mmc);
 902
 903         if (host->present != -1) {
 904                 free_irq(host->board->det_pin, host);
 905                 cancel_delayed_work(&host->mmc->detect);
 906         }
 907
 908         mmc_remove_host(mmc);
 909         at91_mci_disable();
 910         free_irq(AT91RM9200_ID_MCI, host);
 911         mmc_free_host(mmc);
 912
 913         clk_disable(mci_clk);                           /* Disable the peripheral clock */
 914         clk_put(mci_clk);
 915
 916         platform_set_drvdata(pdev, NULL);
 917
 918         pr_debug("MCI Removed\n");
 919
 920         return 0;
 921 }
 922
 923 #ifdef CONFIG_PM
 924 static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
 925 {
 926         struct mmc_host *mmc = platform_get_drvdata(pdev);
 927         int ret = 0;
 928
 929         if (mmc)
 930                 ret = mmc_suspend_host(mmc, state);
 931
 932         return ret;
 933 }
 934
 935 static int at91_mci_resume(struct platform_device *pdev)
 936 {
 937         struct mmc_host *mmc = platform_get_drvdata(pdev);
 938         int ret = 0;
 939
 940         if (mmc)
 941                 ret = mmc_resume_host(mmc);
 942
 943         return ret;
 944 }
 945 #else
 946 #define at91_mci_suspend        NULL
 947 #define at91_mci_resume         NULL
 948 #endif
 949
 950 static struct platform_driver at91_mci_driver = {
 951         .probe          = at91_mci_probe,
 952         .remove         = at91_mci_remove,
 953         .suspend        = at91_mci_suspend,
 954         .resume         = at91_mci_resume,
 955         .driver         = {
 956                 .name   = DRIVER_NAME,
 957                 .owner  = THIS_MODULE,
 958         },
 959 };
 960
 961 static int __init at91_mci_init(void)
 962 {
 963         return platform_driver_register(&at91_mci_driver);
 964 }
 965
 966 static void __exit at91_mci_exit(void)
 967 {
 968         platform_driver_unregister(&at91_mci_driver);
 969 }
 970
 971 module_init(at91_mci_init);
 972 module_exit(at91_mci_exit);
 973
 974 MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
 975 MODULE_AUTHOR("Nick Randell");
 976 MODULE_LICENSE("GPL");