1 /* ------------------------------------------------------------------------- */
2 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
3 /* ------------------------------------------------------------------------- */
4 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 * <Peter dot Milne at D hyphen TACQ dot com>
7 * With acknowledgements to i2c-algo-ibm_ocp.c by
8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
17 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
19 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
20 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
21 * - Make it work with IXP46x chips
22 * - Cleanup function names, coding style, etc
24 * - writing to slave address causes latchup on iop331.
25 * fix: driver refuses to address self.
27 * This program is free software; you can redistribute it and/or modify
28 * it under the terms of the GNU General Public License as published by
29 * the Free Software Foundation, version 2.
32 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/slab.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/sched.h>
40 #include <linux/platform_device.h>
41 #include <linux/i2c.h>
45 #include "i2c-iop3xx.h"
47 /* global unit counter */
50 static inline unsigned char
51 iic_cook_addr(struct i2c_msg
*msg
)
55 addr
= (msg
->addr
<< 1);
57 if (msg
->flags
& I2C_M_RD
)
63 if (msg
->flags
& I2C_M_REV_DIR_ADDR
)
70 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
72 /* Follows devman 9.3 */
73 __raw_writel(IOP3XX_ICR_UNIT_RESET
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
74 __raw_writel(IOP3XX_ISR_CLEARBITS
, iop3xx_adap
->ioaddr
+ SR_OFFSET
);
75 __raw_writel(0, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
79 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
81 u32 cr
= IOP3XX_ICR_GCD
| IOP3XX_ICR_SCLEN
| IOP3XX_ICR_UE
;
84 * Every time unit enable is asserted, GPOD needs to be cleared
85 * on IOP3XX to avoid data corruption on the bus.
87 #ifdef CONFIG_PLAT_IOP
88 if (iop3xx_adap
->id
== 0) {
89 gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW
);
90 gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW
);
92 gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW
);
93 gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW
);
96 /* NB SR bits not same position as CR IE bits :-( */
97 iop3xx_adap
->SR_enabled
=
98 IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
|
99 IOP3XX_ISR_RXFULL
| IOP3XX_ISR_TXEMPTY
;
101 cr
|= IOP3XX_ICR_ALD_IE
| IOP3XX_ICR_BERR_IE
|
102 IOP3XX_ICR_RXFULL_IE
| IOP3XX_ICR_TXEMPTY_IE
;
104 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
108 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
110 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
112 cr
&= ~(IOP3XX_ICR_MSTART
| IOP3XX_ICR_TBYTE
|
113 IOP3XX_ICR_MSTOP
| IOP3XX_ICR_SCLEN
);
115 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
119 * NB: the handler has to clear the source of the interrupt!
120 * Then it passes the SR flags of interest to BH via adap data
123 iop3xx_i2c_irq_handler(int this_irq
, void *dev_id
)
125 struct i2c_algo_iop3xx_data
*iop3xx_adap
= dev_id
;
126 u32 sr
= __raw_readl(iop3xx_adap
->ioaddr
+ SR_OFFSET
);
128 if ((sr
&= iop3xx_adap
->SR_enabled
)) {
129 __raw_writel(sr
, iop3xx_adap
->ioaddr
+ SR_OFFSET
);
130 iop3xx_adap
->SR_received
|= sr
;
131 wake_up_interruptible(&iop3xx_adap
->waitq
);
136 /* check all error conditions, clear them , report most important */
138 iop3xx_i2c_error(u32 sr
)
142 if ((sr
& IOP3XX_ISR_BERRD
)) {
143 if ( !rc
) rc
= -I2C_ERR_BERR
;
145 if ((sr
& IOP3XX_ISR_ALD
)) {
146 if ( !rc
) rc
= -I2C_ERR_ALD
;
152 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
157 spin_lock_irqsave(&iop3xx_adap
->lock
, flags
);
158 sr
= iop3xx_adap
->SR_received
;
159 iop3xx_adap
->SR_received
= 0;
160 spin_unlock_irqrestore(&iop3xx_adap
->lock
, flags
);
166 * sleep until interrupted, then recover and analyse the SR
169 typedef int (* compare_func
)(unsigned test
, unsigned mask
);
170 /* returns 1 on correct comparison */
173 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data
*iop3xx_adap
,
174 unsigned flags
, unsigned* status
,
175 compare_func compare
)
183 interrupted
= wait_event_interruptible_timeout (
185 (done
= compare( sr
= iop3xx_i2c_get_srstat(iop3xx_adap
) ,flags
)),
188 if ((rc
= iop3xx_i2c_error(sr
)) < 0) {
191 } else if (!interrupted
) {
203 * Concrete compare_funcs
206 all_bits_clear(unsigned test
, unsigned mask
)
208 return (test
& mask
) == 0;
212 any_bits_set(unsigned test
, unsigned mask
)
214 return (test
& mask
) != 0;
218 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
220 return iop3xx_i2c_wait_event(
222 IOP3XX_ISR_TXEMPTY
| IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
,
223 status
, any_bits_set
);
227 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
229 return iop3xx_i2c_wait_event(
231 IOP3XX_ISR_RXFULL
| IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
,
232 status
, any_bits_set
);
236 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
238 return iop3xx_i2c_wait_event(
239 iop3xx_adap
, IOP3XX_ISR_UNITBUSY
, status
, all_bits_clear
);
243 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data
*iop3xx_adap
,
246 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
250 /* avoid writing to my slave address (hangs on 80331),
251 * forbidden in Intel developer manual
253 if (msg
->addr
== MYSAR
) {
257 __raw_writel(iic_cook_addr(msg
), iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
259 cr
&= ~(IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
);
260 cr
|= IOP3XX_ICR_MSTART
| IOP3XX_ICR_TBYTE
;
262 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
263 rc
= iop3xx_i2c_wait_tx_done(iop3xx_adap
, &status
);
269 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data
*iop3xx_adap
, char byte
,
272 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
276 __raw_writel(byte
, iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
277 cr
&= ~IOP3XX_ICR_MSTART
;
279 cr
|= IOP3XX_ICR_MSTOP
;
281 cr
&= ~IOP3XX_ICR_MSTOP
;
283 cr
|= IOP3XX_ICR_TBYTE
;
284 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
285 rc
= iop3xx_i2c_wait_tx_done(iop3xx_adap
, &status
);
291 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data
*iop3xx_adap
, char* byte
,
294 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
298 cr
&= ~IOP3XX_ICR_MSTART
;
301 cr
|= IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
;
303 cr
&= ~(IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
);
305 cr
|= IOP3XX_ICR_TBYTE
;
306 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
308 rc
= iop3xx_i2c_wait_rx_done(iop3xx_adap
, &status
);
310 *byte
= __raw_readl(iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
316 iop3xx_i2c_writebytes(struct i2c_adapter
*i2c_adap
, const char *buf
, int count
)
318 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
322 for (ii
= 0; rc
== 0 && ii
!= count
; ++ii
)
323 rc
= iop3xx_i2c_write_byte(iop3xx_adap
, buf
[ii
], ii
==count
-1);
328 iop3xx_i2c_readbytes(struct i2c_adapter
*i2c_adap
, char *buf
, int count
)
330 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
334 for (ii
= 0; rc
== 0 && ii
!= count
; ++ii
)
335 rc
= iop3xx_i2c_read_byte(iop3xx_adap
, &buf
[ii
], ii
==count
-1);
341 * Description: This function implements combined transactions. Combined
342 * transactions consist of combinations of reading and writing blocks of data.
343 * FROM THE SAME ADDRESS
344 * Each transfer (i.e. a read or a write) is separated by a repeated start
348 iop3xx_i2c_handle_msg(struct i2c_adapter
*i2c_adap
, struct i2c_msg
* pmsg
)
350 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
353 rc
= iop3xx_i2c_send_target_addr(iop3xx_adap
, pmsg
);
358 if ((pmsg
->flags
&I2C_M_RD
)) {
359 return iop3xx_i2c_readbytes(i2c_adap
, pmsg
->buf
, pmsg
->len
);
361 return iop3xx_i2c_writebytes(i2c_adap
, pmsg
->buf
, pmsg
->len
);
366 * master_xfer() - main read/write entry
369 iop3xx_i2c_master_xfer(struct i2c_adapter
*i2c_adap
, struct i2c_msg
*msgs
,
372 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
377 iop3xx_i2c_wait_idle(iop3xx_adap
, &status
);
378 iop3xx_i2c_reset(iop3xx_adap
);
379 iop3xx_i2c_enable(iop3xx_adap
);
381 for (im
= 0; ret
== 0 && im
!= num
; im
++) {
382 ret
= iop3xx_i2c_handle_msg(i2c_adap
, &msgs
[im
]);
385 iop3xx_i2c_transaction_cleanup(iop3xx_adap
);
394 iop3xx_i2c_algo_control(struct i2c_adapter
*adapter
, unsigned int cmd
,
401 iop3xx_i2c_func(struct i2c_adapter
*adap
)
403 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
406 static const struct i2c_algorithm iop3xx_i2c_algo
= {
407 .master_xfer
= iop3xx_i2c_master_xfer
,
408 .algo_control
= iop3xx_i2c_algo_control
,
409 .functionality
= iop3xx_i2c_func
,
413 iop3xx_i2c_remove(struct platform_device
*pdev
)
415 struct i2c_adapter
*padapter
= platform_get_drvdata(pdev
);
416 struct i2c_algo_iop3xx_data
*adapter_data
=
417 (struct i2c_algo_iop3xx_data
*)padapter
->algo_data
;
418 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
419 unsigned long cr
= __raw_readl(adapter_data
->ioaddr
+ CR_OFFSET
);
422 * Disable the actual HW unit
424 cr
&= ~(IOP3XX_ICR_ALD_IE
| IOP3XX_ICR_BERR_IE
|
425 IOP3XX_ICR_RXFULL_IE
| IOP3XX_ICR_TXEMPTY_IE
);
426 __raw_writel(cr
, adapter_data
->ioaddr
+ CR_OFFSET
);
428 iounmap((void __iomem
*)adapter_data
->ioaddr
);
429 release_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
);
433 platform_set_drvdata(pdev
, NULL
);
439 iop3xx_i2c_probe(struct platform_device
*pdev
)
441 struct resource
*res
;
443 struct i2c_adapter
*new_adapter
;
444 struct i2c_algo_iop3xx_data
*adapter_data
;
446 new_adapter
= kzalloc(sizeof(struct i2c_adapter
), GFP_KERNEL
);
452 adapter_data
= kzalloc(sizeof(struct i2c_algo_iop3xx_data
), GFP_KERNEL
);
458 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
464 if (!request_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
, pdev
->name
)) {
469 /* set the adapter enumeration # */
470 adapter_data
->id
= i2c_id
++;
472 adapter_data
->ioaddr
= (u32
)ioremap(res
->start
, IOP3XX_I2C_IO_SIZE
);
473 if (!adapter_data
->ioaddr
) {
478 irq
= platform_get_irq(pdev
, 0);
483 ret
= request_irq(irq
, iop3xx_i2c_irq_handler
, 0,
484 pdev
->name
, adapter_data
);
491 memcpy(new_adapter
->name
, pdev
->name
, strlen(pdev
->name
));
492 new_adapter
->id
= I2C_HW_IOP3XX
;
493 new_adapter
->owner
= THIS_MODULE
;
494 new_adapter
->class = I2C_CLASS_HWMON
,
495 new_adapter
->dev
.parent
= &pdev
->dev
;
498 * Default values...should these come in from board code?
500 new_adapter
->timeout
= 100;
501 new_adapter
->retries
= 3;
502 new_adapter
->algo
= &iop3xx_i2c_algo
;
504 init_waitqueue_head(&adapter_data
->waitq
);
505 spin_lock_init(&adapter_data
->lock
);
507 iop3xx_i2c_reset(adapter_data
);
508 iop3xx_i2c_enable(adapter_data
);
510 platform_set_drvdata(pdev
, new_adapter
);
511 new_adapter
->algo_data
= adapter_data
;
513 i2c_add_adapter(new_adapter
);
518 iounmap((void __iomem
*)adapter_data
->ioaddr
);
521 release_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
);
534 static struct platform_driver iop3xx_i2c_driver
= {
535 .probe
= iop3xx_i2c_probe
,
536 .remove
= iop3xx_i2c_remove
,
538 .owner
= THIS_MODULE
,
539 .name
= "IOP3xx-I2C",
544 i2c_iop3xx_init (void)
546 return platform_driver_register(&iop3xx_i2c_driver
);
550 i2c_iop3xx_exit (void)
552 platform_driver_unregister(&iop3xx_i2c_driver
);
556 module_init (i2c_iop3xx_init
);
557 module_exit (i2c_iop3xx_exit
);
559 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
560 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
561 MODULE_LICENSE("GPL");