1 #if !defined(MCF_QSPI_H)
4 #include <asm/mcfqspi.h>
5 #include <linux/types.h>
9 #if defined(CONFIG_M5249)
10 #define MCFQSPI_IRQ_VECTOR 27
11 #define QSPIMOD_OFFSET 0x400
12 #elif defined(CONFIG_M523x)
13 #define MCF5235ICM_INTC0 0xC00
14 #define MCFINTC0_ICR 0x40
15 #define MCFQSPI_IRQ_VECTOR 82
16 #define QSPIMOD_OFFSET 0x340
18 #define MCF5235INTC_IMRL 0x0C
19 #elif (defined(CONFIG_M5282) || defined(CONFIG_M5280))
20 #define MCFQSPI_IRQ_VECTOR (64 + 18)
21 #define QSPIMOD_OFFSET 0x340
23 #define MCFQSPI_IRQ_VECTOR 89
24 #define QSPIMOD_OFFSET 0xa0
29 #define MCFSIM_QMR (0x00 + QSPIMOD_OFFSET) /* mode */
30 #define MCFSIM_QDLYR (0x04 + QSPIMOD_OFFSET) /* delay */
31 #define MCFSIM_QWR (0x08 + QSPIMOD_OFFSET) /* wrap */
32 #define MCFSIM_QIR (0x0c + QSPIMOD_OFFSET) /* interrupt */
33 #define MCFSIM_QAR (0x10 + QSPIMOD_OFFSET) /* address */
34 #define MCFSIM_QDR (0x14 + QSPIMOD_OFFSET) /* address */
36 #define TX_RAM_START 0x00
37 #define RX_RAM_START 0x10
38 #define COMMAND_RAM_START 0x20
40 #define QMR *(volatile u16 *)(MCF_MBAR + MCFSIM_QMR)
41 #define QAR *(volatile u16 *)(MCF_MBAR + MCFSIM_QAR)
42 #define QDR *(volatile u16 *)(MCF_MBAR + MCFSIM_QDR)
43 #define QWR *(volatile u16 *)(MCF_MBAR + MCFSIM_QWR)
44 #define QDLYR *(volatile u16 *)(MCF_MBAR + MCFSIM_QDLYR)
45 #define QIR *(volatile u16 *)(MCF_MBAR + MCFSIM_QIR)
49 #define QMR_MSTR 0x8000 /* master mode enable: must always be set */
50 #define QMR_DOHIE 0x4000 /* shut off (hi-z) Dout between transfers */
51 #define QMR_BITS 0x3c00 /* bits per transfer (size) */
52 #define QMR_CPOL 0x0200 /* clock state when inactive */
53 #define QMR_CPHA 0x0100 /* clock phase: 1 = data taken at rising edge */
54 #define QMR_BAUD 0x00ff /* clock rate divider */
56 #define QIR_WCEF 0x0008 /* write collison */
57 #define QIR_ABRT 0x0004 /* abort */
58 #define QIR_SPIF 0x0001 /* finished */
59 #define QIR_SETUP 0xdd0f /* setup QIR for tranfer start */
60 #define QIR_SETUP_POLL 0xdc0d /* setup QIR for tranfer start */
62 #define QWR_CSIV 0x1000 /* 1 = active low chip selects */
64 #define QDLYR_SPE 0x8000 /* initiates transfer when set */
65 #define QDLYR_QCD 0x7f00 /* start delay between CS and first clock */
66 #define QDLYR_DTL 0x00ff /* delay after CS release */
68 /* QCR: chip selects return to inactive, bits set in QMR[BITS],
69 * after delay set in QDLYR[DTL], pre-delay set in QDLYR[QCD] */
70 #define QCR_SETUP 0x7000
71 #define QCR_CONT 0x8000 /* 1=continuous CS after transfer */
72 #define QCR_SETUP8 0x3000 /* sets BITSE to 0 => eigth bits per transfer */
75 typedef struct qspi_dev
{
76 qspi_read_data read_data
;
77 u8 bits
; /* transfer size, number of bits to transfer for each entry */
78 u8 baud
; /* baud rate */
79 u8 qcd
; /* QSPILCK delay */
80 u8 dtl
; /* delay after transfer */
81 unsigned int qcr_cont
: 1; /* keep CS active throughout transfer */
82 unsigned int odd_mod
: 1; /* if length of buffer is a odd number, 16-bit transfers
83 are finalized with a 8-bit transfer */
84 unsigned int dsp_mod
: 1; /* transfers are bounded to 15/30 bytes
85 (= a multiple of 3 bytes = 1 word) */
86 unsigned int poll_mod
: 1; /* mode polling or interrupt */
87 unsigned int cpol
: 1; /* SPI clock polarity */
88 unsigned int cpha
: 1; /* SPI clock phase */
89 unsigned int dohie
: 1; /* data output high impedance enable */
93 #endif /* MCF_QSPI_H */