arch/sh/drivers/pci/pci-auto.c

   1 /*
   2  * PCI autoconfiguration library
   3  *
   4  * Author: Matt Porter <mporter@mvista.com>
   5  *
   6  * Copyright 2000, 2001 MontaVista Software Inc.
   7  * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
   8  * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 /*
  17  * Modified for MIPS by Jun Sun, jsun@mvista.com
  18  *
  19  * . Simplify the interface between pci_auto and the rest: a single function.
  20  * . Assign resources from low address to upper address.
  21  * . change most int to u32.
  22  *
  23  * Further modified to include it as mips generic code, ppopov@mvista.com.
  24  *
  25  * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
  26  * - Add a top_bus argument to the "early config" functions so that
  27  *   they can set a fake parent bus pointer to convince the underlying
  28  *   pci ops to use type 1 configuration for sub busses.
  29  * - Set bridge base and limit registers correctly.
  30  * - Align io and memory base properly before and after bridge setup.
  31  * - Don't fall through to pci_setup_bars for bridge.
  32  * - Reformat the debug output to look more like lspci's output.
  33  *
  34  * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
  35  *
  36  * 2003-08-05  Paul Mundt <lethal@linux-sh.org>
  37  * - Don't update the BAR values on systems that already have valid addresses
  38  *   and don't want these updated for whatever reason, by way of a new config
  39  *   option check. However, we still read in the old BAR values so that they
  40  *   can still be reported through the debug output.
  41  */
  42
  43 #include <linux/kernel.h>
  44 #include <linux/init.h>
  45 #include <linux/types.h>
  46 #include <linux/pci.h>
  47
  48 #define DEBUG
  49 #ifdef  DEBUG
  50 #define DBG(x...)       printk(x)
  51 #else
  52 #define DBG(x...)
  53 #endif
  54
  55 /*
  56  * These functions are used early on before PCI scanning is done
  57  * and all of the pci_dev and pci_bus structures have been created.
  58  */
  59 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
  60         int top_bus, int busnr, int devfn)
  61 {
  62         static struct pci_dev dev;
  63         static struct pci_bus bus;
  64
  65         dev.bus = &bus;
  66         dev.sysdata = hose;
  67         dev.devfn = devfn;
  68         bus.number = busnr;
  69         bus.ops = hose->pci_ops;
  70
  71         if(busnr != top_bus)
  72                 /* Fake a parent bus structure. */
  73                 bus.parent = &bus;
  74         else
  75                 bus.parent = NULL;
  76
  77         return &dev;
  78 }
  79
  80 #define EARLY_PCI_OP(rw, size, type)                                    \
  81 int early_##rw##_config_##size(struct pci_channel *hose,                \
  82         int top_bus, int bus, int devfn, int offset, type value)        \
  83 {                                                                       \
  84         return pci_##rw##_config_##size(                                \
  85                 fake_pci_dev(hose, top_bus, bus, devfn),                \
  86                 offset, value);                                         \
  87 }
  88
  89 EARLY_PCI_OP(read, byte, u8 *)
  90 EARLY_PCI_OP(read, word, u16 *)
  91 EARLY_PCI_OP(read, dword, u32 *)
  92 EARLY_PCI_OP(write, byte, u8)
  93 EARLY_PCI_OP(write, word, u16)
  94 EARLY_PCI_OP(write, dword, u32)
  95
  96 static struct resource *io_resource_inuse;
  97 static struct resource *mem_resource_inuse;
  98
  99 static u32 pciauto_lower_iospc;
 100 static u32 pciauto_upper_iospc;
 101
 102 static u32 pciauto_lower_memspc;
 103 static u32 pciauto_upper_memspc;
 104
 105 static void __init
 106 pciauto_setup_bars(struct pci_channel *hose,
 107                    int top_bus,
 108                    int current_bus,
 109                    int pci_devfn,
 110                    int bar_limit)
 111 {
 112         u32 bar_response, bar_size, bar_value;
 113         u32 bar, addr_mask, bar_nr = 0;
 114         u32 * upper_limit;
 115         u32 * lower_limit;
 116         int found_mem64 = 0;
 117
 118         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
 119                 u32 bar_addr;
 120
 121                 /* Read the old BAR value */
 122                 early_read_config_dword(hose, top_bus,
 123                                         current_bus,
 124                                         pci_devfn,
 125                                         bar,
 126                                         &bar_addr);
 127
 128                 /* Tickle the BAR and get the response */
 129                 early_write_config_dword(hose, top_bus,
 130                                          current_bus,
 131                                          pci_devfn,
 132                                          bar,
 133                                          0xffffffff);
 134
 135                 early_read_config_dword(hose, top_bus,
 136                                         current_bus,
 137                                         pci_devfn,
 138                                         bar,
 139                                         &bar_response);
 140
 141                 /*
 142                  * Write the old BAR value back out, only update the BAR
 143                  * if we implicitly want resources to be updated, which
 144                  * is done by the generic code further down. -- PFM.
 145                  */
 146                 early_write_config_dword(hose, top_bus,
 147                                          current_bus,
 148                                          pci_devfn,
 149                                          bar,
 150                                          bar_addr);
 151
 152                 /* If BAR is not implemented go to the next BAR */
 153                 if (!bar_response)
 154                         continue;
 155
 156                 /*
 157                  * Workaround for a BAR that doesn't use its upper word,
 158                  * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
 159                  * bdl <brad@ltc.com>
 160                  */
 161                 if (!(bar_response & 0xffff0000))
 162                         bar_response |= 0xffff0000;
 163
 164 retry:
 165                 /* Check the BAR type and set our address mask */
 166                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 167                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 168                         upper_limit = &pciauto_upper_iospc;
 169                         lower_limit = &pciauto_lower_iospc;
 170                         DBG("        I/O");
 171                 } else {
 172                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 173                             PCI_BASE_ADDRESS_MEM_TYPE_64)
 174                                 found_mem64 = 1;
 175
 176                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
 177                         upper_limit = &pciauto_upper_memspc;
 178                         lower_limit = &pciauto_lower_memspc;
 179                         DBG("        Mem");
 180                 }
 181
 182
 183                 /* Calculate requested size */
 184                 bar_size = ~(bar_response & addr_mask) + 1;
 185
 186                 /* Allocate a base address */
 187                 bar_value = (*lower_limit + (bar_size - 1)) & ~(bar_size - 1);
 188
 189                 /* some combos can wrap,  check for this */
 190                 if (bar_value < *lower_limit)
 191                         continue;
 192
 193                 if ((bar_value + bar_size) > *upper_limit) {
 194                         if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 195                                 if (io_resource_inuse->child) {
 196                                         io_resource_inuse =
 197                                                 io_resource_inuse->child;
 198                                         pciauto_lower_iospc =
 199                                                 io_resource_inuse->start;
 200                                         pciauto_upper_iospc =
 201                                                 io_resource_inuse->end + 1;
 202                                         goto retry;
 203                                 }
 204
 205                         } else {
 206                                 if (mem_resource_inuse->child) {
 207                                         mem_resource_inuse =
 208                                                 mem_resource_inuse->child;
 209                                         pciauto_lower_memspc =
 210                                                 mem_resource_inuse->start;
 211                                         pciauto_upper_memspc =
 212                                                 mem_resource_inuse->end + 1;
 213                                         goto retry;
 214                                 }
 215                         }
 216                         DBG(" unavailable -- skipping, value %x size %x\n",
 217                                         bar_value, bar_size);
 218                         continue;
 219                 }
 220
 221 #ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
 222                 /* Write it out and update our limit */
 223                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 224                                          bar, bar_value);
 225 #endif
 226
 227                 *lower_limit = bar_value + bar_size;
 228
 229                 /*
 230                  * If we are a 64-bit decoder then increment to the
 231                  * upper 32 bits of the bar and force it to locate
 232                  * in the lower 4GB of memory.
 233                  */
 234                 if (found_mem64) {
 235                         bar += 4;
 236                         early_write_config_dword(hose, top_bus,
 237                                                  current_bus,
 238                                                  pci_devfn,
 239                                                  bar,
 240                                                  0x00000000);
 241                 }
 242
 243                 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 244
 245                 bar_nr++;
 246         }
 247
 248 }
 249
 250 static void __init
 251 pciauto_prescan_setup_bridge(struct pci_channel *hose,
 252                              int top_bus,
 253                              int current_bus,
 254                              int pci_devfn,
 255                              int sub_bus)
 256 {
 257         /* Configure bus number registers */
 258         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 259                                 PCI_PRIMARY_BUS, current_bus);
 260         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 261                                 PCI_SECONDARY_BUS, sub_bus + 1);
 262         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 263                                 PCI_SUBORDINATE_BUS, 0xff);
 264
 265         /* Align memory and I/O to 1MB and 4KB boundaries. */
 266         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 267                 & ~(0x100000 - 1);
 268         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 269                 & ~(0x1000 - 1);
 270
 271         /* Set base (lower limit) of address range behind bridge. */
 272         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 273                 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
 274         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 275                 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
 276         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 277                 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 278
 279         /* We don't support prefetchable memory for now, so disable */
 280         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 281                                 PCI_PREF_MEMORY_BASE, 0);
 282         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 283                                 PCI_PREF_MEMORY_LIMIT, 0);
 284 }
 285
 286 static void __init
 287 pciauto_postscan_setup_bridge(struct pci_channel *hose,
 288                               int top_bus,
 289                               int current_bus,
 290                               int pci_devfn,
 291                               int sub_bus)
 292 {
 293         u32 temp;
 294
 295         /*
 296          * [jsun] we always bump up baselines a little, so that if there
 297          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 298          * spaces.
 299          */
 300         pciauto_lower_memspc += 1;
 301         pciauto_lower_iospc += 1;
 302
 303         /* Configure bus number registers */
 304         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 305                                 PCI_SUBORDINATE_BUS, sub_bus);
 306
 307         /* Set upper limit of address range behind bridge. */
 308         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 309                 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
 310         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 311                 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
 312         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 313                 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
 314
 315         /* Align memory and I/O to 1MB and 4KB boundaries. */
 316         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 317                 & ~(0x100000 - 1);
 318         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 319                 & ~(0x1000 - 1);
 320
 321         /* Enable memory and I/O accesses, enable bus master */
 322         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 323                 PCI_COMMAND, &temp);
 324         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 325                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 326                 | PCI_COMMAND_MASTER);
 327 }
 328
 329 static void __init
 330 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
 331                         int top_bus,
 332                         int current_bus,
 333                         int pci_devfn,
 334                         int sub_bus)
 335 {
 336         /* Configure bus number registers */
 337         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 338                                 PCI_PRIMARY_BUS, current_bus);
 339         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 340                                 PCI_SECONDARY_BUS, sub_bus + 1);
 341         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 342                                 PCI_SUBORDINATE_BUS, 0xff);
 343
 344         /* Align memory and I/O to 4KB and 4 byte boundaries. */
 345         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 346                 & ~(0x1000 - 1);
 347         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 348                 & ~(0x4 - 1);
 349
 350         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 351                 PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
 352         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 353                 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
 354 }
 355
 356 static void __init
 357 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
 358                         int top_bus,
 359                         int current_bus,
 360                         int pci_devfn,
 361                         int sub_bus)
 362 {
 363         u32 temp;
 364
 365         /*
 366          * [jsun] we always bump up baselines a little, so that if there
 367          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 368          * spaces.
 369          */
 370         pciauto_lower_memspc += 1;
 371         pciauto_lower_iospc += 1;
 372
 373         /*
 374          * Configure subordinate bus number.  The PCI subsystem
 375          * bus scan will renumber buses (reserving three additional
 376          * for this PCI<->CardBus bridge for the case where a CardBus
 377          * adapter contains a P2P or CB2CB bridge.
 378          */
 379
 380         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 381                                 PCI_SUBORDINATE_BUS, sub_bus);
 382
 383         /*
 384          * Reserve an additional 4MB for mem space and 16KB for
 385          * I/O space.  This should cover any additional space
 386          * requirement of unusual CardBus devices with
 387          * additional bridges that can consume more address space.
 388          *
 389          * Although pcmcia-cs currently will reprogram bridge
 390          * windows, the goal is to add an option to leave them
 391          * alone and use the bridge window ranges as the regions
 392          * that are searched for free resources upon hot-insertion
 393          * of a device.  This will allow a PCI<->CardBus bridge
 394          * configured by this routine to happily live behind a
 395          * P2P bridge in a system.
 396          */
 397         /* Align memory and I/O to 4KB and 4 byte boundaries. */
 398         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 399                 & ~(0x1000 - 1);
 400         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 401                 & ~(0x4 - 1);
 402         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 403         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 404                 PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
 405         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 406                 PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
 407
 408         /* Enable memory and I/O accesses, enable bus master */
 409         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 410                 PCI_COMMAND, &temp);
 411         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 412                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 413                 PCI_COMMAND_MASTER);
 414 }
 415
 416 #define PCIAUTO_IDE_MODE_MASK           0x05
 417
 418 static int __init
 419 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 420 {
 421         int sub_bus;
 422         u32 pci_devfn, pci_class, cmdstat, found_multi=0;
 423         unsigned short vid, did;
 424         unsigned char header_type;
 425         int devfn_start = 0;
 426         int devfn_stop = 0xff;
 427
 428         sub_bus = current_bus;
 429
 430         if (hose->first_devfn)
 431                 devfn_start = hose->first_devfn;
 432         if (hose->last_devfn)
 433                 devfn_stop = hose->last_devfn;
 434
 435         for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
 436
 437                 if (PCI_FUNC(pci_devfn) && !found_multi)
 438                         continue;
 439
 440                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 441                                        PCI_VENDOR_ID, &vid);
 442
 443                 if (vid == 0xffff) continue;
 444
 445                 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 446                                        PCI_HEADER_TYPE, &header_type);
 447
 448                 if (!PCI_FUNC(pci_devfn))
 449                         found_multi = header_type & 0x80;
 450
 451                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 452                                        PCI_DEVICE_ID, &did);
 453
 454                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 455                                         PCI_CLASS_REVISION, &pci_class);
 456
 457                 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
 458                         current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
 459                         pci_class >> 16, vid, did);
 460                 if (pci_class & 0xff)
 461                         DBG(" (rev %.2x)", pci_class & 0xff);
 462                 DBG("\n");
 463
 464                 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 465                         DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 466                                 current_bus, sub_bus + 1);
 467                         pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 468                                                      pci_devfn, sub_bus);
 469                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 470                                 sub_bus + 1,
 471                                 pciauto_lower_iospc, pciauto_lower_memspc);
 472                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 473                         DBG("Back to bus %.2x\n", current_bus);
 474                         pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 475                                                         pci_devfn, sub_bus);
 476                         continue;
 477                 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
 478                         DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
 479                                 current_bus, sub_bus + 1);
 480                         DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
 481                         /* Place CardBus Socket/ExCA registers */
 482                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
 483
 484                         pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
 485                                         current_bus, pci_devfn, sub_bus);
 486
 487                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 488                                 sub_bus + 1,
 489                                 pciauto_lower_iospc, pciauto_lower_memspc);
 490                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 491                         DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
 492                         pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
 493                                         current_bus, pci_devfn, sub_bus);
 494                         continue;
 495                 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 496
 497                         unsigned char prg_iface;
 498
 499                         early_read_config_byte(hose, top_bus, current_bus,
 500                                 pci_devfn, PCI_CLASS_PROG, &prg_iface);
 501                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 502                                 DBG("Skipping legacy mode IDE controller\n");
 503                                 continue;
 504                         }
 505                 }
 506
 507                 /*
 508                  * Found a peripheral, enable some standard
 509                  * settings
 510                  */
 511                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 512                                         PCI_COMMAND, &cmdstat);
 513                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 514                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 515                                          PCI_COMMAND_MEMORY |
 516                                          PCI_COMMAND_MASTER);
 517 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 518                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 519                                         PCI_LATENCY_TIMER, 0x80);
 520 #endif
 521
 522                 /* Allocate PCI I/O and/or memory space */
 523                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
 524         }
 525         return sub_bus;
 526 }
 527
 528 int __init
 529 pciauto_assign_resources(int busno, struct pci_channel *hose)
 530 {
 531         /* setup resource limits */
 532         io_resource_inuse = hose->io_resource;
 533         mem_resource_inuse = hose->mem_resource;
 534
 535         pciauto_lower_iospc = io_resource_inuse->start;
 536         pciauto_upper_iospc = io_resource_inuse->end + 1;
 537         pciauto_lower_memspc = mem_resource_inuse->start;
 538         pciauto_upper_memspc = mem_resource_inuse->end + 1;
 539         DBG("Autoconfig PCI channel 0x%p\n", hose);
 540         DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
 541                 busno, pciauto_lower_iospc, pciauto_upper_iospc,
 542                 pciauto_lower_memspc, pciauto_upper_memspc);
 543
 544         return pciauto_bus_scan(hose, busno, busno);
 545 }