2 * head.S for Altera's Excalibur development board with nios processor
4 * (c) Vic Phillips, Microtronix Datacom Ltd., 2001
5 * (C) Copyright 2004 Microtronix Datacom Ltd
7 * Based on the following from the Excalibur sdk distribution:
8 * NA_MemoryMap.s, NR_JumpToStart.s, NR_Setup.s, NR_CWPManager.s
10 * This program is free software; you can redistribute it and/or modify it under
11 * the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 675
22 * Mass Ave, Cambridge, MA 02139, USA.
26 #include <asm/asm-offsets.h>
27 #include <asm/asm-macros.h>
30 #ifdef CONFIG_CRC_CHECK
31 /**********************************************/
32 /* Define where the CRC table lives in flash. */
33 /* The __CRC_Sector_Size is the flash sector */
34 /* size for the address range. */
35 /**********************************************/
37 GEQU __CRC_Table_Begin,(na_flash)+0x4000 /* Second sector of main board flash */
38 GEQU __CRC_Sector_Size,0x2000
42 * This global variable is used as an extension to the nios'
43 * STATUS register to emulate a user/supervisor mode.
48 .global status_extension
52 .global _current_thread
56 * Input(s): passed from u-boot
57 * r4 - Optional pointer to a board information structure.
58 * r5 - Optional pointer to the physical starting address of the init RAM
60 * r6 - Optional pointer to the physical ending address of the init RAM
62 * r7 - Optional pointer to the physical starting address of any kernel
63 * command-line parameters.
67 * First executable code - detected and jumped to by the ROM bootstrap
68 * if the code resides in flash (looks for "Nios" at offset 0x0c from
69 * the potential executable image).
74 wrctl status,r0 /* Disable interrupts */
76 /* Flush all cache lines within the instruction cache */
78 movia r1,NIOS2_ICACHE_SIZE
79 movui r2,NIOS2_ICACHE_LINE_SIZE
87 /* This is the default location for the exception
88 * handler. Code in jump to our handler
95 * After flushing the instruction cache, we must flush the data
99 movia r1,NIOS2_DCACHE_SIZE
100 movi r2,NIOS2_DCACHE_LINE_SIZE
108 #ifdef CONFIG_BREAK_ON_START
110 #endif //CONFIG_BREAK_ON_START
111 nextpc r1 /* Find out where we are */
114 beq r1,r2,finish_move /* We are running in RAM done */
115 addi r1,r1,(_start - chkadr) /* Source */
116 movia r2,_start /* Destination */
117 movia r3,__data_end /* End of copy */
119 loop_move: // r1: src, r2: dest, r3: last dest
120 ldw r8,0(r1) // load a word from [r1]
121 stw r8,0(r2) // stort a word to dest [r2]
122 flushd 0(r2) // Flush cache for safty
123 addi r1,r1,4 // inc the src addr
124 addi r2,r2,4 // inc the dest addr
127 movia r1,finish_move // VMA(_start)->l1
128 jmp r1 // jmp to _start
132 //------------------------------------
133 // Disable interrupts on known devices
136 #ifdef NA_ENET_RESET_ASM
137 movia r1,NA_ENET_RESET_ASM // ethernet reset address
138 stwio r0,0(r1) // reset
140 #ifdef NA_ENET_RESET_N_ASM
141 movia r1,NA_ENET_RESET_N_ASM // ethernet reset address
142 stwio r0,0(r1) // reset
144 nop // give it some time
150 movia r1,NA_TIMER0_ASM // get timer address
151 stwio r0,NP_TIMERCONTROL_ASM(r1) // clear interrupt enable
152 stwio r0,NP_TIMERSTATUS_ASM(r1) // clear interrupt condition
155 movia r1,NA_UART0_ASM
156 stwio r0,NP_UARTCONTROL_ASM(r1) // clear interrupt enable
157 stwio r0,NP_UARTSTATUS_ASM(r1) // clear interrupt status
160 movia r1,NA_UART1_ASM
161 stwio r0,NP_UARTCONTROL_ASM(r1) // clear interrupt enable
162 stwio r0,NP_UARTSTATUS_ASM(r1) // clear interrupt status
165 movia r1,NA_UART2_ASM
166 stwio r0,NP_UARTCONTROL_ASM(r1) // clear interrupt enable
167 stwio r0,NP_UARTSTATUS_ASM(r1) // clear interrupt status
170 movia r1,NA_UART3_ASM
171 stwio r0,NP_UARTCONTROL_ASM(r1) // clear interrupt enable
172 stwio r0,NP_UARTSTATUS_ASM(r1) // clear interrupt status
174 #ifdef NA_IDE_INTERFACE_ASM
175 movia r1,NA_IDE_INTERFACE_ASM // ATA reset
176 stwio r0,0(r1) // write to control register
179 #ifdef NA_ENET_RESET_ASM
180 movia r1,NA_ENET_RESET_ASM // ethernet reset address
184 #ifdef NA_ENET_RESET_N_ASM
185 movia r1,NA_ENET_RESET_N_ASM // ethernet reset address
190 wrctl ienable,r0 // Mask off all possible interrupts
192 //------------------------------------------------------
193 // Zero out the .bss segment (uninitialized common data)
195 movia r2,__bss_start // presume nothing is between
196 movia r1,_end // the .bss and _end.
202 //------------------------------------------------------
203 // Call main() with interrupts disabled
205 movia r1,status_extension // get the STATUS extension address
206 movi r2,PS_S_ASM // set initial mode = supervisor
209 movia r1,init_thread_union // set stack at top of the task union
210 addi sp,r1,THREAD_SIZE_ASM
211 movia r2,_current_thread // Remember current thread
214 movia r1,nios2_boot_init // save args r4-r7 passed from u-boot
217 movia r1,main // call main as a subroutine
220 //------------------------------------------------------------------
221 // If we return from main, break to the oci debugger and buggered we are
225 /* End of startup code */