arch/nios2nommu/drivers/pci/pci-auto.c

   1 /*
   2  * PCI autoconfiguration library
   3  *
   4  * Author: Matt Porter <mporter@mvista.com>
   5  *
   6  * Copyright 2000, 2001 MontaVista Software Inc.
   7  * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
   8  * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 /*
  17  * Modified for MIPS by Jun Sun, jsun@mvista.com
  18  *
  19  * . Simplify the interface between pci_auto and the rest: a single function.
  20  * . Assign resources from low address to upper address.
  21  * . change most int to u32.
  22  *
  23  * Further modified to include it as mips generic code, ppopov@mvista.com.
  24  *
  25  * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
  26  * - Add a top_bus argument to the "early config" functions so that
  27  *   they can set a fake parent bus pointer to convince the underlying
  28  *   pci ops to use type 1 configuration for sub busses.
  29  * - Set bridge base and limit registers correctly.
  30  * - Align io and memory base properly before and after bridge setup.
  31  * - Don't fall through to pci_setup_bars for bridge.
  32  * - Reformat the debug output to look more like lspci's output.
  33  *
  34  * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
  35  *
  36  * 2003-08-05  Paul Mundt <lethal@linux-sh.org>
  37  * - Don't update the BAR values on systems that already have valid addresses
  38  *   and don't want these updated for whatever reason, by way of a new config
  39  *   option check. However, we still read in the old BAR values so that they
  40  *   can still be reported through the debug output.
  41  */
  42
  43 #include <linux/kernel.h>
  44 #include <linux/init.h>
  45 #include <linux/types.h>
  46 #include <linux/pci.h>
  47
  48 #undef  DEBUG
  49 #define DEBUG       // you can remove debug message here
  50
  51 #ifdef  DEBUG
  52 #define DBG(x...)       printk(x)
  53 #else
  54 #define DBG(x...)
  55 #endif
  56
  57 /*
  58  * These functions are used early on before PCI scanning is done
  59  * and all of the pci_dev and pci_bus structures have been created.
  60  */
  61 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
  62         int top_bus, int busnr, int devfn)
  63 {
  64         static struct pci_dev dev;
  65         static struct pci_bus bus;
  66
  67         dev.bus = &bus;
  68         dev.sysdata = hose;
  69         dev.devfn = devfn;
  70         bus.number = busnr;
  71         bus.ops = hose->pci_ops;
  72
  73         if(busnr != top_bus)
  74                 /* Fake a parent bus structure. */
  75                 bus.parent = &bus;
  76         else
  77                 bus.parent = NULL;
  78
  79         return &dev;
  80 }
  81
  82 #define EARLY_PCI_OP(rw, size, type)                                    \
  83 int early_##rw##_config_##size(struct pci_channel *hose,                \
  84         int top_bus, int bus, int devfn, int offset, type value)        \
  85 {                                                                       \
  86         return pci_##rw##_config_##size(                                \
  87                 fake_pci_dev(hose, top_bus, bus, devfn),                \
  88                 offset, value);                                         \
  89 }
  90
  91 EARLY_PCI_OP(read, byte, u8 *)
  92 EARLY_PCI_OP(read, word, u16 *)
  93 EARLY_PCI_OP(read, dword, u32 *)
  94 EARLY_PCI_OP(write, byte, u8)
  95 EARLY_PCI_OP(write, word, u16)
  96 EARLY_PCI_OP(write, dword, u32)
  97
  98 static struct resource *io_resource_inuse;
  99 static struct resource *mem_resource_inuse;
 100
 101 static u32 pciauto_lower_iospc;
 102 static u32 pciauto_upper_iospc;
 103
 104 static u32 pciauto_lower_memspc;
 105 static u32 pciauto_upper_memspc;
 106
 107 static void __init
 108 pciauto_setup_bars(struct pci_channel *hose,
 109                    int top_bus,
 110                    int current_bus,
 111                    int pci_devfn,
 112                    int bar_limit)
 113 {
 114         u32 bar_response, bar_size, bar_value;
 115         u32 bar, addr_mask, bar_nr = 0;
 116         u32 * upper_limit;
 117         u32 * lower_limit;
 118         int found_mem64 = 0;
 119
 120         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
 121 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 122                 u32 bar_addr;
 123
 124                 /* Read the old BAR value */
 125                 early_read_config_dword(hose, top_bus,
 126                                         current_bus,
 127                                         pci_devfn,
 128                                         bar,
 129                                         &bar_addr);
 130 #endif
 131
 132                 /* Tickle the BAR and get the response */
 133                 early_write_config_dword(hose, top_bus,
 134                                          current_bus,
 135                                          pci_devfn,
 136                                          bar,
 137                                          0xffffffff);
 138
 139                 early_read_config_dword(hose, top_bus,
 140                                         current_bus,
 141                                         pci_devfn,
 142                                         bar,
 143                                         &bar_response);
 144
 145 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 146                 /*
 147                  * Write the old BAR value back out, only update the BAR
 148                  * if we implicitly want resources to be updated, which
 149                  * is done by the generic code further down. -- PFM.
 150                  */
 151                 early_write_config_dword(hose, top_bus,
 152                                          current_bus,
 153                                          pci_devfn,
 154                                          bar,
 155                                          bar_addr);
 156 #endif
 157
 158                 /* If BAR is not implemented go to the next BAR */
 159                 if (!bar_response)
 160                         continue;
 161
 162                 /*
 163                  * Workaround for a BAR that doesn't use its upper word,
 164                  * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
 165                  * bdl <brad@ltc.com>
 166                  */
 167                 if (!(bar_response & 0xffff0000))
 168                         bar_response |= 0xffff0000;
 169
 170 retry:
 171                 /* Check the BAR type and set our address mask */
 172                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 173                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 174                         upper_limit = &pciauto_upper_iospc;
 175                         lower_limit = &pciauto_lower_iospc;
 176                         DBG("        I/O");
 177                 } else {
 178                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 179                             PCI_BASE_ADDRESS_MEM_TYPE_64)
 180                                 found_mem64 = 1;
 181
 182                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
 183                         upper_limit = &pciauto_upper_memspc;
 184                         lower_limit = &pciauto_lower_memspc;
 185                         DBG("        Mem");
 186                 }
 187
 188
 189                 /* Calculate requested size */
 190                 bar_size = ~(bar_response & addr_mask) + 1;
 191
 192                 /* Allocate a base address */
 193                 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
 194
 195                 if ((bar_value + bar_size) > *upper_limit) {
 196                         if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 197                                 if (io_resource_inuse->child) {
 198                                         io_resource_inuse =
 199                                                 io_resource_inuse->child;
 200                                         pciauto_lower_iospc =
 201                                                 io_resource_inuse->start;
 202                                         pciauto_upper_iospc =
 203                                                 io_resource_inuse->end + 1;
 204                                         goto retry;
 205                                 }
 206
 207                         } else {
 208                                 if (mem_resource_inuse->child) {
 209                                         mem_resource_inuse =
 210                                                 mem_resource_inuse->child;
 211                                         pciauto_lower_memspc =
 212                                                 mem_resource_inuse->start;
 213                                         pciauto_upper_memspc =
 214                                                 mem_resource_inuse->end + 1;
 215                                         goto retry;
 216                                 }
 217                         }
 218                         DBG(" unavailable -- skipping, value %x size %x\n",
 219                                         bar_value, bar_size);
 220                         continue;
 221                 }
 222
 223 #ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
 224                 /* Write it out and update our limit */
 225                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 226                                          bar, bar_value);
 227 #endif
 228
 229                 *lower_limit = bar_value + bar_size;
 230
 231                 /*
 232                  * If we are a 64-bit decoder then increment to the
 233                  * upper 32 bits of the bar and force it to locate
 234                  * in the lower 4GB of memory.
 235                  */
 236                 if (found_mem64) {
 237                         bar += 4;
 238                         early_write_config_dword(hose, top_bus,
 239                                                  current_bus,
 240                                                  pci_devfn,
 241                                                  bar,
 242                                                  0x00000000);
 243                 }
 244
 245                 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 246
 247                 bar_nr++;
 248         }
 249
 250 }
 251
 252 static void __init
 253 pciauto_prescan_setup_bridge(struct pci_channel *hose,
 254                              int top_bus,
 255                              int current_bus,
 256                              int pci_devfn,
 257                              int sub_bus)
 258 {
 259         /* Configure bus number registers */
 260         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 261                                 PCI_PRIMARY_BUS, current_bus);
 262         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 263                                 PCI_SECONDARY_BUS, sub_bus + 1);
 264         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 265                                 PCI_SUBORDINATE_BUS, 0xff);
 266
 267         /* Align memory and I/O to 1MB and 4KB boundaries. */
 268         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 269                 & ~(0x100000 - 1);
 270         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 271                 & ~(0x1000 - 1);
 272
 273         /* Set base (lower limit) of address range behind bridge. */
 274         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 275                 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
 276         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 277                 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
 278         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 279                 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 280
 281         /* We don't support prefetchable memory for now, so disable */
 282         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 283                                 PCI_PREF_MEMORY_BASE, 0);
 284         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 285                                 PCI_PREF_MEMORY_LIMIT, 0);
 286 }
 287
 288 static void __init
 289 pciauto_postscan_setup_bridge(struct pci_channel *hose,
 290                               int top_bus,
 291                               int current_bus,
 292                               int pci_devfn,
 293                               int sub_bus)
 294 {
 295         u32 temp;
 296
 297         /*
 298          * [jsun] we always bump up baselines a little, so that if there
 299          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 300          * spaces.
 301          */
 302         pciauto_lower_memspc += 1;
 303         pciauto_lower_iospc += 1;
 304
 305         /* Configure bus number registers */
 306         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 307                                 PCI_SUBORDINATE_BUS, sub_bus);
 308
 309         /* Set upper limit of address range behind bridge. */
 310         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 311                 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
 312         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 313                 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
 314         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 315                 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
 316
 317         /* Align memory and I/O to 1MB and 4KB boundaries. */
 318         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 319                 & ~(0x100000 - 1);
 320         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 321                 & ~(0x1000 - 1);
 322
 323         /* Enable memory and I/O accesses, enable bus master */
 324         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 325                 PCI_COMMAND, &temp);
 326         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 327                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 328                 | PCI_COMMAND_MASTER);
 329 }
 330
 331 static void __init
 332 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
 333                         int top_bus,
 334                         int current_bus,
 335                         int pci_devfn,
 336                         int sub_bus)
 337 {
 338         /* Configure bus number registers */
 339         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 340                                 PCI_PRIMARY_BUS, current_bus);
 341         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 342                                 PCI_SECONDARY_BUS, sub_bus + 1);
 343         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 344                                 PCI_SUBORDINATE_BUS, 0xff);
 345
 346         /* Align memory and I/O to 4KB and 4 byte boundaries. */
 347         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 348                 & ~(0x1000 - 1);
 349         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 350                 & ~(0x4 - 1);
 351
 352         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 353                 PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
 354         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 355                 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
 356 }
 357
 358 static void __init
 359 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
 360                         int top_bus,
 361                         int current_bus,
 362                         int pci_devfn,
 363                         int sub_bus)
 364 {
 365         u32 temp;
 366
 367 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 368         /*
 369          * [jsun] we always bump up baselines a little, so that if there
 370          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 371          * spaces.
 372          */
 373         pciauto_lower_memspc += 1;
 374         pciauto_lower_iospc += 1;
 375 #endif
 376
 377         /*
 378          * Configure subordinate bus number.  The PCI subsystem
 379          * bus scan will renumber buses (reserving three additional
 380          * for this PCI<->CardBus bridge for the case where a CardBus
 381          * adapter contains a P2P or CB2CB bridge.
 382          */
 383
 384         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 385                                 PCI_SUBORDINATE_BUS, sub_bus);
 386
 387         /*
 388          * Reserve an additional 4MB for mem space and 16KB for
 389          * I/O space.  This should cover any additional space
 390          * requirement of unusual CardBus devices with
 391          * additional bridges that can consume more address space.
 392          *
 393          * Although pcmcia-cs currently will reprogram bridge
 394          * windows, the goal is to add an option to leave them
 395          * alone and use the bridge window ranges as the regions
 396          * that are searched for free resources upon hot-insertion
 397          * of a device.  This will allow a PCI<->CardBus bridge
 398          * configured by this routine to happily live behind a
 399          * P2P bridge in a system.
 400          */
 401 #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
 402         pciauto_lower_memspc += 0x00400000;
 403         pciauto_lower_iospc += 0x00004000;
 404 #endif
 405
 406         /* Align memory and I/O to 4KB and 4 byte boundaries. */
 407         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 408                 & ~(0x1000 - 1);
 409         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 410                 & ~(0x4 - 1);
 411         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 412         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 413                 PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
 414         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 415                 PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
 416
 417         /* Enable memory and I/O accesses, enable bus master */
 418         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 419                 PCI_COMMAND, &temp);
 420         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 421                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 422                 PCI_COMMAND_MASTER);
 423 }
 424
 425 #define PCIAUTO_IDE_MODE_MASK           0x05
 426
 427 static int __init
 428 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 429 {
 430         int sub_bus;
 431         u32 pci_devfn, pci_class, cmdstat, found_multi=0;
 432         unsigned short vid, did;
 433         unsigned char header_type;
 434         int devfn_start = 0;
 435         int devfn_stop = 0xff;
 436
 437         sub_bus = current_bus;
 438
 439         if (hose->first_devfn)
 440                 devfn_start = hose->first_devfn;
 441         if (hose->last_devfn)
 442                 devfn_stop = hose->last_devfn;
 443
 444         for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
 445
 446                 if (PCI_FUNC(pci_devfn) && !found_multi)
 447                         continue;
 448
 449                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 450                                        PCI_VENDOR_ID, &vid);
 451
 452                 if (vid == 0xffff) continue;
 453
 454                 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 455                                        PCI_HEADER_TYPE, &header_type);
 456
 457                 if (!PCI_FUNC(pci_devfn))
 458                         found_multi = header_type & 0x80;
 459
 460                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 461                                        PCI_DEVICE_ID, &did);
 462
 463                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 464                                         PCI_CLASS_REVISION, &pci_class);
 465
 466                 if ((pci_class & 0xff000000)==0) continue;   // devices before pci 2.0
 467
 468                 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
 469                         current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
 470                         pci_class >> 16, vid, did);
 471                 if (pci_class & 0xff)
 472                         DBG(" (rev %.2x)", pci_class & 0xff);
 473                 DBG("\n");
 474
 475                 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 476                         DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 477                                 current_bus, sub_bus + 1);
 478 #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
 479                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1);
 480 #endif
 481                         pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 482                                                      pci_devfn, sub_bus);
 483                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 484                                 sub_bus + 1,
 485                                 pciauto_lower_iospc, pciauto_lower_memspc);
 486                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 487                         DBG("Back to bus %.2x\n", current_bus);
 488                         pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 489                                                         pci_devfn, sub_bus);
 490                         continue;
 491                 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
 492                         DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
 493                                 current_bus, sub_bus + 1);
 494                         DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
 495                         /* Place CardBus Socket/ExCA registers */
 496                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
 497
 498                         pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
 499                                         current_bus, pci_devfn, sub_bus);
 500
 501                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 502                                 sub_bus + 1,
 503                                 pciauto_lower_iospc, pciauto_lower_memspc);
 504                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 505                         DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
 506                         pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
 507                                         current_bus, pci_devfn, sub_bus);
 508                         continue;
 509                 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 510
 511                         unsigned char prg_iface;
 512
 513                         early_read_config_byte(hose, top_bus, current_bus,
 514                                 pci_devfn, PCI_CLASS_PROG, &prg_iface);
 515                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 516                                 DBG("Skipping legacy mode IDE controller\n");
 517                                 continue;
 518                         }
 519                 }
 520
 521                 /*
 522                  * Found a peripheral, enable some standard
 523                  * settings
 524                  */
 525                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 526                                         PCI_COMMAND, &cmdstat);
 527                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 528                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 529                                          PCI_COMMAND_MEMORY |
 530                                          PCI_COMMAND_MASTER);
 531 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 532                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 533                                         PCI_LATENCY_TIMER, 0x80);
 534 #endif
 535
 536                 /* Allocate PCI I/O and/or memory space */
 537                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
 538         }
 539         return sub_bus;
 540 }
 541
 542 int __init
 543 pciauto_assign_resources(int busno, struct pci_channel *hose)
 544 {
 545         /* setup resource limits */
 546         io_resource_inuse = hose->io_resource;
 547         mem_resource_inuse = hose->mem_resource;
 548
 549         pciauto_lower_iospc = io_resource_inuse->start;
 550         pciauto_upper_iospc = io_resource_inuse->end + 1;
 551         pciauto_lower_memspc = mem_resource_inuse->start;
 552         pciauto_upper_memspc = mem_resource_inuse->end + 1;
 553         DBG("Autoconfig PCI channel 0x%p\n", hose);
 554         DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
 555                 busno, pciauto_lower_iospc, pciauto_upper_iospc,
 556                 pciauto_lower_memspc, pciauto_upper_memspc);
 557
 558         return pciauto_bus_scan(hose, busno, busno);
 559 }