| blob | 4f0d9361d21aad6edb639693a5eefbb03eaa8139 |
1 /*
2 * linux/arch/arm/mm/proc-xsc3.S
3 *
4 * Original Author: Matthew Gilbert
5 * Current Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright 2004 (C) Intel Corp.
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is an
15 * extension to Intel's original XScale core that adds the following
16 * features:
17 *
18 * - ARMv6 Supersections
19 * - Low Locality Reference pages (replaces mini-cache)
20 * - 36-bit addressing
21 * - L2 cache
22 * - Cache-coherency if chipset supports it
23 *
24 * Based on orignal XScale code by Nicolas Pitre
25 */
27 #include <linux/linkage.h>
28 #include <linux/init.h>
29 #include <asm/assembler.h>
30 #include <asm/procinfo.h>
31 #include <asm/hardware.h>
32 #include <asm/pgtable.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/page.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
38 #ifndef CONFIG_MMU
39 #error "need to be revisited"
40 #endif
41 /*
42 * This is the maximum size of an area which will be flushed. If the
43 * area is larger than this, then we flush the whole cache.
44 */
45 #define MAX_AREA_SIZE 32768
47 /*
48 * The cache line size of the I and D cache.
49 */
50 #define CACHELINESIZE 32
52 /*
53 * The size of the data cache.
54 */
55 #define CACHESIZE 32768
57 /*
58 * Run with L2 enabled.
59 */
60 #define L2_CACHE_ENABLE 1
62 /*
63 * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
64 */
65 #define BTB_ENABLE 0
67 /*
68 * This macro is used to wait for a CP15 write and is needed
69 * when we have to ensure that the last operation to the co-pro
70 * was completed before continuing with operation.
71 */
72 .macro cpwait_ret, lr, rd
73 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
74 sub pc, \lr, \rd, LSR #32 @ wait for completion and
75 @ flush instruction pipeline
76 .endm
78 /*
79 * This macro cleans & invalidates the entire xsc3 dcache by set & way.
80 */
82 .macro clean_d_cache rd, rs
83 mov \rd, #0x1f00
84 orr \rd, \rd, #0x00e0
85 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/inv set/way
86 adds \rd, \rd, #0x40000000
87 bcc 1b
88 subs \rd, \rd, #0x20
89 bpl 1b
90 .endm
92 .text
94 /*
95 * cpu_xsc3_proc_init()
96 *
97 * Nothing too exciting at the moment
98 */
99 ENTRY(cpu_xsc3_proc_init)
100 mov pc, lr
102 /*
103 * cpu_xsc3_proc_fin()
104 */
105 ENTRY(cpu_xsc3_proc_fin)
106 str lr, [sp, #-4]!
107 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
108 msr cpsr_c, r0
109 bl xsc3_flush_kern_cache_all @ clean caches
110 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
111 bic r0, r0, #0x1800 @ ...IZ...........
112 bic r0, r0, #0x0006 @ .............CA.
113 mcr p15, 0, r0, c1, c0, 0 @ disable caches
114 ldr pc, [sp], #4
116 /*
117 * cpu_xsc3_reset(loc)
118 *
119 * Perform a soft reset of the system. Put the CPU into the
120 * same state as it would be if it had been reset, and branch
121 * to what would be the reset vector.
122 *
123 * loc: location to jump to for soft reset
124 */
125 .align 5
126 ENTRY(cpu_xsc3_reset)
127 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
128 msr cpsr_c, r1 @ reset CPSR
129 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
130 bic r1, r1, #0x0086 @ ........B....CA.
131 bic r1, r1, #0x3900 @ ..VIZ..S........
132 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
133 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
134 bic r1, r1, #0x0001 @ ...............M
135 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
136 @ CAUTION: MMU turned off from this point. We count on the pipeline
137 @ already containing those two last instructions to survive.
138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
139 mov pc, r0
141 /*
142 * cpu_xsc3_do_idle()
143 *
144 * Cause the processor to idle
145 *
146 * For now we do nothing but go to idle mode for every case
147 *
148 * XScale supports clock switching, but using idle mode support
149 * allows external hardware to react to system state changes.
151 MMG: Come back to this one.
152 */
153 .align 5
155 ENTRY(cpu_xsc3_do_idle)
156 mov r0, #1
157 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
158 mov pc, lr
160 /* ================================= CACHE ================================ */
162 /*
163 * flush_user_cache_all()
164 *
165 * Invalidate all cache entries in a particular address
166 * space.
167 */
168 ENTRY(xsc3_flush_user_cache_all)
169 /* FALLTHROUGH */
171 /*
172 * flush_kern_cache_all()
173 *
174 * Clean and invalidate the entire cache.
175 */
176 ENTRY(xsc3_flush_kern_cache_all)
177 mov r2, #VM_EXEC
178 mov ip, #0
179 __flush_whole_cache:
180 clean_d_cache r0, r1
181 tst r2, #VM_EXEC
182 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
183 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
184 mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
185 mov pc, lr
187 /*
188 * flush_user_cache_range(start, end, vm_flags)
189 *
190 * Invalidate a range of cache entries in the specified
191 * address space.
192 *
193 * - start - start address (may not be aligned)
194 * - end - end address (exclusive, may not be aligned)
195 * - vma - vma_area_struct describing address space
196 */
197 .align 5
198 ENTRY(xsc3_flush_user_cache_range)
199 mov ip, #0
200 sub r3, r1, r0 @ calculate total size
201 cmp r3, #MAX_AREA_SIZE
202 bhs __flush_whole_cache
204 1: tst r2, #VM_EXEC
205 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
206 mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate D cache line
207 add r0, r0, #CACHELINESIZE
208 cmp r0, r1
209 blo 1b
210 tst r2, #VM_EXEC
211 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
212 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
213 mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
214 mov pc, lr
216 /*
217 * coherent_kern_range(start, end)
218 *
219 * Ensure coherency between the Icache and the Dcache in the
220 * region described by start. If you have non-snooping
221 * Harvard caches, you need to implement this function.
222 *
223 * - start - virtual start address
224 * - end - virtual end address
225 *
226 * Note: single I-cache line invalidation isn't used here since
227 * it also trashes the mini I-cache used by JTAG debuggers.
228 */
229 ENTRY(xsc3_coherent_kern_range)
230 /* FALLTHROUGH */
231 ENTRY(xsc3_coherent_user_range)
232 bic r0, r0, #CACHELINESIZE - 1
233 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
234 add r0, r0, #CACHELINESIZE
235 cmp r0, r1
236 blo 1b
237 mov r0, #0
238 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
239 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
240 mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
241 mov pc, lr
243 /*
244 * flush_kern_dcache_page(void *page)
245 *
246 * Ensure no D cache aliasing occurs, either with itself or
247 * the I cache
248 *
249 * - addr - page aligned address
250 */
251 ENTRY(xsc3_flush_kern_dcache_page)
252 add r1, r0, #PAGE_SZ
253 1: mcr p15, 0, r0, c7, c14, 1 @ Clean/Invalidate D Cache line
254 add r0, r0, #CACHELINESIZE
255 cmp r0, r1
256 blo 1b
257 mov r0, #0
258 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
259 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
260 mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
261 mov pc, lr
263 /*
264 * dma_inv_range(start, end)
265 *
266 * Invalidate (discard) the specified virtual address range.
267 * May not write back any entries. If 'start' or 'end'
268 * are not cache line aligned, those lines must be written
269 * back.
270 *
271 * - start - virtual start address
272 * - end - virtual end address
273 */
274 ENTRY(xsc3_dma_inv_range)
275 tst r0, #CACHELINESIZE - 1
276 bic r0, r0, #CACHELINESIZE - 1
277 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D entry
278 mcrne p15, 1, r0, c7, c11, 1 @ clean L2 D entry
279 tst r1, #CACHELINESIZE - 1
280 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D entry
281 mcrne p15, 1, r1, c7, c11, 1 @ clean L2 D entry
282 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D entry
283 mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
284 add r0, r0, #CACHELINESIZE
285 cmp r0, r1
286 blo 1b
287 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
288 mov pc, lr
290 /*
291 * dma_clean_range(start, end)
292 *
293 * Clean the specified virtual address range.
294 *
295 * - start - virtual start address
296 * - end - virtual end address
297 */
298 ENTRY(xsc3_dma_clean_range)
299 bic r0, r0, #CACHELINESIZE - 1
300 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D entry
301 mcr p15, 1, r0, c7, c11, 1 @ clean L2 D entry
302 add r0, r0, #CACHELINESIZE
303 cmp r0, r1
304 blo 1b
305 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
306 mov pc, lr
308 /*
309 * dma_flush_range(start, end)
310 *
311 * Clean and invalidate the specified virtual address range.
312 *
313 * - start - virtual start address
314 * - end - virtual end address
315 */
316 ENTRY(xsc3_dma_flush_range)
317 bic r0, r0, #CACHELINESIZE - 1
318 1: mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate L1 D cache line
319 mcr p15, 1, r0, c7, c11, 1 @ Clean L2 D cache line
320 mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
321 add r0, r0, #CACHELINESIZE
322 cmp r0, r1
323 blo 1b
324 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
325 mov pc, lr
327 ENTRY(xsc3_cache_fns)
328 .long xsc3_flush_kern_cache_all
329 .long xsc3_flush_user_cache_all
330 .long xsc3_flush_user_cache_range
331 .long xsc3_coherent_kern_range
332 .long xsc3_coherent_user_range
333 .long xsc3_flush_kern_dcache_page
334 .long xsc3_dma_inv_range
335 .long xsc3_dma_clean_range
336 .long xsc3_dma_flush_range
338 ENTRY(cpu_xsc3_dcache_clean_area)
339 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
340 add r0, r0, #CACHELINESIZE
341 subs r1, r1, #CACHELINESIZE
342 bhi 1b
343 mov pc, lr
345 /* =============================== PageTable ============================== */
347 /*
348 * cpu_xsc3_switch_mm(pgd)
349 *
350 * Set the translation base pointer to be as described by pgd.
351 *
352 * pgd: new page tables
353 */
354 .align 5
355 ENTRY(cpu_xsc3_switch_mm)
356 clean_d_cache r1, r2
357 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
358 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
359 mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
360 #ifdef L2_CACHE_ENABLE
361 orr r0, r0, #0x18 @ cache the page table in L2
362 #endif
363 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
364 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
365 cpwait_ret lr, ip
367 /*
368 * cpu_xsc3_set_pte(ptep, pte)
369 *
370 * Set a PTE and flush it out
371 *
372 */
373 .align 5
374 ENTRY(cpu_xsc3_set_pte)
375 str r1, [r0], #-2048 @ linux version
377 bic r2, r1, #0xdf0 @ Keep C, B, coherency bits
378 orr r2, r2, #PTE_TYPE_EXT @ extended page
380 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
382 tst r3, #L_PTE_USER @ User?
383 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
385 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
386 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
387 @ combined with user -> user r/w
389 #if L2_CACHE_ENABLE
390 @ If its cacheable it needs to be in L2 also.
391 eor ip, r1, #L_PTE_CACHEABLE
392 tst ip, #L_PTE_CACHEABLE
393 orreq r2, r2, #PTE_EXT_TEX(0x5)
394 #endif
396 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
397 movne r2, #0 @ no -> fault
399 str r2, [r0] @ hardware version
400 mov ip, #0
401 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line mcr
402 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
403 mov pc, lr
405 .ltorg
407 .align
409 __INIT
411 .type __xsc3_setup, #function
412 __xsc3_setup:
413 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
414 msr cpsr_c, r0
415 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
416 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
417 mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
418 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
419 #if L2_CACHE_ENABLE
420 orr r4, r4, #0x18 @ cache the page table in L2
421 #endif
422 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
423 mov r0, #1 @ Allow access to CP0 and CP13
424 orr r0, r0, #1 << 13 @ Its undefined whether this
425 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
426 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
427 and r0, r0, #2 @ preserve bit P bit setting
428 #if L2_CACHE_ENABLE
429 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
430 #endif
431 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
433 adr r5, xsc3_crval
434 ldmia r5, {r5, r6}
435 mrc p15, 0, r0, c1, c0, 0 @ get control register
436 bic r0, r0, r5 @ .... .... .... ..A.
437 orr r0, r0, r6 @ .... .... .... .C.M
438 #if BTB_ENABLE
439 orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
440 #endif
441 #if L2_CACHE_ENABLE
442 orr r0, r0, #0x04000000 @ L2 enable
443 #endif
444 mov pc, lr
446 .size __xsc3_setup, . - __xsc3_setup
448 .type xsc3_crval, #object
449 xsc3_crval:
450 crval clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
452 __INITDATA
454 /*
455 * Purpose : Function pointers used to access above functions - all calls
456 * come through these
457 */
459 .type xsc3_processor_functions, #object
460 ENTRY(xsc3_processor_functions)
461 .word v5t_early_abort
462 .word cpu_xsc3_proc_init
463 .word cpu_xsc3_proc_fin
464 .word cpu_xsc3_reset
465 .word cpu_xsc3_do_idle
466 .word cpu_xsc3_dcache_clean_area
467 .word cpu_xsc3_switch_mm
468 .word cpu_xsc3_set_pte
469 .size xsc3_processor_functions, . - xsc3_processor_functions
471 .section ".rodata"
473 .type cpu_arch_name, #object
474 cpu_arch_name:
475 .asciz "armv5te"
476 .size cpu_arch_name, . - cpu_arch_name
478 .type cpu_elf_name, #object
479 cpu_elf_name:
480 .asciz "v5"
481 .size cpu_elf_name, . - cpu_elf_name
483 .type cpu_xsc3_name, #object
484 cpu_xsc3_name:
485 .asciz "XScale-Core3"
486 .size cpu_xsc3_name, . - cpu_xsc3_name
488 .align
490 .section ".proc.info.init", #alloc, #execinstr
492 .type __xsc3_proc_info,#object
493 __xsc3_proc_info:
494 .long 0x69056000
495 .long 0xffffe000
496 .long PMD_TYPE_SECT | \
497 PMD_SECT_BUFFERABLE | \
498 PMD_SECT_CACHEABLE | \
499 PMD_SECT_AP_WRITE | \
500 PMD_SECT_AP_READ
501 .long PMD_TYPE_SECT | \
502 PMD_SECT_AP_WRITE | \
503 PMD_SECT_AP_READ
504 b __xsc3_setup
505 .long cpu_arch_name
506 .long cpu_elf_name
507 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
508 .long cpu_xsc3_name
509 .long xsc3_processor_functions
510 .long v4wbi_tlb_fns
511 .long xsc3_mc_user_fns
512 .long xsc3_cache_fns
513 .size __xsc3_proc_info, . - __xsc3_proc_info